1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.17 2005/02/12 04:00:13 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 36 */ 37 38 /* 39 * RealTek 8129/8139 PCI NIC driver 40 * 41 * Supports several extremely cheap PCI 10/100 adapters based on 42 * the RealTek chipset. Datasheets can be obtained from 43 * www.realtek.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 52 * probably the worst PCI ethernet controller ever made, with the possible 53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 54 * DMA, but it has a terrible interface that nullifies any performance 55 * gains that bus-master DMA usually offers. 56 * 57 * For transmission, the chip offers a series of four TX descriptor 58 * registers. Each transmit frame must be in a contiguous buffer, aligned 59 * on a longword (32-bit) boundary. This means we almost always have to 60 * do mbuf copies in order to transmit a frame, except in the unlikely 61 * case where a) the packet fits into a single mbuf, and b) the packet 62 * is 32-bit aligned within the mbuf's data area. The presence of only 63 * four descriptor registers means that we can never have more than four 64 * packets queued for transmission at any one time. 65 * 66 * Reception is not much better. The driver has to allocate a single large 67 * buffer area (up to 64K in size) into which the chip will DMA received 68 * frames. Because we don't know where within this region received packets 69 * will begin or end, we have no choice but to copy data from the buffer 70 * area into mbufs in order to pass the packets up to the higher protocol 71 * levels. 72 * 73 * It's impossible given this rotten design to really achieve decent 74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 75 * some equally overmuscled CPU to drive it. 76 * 77 * On the bright side, the 8139 does have a built-in PHY, although 78 * rather than using an MDIO serial interface like most other NICs, the 79 * PHY registers are directly accessible through the 8139's register 80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 81 * filter. 82 * 83 * The 8129 chip is an older version of the 8139 that uses an external PHY 84 * chip. The 8129 has a serial MDIO interface for accessing the MII where 85 * the 8139 lets you directly access the on-board PHY registers. We need 86 * to select which interface to use depending on the chip type. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/module.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <machine/bus_pio.h> 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/netif/mii_layer/mii.h> 116 #include <dev/netif/mii_layer/miivar.h> 117 118 #include <bus/pci/pcireg.h> 119 #include <bus/pci/pcivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 /* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132 #define RL_USEIOSPACE 133 134 #include <dev/netif/rl/if_rlreg.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static struct rl_type { 140 uint16_t rl_vid; 141 uint16_t rl_did; 142 const char *rl_name; 143 } rl_devs[] = { 144 { RT_VENDORID, RT_DEVICEID_8129, 145 "RealTek 8129 10/100BaseTX" }, 146 { RT_VENDORID, RT_DEVICEID_8139, 147 "RealTek 8139 10/100BaseTX" }, 148 { RT_VENDORID, RT_DEVICEID_8138, 149 "RealTek 8139 10/100BaseTX CardBus" }, 150 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 151 "Accton MPX 5030/5038 10/100BaseTX" }, 152 { DELTA_VENDORID, DELTA_DEVICEID_8139, 153 "Delta Electronics 8139 10/100BaseTX" }, 154 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 155 "Addtron Technolgy 8139 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 157 "D-Link DFE-530TX+ 10/100BaseTX" }, 158 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 159 "D-Link DFE-690TX 10/100BaseTX" }, 160 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 161 "Nortel Networks 10/100BaseTX" }, 162 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 163 "Peppercon AG ROL/F" }, 164 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 165 "Corega FEther CB-TXD" }, 166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 167 "Corega FEtherII CB-TXD" }, 168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 169 "Planex FNW-3800-TX" }, 170 { 0, 0, NULL } 171 }; 172 173 static int rl_probe(device_t); 174 static int rl_attach(device_t); 175 static int rl_detach(device_t); 176 177 static int rl_encap(struct rl_softc *, struct mbuf * ); 178 179 static void rl_rxeof(struct rl_softc *); 180 static void rl_txeof(struct rl_softc *); 181 static void rl_intr(void *); 182 static void rl_tick(void *); 183 static void rl_start(struct ifnet *); 184 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 185 static void rl_init(void *); 186 static void rl_stop (struct rl_softc *); 187 static void rl_watchdog(struct ifnet *); 188 static int rl_suspend(device_t); 189 static int rl_resume(device_t); 190 static void rl_shutdown(device_t); 191 static int rl_ifmedia_upd(struct ifnet *); 192 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 193 194 static void rl_eeprom_putbyte(struct rl_softc *, int); 195 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 196 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 197 static void rl_mii_sync(struct rl_softc *); 198 static void rl_mii_send(struct rl_softc *, uint32_t, int); 199 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 200 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 201 202 static int rl_miibus_readreg(device_t, int, int); 203 static int rl_miibus_writereg(device_t, int, int, int); 204 static void rl_miibus_statchg(device_t); 205 206 static void rl_setmulti(struct rl_softc *); 207 static void rl_reset(struct rl_softc *); 208 static void rl_list_tx_init(struct rl_softc *); 209 210 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 211 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 212 213 #ifdef RL_USEIOSPACE 214 #define RL_RES SYS_RES_IOPORT 215 #define RL_RID RL_PCI_LOIO 216 #else 217 #define RL_RES SYS_RES_MEMORY 218 #define RL_RID RL_PCI_LOMEM 219 #endif 220 221 static device_method_t rl_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, rl_probe), 224 DEVMETHOD(device_attach, rl_attach), 225 DEVMETHOD(device_detach, rl_detach), 226 DEVMETHOD(device_suspend, rl_suspend), 227 DEVMETHOD(device_resume, rl_resume), 228 DEVMETHOD(device_shutdown, rl_shutdown), 229 230 /* bus interface */ 231 DEVMETHOD(bus_print_child, bus_generic_print_child), 232 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 233 234 /* MII interface */ 235 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 236 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 237 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 238 239 { 0, 0 } 240 }; 241 242 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 243 static devclass_t rl_devclass; 244 245 DECLARE_DUMMY_MODULE(if_rl); 246 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 247 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 248 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 249 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 250 251 #define EE_SET(x) \ 252 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 253 254 #define EE_CLR(x) \ 255 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 256 257 static void 258 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 259 { 260 struct rl_softc *sc = arg; 261 262 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 263 } 264 265 static void 266 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 267 { 268 struct rl_softc *sc = arg; 269 270 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 271 } 272 273 /* 274 * Send a read command and address to the EEPROM, check for ACK. 275 */ 276 static void 277 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 278 { 279 int d, i; 280 281 d = addr | sc->rl_eecmd_read; 282 283 /* 284 * Feed in each bit and strobe the clock. 285 */ 286 for (i = 0x400; i; i >>= 1) { 287 if (d & i) 288 EE_SET(RL_EE_DATAIN); 289 else 290 EE_CLR(RL_EE_DATAIN); 291 DELAY(100); 292 EE_SET(RL_EE_CLK); 293 DELAY(150); 294 EE_CLR(RL_EE_CLK); 295 DELAY(100); 296 } 297 } 298 299 /* 300 * Read a word of data stored in the EEPROM at address 'addr.' 301 */ 302 static void 303 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 304 { 305 int i; 306 uint16_t word = 0; 307 308 /* Enter EEPROM access mode. */ 309 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 310 311 /* 312 * Send address of word we want to read. 313 */ 314 rl_eeprom_putbyte(sc, addr); 315 316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 317 318 /* 319 * Start reading bits from EEPROM. 320 */ 321 for (i = 0x8000; i; i >>= 1) { 322 EE_SET(RL_EE_CLK); 323 DELAY(100); 324 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 325 word |= i; 326 EE_CLR(RL_EE_CLK); 327 DELAY(100); 328 } 329 330 /* Turn off EEPROM access mode. */ 331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 332 333 *dest = word; 334 } 335 336 /* 337 * Read a sequence of words from the EEPROM. 338 */ 339 static void 340 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 341 { 342 int i; 343 u_int16_t word = 0, *ptr; 344 345 for (i = 0; i < cnt; i++) { 346 rl_eeprom_getword(sc, off + i, &word); 347 ptr = (u_int16_t *)(dest + (i * 2)); 348 if (swap) 349 *ptr = ntohs(word); 350 else 351 *ptr = word; 352 } 353 } 354 355 356 /* 357 * MII access routines are provided for the 8129, which 358 * doesn't have a built-in PHY. For the 8139, we fake things 359 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 360 * direct access PHY registers. 361 */ 362 #define MII_SET(x) \ 363 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 364 365 #define MII_CLR(x) \ 366 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 367 368 /* 369 * Sync the PHYs by setting data bit and strobing the clock 32 times. 370 */ 371 static void 372 rl_mii_sync(struct rl_softc *sc) 373 { 374 int i; 375 376 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 377 378 for (i = 0; i < 32; i++) { 379 MII_SET(RL_MII_CLK); 380 DELAY(1); 381 MII_CLR(RL_MII_CLK); 382 DELAY(1); 383 } 384 } 385 386 /* 387 * Clock a series of bits through the MII. 388 */ 389 static void 390 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 391 { 392 int i; 393 394 MII_CLR(RL_MII_CLK); 395 396 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 397 if (bits & i) 398 MII_SET(RL_MII_DATAOUT); 399 else 400 MII_CLR(RL_MII_DATAOUT); 401 DELAY(1); 402 MII_CLR(RL_MII_CLK); 403 DELAY(1); 404 MII_SET(RL_MII_CLK); 405 } 406 } 407 408 /* 409 * Read an PHY register through the MII. 410 */ 411 static int 412 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 413 { 414 int i, ack, s; 415 416 s = splimp(); 417 418 /* 419 * Set up frame for RX. 420 */ 421 frame->mii_stdelim = RL_MII_STARTDELIM; 422 frame->mii_opcode = RL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 CSR_WRITE_2(sc, RL_MII, 0); 427 428 /* 429 * Turn on data xmit. 430 */ 431 MII_SET(RL_MII_DIR); 432 433 rl_mii_sync(sc); 434 435 /* 436 * Send command/address info. 437 */ 438 rl_mii_send(sc, frame->mii_stdelim, 2); 439 rl_mii_send(sc, frame->mii_opcode, 2); 440 rl_mii_send(sc, frame->mii_phyaddr, 5); 441 rl_mii_send(sc, frame->mii_regaddr, 5); 442 443 /* Idle bit */ 444 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 445 DELAY(1); 446 MII_SET(RL_MII_CLK); 447 DELAY(1); 448 449 /* Turn off xmit. */ 450 MII_CLR(RL_MII_DIR); 451 452 /* Check for ack */ 453 MII_CLR(RL_MII_CLK); 454 DELAY(1); 455 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 456 MII_SET(RL_MII_CLK); 457 DELAY(1); 458 459 /* 460 * Now try reading data bits. If the ack failed, we still 461 * need to clock through 16 cycles to keep the PHY(s) in sync. 462 */ 463 if (ack) { 464 for(i = 0; i < 16; i++) { 465 MII_CLR(RL_MII_CLK); 466 DELAY(1); 467 MII_SET(RL_MII_CLK); 468 DELAY(1); 469 } 470 } else { 471 for (i = 0x8000; i; i >>= 1) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 if (!ack) { 475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 476 frame->mii_data |= i; 477 DELAY(1); 478 } 479 MII_SET(RL_MII_CLK); 480 DELAY(1); 481 } 482 } 483 484 MII_CLR(RL_MII_CLK); 485 DELAY(1); 486 MII_SET(RL_MII_CLK); 487 DELAY(1); 488 489 splx(s); 490 491 return(ack ? 1 : 0); 492 } 493 494 /* 495 * Write to a PHY register through the MII. 496 */ 497 static int 498 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 499 { 500 int s; 501 502 s = splimp(); 503 /* 504 * Set up frame for TX. 505 */ 506 507 frame->mii_stdelim = RL_MII_STARTDELIM; 508 frame->mii_opcode = RL_MII_WRITEOP; 509 frame->mii_turnaround = RL_MII_TURNAROUND; 510 511 /* 512 * Turn on data output. 513 */ 514 MII_SET(RL_MII_DIR); 515 516 rl_mii_sync(sc); 517 518 rl_mii_send(sc, frame->mii_stdelim, 2); 519 rl_mii_send(sc, frame->mii_opcode, 2); 520 rl_mii_send(sc, frame->mii_phyaddr, 5); 521 rl_mii_send(sc, frame->mii_regaddr, 5); 522 rl_mii_send(sc, frame->mii_turnaround, 2); 523 rl_mii_send(sc, frame->mii_data, 16); 524 525 /* Idle bit. */ 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 MII_CLR(RL_MII_CLK); 529 DELAY(1); 530 531 /* 532 * Turn off xmit. 533 */ 534 MII_CLR(RL_MII_DIR); 535 536 splx(s); 537 538 return(0); 539 } 540 541 static int 542 rl_miibus_readreg(device_t dev, int phy, int reg) 543 { 544 struct rl_softc *sc; 545 struct rl_mii_frame frame; 546 uint16_t rval = 0; 547 uint16_t rl8139_reg = 0; 548 549 sc = device_get_softc(dev); 550 551 if (sc->rl_type == RL_8139) { 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return(0); 555 switch (reg) { 556 case MII_BMCR: 557 rl8139_reg = RL_BMCR; 558 break; 559 case MII_BMSR: 560 rl8139_reg = RL_BMSR; 561 break; 562 case MII_ANAR: 563 rl8139_reg = RL_ANAR; 564 break; 565 case MII_ANER: 566 rl8139_reg = RL_ANER; 567 break; 568 case MII_ANLPAR: 569 rl8139_reg = RL_LPAR; 570 break; 571 case MII_PHYIDR1: 572 case MII_PHYIDR2: 573 return(0); 574 break; 575 /* 576 * Allow the rlphy driver to read the media status 577 * register. If we have a link partner which does not 578 * support NWAY, this is the register which will tell 579 * us the results of parallel detection. 580 */ 581 case RL_MEDIASTAT: 582 rval = CSR_READ_1(sc, RL_MEDIASTAT); 583 return(rval); 584 default: 585 device_printf(dev, "bad phy register\n"); 586 return(0); 587 } 588 rval = CSR_READ_2(sc, rl8139_reg); 589 return(rval); 590 } 591 592 bzero(&frame, sizeof(frame)); 593 594 frame.mii_phyaddr = phy; 595 frame.mii_regaddr = reg; 596 rl_mii_readreg(sc, &frame); 597 598 return(frame.mii_data); 599 } 600 601 static int 602 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 603 { 604 struct rl_softc *sc; 605 struct rl_mii_frame frame; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 610 if (sc->rl_type == RL_8139) { 611 /* Pretend the internal PHY is only at address 0 */ 612 if (phy) 613 return(0); 614 switch (reg) { 615 case MII_BMCR: 616 rl8139_reg = RL_BMCR; 617 break; 618 case MII_BMSR: 619 rl8139_reg = RL_BMSR; 620 break; 621 case MII_ANAR: 622 rl8139_reg = RL_ANAR; 623 break; 624 case MII_ANER: 625 rl8139_reg = RL_ANER; 626 break; 627 case MII_ANLPAR: 628 rl8139_reg = RL_LPAR; 629 break; 630 case MII_PHYIDR1: 631 case MII_PHYIDR2: 632 return(0); 633 default: 634 device_printf(dev, "bad phy register\n"); 635 return(0); 636 } 637 CSR_WRITE_2(sc, rl8139_reg, data); 638 return(0); 639 } 640 641 bzero(&frame, sizeof(frame)); 642 643 frame.mii_phyaddr = phy; 644 frame.mii_regaddr = reg; 645 frame.mii_data = data; 646 647 rl_mii_writereg(sc, &frame); 648 649 return(0); 650 } 651 652 static void 653 rl_miibus_statchg(device_t dev) 654 { 655 } 656 657 /* 658 * Program the 64-bit multicast hash filter. 659 */ 660 static void 661 rl_setmulti(struct rl_softc *sc) 662 { 663 struct ifnet *ifp; 664 int h = 0; 665 uint32_t hashes[2] = { 0, 0 }; 666 struct ifmultiaddr *ifma; 667 uint32_t rxfilt; 668 int mcnt = 0; 669 670 ifp = &sc->arpcom.ac_if; 671 672 rxfilt = CSR_READ_4(sc, RL_RXCFG); 673 674 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 675 rxfilt |= RL_RXCFG_RX_MULTI; 676 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 677 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 678 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 679 return; 680 } 681 682 /* first, zot all the existing hash bits */ 683 CSR_WRITE_4(sc, RL_MAR0, 0); 684 CSR_WRITE_4(sc, RL_MAR4, 0); 685 686 /* now program new ones */ 687 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 688 if (ifma->ifma_addr->sa_family != AF_LINK) 689 continue; 690 h = ether_crc32_be( 691 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 692 ETHER_ADDR_LEN >> 26); 693 if (h < 32) 694 hashes[0] |= (1 << h); 695 else 696 hashes[1] |= (1 << (h - 32)); 697 mcnt++; 698 } 699 700 if (mcnt) 701 rxfilt |= RL_RXCFG_RX_MULTI; 702 else 703 rxfilt &= ~RL_RXCFG_RX_MULTI; 704 705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 708 } 709 710 static void 711 rl_reset(struct rl_softc *sc) 712 { 713 int i; 714 715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 716 717 for (i = 0; i < RL_TIMEOUT; i++) { 718 DELAY(10); 719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 720 break; 721 } 722 if (i == RL_TIMEOUT) 723 device_printf(sc->rl_dev, "reset never completed!\n"); 724 } 725 726 /* 727 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 728 * IDs against our list and return a device name if we find a match. 729 * 730 * Return with a value < 0 to give re(4) a change to attach. 731 */ 732 static int 733 rl_probe(device_t dev) 734 { 735 struct rl_type *t; 736 uint16_t product = pci_get_device(dev); 737 uint16_t vendor = pci_get_vendor(dev); 738 739 for (t = rl_devs; t->rl_name != NULL; t++) { 740 if (vendor == t->rl_vid && product == t->rl_did) { 741 device_set_desc(dev, t->rl_name); 742 return(-100); 743 } 744 } 745 746 return(ENXIO); 747 } 748 749 /* 750 * Attach the interface. Allocate softc structures, do ifmedia 751 * setup and ethernet/BPF attach. 752 */ 753 static int 754 rl_attach(device_t dev) 755 { 756 uint8_t eaddr[ETHER_ADDR_LEN]; 757 uint16_t as[3]; 758 struct rl_softc *sc; 759 struct ifnet *ifp; 760 uint16_t rl_did = 0; 761 int error = 0, rid, i; 762 763 sc = device_get_softc(dev); 764 sc->rl_dev = dev; 765 766 /* 767 * Handle power management nonsense. 768 */ 769 770 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 771 uint32_t iobase, membase, irq; 772 773 /* Save important PCI config data. */ 774 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 775 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 776 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 777 778 /* Reset the power state. */ 779 device_printf(dev, "chip is is in D%d power mode " 780 "-- setting to D0\n", pci_get_powerstate(dev)); 781 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 782 783 /* Restore PCI config data. */ 784 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 785 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 786 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 787 } 788 789 /* 790 * Map control/status registers. 791 */ 792 pci_enable_busmaster(dev); 793 pci_enable_io(dev, RL_RES); 794 795 rid = RL_RID; 796 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 797 0, ~0, 1, RF_ACTIVE); 798 799 if (sc->rl_res == NULL) { 800 device_printf(dev, "couldn't map ports/memory\n"); 801 error = ENXIO; 802 goto fail; 803 } 804 805 sc->rl_btag = rman_get_bustag(sc->rl_res); 806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 807 808 rid = 0; 809 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 810 RF_SHAREABLE | RF_ACTIVE); 811 812 if (sc->rl_irq == NULL) { 813 device_printf(dev, "couldn't map interrupt\n"); 814 error = ENXIO; 815 goto fail; 816 } 817 818 callout_init(&sc->rl_stat_timer); 819 820 /* Reset the adapter. */ 821 rl_reset(sc); 822 823 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 824 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 825 if (rl_did != 0x8129) 826 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 827 828 /* 829 * Get station address from the EEPROM. 830 */ 831 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 832 for (i = 0; i < 3; i++) { 833 eaddr[(i * 2) + 0] = as[i] & 0xff; 834 eaddr[(i * 2) + 1] = as[i] >> 8; 835 } 836 837 /* 838 * Now read the exact device type from the EEPROM to find 839 * out if it's an 8129 or 8139. 840 */ 841 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 842 843 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 844 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 845 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 || 846 rl_did == DLINK_DEVICEID_690TXD || 847 rl_did == COREGA_DEVICEID_FETHERCBTXD || 848 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 849 rl_did == PLANEX_DEVICEID_FNW3800TX) 850 sc->rl_type = RL_8139; 851 else if (rl_did == RT_DEVICEID_8129) 852 sc->rl_type = RL_8129; 853 else { 854 device_printf(dev, "unknown device ID: %x\n", rl_did); 855 error = ENXIO; 856 goto fail; 857 } 858 859 #define RL_NSEG_NEW 32 860 error = bus_dma_tag_create(NULL, /* parent */ 861 1, 0, /* alignment, boundary */ 862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 863 BUS_SPACE_MAXADDR, /* highaddr */ 864 NULL, NULL, /* filter, filterarg */ 865 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 866 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 867 BUS_DMA_ALLOCNOW, /* flags */ 868 &sc->rl_parent_tag); 869 870 if (error) { 871 device_printf(dev, "can't create parent tag\n"); 872 goto fail; 873 } 874 875 /* 876 * Now allocate a tag for the DMA descriptor lists. 877 * All of our lists are allocated as a contiguous block 878 * of memory. 879 */ 880 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 881 1, 0, /* alignment, boundary */ 882 BUS_SPACE_MAXADDR, /* lowaddr */ 883 BUS_SPACE_MAXADDR, /* highaddr */ 884 NULL, NULL, /* filter, filterarg */ 885 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */ 886 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 887 0, /* flags */ 888 &sc->rl_tag); 889 890 if (error) { 891 device_printf(dev, "can't create RX tag\n"); 892 goto fail; 893 } 894 895 /* 896 * Now allocate a chunk of DMA-able memory based on the tag 897 * we just created. 898 */ 899 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf, 900 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap); 901 902 if (error) { 903 device_printf(dev, "can't allocate RX memory!\n"); 904 error = ENXIO; 905 goto fail; 906 } 907 908 /* Leave a few bytes before the start of the RX ring buffer. */ 909 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 910 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 911 912 /* Do MII setup */ 913 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 914 rl_ifmedia_sts)) { 915 device_printf(dev, "MII without any phy!\n"); 916 error = ENXIO; 917 goto fail; 918 } 919 920 ifp = &sc->arpcom.ac_if; 921 ifp->if_softc = sc; 922 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 923 ifp->if_mtu = ETHERMTU; 924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 925 ifp->if_ioctl = rl_ioctl; 926 ifp->if_start = rl_start; 927 ifp->if_watchdog = rl_watchdog; 928 ifp->if_init = rl_init; 929 ifp->if_baudrate = 10000000; 930 ifp->if_capabilities = IFCAP_VLAN_MTU; 931 #ifdef DEVICE_POLLING 932 ifp->if_capabilities |= IFCAP_POLLING; 933 #endif 934 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 935 ifq_set_ready(&ifp->if_snd); 936 937 /* 938 * Call MI attach routine. 939 */ 940 ether_ifattach(ifp, eaddr); 941 942 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr, 943 sc, &sc->rl_intrhand); 944 945 if (error) { 946 device_printf(dev, "couldn't set up irq\n"); 947 ether_ifdetach(ifp); 948 goto fail; 949 } 950 951 return(0); 952 953 fail: 954 rl_detach(dev); 955 return(error); 956 } 957 958 static int 959 rl_detach(device_t dev) 960 { 961 struct rl_softc *sc; 962 struct ifnet *ifp; 963 int s; 964 965 sc = device_get_softc(dev); 966 ifp = &sc->arpcom.ac_if; 967 968 s = splimp(); 969 970 if (device_is_attached(dev)) { 971 rl_stop(sc); 972 ether_ifdetach(ifp); 973 } 974 975 if (sc->rl_miibus) 976 device_delete_child(dev, sc->rl_miibus); 977 bus_generic_detach(dev); 978 979 if (sc->rl_intrhand) 980 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 981 splx(s); 982 983 if (sc->rl_irq) 984 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 985 if (sc->rl_res) 986 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 987 988 if (sc->rl_cdata.rl_rx_buf) { 989 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 990 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 991 sc->rl_cdata.rl_rx_dmamap); 992 } 993 if (sc->rl_tag) 994 bus_dma_tag_destroy(sc->rl_tag); 995 if (sc->rl_parent_tag) 996 bus_dma_tag_destroy(sc->rl_parent_tag); 997 998 return(0); 999 } 1000 1001 /* 1002 * Initialize the transmit descriptors. 1003 */ 1004 static void 1005 rl_list_tx_init(struct rl_softc *sc) 1006 { 1007 struct rl_chain_data *cd; 1008 int i; 1009 1010 cd = &sc->rl_cdata; 1011 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1012 cd->rl_tx_chain[i] = NULL; 1013 CSR_WRITE_4(sc, 1014 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1015 } 1016 1017 sc->rl_cdata.cur_tx = 0; 1018 sc->rl_cdata.last_tx = 0; 1019 } 1020 1021 /* 1022 * A frame has been uploaded: pass the resulting mbuf chain up to 1023 * the higher level protocols. 1024 * 1025 * You know there's something wrong with a PCI bus-master chip design 1026 * when you have to use m_devget(). 1027 * 1028 * The receive operation is badly documented in the datasheet, so I'll 1029 * attempt to document it here. The driver provides a buffer area and 1030 * places its base address in the RX buffer start address register. 1031 * The chip then begins copying frames into the RX buffer. Each frame 1032 * is preceded by a 32-bit RX status word which specifies the length 1033 * of the frame and certain other status bits. Each frame (starting with 1034 * the status word) is also 32-bit aligned. The frame length is in the 1035 * first 16 bits of the status word; the lower 15 bits correspond with 1036 * the 'rx status register' mentioned in the datasheet. 1037 * 1038 * Note: to make the Alpha happy, the frame payload needs to be aligned 1039 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1040 * the ring buffer starting at an address two bytes before the actual 1041 * data location. We can then shave off the first two bytes using m_adj(). 1042 * The reason we do this is because m_devget() doesn't let us specify an 1043 * offset into the mbuf storage space, so we have to artificially create 1044 * one. The ring is allocated in such a way that there are a few unused 1045 * bytes of space preceecing it so that it will be safe for us to do the 1046 * 2-byte backstep even if reading from the ring at offset 0. 1047 */ 1048 static void 1049 rl_rxeof(struct rl_softc *sc) 1050 { 1051 struct mbuf *m; 1052 struct ifnet *ifp; 1053 int total_len = 0; 1054 uint32_t rxstat; 1055 caddr_t rxbufpos; 1056 int wrap = 0; 1057 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1062 BUS_DMASYNC_POSTREAD); 1063 1064 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1065 1066 /* Do not try to read past this point. */ 1067 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1068 1069 if (limit < cur_rx) 1070 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1071 else 1072 max_bytes = limit - cur_rx; 1073 1074 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1075 #ifdef DEVICE_POLLING 1076 if (ifp->if_flags & IFF_POLLING) { 1077 if (sc->rxcycles <= 0) 1078 break; 1079 sc->rxcycles--; 1080 } 1081 #endif /* DEVICE_POLLING */ 1082 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1083 rxstat = le32toh(*(uint32_t *)rxbufpos); 1084 1085 /* 1086 * Here's a totally undocumented fact for you. When the 1087 * RealTek chip is in the process of copying a packet into 1088 * RAM for you, the length will be 0xfff0. If you spot a 1089 * packet header with this value, you need to stop. The 1090 * datasheet makes absolutely no mention of this and 1091 * RealTek should be shot for this. 1092 */ 1093 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1094 break; 1095 1096 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1097 ifp->if_ierrors++; 1098 rl_init(sc); 1099 return; 1100 } 1101 1102 /* No errors; receive the packet. */ 1103 total_len = rxstat >> 16; 1104 rx_bytes += total_len + 4; 1105 1106 /* 1107 * XXX The RealTek chip includes the CRC with every 1108 * received frame, and there's no way to turn this 1109 * behavior off (at least, I can't find anything in 1110 * the manual that explains how to do it) so we have 1111 * to trim off the CRC manually. 1112 */ 1113 total_len -= ETHER_CRC_LEN; 1114 1115 /* 1116 * Avoid trying to read more bytes than we know 1117 * the chip has prepared for us. 1118 */ 1119 if (rx_bytes > max_bytes) 1120 break; 1121 1122 rxbufpos = sc->rl_cdata.rl_rx_buf + 1123 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1124 1125 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1126 rxbufpos = sc->rl_cdata.rl_rx_buf; 1127 1128 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1129 1130 if (total_len > wrap) { 1131 /* 1132 * Fool m_devget() into thinking we want to copy 1133 * the whole buffer so we don't end up fragmenting 1134 * the data. 1135 */ 1136 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1137 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1138 if (m == NULL) { 1139 ifp->if_ierrors++; 1140 } else { 1141 m_adj(m, RL_ETHER_ALIGN); 1142 m_copyback(m, wrap, total_len - wrap, 1143 sc->rl_cdata.rl_rx_buf); 1144 } 1145 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1146 } else { 1147 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1148 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1149 if (m == NULL) { 1150 ifp->if_ierrors++; 1151 } else 1152 m_adj(m, RL_ETHER_ALIGN); 1153 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1154 } 1155 1156 /* 1157 * Round up to 32-bit boundary. 1158 */ 1159 cur_rx = (cur_rx + 3) & ~3; 1160 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1161 1162 if (m == NULL) 1163 continue; 1164 1165 ifp->if_ipackets++; 1166 1167 (*ifp->if_input)(ifp, m); 1168 } 1169 } 1170 1171 /* 1172 * A frame was downloaded to the chip. It's safe for us to clean up 1173 * the list buffers. 1174 */ 1175 static void 1176 rl_txeof(struct rl_softc *sc) 1177 { 1178 struct ifnet *ifp; 1179 uint32_t txstat; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 1183 /* 1184 * Go through our tx list and free mbufs for those 1185 * frames that have been uploaded. 1186 */ 1187 do { 1188 if (RL_LAST_TXMBUF(sc) == NULL) 1189 break; 1190 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1191 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1192 RL_TXSTAT_TXABRT)) == 0) 1193 break; 1194 1195 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1196 1197 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1198 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1199 m_freem(RL_LAST_TXMBUF(sc)); 1200 RL_LAST_TXMBUF(sc) = NULL; 1201 1202 if ((txstat & RL_TXSTAT_TX_OK) == 0) { 1203 int oldthresh; 1204 1205 ifp->if_oerrors++; 1206 if ((txstat & RL_TXSTAT_TXABRT) || 1207 (txstat & RL_TXSTAT_OUTOFWIN)) 1208 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1209 oldthresh = sc->rl_txthresh; 1210 /* error recovery */ 1211 rl_reset(sc); 1212 rl_init(sc); 1213 /* 1214 * If there was a transmit underrun, 1215 * bump the TX threshold. 1216 */ 1217 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1218 sc->rl_txthresh = oldthresh + 32; 1219 return; 1220 } 1221 ifp->if_opackets++; 1222 RL_INC(sc->rl_cdata.last_tx); 1223 ifp->if_flags &= ~IFF_OACTIVE; 1224 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1225 1226 if (RL_LAST_TXMBUF(sc) == NULL) 1227 ifp->if_timer = 0; 1228 else if (ifp->if_timer == 0) 1229 ifp->if_timer = 5; 1230 } 1231 1232 static void 1233 rl_tick(void *xsc) 1234 { 1235 struct rl_softc *sc = xsc; 1236 struct mii_data *mii; 1237 int s; 1238 1239 s = splimp(); 1240 1241 mii = device_get_softc(sc->rl_miibus); 1242 mii_tick(mii); 1243 1244 splx(s); 1245 1246 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1247 } 1248 1249 #ifdef DEVICE_POLLING 1250 static poll_handler_t rl_poll; 1251 1252 static void 1253 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1254 { 1255 struct rl_softc *sc = ifp->if_softc; 1256 1257 if ((ifp->if_capenable & IFCAP_POLLING) == 0) { 1258 ether_poll_deregister(ifp); 1259 cmd = POLL_DEREGISTER; 1260 } 1261 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1262 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1263 return; 1264 } 1265 1266 sc->rxcycles = count; 1267 rl_rxeof(sc); 1268 rl_txeof(sc); 1269 if (!ifq_is_empty(&ifp->if_snd)) 1270 rl_start(ifp); 1271 1272 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1273 uint16_t status; 1274 1275 status = CSR_READ_2(sc, RL_ISR); 1276 if (status == 0xffff) 1277 return; 1278 if (status) 1279 CSR_WRITE_2(sc, RL_ISR, status); 1280 1281 /* 1282 * XXX check behaviour on receiver stalls. 1283 */ 1284 1285 if (status & RL_ISR_SYSTEM_ERR) { 1286 rl_reset(sc); 1287 rl_init(sc); 1288 } 1289 } 1290 } 1291 #endif /* DEVICE_POLLING */ 1292 1293 static void 1294 rl_intr(void *arg) 1295 { 1296 struct rl_softc *sc; 1297 struct ifnet *ifp; 1298 uint16_t status; 1299 1300 sc = arg; 1301 1302 if (sc->suspended) 1303 return; 1304 1305 ifp = &sc->arpcom.ac_if; 1306 #ifdef DEVICE_POLLING 1307 if (ifp->if_flags & IFF_POLLING) 1308 return; 1309 if ((ifp->if_capenable & IFCAP_POLLING) && 1310 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1311 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1312 rl_poll(ifp, 0, 1); 1313 return; 1314 } 1315 #endif /* DEVICE_POLLING */ 1316 1317 for (;;) { 1318 status = CSR_READ_2(sc, RL_ISR); 1319 /* If the card has gone away, the read returns 0xffff. */ 1320 if (status == 0xffff) 1321 break; 1322 1323 if (status != 0) 1324 CSR_WRITE_2(sc, RL_ISR, status); 1325 1326 if ((status & RL_INTRS) == 0) 1327 break; 1328 1329 if (status & RL_ISR_RX_OK) 1330 rl_rxeof(sc); 1331 1332 if (status & RL_ISR_RX_ERR) 1333 rl_rxeof(sc); 1334 1335 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1336 rl_txeof(sc); 1337 1338 if (status & RL_ISR_SYSTEM_ERR) { 1339 rl_reset(sc); 1340 rl_init(sc); 1341 } 1342 1343 } 1344 1345 if (!ifq_is_empty(&ifp->if_snd)) 1346 rl_start(ifp); 1347 } 1348 1349 /* 1350 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1351 * pointers to the fragment pointers. 1352 */ 1353 static int 1354 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1355 { 1356 struct mbuf *m_new = NULL; 1357 1358 /* 1359 * The RealTek is brain damaged and wants longword-aligned 1360 * TX buffers, plus we can only have one fragment buffer 1361 * per packet. We have to copy pretty much all the time. 1362 */ 1363 m_new = m_defrag(m_head, MB_DONTWAIT); 1364 1365 if (m_new == NULL) { 1366 m_freem(m_head); 1367 return(1); 1368 } 1369 m_head = m_new; 1370 1371 /* Pad frames to at least 60 bytes. */ 1372 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1373 /* 1374 * Make security concious people happy: zero out the 1375 * bytes in the pad area, since we don't know what 1376 * this mbuf cluster buffer's previous user might 1377 * have left in it. 1378 */ 1379 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1380 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1381 m_head->m_pkthdr.len += 1382 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1383 m_head->m_len = m_head->m_pkthdr.len; 1384 } 1385 1386 RL_CUR_TXMBUF(sc) = m_head; 1387 1388 return(0); 1389 } 1390 1391 /* 1392 * Main transmit routine. 1393 */ 1394 1395 static void 1396 rl_start(struct ifnet *ifp) 1397 { 1398 struct rl_softc *sc; 1399 struct mbuf *m_head = NULL; 1400 1401 sc = ifp->if_softc; 1402 1403 while(RL_CUR_TXMBUF(sc) == NULL) { 1404 m_head = ifq_dequeue(&ifp->if_snd); 1405 if (m_head == NULL) 1406 break; 1407 1408 if (rl_encap(sc, m_head)) 1409 break; 1410 1411 /* 1412 * If there's a BPF listener, bounce a copy of this frame 1413 * to him. 1414 */ 1415 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1416 1417 /* 1418 * Transmit the frame. 1419 */ 1420 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1421 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1422 mtod(RL_CUR_TXMBUF(sc), void *), 1423 RL_CUR_TXMBUF(sc)->m_pkthdr.len, 1424 rl_dma_map_txbuf, sc, 0); 1425 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1426 BUS_DMASYNC_PREREAD); 1427 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1428 RL_TXTHRESH(sc->rl_txthresh) | 1429 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1430 1431 RL_INC(sc->rl_cdata.cur_tx); 1432 1433 /* 1434 * Set a timeout in case the chip goes out to lunch. 1435 */ 1436 ifp->if_timer = 5; 1437 } 1438 1439 /* 1440 * We broke out of the loop because all our TX slots are 1441 * full. Mark the NIC as busy until it drains some of the 1442 * packets from the queue. 1443 */ 1444 if (RL_CUR_TXMBUF(sc) != NULL) 1445 ifp->if_flags |= IFF_OACTIVE; 1446 } 1447 1448 static void 1449 rl_init(void *xsc) 1450 { 1451 struct rl_softc *sc = xsc; 1452 struct ifnet *ifp = &sc->arpcom.ac_if; 1453 struct mii_data *mii; 1454 int s; 1455 uint32_t rxcfg = 0; 1456 1457 s = splimp(); 1458 1459 mii = device_get_softc(sc->rl_miibus); 1460 1461 /* 1462 * Cancel pending I/O and free all RX/TX buffers. 1463 */ 1464 rl_stop(sc); 1465 1466 /* 1467 * Init our MAC address. Even though the chipset documentation 1468 * doesn't mention it, we need to enter "Config register write enable" 1469 * mode to modify the ID registers. 1470 */ 1471 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1472 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1473 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1474 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1475 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1476 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1477 1478 /* Init the RX buffer pointer register. */ 1479 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1480 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, 1481 sc, 0); 1482 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1483 BUS_DMASYNC_PREWRITE); 1484 1485 /* Init TX descriptors. */ 1486 rl_list_tx_init(sc); 1487 1488 /* 1489 * Enable transmit and receive. 1490 */ 1491 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1492 1493 /* 1494 * Set the initial TX and RX configuration. 1495 */ 1496 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1497 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1498 1499 /* Set the individual bit to receive frames for this host only. */ 1500 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1501 rxcfg |= RL_RXCFG_RX_INDIV; 1502 1503 /* If we want promiscuous mode, set the allframes bit. */ 1504 if (ifp->if_flags & IFF_PROMISC) { 1505 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1506 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1507 } else { 1508 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1509 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1510 } 1511 1512 /* 1513 * Set capture broadcast bit to capture broadcast frames. 1514 */ 1515 if (ifp->if_flags & IFF_BROADCAST) { 1516 rxcfg |= RL_RXCFG_RX_BROAD; 1517 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1518 } else { 1519 rxcfg &= ~RL_RXCFG_RX_BROAD; 1520 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1521 } 1522 1523 /* 1524 * Program the multicast filter, if necessary. 1525 */ 1526 rl_setmulti(sc); 1527 1528 #ifdef DEVICE_POLLING 1529 /* 1530 * Only enable interrupts if we are polling, keep them off otherwise. 1531 */ 1532 if (ifp->if_flags & IFF_POLLING) 1533 CSR_WRITE_2(sc, RL_IMR, 0); 1534 else 1535 #endif /* DEVICE_POLLING */ 1536 /* 1537 * Enable interrupts. 1538 */ 1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1540 1541 /* Set initial TX threshold */ 1542 sc->rl_txthresh = RL_TX_THRESH_INIT; 1543 1544 /* Start RX/TX process. */ 1545 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1546 1547 /* Enable receiver and transmitter. */ 1548 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1549 1550 mii_mediachg(mii); 1551 1552 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1553 1554 ifp->if_flags |= IFF_RUNNING; 1555 ifp->if_flags &= ~IFF_OACTIVE; 1556 1557 splx(s); 1558 1559 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1560 } 1561 1562 /* 1563 * Set media options. 1564 */ 1565 static int 1566 rl_ifmedia_upd(struct ifnet *ifp) 1567 { 1568 struct rl_softc *sc; 1569 struct mii_data *mii; 1570 1571 sc = ifp->if_softc; 1572 mii = device_get_softc(sc->rl_miibus); 1573 mii_mediachg(mii); 1574 1575 return(0); 1576 } 1577 1578 /* 1579 * Report current media status. 1580 */ 1581 static void 1582 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1583 { 1584 struct rl_softc *sc = ifp->if_softc; 1585 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1586 1587 mii_pollstat(mii); 1588 ifmr->ifm_active = mii->mii_media_active; 1589 ifmr->ifm_status = mii->mii_media_status; 1590 } 1591 1592 static int 1593 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1594 { 1595 struct rl_softc *sc = ifp->if_softc; 1596 struct ifreq *ifr = (struct ifreq *) data; 1597 struct mii_data *mii; 1598 int s, error = 0; 1599 1600 s = splimp(); 1601 1602 switch (command) { 1603 case SIOCSIFFLAGS: 1604 if (ifp->if_flags & IFF_UP) { 1605 rl_init(sc); 1606 } else { 1607 if (ifp->if_flags & IFF_RUNNING) 1608 rl_stop(sc); 1609 } 1610 error = 0; 1611 break; 1612 case SIOCADDMULTI: 1613 case SIOCDELMULTI: 1614 rl_setmulti(sc); 1615 error = 0; 1616 break; 1617 case SIOCGIFMEDIA: 1618 case SIOCSIFMEDIA: 1619 mii = device_get_softc(sc->rl_miibus); 1620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1621 break; 1622 case SIOCSIFCAP: 1623 ifp->if_capenable &= ~IFCAP_POLLING; 1624 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1625 break; 1626 default: 1627 error = ether_ioctl(ifp, command, data); 1628 break; 1629 } 1630 1631 splx(s); 1632 1633 return(error); 1634 } 1635 1636 static void 1637 rl_watchdog(struct ifnet *ifp) 1638 { 1639 struct rl_softc *sc = ifp->if_softc; 1640 int s; 1641 1642 s = splimp(); 1643 1644 device_printf(sc->rl_dev, "watchdog timeout\n"); 1645 ifp->if_oerrors++; 1646 1647 rl_txeof(sc); 1648 rl_rxeof(sc); 1649 rl_init(sc); 1650 1651 splx(s); 1652 } 1653 1654 /* 1655 * Stop the adapter and free any mbufs allocated to the 1656 * RX and TX lists. 1657 */ 1658 static void 1659 rl_stop(struct rl_softc *sc) 1660 { 1661 struct ifnet *ifp = &sc->arpcom.ac_if; 1662 int i; 1663 1664 ifp->if_timer = 0; 1665 1666 callout_stop(&sc->rl_stat_timer); 1667 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1668 #ifdef DEVICE_POLLING 1669 ether_poll_deregister(ifp); 1670 #endif /* DEVICE_POLLING */ 1671 1672 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1673 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1674 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1675 1676 /* 1677 * Free the TX list buffers. 1678 */ 1679 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1680 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1681 bus_dmamap_unload(sc->rl_tag, 1682 sc->rl_cdata.rl_tx_dmamap[i]); 1683 bus_dmamap_destroy(sc->rl_tag, 1684 sc->rl_cdata.rl_tx_dmamap[i]); 1685 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1686 sc->rl_cdata.rl_tx_chain[i] = NULL; 1687 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1688 0x0000000); 1689 } 1690 } 1691 } 1692 1693 /* 1694 * Stop all chip I/O so that the kernel's probe routines don't 1695 * get confused by errant DMAs when rebooting. 1696 */ 1697 static void 1698 rl_shutdown(device_t dev) 1699 { 1700 struct rl_softc *sc; 1701 1702 sc = device_get_softc(dev); 1703 1704 rl_stop(sc); 1705 } 1706 1707 /* 1708 * Device suspend routine. Stop the interface and save some PCI 1709 * settings in case the BIOS doesn't restore them properly on 1710 * resume. 1711 */ 1712 static int 1713 rl_suspend(device_t dev) 1714 { 1715 struct rl_softc *sc = device_get_softc(dev); 1716 int i; 1717 1718 rl_stop(sc); 1719 1720 for (i = 0; i < 5; i++) 1721 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1722 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1723 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1724 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1725 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1726 1727 sc->suspended = 1; 1728 1729 return (0); 1730 } 1731 1732 /* 1733 * Device resume routine. Restore some PCI settings in case the BIOS 1734 * doesn't, re-enable busmastering, and restart the interface if 1735 * appropriate. 1736 */ 1737 static int rl_resume(device_t dev) 1738 { 1739 struct rl_softc *sc = device_get_softc(dev); 1740 struct ifnet *ifp = &sc->arpcom.ac_if; 1741 int i; 1742 1743 /* better way to do this? */ 1744 for (i = 0; i < 5; i++) 1745 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1746 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1747 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1748 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1749 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1750 1751 /* reenable busmastering */ 1752 pci_enable_busmaster(dev); 1753 pci_enable_io(dev, RL_RES); 1754 1755 /* reinitialize interface if necessary */ 1756 if (ifp->if_flags & IFF_UP) 1757 rl_init(sc); 1758 1759 sc->suspended = 0; 1760 1761 return (0); 1762 } 1763