1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.22 2005/05/25 01:44:28 dillon Exp $ 34 */ 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 50 * probably the worst PCI ethernet controller ever made, with the possible 51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 52 * DMA, but it has a terrible interface that nullifies any performance 53 * gains that bus-master DMA usually offers. 54 * 55 * For transmission, the chip offers a series of four TX descriptor 56 * registers. Each transmit frame must be in a contiguous buffer, aligned 57 * on a longword (32-bit) boundary. This means we almost always have to 58 * do mbuf copies in order to transmit a frame, except in the unlikely 59 * case where a) the packet fits into a single mbuf, and b) the packet 60 * is 32-bit aligned within the mbuf's data area. The presence of only 61 * four descriptor registers means that we can never have more than four 62 * packets queued for transmission at any one time. 63 * 64 * Reception is not much better. The driver has to allocate a single large 65 * buffer area (up to 64K in size) into which the chip will DMA received 66 * frames. Because we don't know where within this region received packets 67 * will begin or end, we have no choice but to copy data from the buffer 68 * area into mbufs in order to pass the packets up to the higher protocol 69 * levels. 70 * 71 * It's impossible given this rotten design to really achieve decent 72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 73 * some equally overmuscled CPU to drive it. 74 * 75 * On the bright side, the 8139 does have a built-in PHY, although 76 * rather than using an MDIO serial interface like most other NICs, the 77 * PHY registers are directly accessible through the 8139's register 78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 79 * filter. 80 * 81 * The 8129 chip is an older version of the 8139 that uses an external PHY 82 * chip. The 8129 has a serial MDIO interface for accessing the MII where 83 * the 8139 lets you directly access the on-board PHY registers. We need 84 * to select which interface to use depending on the chip type. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/module.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/ifq_var.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus_pio.h> 107 #include <machine/bus_memio.h> 108 #include <machine/bus.h> 109 #include <machine/resource.h> 110 #include <sys/bus.h> 111 #include <sys/rman.h> 112 113 #include <dev/netif/mii_layer/mii.h> 114 #include <dev/netif/mii_layer/miivar.h> 115 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 /* "controller miibus0" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 /* 123 * Default to using PIO access for this driver. On SMP systems, 124 * there appear to be problems with memory mapped mode: it looks like 125 * doing too many memory mapped access back to back in rapid succession 126 * can hang the bus. I'm inclined to blame this on crummy design/construction 127 * on the part of RealTek. Memory mapped mode does appear to work on 128 * uniprocessor systems though. 129 */ 130 #define RL_USEIOSPACE 131 132 #include <dev/netif/rl/if_rlreg.h> 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct rl_type { 138 uint16_t rl_vid; 139 uint16_t rl_did; 140 const char *rl_name; 141 } rl_devs[] = { 142 { RT_VENDORID, RT_DEVICEID_8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { RT_VENDORID, RT_DEVICEID_8138, 147 "RealTek 8139 10/100BaseTX CardBus" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 157 "D-Link DFE-690TX 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 159 "Nortel Networks 10/100BaseTX" }, 160 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 161 "Peppercon AG ROL/F" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 163 "Corega FEther CB-TXD" }, 164 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 165 "Corega FEtherII CB-TXD" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 167 "Planex FNW-3800-TX" }, 168 { 0, 0, NULL } 169 }; 170 171 static int rl_probe(device_t); 172 static int rl_attach(device_t); 173 static int rl_detach(device_t); 174 175 static int rl_encap(struct rl_softc *, struct mbuf * ); 176 177 static void rl_rxeof(struct rl_softc *); 178 static void rl_txeof(struct rl_softc *); 179 static void rl_intr(void *); 180 static void rl_tick(void *); 181 static void rl_start(struct ifnet *); 182 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 183 static void rl_init(void *); 184 static void rl_stop (struct rl_softc *); 185 static void rl_watchdog(struct ifnet *); 186 static int rl_suspend(device_t); 187 static int rl_resume(device_t); 188 static void rl_shutdown(device_t); 189 static int rl_ifmedia_upd(struct ifnet *); 190 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 192 static void rl_eeprom_putbyte(struct rl_softc *, int); 193 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 194 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 195 static void rl_mii_sync(struct rl_softc *); 196 static void rl_mii_send(struct rl_softc *, uint32_t, int); 197 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 198 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 199 200 static int rl_miibus_readreg(device_t, int, int); 201 static int rl_miibus_writereg(device_t, int, int, int); 202 static void rl_miibus_statchg(device_t); 203 204 static void rl_setmulti(struct rl_softc *); 205 static void rl_reset(struct rl_softc *); 206 static void rl_list_tx_init(struct rl_softc *); 207 208 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 209 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 210 #ifdef DEVICE_POLLING 211 static poll_handler_t rl_poll; 212 #endif 213 214 #ifdef RL_USEIOSPACE 215 #define RL_RES SYS_RES_IOPORT 216 #define RL_RID RL_PCI_LOIO 217 #else 218 #define RL_RES SYS_RES_MEMORY 219 #define RL_RID RL_PCI_LOMEM 220 #endif 221 222 static device_method_t rl_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_probe, rl_probe), 225 DEVMETHOD(device_attach, rl_attach), 226 DEVMETHOD(device_detach, rl_detach), 227 DEVMETHOD(device_suspend, rl_suspend), 228 DEVMETHOD(device_resume, rl_resume), 229 DEVMETHOD(device_shutdown, rl_shutdown), 230 231 /* bus interface */ 232 DEVMETHOD(bus_print_child, bus_generic_print_child), 233 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 234 235 /* MII interface */ 236 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 237 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 238 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 239 240 { 0, 0 } 241 }; 242 243 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 244 static devclass_t rl_devclass; 245 246 DECLARE_DUMMY_MODULE(if_rl); 247 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 248 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 249 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 250 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 251 252 #define EE_SET(x) \ 253 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 254 255 #define EE_CLR(x) \ 256 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 257 258 static void 259 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 260 { 261 struct rl_softc *sc = arg; 262 263 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 264 } 265 266 static void 267 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 268 { 269 struct rl_softc *sc = arg; 270 271 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 272 } 273 274 /* 275 * Send a read command and address to the EEPROM, check for ACK. 276 */ 277 static void 278 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 279 { 280 int d, i; 281 282 d = addr | sc->rl_eecmd_read; 283 284 /* 285 * Feed in each bit and strobe the clock. 286 */ 287 for (i = 0x400; i; i >>= 1) { 288 if (d & i) 289 EE_SET(RL_EE_DATAIN); 290 else 291 EE_CLR(RL_EE_DATAIN); 292 DELAY(100); 293 EE_SET(RL_EE_CLK); 294 DELAY(150); 295 EE_CLR(RL_EE_CLK); 296 DELAY(100); 297 } 298 } 299 300 /* 301 * Read a word of data stored in the EEPROM at address 'addr.' 302 */ 303 static void 304 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 305 { 306 int i; 307 uint16_t word = 0; 308 309 /* Enter EEPROM access mode. */ 310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 311 312 /* 313 * Send address of word we want to read. 314 */ 315 rl_eeprom_putbyte(sc, addr); 316 317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 318 319 /* 320 * Start reading bits from EEPROM. 321 */ 322 for (i = 0x8000; i; i >>= 1) { 323 EE_SET(RL_EE_CLK); 324 DELAY(100); 325 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 326 word |= i; 327 EE_CLR(RL_EE_CLK); 328 DELAY(100); 329 } 330 331 /* Turn off EEPROM access mode. */ 332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 333 334 *dest = word; 335 } 336 337 /* 338 * Read a sequence of words from the EEPROM. 339 */ 340 static void 341 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 342 { 343 int i; 344 u_int16_t word = 0, *ptr; 345 346 for (i = 0; i < cnt; i++) { 347 rl_eeprom_getword(sc, off + i, &word); 348 ptr = (u_int16_t *)(dest + (i * 2)); 349 if (swap) 350 *ptr = ntohs(word); 351 else 352 *ptr = word; 353 } 354 } 355 356 357 /* 358 * MII access routines are provided for the 8129, which 359 * doesn't have a built-in PHY. For the 8139, we fake things 360 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 361 * direct access PHY registers. 362 */ 363 #define MII_SET(x) \ 364 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 365 366 #define MII_CLR(x) \ 367 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 368 369 /* 370 * Sync the PHYs by setting data bit and strobing the clock 32 times. 371 */ 372 static void 373 rl_mii_sync(struct rl_softc *sc) 374 { 375 int i; 376 377 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 378 379 for (i = 0; i < 32; i++) { 380 MII_SET(RL_MII_CLK); 381 DELAY(1); 382 MII_CLR(RL_MII_CLK); 383 DELAY(1); 384 } 385 } 386 387 /* 388 * Clock a series of bits through the MII. 389 */ 390 static void 391 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 392 { 393 int i; 394 395 MII_CLR(RL_MII_CLK); 396 397 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 398 if (bits & i) 399 MII_SET(RL_MII_DATAOUT); 400 else 401 MII_CLR(RL_MII_DATAOUT); 402 DELAY(1); 403 MII_CLR(RL_MII_CLK); 404 DELAY(1); 405 MII_SET(RL_MII_CLK); 406 } 407 } 408 409 /* 410 * Read an PHY register through the MII. 411 */ 412 static int 413 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 414 { 415 int i, ack, s; 416 417 s = splimp(); 418 419 /* 420 * Set up frame for RX. 421 */ 422 frame->mii_stdelim = RL_MII_STARTDELIM; 423 frame->mii_opcode = RL_MII_READOP; 424 frame->mii_turnaround = 0; 425 frame->mii_data = 0; 426 427 CSR_WRITE_2(sc, RL_MII, 0); 428 429 /* 430 * Turn on data xmit. 431 */ 432 MII_SET(RL_MII_DIR); 433 434 rl_mii_sync(sc); 435 436 /* 437 * Send command/address info. 438 */ 439 rl_mii_send(sc, frame->mii_stdelim, 2); 440 rl_mii_send(sc, frame->mii_opcode, 2); 441 rl_mii_send(sc, frame->mii_phyaddr, 5); 442 rl_mii_send(sc, frame->mii_regaddr, 5); 443 444 /* Idle bit */ 445 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 446 DELAY(1); 447 MII_SET(RL_MII_CLK); 448 DELAY(1); 449 450 /* Turn off xmit. */ 451 MII_CLR(RL_MII_DIR); 452 453 /* Check for ack */ 454 MII_CLR(RL_MII_CLK); 455 DELAY(1); 456 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 457 MII_SET(RL_MII_CLK); 458 DELAY(1); 459 460 /* 461 * Now try reading data bits. If the ack failed, we still 462 * need to clock through 16 cycles to keep the PHY(s) in sync. 463 */ 464 if (ack) { 465 for(i = 0; i < 16; i++) { 466 MII_CLR(RL_MII_CLK); 467 DELAY(1); 468 MII_SET(RL_MII_CLK); 469 DELAY(1); 470 } 471 } else { 472 for (i = 0x8000; i; i >>= 1) { 473 MII_CLR(RL_MII_CLK); 474 DELAY(1); 475 if (!ack) { 476 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 477 frame->mii_data |= i; 478 DELAY(1); 479 } 480 MII_SET(RL_MII_CLK); 481 DELAY(1); 482 } 483 } 484 485 MII_CLR(RL_MII_CLK); 486 DELAY(1); 487 MII_SET(RL_MII_CLK); 488 DELAY(1); 489 490 splx(s); 491 492 return(ack ? 1 : 0); 493 } 494 495 /* 496 * Write to a PHY register through the MII. 497 */ 498 static int 499 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 500 { 501 int s; 502 503 s = splimp(); 504 /* 505 * Set up frame for TX. 506 */ 507 508 frame->mii_stdelim = RL_MII_STARTDELIM; 509 frame->mii_opcode = RL_MII_WRITEOP; 510 frame->mii_turnaround = RL_MII_TURNAROUND; 511 512 /* 513 * Turn on data output. 514 */ 515 MII_SET(RL_MII_DIR); 516 517 rl_mii_sync(sc); 518 519 rl_mii_send(sc, frame->mii_stdelim, 2); 520 rl_mii_send(sc, frame->mii_opcode, 2); 521 rl_mii_send(sc, frame->mii_phyaddr, 5); 522 rl_mii_send(sc, frame->mii_regaddr, 5); 523 rl_mii_send(sc, frame->mii_turnaround, 2); 524 rl_mii_send(sc, frame->mii_data, 16); 525 526 /* Idle bit. */ 527 MII_SET(RL_MII_CLK); 528 DELAY(1); 529 MII_CLR(RL_MII_CLK); 530 DELAY(1); 531 532 /* 533 * Turn off xmit. 534 */ 535 MII_CLR(RL_MII_DIR); 536 537 splx(s); 538 539 return(0); 540 } 541 542 static int 543 rl_miibus_readreg(device_t dev, int phy, int reg) 544 { 545 struct rl_softc *sc; 546 struct rl_mii_frame frame; 547 uint16_t rval = 0; 548 uint16_t rl8139_reg = 0; 549 550 sc = device_get_softc(dev); 551 552 if (sc->rl_type == RL_8139) { 553 /* Pretend the internal PHY is only at address 0 */ 554 if (phy) 555 return(0); 556 switch (reg) { 557 case MII_BMCR: 558 rl8139_reg = RL_BMCR; 559 break; 560 case MII_BMSR: 561 rl8139_reg = RL_BMSR; 562 break; 563 case MII_ANAR: 564 rl8139_reg = RL_ANAR; 565 break; 566 case MII_ANER: 567 rl8139_reg = RL_ANER; 568 break; 569 case MII_ANLPAR: 570 rl8139_reg = RL_LPAR; 571 break; 572 case MII_PHYIDR1: 573 case MII_PHYIDR2: 574 return(0); 575 break; 576 /* 577 * Allow the rlphy driver to read the media status 578 * register. If we have a link partner which does not 579 * support NWAY, this is the register which will tell 580 * us the results of parallel detection. 581 */ 582 case RL_MEDIASTAT: 583 rval = CSR_READ_1(sc, RL_MEDIASTAT); 584 return(rval); 585 default: 586 device_printf(dev, "bad phy register\n"); 587 return(0); 588 } 589 rval = CSR_READ_2(sc, rl8139_reg); 590 return(rval); 591 } 592 593 bzero(&frame, sizeof(frame)); 594 595 frame.mii_phyaddr = phy; 596 frame.mii_regaddr = reg; 597 rl_mii_readreg(sc, &frame); 598 599 return(frame.mii_data); 600 } 601 602 static int 603 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 604 { 605 struct rl_softc *sc; 606 struct rl_mii_frame frame; 607 u_int16_t rl8139_reg = 0; 608 609 sc = device_get_softc(dev); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) 614 return(0); 615 switch (reg) { 616 case MII_BMCR: 617 rl8139_reg = RL_BMCR; 618 break; 619 case MII_BMSR: 620 rl8139_reg = RL_BMSR; 621 break; 622 case MII_ANAR: 623 rl8139_reg = RL_ANAR; 624 break; 625 case MII_ANER: 626 rl8139_reg = RL_ANER; 627 break; 628 case MII_ANLPAR: 629 rl8139_reg = RL_LPAR; 630 break; 631 case MII_PHYIDR1: 632 case MII_PHYIDR2: 633 return(0); 634 default: 635 device_printf(dev, "bad phy register\n"); 636 return(0); 637 } 638 CSR_WRITE_2(sc, rl8139_reg, data); 639 return(0); 640 } 641 642 bzero(&frame, sizeof(frame)); 643 644 frame.mii_phyaddr = phy; 645 frame.mii_regaddr = reg; 646 frame.mii_data = data; 647 648 rl_mii_writereg(sc, &frame); 649 650 return(0); 651 } 652 653 static void 654 rl_miibus_statchg(device_t dev) 655 { 656 } 657 658 /* 659 * Program the 64-bit multicast hash filter. 660 */ 661 static void 662 rl_setmulti(struct rl_softc *sc) 663 { 664 struct ifnet *ifp; 665 int h = 0; 666 uint32_t hashes[2] = { 0, 0 }; 667 struct ifmultiaddr *ifma; 668 uint32_t rxfilt; 669 int mcnt = 0; 670 671 ifp = &sc->arpcom.ac_if; 672 673 rxfilt = CSR_READ_4(sc, RL_RXCFG); 674 675 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 676 rxfilt |= RL_RXCFG_RX_MULTI; 677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 678 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 679 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 680 return; 681 } 682 683 /* first, zot all the existing hash bits */ 684 CSR_WRITE_4(sc, RL_MAR0, 0); 685 CSR_WRITE_4(sc, RL_MAR4, 0); 686 687 /* now program new ones */ 688 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 689 if (ifma->ifma_addr->sa_family != AF_LINK) 690 continue; 691 h = ether_crc32_be( 692 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 693 ETHER_ADDR_LEN >> 26); 694 if (h < 32) 695 hashes[0] |= (1 << h); 696 else 697 hashes[1] |= (1 << (h - 32)); 698 mcnt++; 699 } 700 701 if (mcnt) 702 rxfilt |= RL_RXCFG_RX_MULTI; 703 else 704 rxfilt &= ~RL_RXCFG_RX_MULTI; 705 706 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 707 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 708 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 709 } 710 711 static void 712 rl_reset(struct rl_softc *sc) 713 { 714 int i; 715 716 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 717 718 for (i = 0; i < RL_TIMEOUT; i++) { 719 DELAY(10); 720 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 721 break; 722 } 723 if (i == RL_TIMEOUT) 724 device_printf(sc->rl_dev, "reset never completed!\n"); 725 } 726 727 /* 728 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 729 * IDs against our list and return a device name if we find a match. 730 * 731 * Return with a value < 0 to give re(4) a change to attach. 732 */ 733 static int 734 rl_probe(device_t dev) 735 { 736 struct rl_type *t; 737 uint16_t product = pci_get_device(dev); 738 uint16_t vendor = pci_get_vendor(dev); 739 740 for (t = rl_devs; t->rl_name != NULL; t++) { 741 if (vendor == t->rl_vid && product == t->rl_did) { 742 device_set_desc(dev, t->rl_name); 743 return(-100); 744 } 745 } 746 747 return(ENXIO); 748 } 749 750 /* 751 * Attach the interface. Allocate softc structures, do ifmedia 752 * setup and ethernet/BPF attach. 753 */ 754 static int 755 rl_attach(device_t dev) 756 { 757 uint8_t eaddr[ETHER_ADDR_LEN]; 758 uint16_t as[3]; 759 struct rl_softc *sc; 760 struct ifnet *ifp; 761 uint16_t rl_did = 0; 762 int error = 0, rid, i; 763 764 sc = device_get_softc(dev); 765 sc->rl_dev = dev; 766 767 /* 768 * Handle power management nonsense. 769 */ 770 771 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 772 uint32_t iobase, membase, irq; 773 774 /* Save important PCI config data. */ 775 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 776 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 777 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 778 779 /* Reset the power state. */ 780 device_printf(dev, "chip is is in D%d power mode " 781 "-- setting to D0\n", pci_get_powerstate(dev)); 782 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 783 784 /* Restore PCI config data. */ 785 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 786 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 787 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 788 } 789 790 /* 791 * Map control/status registers. 792 */ 793 pci_enable_busmaster(dev); 794 pci_enable_io(dev, RL_RES); 795 796 rid = RL_RID; 797 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 798 799 if (sc->rl_res == NULL) { 800 device_printf(dev, "couldn't map ports/memory\n"); 801 error = ENXIO; 802 goto fail; 803 } 804 805 sc->rl_btag = rman_get_bustag(sc->rl_res); 806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 807 808 rid = 0; 809 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 810 RF_SHAREABLE | RF_ACTIVE); 811 812 if (sc->rl_irq == NULL) { 813 device_printf(dev, "couldn't map interrupt\n"); 814 error = ENXIO; 815 goto fail; 816 } 817 818 callout_init(&sc->rl_stat_timer); 819 820 /* Reset the adapter. */ 821 rl_reset(sc); 822 823 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 824 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 825 if (rl_did != 0x8129) 826 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 827 828 /* 829 * Get station address from the EEPROM. 830 */ 831 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 832 for (i = 0; i < 3; i++) { 833 eaddr[(i * 2) + 0] = as[i] & 0xff; 834 eaddr[(i * 2) + 1] = as[i] >> 8; 835 } 836 837 /* 838 * Now read the exact device type from the EEPROM to find 839 * out if it's an 8129 or 8139. 840 */ 841 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 842 843 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 844 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 845 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 || 846 rl_did == DLINK_DEVICEID_690TXD || 847 rl_did == COREGA_DEVICEID_FETHERCBTXD || 848 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 849 rl_did == PLANEX_DEVICEID_FNW3800TX) 850 sc->rl_type = RL_8139; 851 else if (rl_did == RT_DEVICEID_8129) 852 sc->rl_type = RL_8129; 853 else { 854 device_printf(dev, "unknown device ID: %x\n", rl_did); 855 error = ENXIO; 856 goto fail; 857 } 858 859 #define RL_NSEG_NEW 32 860 error = bus_dma_tag_create(NULL, /* parent */ 861 1, 0, /* alignment, boundary */ 862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 863 BUS_SPACE_MAXADDR, /* highaddr */ 864 NULL, NULL, /* filter, filterarg */ 865 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 866 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 867 BUS_DMA_ALLOCNOW, /* flags */ 868 &sc->rl_parent_tag); 869 870 if (error) { 871 device_printf(dev, "can't create parent tag\n"); 872 goto fail; 873 } 874 875 /* 876 * Now allocate a tag for the DMA descriptor lists. 877 * All of our lists are allocated as a contiguous block 878 * of memory. 879 */ 880 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 881 1, 0, /* alignment, boundary */ 882 BUS_SPACE_MAXADDR, /* lowaddr */ 883 BUS_SPACE_MAXADDR, /* highaddr */ 884 NULL, NULL, /* filter, filterarg */ 885 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */ 886 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 887 0, /* flags */ 888 &sc->rl_tag); 889 890 if (error) { 891 device_printf(dev, "can't create RX tag\n"); 892 goto fail; 893 } 894 895 /* 896 * Now allocate a chunk of DMA-able memory based on the tag 897 * we just created. 898 */ 899 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf, 900 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap); 901 902 if (error) { 903 device_printf(dev, "can't allocate RX memory!\n"); 904 error = ENXIO; 905 goto fail; 906 } 907 908 /* Leave a few bytes before the start of the RX ring buffer. */ 909 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 910 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 911 912 /* Do MII setup */ 913 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 914 rl_ifmedia_sts)) { 915 device_printf(dev, "MII without any phy!\n"); 916 error = ENXIO; 917 goto fail; 918 } 919 920 ifp = &sc->arpcom.ac_if; 921 ifp->if_softc = sc; 922 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 923 ifp->if_mtu = ETHERMTU; 924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 925 ifp->if_ioctl = rl_ioctl; 926 ifp->if_start = rl_start; 927 ifp->if_watchdog = rl_watchdog; 928 ifp->if_init = rl_init; 929 ifp->if_baudrate = 10000000; 930 ifp->if_capabilities = IFCAP_VLAN_MTU; 931 #ifdef DEVICE_POLLING 932 ifp->if_poll = rl_poll; 933 #endif 934 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 935 ifq_set_ready(&ifp->if_snd); 936 937 /* 938 * Call MI attach routine. 939 */ 940 ether_ifattach(ifp, eaddr); 941 942 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr, 943 sc, &sc->rl_intrhand, NULL); 944 945 if (error) { 946 device_printf(dev, "couldn't set up irq\n"); 947 ether_ifdetach(ifp); 948 goto fail; 949 } 950 951 return(0); 952 953 fail: 954 rl_detach(dev); 955 return(error); 956 } 957 958 static int 959 rl_detach(device_t dev) 960 { 961 struct rl_softc *sc; 962 struct ifnet *ifp; 963 int s; 964 965 sc = device_get_softc(dev); 966 ifp = &sc->arpcom.ac_if; 967 968 s = splimp(); 969 970 if (device_is_attached(dev)) { 971 rl_stop(sc); 972 ether_ifdetach(ifp); 973 } 974 975 if (sc->rl_miibus) 976 device_delete_child(dev, sc->rl_miibus); 977 bus_generic_detach(dev); 978 979 if (sc->rl_intrhand) 980 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 981 splx(s); 982 983 if (sc->rl_irq) 984 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 985 if (sc->rl_res) 986 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 987 988 if (sc->rl_cdata.rl_rx_buf) { 989 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 990 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 991 sc->rl_cdata.rl_rx_dmamap); 992 } 993 if (sc->rl_tag) 994 bus_dma_tag_destroy(sc->rl_tag); 995 if (sc->rl_parent_tag) 996 bus_dma_tag_destroy(sc->rl_parent_tag); 997 998 return(0); 999 } 1000 1001 /* 1002 * Initialize the transmit descriptors. 1003 */ 1004 static void 1005 rl_list_tx_init(struct rl_softc *sc) 1006 { 1007 struct rl_chain_data *cd; 1008 int i; 1009 1010 cd = &sc->rl_cdata; 1011 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1012 cd->rl_tx_chain[i] = NULL; 1013 CSR_WRITE_4(sc, 1014 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1015 } 1016 1017 sc->rl_cdata.cur_tx = 0; 1018 sc->rl_cdata.last_tx = 0; 1019 } 1020 1021 /* 1022 * A frame has been uploaded: pass the resulting mbuf chain up to 1023 * the higher level protocols. 1024 * 1025 * You know there's something wrong with a PCI bus-master chip design 1026 * when you have to use m_devget(). 1027 * 1028 * The receive operation is badly documented in the datasheet, so I'll 1029 * attempt to document it here. The driver provides a buffer area and 1030 * places its base address in the RX buffer start address register. 1031 * The chip then begins copying frames into the RX buffer. Each frame 1032 * is preceded by a 32-bit RX status word which specifies the length 1033 * of the frame and certain other status bits. Each frame (starting with 1034 * the status word) is also 32-bit aligned. The frame length is in the 1035 * first 16 bits of the status word; the lower 15 bits correspond with 1036 * the 'rx status register' mentioned in the datasheet. 1037 * 1038 * Note: to make the Alpha happy, the frame payload needs to be aligned 1039 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1040 * the ring buffer starting at an address two bytes before the actual 1041 * data location. We can then shave off the first two bytes using m_adj(). 1042 * The reason we do this is because m_devget() doesn't let us specify an 1043 * offset into the mbuf storage space, so we have to artificially create 1044 * one. The ring is allocated in such a way that there are a few unused 1045 * bytes of space preceecing it so that it will be safe for us to do the 1046 * 2-byte backstep even if reading from the ring at offset 0. 1047 */ 1048 static void 1049 rl_rxeof(struct rl_softc *sc) 1050 { 1051 struct mbuf *m; 1052 struct ifnet *ifp; 1053 int total_len = 0; 1054 uint32_t rxstat; 1055 caddr_t rxbufpos; 1056 int wrap = 0; 1057 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1062 BUS_DMASYNC_POSTREAD); 1063 1064 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1065 1066 /* Do not try to read past this point. */ 1067 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1068 1069 if (limit < cur_rx) 1070 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1071 else 1072 max_bytes = limit - cur_rx; 1073 1074 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1075 #ifdef DEVICE_POLLING 1076 if (ifp->if_flags & IFF_POLLING) { 1077 if (sc->rxcycles <= 0) 1078 break; 1079 sc->rxcycles--; 1080 } 1081 #endif /* DEVICE_POLLING */ 1082 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1083 rxstat = le32toh(*(uint32_t *)rxbufpos); 1084 1085 /* 1086 * Here's a totally undocumented fact for you. When the 1087 * RealTek chip is in the process of copying a packet into 1088 * RAM for you, the length will be 0xfff0. If you spot a 1089 * packet header with this value, you need to stop. The 1090 * datasheet makes absolutely no mention of this and 1091 * RealTek should be shot for this. 1092 */ 1093 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1094 break; 1095 1096 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1097 ifp->if_ierrors++; 1098 rl_init(sc); 1099 return; 1100 } 1101 1102 /* No errors; receive the packet. */ 1103 total_len = rxstat >> 16; 1104 rx_bytes += total_len + 4; 1105 1106 /* 1107 * XXX The RealTek chip includes the CRC with every 1108 * received frame, and there's no way to turn this 1109 * behavior off (at least, I can't find anything in 1110 * the manual that explains how to do it) so we have 1111 * to trim off the CRC manually. 1112 */ 1113 total_len -= ETHER_CRC_LEN; 1114 1115 /* 1116 * Avoid trying to read more bytes than we know 1117 * the chip has prepared for us. 1118 */ 1119 if (rx_bytes > max_bytes) 1120 break; 1121 1122 rxbufpos = sc->rl_cdata.rl_rx_buf + 1123 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1124 1125 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1126 rxbufpos = sc->rl_cdata.rl_rx_buf; 1127 1128 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1129 1130 if (total_len > wrap) { 1131 /* 1132 * Fool m_devget() into thinking we want to copy 1133 * the whole buffer so we don't end up fragmenting 1134 * the data. 1135 */ 1136 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1137 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1138 if (m == NULL) { 1139 ifp->if_ierrors++; 1140 } else { 1141 m_adj(m, RL_ETHER_ALIGN); 1142 m_copyback(m, wrap, total_len - wrap, 1143 sc->rl_cdata.rl_rx_buf); 1144 } 1145 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1146 } else { 1147 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1148 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1149 if (m == NULL) { 1150 ifp->if_ierrors++; 1151 } else 1152 m_adj(m, RL_ETHER_ALIGN); 1153 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1154 } 1155 1156 /* 1157 * Round up to 32-bit boundary. 1158 */ 1159 cur_rx = (cur_rx + 3) & ~3; 1160 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1161 1162 if (m == NULL) 1163 continue; 1164 1165 ifp->if_ipackets++; 1166 1167 (*ifp->if_input)(ifp, m); 1168 } 1169 } 1170 1171 /* 1172 * A frame was downloaded to the chip. It's safe for us to clean up 1173 * the list buffers. 1174 */ 1175 static void 1176 rl_txeof(struct rl_softc *sc) 1177 { 1178 struct ifnet *ifp; 1179 uint32_t txstat; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 1183 /* 1184 * Go through our tx list and free mbufs for those 1185 * frames that have been uploaded. 1186 */ 1187 do { 1188 if (RL_LAST_TXMBUF(sc) == NULL) 1189 break; 1190 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1191 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1192 RL_TXSTAT_TXABRT)) == 0) 1193 break; 1194 1195 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1196 1197 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1198 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1199 m_freem(RL_LAST_TXMBUF(sc)); 1200 RL_LAST_TXMBUF(sc) = NULL; 1201 RL_INC(sc->rl_cdata.last_tx); 1202 1203 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1204 sc->rl_txthresh += 32; 1205 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1206 sc->rl_txthresh = RL_TX_THRESH_MAX; 1207 } 1208 1209 if (txstat & RL_TXSTAT_TX_OK) { 1210 ifp->if_opackets++; 1211 } else { 1212 ifp->if_oerrors++; 1213 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1214 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1215 } 1216 ifp->if_flags &= ~IFF_OACTIVE; 1217 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1218 1219 if (RL_LAST_TXMBUF(sc) == NULL) 1220 ifp->if_timer = 0; 1221 else if (ifp->if_timer == 0) 1222 ifp->if_timer = 5; 1223 } 1224 1225 static void 1226 rl_tick(void *xsc) 1227 { 1228 struct rl_softc *sc = xsc; 1229 struct mii_data *mii; 1230 int s; 1231 1232 s = splimp(); 1233 1234 mii = device_get_softc(sc->rl_miibus); 1235 mii_tick(mii); 1236 1237 splx(s); 1238 1239 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1240 } 1241 1242 #ifdef DEVICE_POLLING 1243 1244 static void 1245 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1246 { 1247 struct rl_softc *sc = ifp->if_softc; 1248 1249 switch(cmd) { 1250 case POLL_REGISTER: 1251 /* disable interrupts */ 1252 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1253 break; 1254 case POLL_DEREGISTER: 1255 /* enable interrupts */ 1256 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1257 break; 1258 default: 1259 sc->rxcycles = count; 1260 rl_rxeof(sc); 1261 rl_txeof(sc); 1262 if (!ifq_is_empty(&ifp->if_snd)) 1263 rl_start(ifp); 1264 1265 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1266 uint16_t status; 1267 1268 status = CSR_READ_2(sc, RL_ISR); 1269 if (status == 0xffff) 1270 return; 1271 if (status) 1272 CSR_WRITE_2(sc, RL_ISR, status); 1273 1274 /* 1275 * XXX check behaviour on receiver stalls. 1276 */ 1277 1278 if (status & RL_ISR_SYSTEM_ERR) { 1279 rl_reset(sc); 1280 rl_init(sc); 1281 } 1282 } 1283 break; 1284 } 1285 } 1286 #endif /* DEVICE_POLLING */ 1287 1288 static void 1289 rl_intr(void *arg) 1290 { 1291 struct rl_softc *sc; 1292 struct ifnet *ifp; 1293 uint16_t status; 1294 1295 sc = arg; 1296 1297 if (sc->suspended) 1298 return; 1299 1300 ifp = &sc->arpcom.ac_if; 1301 1302 for (;;) { 1303 status = CSR_READ_2(sc, RL_ISR); 1304 /* If the card has gone away, the read returns 0xffff. */ 1305 if (status == 0xffff) 1306 break; 1307 1308 if (status != 0) 1309 CSR_WRITE_2(sc, RL_ISR, status); 1310 1311 if ((status & RL_INTRS) == 0) 1312 break; 1313 1314 if (status & RL_ISR_RX_OK) 1315 rl_rxeof(sc); 1316 1317 if (status & RL_ISR_RX_ERR) 1318 rl_rxeof(sc); 1319 1320 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1321 rl_txeof(sc); 1322 1323 if (status & RL_ISR_SYSTEM_ERR) { 1324 rl_reset(sc); 1325 rl_init(sc); 1326 } 1327 1328 } 1329 1330 if (!ifq_is_empty(&ifp->if_snd)) 1331 rl_start(ifp); 1332 } 1333 1334 /* 1335 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1336 * pointers to the fragment pointers. 1337 */ 1338 static int 1339 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1340 { 1341 struct mbuf *m_new = NULL; 1342 1343 /* 1344 * The RealTek is brain damaged and wants longword-aligned 1345 * TX buffers, plus we can only have one fragment buffer 1346 * per packet. We have to copy pretty much all the time. 1347 */ 1348 m_new = m_defrag(m_head, MB_DONTWAIT); 1349 1350 if (m_new == NULL) { 1351 m_freem(m_head); 1352 return(1); 1353 } 1354 m_head = m_new; 1355 1356 /* Pad frames to at least 60 bytes. */ 1357 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1358 /* 1359 * Make security concious people happy: zero out the 1360 * bytes in the pad area, since we don't know what 1361 * this mbuf cluster buffer's previous user might 1362 * have left in it. 1363 */ 1364 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1365 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1366 m_head->m_pkthdr.len += 1367 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1368 m_head->m_len = m_head->m_pkthdr.len; 1369 } 1370 1371 RL_CUR_TXMBUF(sc) = m_head; 1372 1373 return(0); 1374 } 1375 1376 /* 1377 * Main transmit routine. 1378 */ 1379 1380 static void 1381 rl_start(struct ifnet *ifp) 1382 { 1383 struct rl_softc *sc; 1384 struct mbuf *m_head = NULL; 1385 1386 sc = ifp->if_softc; 1387 1388 while(RL_CUR_TXMBUF(sc) == NULL) { 1389 m_head = ifq_dequeue(&ifp->if_snd); 1390 if (m_head == NULL) 1391 break; 1392 1393 if (rl_encap(sc, m_head)) 1394 break; 1395 1396 /* 1397 * If there's a BPF listener, bounce a copy of this frame 1398 * to him. 1399 */ 1400 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1401 1402 /* 1403 * Transmit the frame. 1404 */ 1405 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1406 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1407 mtod(RL_CUR_TXMBUF(sc), void *), 1408 RL_CUR_TXMBUF(sc)->m_pkthdr.len, 1409 rl_dma_map_txbuf, sc, 0); 1410 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1411 BUS_DMASYNC_PREREAD); 1412 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1413 RL_TXTHRESH(sc->rl_txthresh) | 1414 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1415 1416 RL_INC(sc->rl_cdata.cur_tx); 1417 1418 /* 1419 * Set a timeout in case the chip goes out to lunch. 1420 */ 1421 ifp->if_timer = 5; 1422 } 1423 1424 /* 1425 * We broke out of the loop because all our TX slots are 1426 * full. Mark the NIC as busy until it drains some of the 1427 * packets from the queue. 1428 */ 1429 if (RL_CUR_TXMBUF(sc) != NULL) 1430 ifp->if_flags |= IFF_OACTIVE; 1431 } 1432 1433 static void 1434 rl_init(void *xsc) 1435 { 1436 struct rl_softc *sc = xsc; 1437 struct ifnet *ifp = &sc->arpcom.ac_if; 1438 struct mii_data *mii; 1439 int s; 1440 uint32_t rxcfg = 0; 1441 1442 s = splimp(); 1443 1444 mii = device_get_softc(sc->rl_miibus); 1445 1446 /* 1447 * Cancel pending I/O and free all RX/TX buffers. 1448 */ 1449 rl_stop(sc); 1450 1451 /* 1452 * Init our MAC address. Even though the chipset documentation 1453 * doesn't mention it, we need to enter "Config register write enable" 1454 * mode to modify the ID registers. 1455 */ 1456 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1457 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1458 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1459 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1460 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1461 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1462 1463 /* Init the RX buffer pointer register. */ 1464 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1465 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, 1466 sc, 0); 1467 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1468 BUS_DMASYNC_PREWRITE); 1469 1470 /* Init TX descriptors. */ 1471 rl_list_tx_init(sc); 1472 1473 /* 1474 * Enable transmit and receive. 1475 */ 1476 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1477 1478 /* 1479 * Set the initial TX and RX configuration. 1480 */ 1481 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1482 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1483 1484 /* Set the individual bit to receive frames for this host only. */ 1485 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1486 rxcfg |= RL_RXCFG_RX_INDIV; 1487 1488 /* If we want promiscuous mode, set the allframes bit. */ 1489 if (ifp->if_flags & IFF_PROMISC) { 1490 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1491 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1492 } else { 1493 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1494 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1495 } 1496 1497 /* 1498 * Set capture broadcast bit to capture broadcast frames. 1499 */ 1500 if (ifp->if_flags & IFF_BROADCAST) { 1501 rxcfg |= RL_RXCFG_RX_BROAD; 1502 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1503 } else { 1504 rxcfg &= ~RL_RXCFG_RX_BROAD; 1505 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1506 } 1507 1508 /* 1509 * Program the multicast filter, if necessary. 1510 */ 1511 rl_setmulti(sc); 1512 1513 #ifdef DEVICE_POLLING 1514 /* 1515 * Only enable interrupts if we are polling, keep them off otherwise. 1516 */ 1517 if (ifp->if_flags & IFF_POLLING) 1518 CSR_WRITE_2(sc, RL_IMR, 0); 1519 else 1520 #endif /* DEVICE_POLLING */ 1521 /* 1522 * Enable interrupts. 1523 */ 1524 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1525 1526 /* Set initial TX threshold */ 1527 sc->rl_txthresh = RL_TX_THRESH_INIT; 1528 1529 /* Start RX/TX process. */ 1530 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1531 1532 /* Enable receiver and transmitter. */ 1533 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1534 1535 mii_mediachg(mii); 1536 1537 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1538 1539 ifp->if_flags |= IFF_RUNNING; 1540 ifp->if_flags &= ~IFF_OACTIVE; 1541 1542 splx(s); 1543 1544 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1545 } 1546 1547 /* 1548 * Set media options. 1549 */ 1550 static int 1551 rl_ifmedia_upd(struct ifnet *ifp) 1552 { 1553 struct rl_softc *sc; 1554 struct mii_data *mii; 1555 1556 sc = ifp->if_softc; 1557 mii = device_get_softc(sc->rl_miibus); 1558 mii_mediachg(mii); 1559 1560 return(0); 1561 } 1562 1563 /* 1564 * Report current media status. 1565 */ 1566 static void 1567 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1568 { 1569 struct rl_softc *sc = ifp->if_softc; 1570 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1571 1572 mii_pollstat(mii); 1573 ifmr->ifm_active = mii->mii_media_active; 1574 ifmr->ifm_status = mii->mii_media_status; 1575 } 1576 1577 static int 1578 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1579 { 1580 struct rl_softc *sc = ifp->if_softc; 1581 struct ifreq *ifr = (struct ifreq *) data; 1582 struct mii_data *mii; 1583 int s, error = 0; 1584 1585 s = splimp(); 1586 1587 switch (command) { 1588 case SIOCSIFFLAGS: 1589 if (ifp->if_flags & IFF_UP) { 1590 rl_init(sc); 1591 } else { 1592 if (ifp->if_flags & IFF_RUNNING) 1593 rl_stop(sc); 1594 } 1595 error = 0; 1596 break; 1597 case SIOCADDMULTI: 1598 case SIOCDELMULTI: 1599 rl_setmulti(sc); 1600 error = 0; 1601 break; 1602 case SIOCGIFMEDIA: 1603 case SIOCSIFMEDIA: 1604 mii = device_get_softc(sc->rl_miibus); 1605 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1606 break; 1607 case SIOCSIFCAP: 1608 break; 1609 default: 1610 error = ether_ioctl(ifp, command, data); 1611 break; 1612 } 1613 1614 splx(s); 1615 1616 return(error); 1617 } 1618 1619 static void 1620 rl_watchdog(struct ifnet *ifp) 1621 { 1622 struct rl_softc *sc = ifp->if_softc; 1623 int s; 1624 1625 s = splimp(); 1626 1627 device_printf(sc->rl_dev, "watchdog timeout\n"); 1628 ifp->if_oerrors++; 1629 1630 rl_txeof(sc); 1631 rl_rxeof(sc); 1632 rl_init(sc); 1633 1634 splx(s); 1635 } 1636 1637 /* 1638 * Stop the adapter and free any mbufs allocated to the 1639 * RX and TX lists. 1640 */ 1641 static void 1642 rl_stop(struct rl_softc *sc) 1643 { 1644 struct ifnet *ifp = &sc->arpcom.ac_if; 1645 int i; 1646 1647 ifp->if_timer = 0; 1648 1649 callout_stop(&sc->rl_stat_timer); 1650 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1651 1652 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1653 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1654 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1655 1656 /* 1657 * Free the TX list buffers. 1658 */ 1659 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1660 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1661 bus_dmamap_unload(sc->rl_tag, 1662 sc->rl_cdata.rl_tx_dmamap[i]); 1663 bus_dmamap_destroy(sc->rl_tag, 1664 sc->rl_cdata.rl_tx_dmamap[i]); 1665 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1666 sc->rl_cdata.rl_tx_chain[i] = NULL; 1667 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1668 0x0000000); 1669 } 1670 } 1671 } 1672 1673 /* 1674 * Stop all chip I/O so that the kernel's probe routines don't 1675 * get confused by errant DMAs when rebooting. 1676 */ 1677 static void 1678 rl_shutdown(device_t dev) 1679 { 1680 struct rl_softc *sc; 1681 1682 sc = device_get_softc(dev); 1683 1684 rl_stop(sc); 1685 } 1686 1687 /* 1688 * Device suspend routine. Stop the interface and save some PCI 1689 * settings in case the BIOS doesn't restore them properly on 1690 * resume. 1691 */ 1692 static int 1693 rl_suspend(device_t dev) 1694 { 1695 struct rl_softc *sc = device_get_softc(dev); 1696 int i; 1697 1698 rl_stop(sc); 1699 1700 for (i = 0; i < 5; i++) 1701 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1702 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1703 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1704 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1705 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1706 1707 sc->suspended = 1; 1708 1709 return (0); 1710 } 1711 1712 /* 1713 * Device resume routine. Restore some PCI settings in case the BIOS 1714 * doesn't, re-enable busmastering, and restart the interface if 1715 * appropriate. 1716 */ 1717 static int rl_resume(device_t dev) 1718 { 1719 struct rl_softc *sc = device_get_softc(dev); 1720 struct ifnet *ifp = &sc->arpcom.ac_if; 1721 int i; 1722 1723 /* better way to do this? */ 1724 for (i = 0; i < 5; i++) 1725 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1726 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1727 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1728 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1729 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1730 1731 /* reenable busmastering */ 1732 pci_enable_busmaster(dev); 1733 pci_enable_io(dev, RL_RES); 1734 1735 /* reinitialize interface if necessary */ 1736 if (ifp->if_flags & IFF_UP) 1737 rl_init(sc); 1738 1739 sc->suspended = 0; 1740 1741 return (0); 1742 } 1743