1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.29 2005/11/28 17:13:43 dillon Exp $ 34 */ 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 50 * probably the worst PCI ethernet controller ever made, with the possible 51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 52 * DMA, but it has a terrible interface that nullifies any performance 53 * gains that bus-master DMA usually offers. 54 * 55 * For transmission, the chip offers a series of four TX descriptor 56 * registers. Each transmit frame must be in a contiguous buffer, aligned 57 * on a longword (32-bit) boundary. This means we almost always have to 58 * do mbuf copies in order to transmit a frame, except in the unlikely 59 * case where a) the packet fits into a single mbuf, and b) the packet 60 * is 32-bit aligned within the mbuf's data area. The presence of only 61 * four descriptor registers means that we can never have more than four 62 * packets queued for transmission at any one time. 63 * 64 * Reception is not much better. The driver has to allocate a single large 65 * buffer area (up to 64K in size) into which the chip will DMA received 66 * frames. Because we don't know where within this region received packets 67 * will begin or end, we have no choice but to copy data from the buffer 68 * area into mbufs in order to pass the packets up to the higher protocol 69 * levels. 70 * 71 * It's impossible given this rotten design to really achieve decent 72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 73 * some equally overmuscled CPU to drive it. 74 * 75 * On the bright side, the 8139 does have a built-in PHY, although 76 * rather than using an MDIO serial interface like most other NICs, the 77 * PHY registers are directly accessible through the 8139's register 78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 79 * filter. 80 * 81 * The 8129 chip is an older version of the 8139 that uses an external PHY 82 * chip. The 8129 has a serial MDIO interface for accessing the MII where 83 * the 8139 lets you directly access the on-board PHY registers. We need 84 * to select which interface to use depending on the chip type. 85 */ 86 87 #include "opt_polling.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/module.h> 97 #include <sys/socket.h> 98 #include <sys/serialize.h> 99 #include <sys/thread2.h> 100 101 #include <net/if.h> 102 #include <net/ifq_var.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 108 #include <net/bpf.h> 109 110 #include <machine/bus_pio.h> 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <dev/netif/mii_layer/mii.h> 118 #include <dev/netif/mii_layer/miivar.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 /* "controller miibus0" required. See GENERIC if you get errors here. */ 124 #include "miibus_if.h" 125 126 /* 127 * Default to using PIO access for this driver. On SMP systems, 128 * there appear to be problems with memory mapped mode: it looks like 129 * doing too many memory mapped access back to back in rapid succession 130 * can hang the bus. I'm inclined to blame this on crummy design/construction 131 * on the part of RealTek. Memory mapped mode does appear to work on 132 * uniprocessor systems though. 133 */ 134 #define RL_USEIOSPACE 135 136 #include <dev/netif/rl/if_rlreg.h> 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct rl_type { 142 uint16_t rl_vid; 143 uint16_t rl_did; 144 const char *rl_name; 145 } rl_devs[] = { 146 { RT_VENDORID, RT_DEVICEID_8129, 147 "RealTek 8129 10/100BaseTX" }, 148 { RT_VENDORID, RT_DEVICEID_8139, 149 "RealTek 8139 10/100BaseTX" }, 150 { RT_VENDORID, RT_DEVICEID_8138, 151 "RealTek 8139 10/100BaseTX CardBus" }, 152 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 153 "Accton MPX 5030/5038 10/100BaseTX" }, 154 { DELTA_VENDORID, DELTA_DEVICEID_8139, 155 "Delta Electronics 8139 10/100BaseTX" }, 156 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 157 "Addtron Technolgy 8139 10/100BaseTX" }, 158 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 159 "D-Link DFE-530TX+ 10/100BaseTX" }, 160 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 161 "D-Link DFE-690TX 10/100BaseTX" }, 162 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 163 "Nortel Networks 10/100BaseTX" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 165 "Peppercon AG ROL/F" }, 166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 167 "Corega FEther CB-TXD" }, 168 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 169 "Corega FEtherII CB-TXD" }, 170 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 171 "Planex FNW-3800-TX" }, 172 { 0, 0, NULL } 173 }; 174 175 static int rl_probe(device_t); 176 static int rl_attach(device_t); 177 static int rl_detach(device_t); 178 179 static int rl_encap(struct rl_softc *, struct mbuf * ); 180 181 static void rl_rxeof(struct rl_softc *); 182 static void rl_txeof(struct rl_softc *); 183 static void rl_intr(void *); 184 static void rl_tick(void *); 185 static void rl_start(struct ifnet *); 186 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 187 static void rl_init(void *); 188 static void rl_stop (struct rl_softc *); 189 static void rl_watchdog(struct ifnet *); 190 static int rl_suspend(device_t); 191 static int rl_resume(device_t); 192 static void rl_shutdown(device_t); 193 static int rl_ifmedia_upd(struct ifnet *); 194 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 195 196 static void rl_eeprom_putbyte(struct rl_softc *, int); 197 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 198 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 199 static void rl_mii_sync(struct rl_softc *); 200 static void rl_mii_send(struct rl_softc *, uint32_t, int); 201 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 202 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 203 204 static int rl_miibus_readreg(device_t, int, int); 205 static int rl_miibus_writereg(device_t, int, int, int); 206 static void rl_miibus_statchg(device_t); 207 208 static void rl_setmulti(struct rl_softc *); 209 static void rl_reset(struct rl_softc *); 210 static void rl_list_tx_init(struct rl_softc *); 211 212 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 213 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 214 #ifdef DEVICE_POLLING 215 static poll_handler_t rl_poll; 216 #endif 217 218 #ifdef RL_USEIOSPACE 219 #define RL_RES SYS_RES_IOPORT 220 #define RL_RID RL_PCI_LOIO 221 #else 222 #define RL_RES SYS_RES_MEMORY 223 #define RL_RID RL_PCI_LOMEM 224 #endif 225 226 static device_method_t rl_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, rl_probe), 229 DEVMETHOD(device_attach, rl_attach), 230 DEVMETHOD(device_detach, rl_detach), 231 DEVMETHOD(device_suspend, rl_suspend), 232 DEVMETHOD(device_resume, rl_resume), 233 DEVMETHOD(device_shutdown, rl_shutdown), 234 235 /* bus interface */ 236 DEVMETHOD(bus_print_child, bus_generic_print_child), 237 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 241 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 242 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 243 244 { 0, 0 } 245 }; 246 247 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 248 static devclass_t rl_devclass; 249 250 DECLARE_DUMMY_MODULE(if_rl); 251 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 252 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 253 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 254 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 255 256 #define EE_SET(x) \ 257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 258 259 #define EE_CLR(x) \ 260 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 261 262 static void 263 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 264 { 265 struct rl_softc *sc = arg; 266 267 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 268 } 269 270 static void 271 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 272 { 273 struct rl_softc *sc = arg; 274 275 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 276 } 277 278 /* 279 * Send a read command and address to the EEPROM, check for ACK. 280 */ 281 static void 282 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 283 { 284 int d, i; 285 286 d = addr | sc->rl_eecmd_read; 287 288 /* 289 * Feed in each bit and strobe the clock. 290 */ 291 for (i = 0x400; i; i >>= 1) { 292 if (d & i) 293 EE_SET(RL_EE_DATAIN); 294 else 295 EE_CLR(RL_EE_DATAIN); 296 DELAY(100); 297 EE_SET(RL_EE_CLK); 298 DELAY(150); 299 EE_CLR(RL_EE_CLK); 300 DELAY(100); 301 } 302 } 303 304 /* 305 * Read a word of data stored in the EEPROM at address 'addr.' 306 */ 307 static void 308 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 309 { 310 int i; 311 uint16_t word = 0; 312 313 /* Enter EEPROM access mode. */ 314 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 315 316 /* 317 * Send address of word we want to read. 318 */ 319 rl_eeprom_putbyte(sc, addr); 320 321 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 322 323 /* 324 * Start reading bits from EEPROM. 325 */ 326 for (i = 0x8000; i; i >>= 1) { 327 EE_SET(RL_EE_CLK); 328 DELAY(100); 329 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 330 word |= i; 331 EE_CLR(RL_EE_CLK); 332 DELAY(100); 333 } 334 335 /* Turn off EEPROM access mode. */ 336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 337 338 *dest = word; 339 } 340 341 /* 342 * Read a sequence of words from the EEPROM. 343 */ 344 static void 345 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 346 { 347 int i; 348 u_int16_t word = 0, *ptr; 349 350 for (i = 0; i < cnt; i++) { 351 rl_eeprom_getword(sc, off + i, &word); 352 ptr = (u_int16_t *)(dest + (i * 2)); 353 if (swap) 354 *ptr = ntohs(word); 355 else 356 *ptr = word; 357 } 358 } 359 360 361 /* 362 * MII access routines are provided for the 8129, which 363 * doesn't have a built-in PHY. For the 8139, we fake things 364 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 365 * direct access PHY registers. 366 */ 367 #define MII_SET(x) \ 368 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 369 370 #define MII_CLR(x) \ 371 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 372 373 /* 374 * Sync the PHYs by setting data bit and strobing the clock 32 times. 375 */ 376 static void 377 rl_mii_sync(struct rl_softc *sc) 378 { 379 int i; 380 381 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 382 383 for (i = 0; i < 32; i++) { 384 MII_SET(RL_MII_CLK); 385 DELAY(1); 386 MII_CLR(RL_MII_CLK); 387 DELAY(1); 388 } 389 } 390 391 /* 392 * Clock a series of bits through the MII. 393 */ 394 static void 395 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 396 { 397 int i; 398 399 MII_CLR(RL_MII_CLK); 400 401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 402 if (bits & i) 403 MII_SET(RL_MII_DATAOUT); 404 else 405 MII_CLR(RL_MII_DATAOUT); 406 DELAY(1); 407 MII_CLR(RL_MII_CLK); 408 DELAY(1); 409 MII_SET(RL_MII_CLK); 410 } 411 } 412 413 /* 414 * Read an PHY register through the MII. 415 */ 416 static int 417 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 418 { 419 int ack, i; 420 421 /* 422 * Set up frame for RX. 423 */ 424 frame->mii_stdelim = RL_MII_STARTDELIM; 425 frame->mii_opcode = RL_MII_READOP; 426 frame->mii_turnaround = 0; 427 frame->mii_data = 0; 428 429 CSR_WRITE_2(sc, RL_MII, 0); 430 431 /* 432 * Turn on data xmit. 433 */ 434 MII_SET(RL_MII_DIR); 435 436 rl_mii_sync(sc); 437 438 /* 439 * Send command/address info. 440 */ 441 rl_mii_send(sc, frame->mii_stdelim, 2); 442 rl_mii_send(sc, frame->mii_opcode, 2); 443 rl_mii_send(sc, frame->mii_phyaddr, 5); 444 rl_mii_send(sc, frame->mii_regaddr, 5); 445 446 /* Idle bit */ 447 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 448 DELAY(1); 449 MII_SET(RL_MII_CLK); 450 DELAY(1); 451 452 /* Turn off xmit. */ 453 MII_CLR(RL_MII_DIR); 454 455 /* Check for ack */ 456 MII_CLR(RL_MII_CLK); 457 DELAY(1); 458 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 459 MII_SET(RL_MII_CLK); 460 DELAY(1); 461 462 /* 463 * Now try reading data bits. If the ack failed, we still 464 * need to clock through 16 cycles to keep the PHY(s) in sync. 465 */ 466 if (ack) { 467 for(i = 0; i < 16; i++) { 468 MII_CLR(RL_MII_CLK); 469 DELAY(1); 470 MII_SET(RL_MII_CLK); 471 DELAY(1); 472 } 473 } else { 474 for (i = 0x8000; i; i >>= 1) { 475 MII_CLR(RL_MII_CLK); 476 DELAY(1); 477 if (!ack) { 478 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 479 frame->mii_data |= i; 480 DELAY(1); 481 } 482 MII_SET(RL_MII_CLK); 483 DELAY(1); 484 } 485 } 486 487 MII_CLR(RL_MII_CLK); 488 DELAY(1); 489 MII_SET(RL_MII_CLK); 490 DELAY(1); 491 492 return(ack ? 1 : 0); 493 } 494 495 /* 496 * Write to a PHY register through the MII. 497 */ 498 static int 499 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 500 { 501 /* 502 * Set up frame for TX. 503 */ 504 frame->mii_stdelim = RL_MII_STARTDELIM; 505 frame->mii_opcode = RL_MII_WRITEOP; 506 frame->mii_turnaround = RL_MII_TURNAROUND; 507 508 /* 509 * Turn on data output. 510 */ 511 MII_SET(RL_MII_DIR); 512 513 rl_mii_sync(sc); 514 515 rl_mii_send(sc, frame->mii_stdelim, 2); 516 rl_mii_send(sc, frame->mii_opcode, 2); 517 rl_mii_send(sc, frame->mii_phyaddr, 5); 518 rl_mii_send(sc, frame->mii_regaddr, 5); 519 rl_mii_send(sc, frame->mii_turnaround, 2); 520 rl_mii_send(sc, frame->mii_data, 16); 521 522 /* Idle bit. */ 523 MII_SET(RL_MII_CLK); 524 DELAY(1); 525 MII_CLR(RL_MII_CLK); 526 DELAY(1); 527 528 /* 529 * Turn off xmit. 530 */ 531 MII_CLR(RL_MII_DIR); 532 533 return(0); 534 } 535 536 static int 537 rl_miibus_readreg(device_t dev, int phy, int reg) 538 { 539 struct rl_softc *sc; 540 struct rl_mii_frame frame; 541 uint16_t rval = 0; 542 uint16_t rl8139_reg = 0; 543 544 sc = device_get_softc(dev); 545 546 if (sc->rl_type == RL_8139) { 547 /* Pretend the internal PHY is only at address 0 */ 548 if (phy) 549 return(0); 550 switch (reg) { 551 case MII_BMCR: 552 rl8139_reg = RL_BMCR; 553 break; 554 case MII_BMSR: 555 rl8139_reg = RL_BMSR; 556 break; 557 case MII_ANAR: 558 rl8139_reg = RL_ANAR; 559 break; 560 case MII_ANER: 561 rl8139_reg = RL_ANER; 562 break; 563 case MII_ANLPAR: 564 rl8139_reg = RL_LPAR; 565 break; 566 case MII_PHYIDR1: 567 case MII_PHYIDR2: 568 return(0); 569 break; 570 /* 571 * Allow the rlphy driver to read the media status 572 * register. If we have a link partner which does not 573 * support NWAY, this is the register which will tell 574 * us the results of parallel detection. 575 */ 576 case RL_MEDIASTAT: 577 rval = CSR_READ_1(sc, RL_MEDIASTAT); 578 return(rval); 579 default: 580 device_printf(dev, "bad phy register\n"); 581 return(0); 582 } 583 rval = CSR_READ_2(sc, rl8139_reg); 584 return(rval); 585 } 586 587 bzero(&frame, sizeof(frame)); 588 589 frame.mii_phyaddr = phy; 590 frame.mii_regaddr = reg; 591 rl_mii_readreg(sc, &frame); 592 593 return(frame.mii_data); 594 } 595 596 static int 597 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 598 { 599 struct rl_softc *sc; 600 struct rl_mii_frame frame; 601 u_int16_t rl8139_reg = 0; 602 603 sc = device_get_softc(dev); 604 605 if (sc->rl_type == RL_8139) { 606 /* Pretend the internal PHY is only at address 0 */ 607 if (phy) 608 return(0); 609 switch (reg) { 610 case MII_BMCR: 611 rl8139_reg = RL_BMCR; 612 break; 613 case MII_BMSR: 614 rl8139_reg = RL_BMSR; 615 break; 616 case MII_ANAR: 617 rl8139_reg = RL_ANAR; 618 break; 619 case MII_ANER: 620 rl8139_reg = RL_ANER; 621 break; 622 case MII_ANLPAR: 623 rl8139_reg = RL_LPAR; 624 break; 625 case MII_PHYIDR1: 626 case MII_PHYIDR2: 627 return(0); 628 default: 629 device_printf(dev, "bad phy register\n"); 630 return(0); 631 } 632 CSR_WRITE_2(sc, rl8139_reg, data); 633 return(0); 634 } 635 636 bzero(&frame, sizeof(frame)); 637 638 frame.mii_phyaddr = phy; 639 frame.mii_regaddr = reg; 640 frame.mii_data = data; 641 642 rl_mii_writereg(sc, &frame); 643 644 return(0); 645 } 646 647 static void 648 rl_miibus_statchg(device_t dev) 649 { 650 } 651 652 /* 653 * Program the 64-bit multicast hash filter. 654 */ 655 static void 656 rl_setmulti(struct rl_softc *sc) 657 { 658 struct ifnet *ifp; 659 int h = 0; 660 uint32_t hashes[2] = { 0, 0 }; 661 struct ifmultiaddr *ifma; 662 uint32_t rxfilt; 663 int mcnt = 0; 664 665 ifp = &sc->arpcom.ac_if; 666 667 rxfilt = CSR_READ_4(sc, RL_RXCFG); 668 669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 670 rxfilt |= RL_RXCFG_RX_MULTI; 671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 674 return; 675 } 676 677 /* first, zot all the existing hash bits */ 678 CSR_WRITE_4(sc, RL_MAR0, 0); 679 CSR_WRITE_4(sc, RL_MAR4, 0); 680 681 /* now program new ones */ 682 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 683 if (ifma->ifma_addr->sa_family != AF_LINK) 684 continue; 685 h = ether_crc32_be( 686 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 687 ETHER_ADDR_LEN) >> 26; 688 if (h < 32) 689 hashes[0] |= (1 << h); 690 else 691 hashes[1] |= (1 << (h - 32)); 692 mcnt++; 693 } 694 695 if (mcnt) 696 rxfilt |= RL_RXCFG_RX_MULTI; 697 else 698 rxfilt &= ~RL_RXCFG_RX_MULTI; 699 700 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 701 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 702 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 703 } 704 705 static void 706 rl_reset(struct rl_softc *sc) 707 { 708 int i; 709 710 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 711 712 for (i = 0; i < RL_TIMEOUT; i++) { 713 DELAY(10); 714 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 715 break; 716 } 717 if (i == RL_TIMEOUT) 718 device_printf(sc->rl_dev, "reset never completed!\n"); 719 } 720 721 /* 722 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 723 * IDs against our list and return a device name if we find a match. 724 * 725 * Return with a value < 0 to give re(4) a change to attach. 726 */ 727 static int 728 rl_probe(device_t dev) 729 { 730 struct rl_type *t; 731 uint16_t product = pci_get_device(dev); 732 uint16_t vendor = pci_get_vendor(dev); 733 734 for (t = rl_devs; t->rl_name != NULL; t++) { 735 if (vendor == t->rl_vid && product == t->rl_did) { 736 device_set_desc(dev, t->rl_name); 737 return(-100); 738 } 739 } 740 741 return(ENXIO); 742 } 743 744 /* 745 * Attach the interface. Allocate softc structures, do ifmedia 746 * setup and ethernet/BPF attach. 747 */ 748 static int 749 rl_attach(device_t dev) 750 { 751 uint8_t eaddr[ETHER_ADDR_LEN]; 752 uint16_t as[3]; 753 struct rl_softc *sc; 754 struct ifnet *ifp; 755 uint16_t rl_did = 0; 756 int error = 0, rid, i; 757 758 sc = device_get_softc(dev); 759 sc->rl_dev = dev; 760 761 /* 762 * Handle power management nonsense. 763 */ 764 765 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 766 uint32_t iobase, membase, irq; 767 768 /* Save important PCI config data. */ 769 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 770 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 771 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 772 773 /* Reset the power state. */ 774 device_printf(dev, "chip is is in D%d power mode " 775 "-- setting to D0\n", pci_get_powerstate(dev)); 776 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 777 778 /* Restore PCI config data. */ 779 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 780 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 781 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 782 } 783 784 pci_enable_busmaster(dev); 785 786 rid = RL_RID; 787 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 788 789 if (sc->rl_res == NULL) { 790 device_printf(dev, "couldn't map ports/memory\n"); 791 error = ENXIO; 792 goto fail; 793 } 794 795 sc->rl_btag = rman_get_bustag(sc->rl_res); 796 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 797 798 rid = 0; 799 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 800 RF_SHAREABLE | RF_ACTIVE); 801 802 if (sc->rl_irq == NULL) { 803 device_printf(dev, "couldn't map interrupt\n"); 804 error = ENXIO; 805 goto fail; 806 } 807 808 callout_init(&sc->rl_stat_timer); 809 810 /* Reset the adapter. */ 811 rl_reset(sc); 812 813 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 814 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 815 if (rl_did != 0x8129) 816 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 817 818 /* 819 * Get station address from the EEPROM. 820 */ 821 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 822 for (i = 0; i < 3; i++) { 823 eaddr[(i * 2) + 0] = as[i] & 0xff; 824 eaddr[(i * 2) + 1] = as[i] >> 8; 825 } 826 827 /* 828 * Now read the exact device type from the EEPROM to find 829 * out if it's an 8129 or 8139. 830 */ 831 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 832 833 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 834 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 835 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 || 836 rl_did == DLINK_DEVICEID_690TXD || 837 rl_did == COREGA_DEVICEID_FETHERCBTXD || 838 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 839 rl_did == PLANEX_DEVICEID_FNW3800TX) 840 sc->rl_type = RL_8139; 841 else if (rl_did == RT_DEVICEID_8129) 842 sc->rl_type = RL_8129; 843 else { 844 device_printf(dev, "unknown device ID: %x\n", rl_did); 845 error = ENXIO; 846 goto fail; 847 } 848 849 #define RL_NSEG_NEW 32 850 error = bus_dma_tag_create(NULL, /* parent */ 851 1, 0, /* alignment, boundary */ 852 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 853 BUS_SPACE_MAXADDR, /* highaddr */ 854 NULL, NULL, /* filter, filterarg */ 855 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 856 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 857 BUS_DMA_ALLOCNOW, /* flags */ 858 &sc->rl_parent_tag); 859 860 if (error) { 861 device_printf(dev, "can't create parent tag\n"); 862 goto fail; 863 } 864 865 /* 866 * Now allocate a tag for the DMA descriptor lists. 867 * All of our lists are allocated as a contiguous block 868 * of memory. 869 */ 870 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 871 1, 0, /* alignment, boundary */ 872 BUS_SPACE_MAXADDR, /* lowaddr */ 873 BUS_SPACE_MAXADDR, /* highaddr */ 874 NULL, NULL, /* filter, filterarg */ 875 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */ 876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 877 0, /* flags */ 878 &sc->rl_tag); 879 880 if (error) { 881 device_printf(dev, "can't create RX tag\n"); 882 goto fail; 883 } 884 885 /* 886 * Now allocate a chunk of DMA-able memory based on the tag 887 * we just created. 888 */ 889 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf, 890 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap); 891 892 if (error) { 893 device_printf(dev, "can't allocate RX memory!\n"); 894 error = ENXIO; 895 goto fail; 896 } 897 898 /* Leave a few bytes before the start of the RX ring buffer. */ 899 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 900 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 901 902 /* Do MII setup */ 903 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 904 rl_ifmedia_sts)) { 905 device_printf(dev, "MII without any phy!\n"); 906 error = ENXIO; 907 goto fail; 908 } 909 910 ifp = &sc->arpcom.ac_if; 911 ifp->if_softc = sc; 912 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 913 ifp->if_mtu = ETHERMTU; 914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 915 ifp->if_ioctl = rl_ioctl; 916 ifp->if_start = rl_start; 917 ifp->if_watchdog = rl_watchdog; 918 ifp->if_init = rl_init; 919 ifp->if_baudrate = 10000000; 920 ifp->if_capabilities = IFCAP_VLAN_MTU; 921 #ifdef DEVICE_POLLING 922 ifp->if_poll = rl_poll; 923 #endif 924 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 925 ifq_set_ready(&ifp->if_snd); 926 927 /* 928 * Call MI attach routine. 929 */ 930 ether_ifattach(ifp, eaddr, NULL); 931 932 error = bus_setup_intr(dev, sc->rl_irq, INTR_NETSAFE, rl_intr, 933 sc, &sc->rl_intrhand, ifp->if_serializer); 934 935 if (error) { 936 device_printf(dev, "couldn't set up irq\n"); 937 ether_ifdetach(ifp); 938 goto fail; 939 } 940 941 return(0); 942 943 fail: 944 rl_detach(dev); 945 return(error); 946 } 947 948 static int 949 rl_detach(device_t dev) 950 { 951 struct rl_softc *sc; 952 struct ifnet *ifp; 953 954 sc = device_get_softc(dev); 955 ifp = &sc->arpcom.ac_if; 956 957 lwkt_serialize_enter(ifp->if_serializer); 958 959 if (device_is_attached(dev)) { 960 rl_stop(sc); 961 ether_ifdetach(ifp); 962 } 963 964 if (sc->rl_miibus) 965 device_delete_child(dev, sc->rl_miibus); 966 bus_generic_detach(dev); 967 968 if (sc->rl_intrhand) 969 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 970 971 if (sc->rl_irq) 972 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 973 if (sc->rl_res) 974 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 975 976 if (sc->rl_cdata.rl_rx_buf) { 977 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 978 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 979 sc->rl_cdata.rl_rx_dmamap); 980 } 981 if (sc->rl_tag) 982 bus_dma_tag_destroy(sc->rl_tag); 983 if (sc->rl_parent_tag) 984 bus_dma_tag_destroy(sc->rl_parent_tag); 985 986 lwkt_serialize_exit(ifp->if_serializer); 987 988 return(0); 989 } 990 991 /* 992 * Initialize the transmit descriptors. 993 */ 994 static void 995 rl_list_tx_init(struct rl_softc *sc) 996 { 997 struct rl_chain_data *cd; 998 int i; 999 1000 cd = &sc->rl_cdata; 1001 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1002 cd->rl_tx_chain[i] = NULL; 1003 CSR_WRITE_4(sc, 1004 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1005 } 1006 1007 sc->rl_cdata.cur_tx = 0; 1008 sc->rl_cdata.last_tx = 0; 1009 } 1010 1011 /* 1012 * A frame has been uploaded: pass the resulting mbuf chain up to 1013 * the higher level protocols. 1014 * 1015 * You know there's something wrong with a PCI bus-master chip design 1016 * when you have to use m_devget(). 1017 * 1018 * The receive operation is badly documented in the datasheet, so I'll 1019 * attempt to document it here. The driver provides a buffer area and 1020 * places its base address in the RX buffer start address register. 1021 * The chip then begins copying frames into the RX buffer. Each frame 1022 * is preceded by a 32-bit RX status word which specifies the length 1023 * of the frame and certain other status bits. Each frame (starting with 1024 * the status word) is also 32-bit aligned. The frame length is in the 1025 * first 16 bits of the status word; the lower 15 bits correspond with 1026 * the 'rx status register' mentioned in the datasheet. 1027 * 1028 * Note: to make the Alpha happy, the frame payload needs to be aligned 1029 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1030 * the ring buffer starting at an address two bytes before the actual 1031 * data location. We can then shave off the first two bytes using m_adj(). 1032 * The reason we do this is because m_devget() doesn't let us specify an 1033 * offset into the mbuf storage space, so we have to artificially create 1034 * one. The ring is allocated in such a way that there are a few unused 1035 * bytes of space preceecing it so that it will be safe for us to do the 1036 * 2-byte backstep even if reading from the ring at offset 0. 1037 */ 1038 static void 1039 rl_rxeof(struct rl_softc *sc) 1040 { 1041 struct mbuf *m; 1042 struct ifnet *ifp; 1043 int total_len = 0; 1044 uint32_t rxstat; 1045 caddr_t rxbufpos; 1046 int wrap = 0; 1047 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 1051 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1052 BUS_DMASYNC_POSTREAD); 1053 1054 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1055 1056 /* Do not try to read past this point. */ 1057 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1058 1059 if (limit < cur_rx) 1060 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1061 else 1062 max_bytes = limit - cur_rx; 1063 1064 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1065 #ifdef DEVICE_POLLING 1066 if (ifp->if_flags & IFF_POLLING) { 1067 if (sc->rxcycles <= 0) 1068 break; 1069 sc->rxcycles--; 1070 } 1071 #endif /* DEVICE_POLLING */ 1072 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1073 rxstat = le32toh(*(uint32_t *)rxbufpos); 1074 1075 /* 1076 * Here's a totally undocumented fact for you. When the 1077 * RealTek chip is in the process of copying a packet into 1078 * RAM for you, the length will be 0xfff0. If you spot a 1079 * packet header with this value, you need to stop. The 1080 * datasheet makes absolutely no mention of this and 1081 * RealTek should be shot for this. 1082 */ 1083 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1084 break; 1085 1086 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1087 ifp->if_ierrors++; 1088 rl_init(sc); 1089 return; 1090 } 1091 1092 /* No errors; receive the packet. */ 1093 total_len = rxstat >> 16; 1094 rx_bytes += total_len + 4; 1095 1096 /* 1097 * XXX The RealTek chip includes the CRC with every 1098 * received frame, and there's no way to turn this 1099 * behavior off (at least, I can't find anything in 1100 * the manual that explains how to do it) so we have 1101 * to trim off the CRC manually. 1102 */ 1103 total_len -= ETHER_CRC_LEN; 1104 1105 /* 1106 * Avoid trying to read more bytes than we know 1107 * the chip has prepared for us. 1108 */ 1109 if (rx_bytes > max_bytes) 1110 break; 1111 1112 rxbufpos = sc->rl_cdata.rl_rx_buf + 1113 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1114 1115 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1116 rxbufpos = sc->rl_cdata.rl_rx_buf; 1117 1118 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1119 1120 if (total_len > wrap) { 1121 /* 1122 * Fool m_devget() into thinking we want to copy 1123 * the whole buffer so we don't end up fragmenting 1124 * the data. 1125 */ 1126 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1127 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1128 if (m == NULL) { 1129 ifp->if_ierrors++; 1130 } else { 1131 m_adj(m, RL_ETHER_ALIGN); 1132 m_copyback(m, wrap, total_len - wrap, 1133 sc->rl_cdata.rl_rx_buf); 1134 } 1135 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1136 } else { 1137 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1138 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1139 if (m == NULL) { 1140 ifp->if_ierrors++; 1141 } else 1142 m_adj(m, RL_ETHER_ALIGN); 1143 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1144 } 1145 1146 /* 1147 * Round up to 32-bit boundary. 1148 */ 1149 cur_rx = (cur_rx + 3) & ~3; 1150 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1151 1152 if (m == NULL) 1153 continue; 1154 1155 ifp->if_ipackets++; 1156 1157 ifp->if_input(ifp, m); 1158 } 1159 } 1160 1161 /* 1162 * A frame was downloaded to the chip. It's safe for us to clean up 1163 * the list buffers. 1164 */ 1165 static void 1166 rl_txeof(struct rl_softc *sc) 1167 { 1168 struct ifnet *ifp; 1169 uint32_t txstat; 1170 1171 ifp = &sc->arpcom.ac_if; 1172 1173 /* 1174 * Go through our tx list and free mbufs for those 1175 * frames that have been uploaded. 1176 */ 1177 do { 1178 if (RL_LAST_TXMBUF(sc) == NULL) 1179 break; 1180 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1181 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1182 RL_TXSTAT_TXABRT)) == 0) 1183 break; 1184 1185 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1186 1187 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1188 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1189 m_freem(RL_LAST_TXMBUF(sc)); 1190 RL_LAST_TXMBUF(sc) = NULL; 1191 RL_INC(sc->rl_cdata.last_tx); 1192 1193 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1194 sc->rl_txthresh += 32; 1195 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1196 sc->rl_txthresh = RL_TX_THRESH_MAX; 1197 } 1198 1199 if (txstat & RL_TXSTAT_TX_OK) { 1200 ifp->if_opackets++; 1201 } else { 1202 ifp->if_oerrors++; 1203 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1204 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1205 } 1206 ifp->if_flags &= ~IFF_OACTIVE; 1207 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1208 1209 if (RL_LAST_TXMBUF(sc) == NULL) 1210 ifp->if_timer = 0; 1211 else if (ifp->if_timer == 0) 1212 ifp->if_timer = 5; 1213 } 1214 1215 static void 1216 rl_tick(void *xsc) 1217 { 1218 struct rl_softc *sc = xsc; 1219 struct mii_data *mii; 1220 1221 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1222 1223 mii = device_get_softc(sc->rl_miibus); 1224 mii_tick(mii); 1225 1226 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1227 1228 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1229 } 1230 1231 #ifdef DEVICE_POLLING 1232 1233 static void 1234 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1235 { 1236 struct rl_softc *sc = ifp->if_softc; 1237 1238 switch(cmd) { 1239 case POLL_REGISTER: 1240 /* disable interrupts */ 1241 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1242 break; 1243 case POLL_DEREGISTER: 1244 /* enable interrupts */ 1245 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1246 break; 1247 default: 1248 sc->rxcycles = count; 1249 rl_rxeof(sc); 1250 rl_txeof(sc); 1251 if (!ifq_is_empty(&ifp->if_snd)) 1252 rl_start(ifp); 1253 1254 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1255 uint16_t status; 1256 1257 status = CSR_READ_2(sc, RL_ISR); 1258 if (status == 0xffff) 1259 return; 1260 if (status) 1261 CSR_WRITE_2(sc, RL_ISR, status); 1262 1263 /* 1264 * XXX check behaviour on receiver stalls. 1265 */ 1266 1267 if (status & RL_ISR_SYSTEM_ERR) { 1268 rl_reset(sc); 1269 rl_init(sc); 1270 } 1271 } 1272 break; 1273 } 1274 } 1275 #endif /* DEVICE_POLLING */ 1276 1277 static void 1278 rl_intr(void *arg) 1279 { 1280 struct rl_softc *sc; 1281 struct ifnet *ifp; 1282 uint16_t status; 1283 1284 sc = arg; 1285 1286 if (sc->suspended) 1287 return; 1288 1289 ifp = &sc->arpcom.ac_if; 1290 1291 for (;;) { 1292 status = CSR_READ_2(sc, RL_ISR); 1293 /* If the card has gone away, the read returns 0xffff. */ 1294 if (status == 0xffff) 1295 break; 1296 1297 if (status != 0) 1298 CSR_WRITE_2(sc, RL_ISR, status); 1299 1300 if ((status & RL_INTRS) == 0) 1301 break; 1302 1303 if (status & RL_ISR_RX_OK) 1304 rl_rxeof(sc); 1305 1306 if (status & RL_ISR_RX_ERR) 1307 rl_rxeof(sc); 1308 1309 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1310 rl_txeof(sc); 1311 1312 if (status & RL_ISR_SYSTEM_ERR) { 1313 rl_reset(sc); 1314 rl_init(sc); 1315 } 1316 1317 } 1318 1319 if (!ifq_is_empty(&ifp->if_snd)) 1320 rl_start(ifp); 1321 } 1322 1323 /* 1324 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1325 * pointers to the fragment pointers. 1326 */ 1327 static int 1328 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1329 { 1330 struct mbuf *m_new = NULL; 1331 1332 /* 1333 * The RealTek is brain damaged and wants longword-aligned 1334 * TX buffers, plus we can only have one fragment buffer 1335 * per packet. We have to copy pretty much all the time. 1336 */ 1337 m_new = m_defrag(m_head, MB_DONTWAIT); 1338 1339 if (m_new == NULL) { 1340 m_freem(m_head); 1341 return(1); 1342 } 1343 m_head = m_new; 1344 1345 /* Pad frames to at least 60 bytes. */ 1346 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1347 /* 1348 * Make security concious people happy: zero out the 1349 * bytes in the pad area, since we don't know what 1350 * this mbuf cluster buffer's previous user might 1351 * have left in it. 1352 */ 1353 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1354 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1355 m_head->m_pkthdr.len += 1356 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1357 m_head->m_len = m_head->m_pkthdr.len; 1358 } 1359 1360 RL_CUR_TXMBUF(sc) = m_head; 1361 1362 return(0); 1363 } 1364 1365 /* 1366 * Main transmit routine. 1367 */ 1368 1369 static void 1370 rl_start(struct ifnet *ifp) 1371 { 1372 struct rl_softc *sc; 1373 struct mbuf *m_head = NULL; 1374 1375 sc = ifp->if_softc; 1376 1377 while(RL_CUR_TXMBUF(sc) == NULL) { 1378 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1379 if (m_head == NULL) 1380 break; 1381 1382 if (rl_encap(sc, m_head)) 1383 break; 1384 1385 /* 1386 * If there's a BPF listener, bounce a copy of this frame 1387 * to him. 1388 */ 1389 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1390 1391 /* 1392 * Transmit the frame. 1393 */ 1394 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1395 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1396 mtod(RL_CUR_TXMBUF(sc), void *), 1397 RL_CUR_TXMBUF(sc)->m_pkthdr.len, 1398 rl_dma_map_txbuf, sc, 0); 1399 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1400 BUS_DMASYNC_PREREAD); 1401 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1402 RL_TXTHRESH(sc->rl_txthresh) | 1403 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1404 1405 RL_INC(sc->rl_cdata.cur_tx); 1406 1407 /* 1408 * Set a timeout in case the chip goes out to lunch. 1409 */ 1410 ifp->if_timer = 5; 1411 } 1412 1413 /* 1414 * We broke out of the loop because all our TX slots are 1415 * full. Mark the NIC as busy until it drains some of the 1416 * packets from the queue. 1417 */ 1418 if (RL_CUR_TXMBUF(sc) != NULL) 1419 ifp->if_flags |= IFF_OACTIVE; 1420 } 1421 1422 static void 1423 rl_init(void *xsc) 1424 { 1425 struct rl_softc *sc = xsc; 1426 struct ifnet *ifp = &sc->arpcom.ac_if; 1427 struct mii_data *mii; 1428 uint32_t rxcfg = 0; 1429 1430 mii = device_get_softc(sc->rl_miibus); 1431 1432 /* 1433 * Cancel pending I/O and free all RX/TX buffers. 1434 */ 1435 rl_stop(sc); 1436 1437 /* 1438 * Init our MAC address. Even though the chipset documentation 1439 * doesn't mention it, we need to enter "Config register write enable" 1440 * mode to modify the ID registers. 1441 */ 1442 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1443 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1444 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1445 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1446 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1447 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1448 1449 /* Init the RX buffer pointer register. */ 1450 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1451 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, 1452 sc, 0); 1453 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1454 BUS_DMASYNC_PREWRITE); 1455 1456 /* Init TX descriptors. */ 1457 rl_list_tx_init(sc); 1458 1459 /* 1460 * Enable transmit and receive. 1461 */ 1462 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1463 1464 /* 1465 * Set the initial TX and RX configuration. 1466 */ 1467 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1468 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1469 1470 /* Set the individual bit to receive frames for this host only. */ 1471 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1472 rxcfg |= RL_RXCFG_RX_INDIV; 1473 1474 /* If we want promiscuous mode, set the allframes bit. */ 1475 if (ifp->if_flags & IFF_PROMISC) { 1476 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1477 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1478 } else { 1479 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1480 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1481 } 1482 1483 /* 1484 * Set capture broadcast bit to capture broadcast frames. 1485 */ 1486 if (ifp->if_flags & IFF_BROADCAST) { 1487 rxcfg |= RL_RXCFG_RX_BROAD; 1488 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1489 } else { 1490 rxcfg &= ~RL_RXCFG_RX_BROAD; 1491 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1492 } 1493 1494 /* 1495 * Program the multicast filter, if necessary. 1496 */ 1497 rl_setmulti(sc); 1498 1499 #ifdef DEVICE_POLLING 1500 /* 1501 * Only enable interrupts if we are polling, keep them off otherwise. 1502 */ 1503 if (ifp->if_flags & IFF_POLLING) 1504 CSR_WRITE_2(sc, RL_IMR, 0); 1505 else 1506 #endif /* DEVICE_POLLING */ 1507 /* 1508 * Enable interrupts. 1509 */ 1510 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1511 1512 /* Set initial TX threshold */ 1513 sc->rl_txthresh = RL_TX_THRESH_INIT; 1514 1515 /* Start RX/TX process. */ 1516 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1517 1518 /* Enable receiver and transmitter. */ 1519 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1520 1521 mii_mediachg(mii); 1522 1523 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1524 1525 ifp->if_flags |= IFF_RUNNING; 1526 ifp->if_flags &= ~IFF_OACTIVE; 1527 1528 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1529 } 1530 1531 /* 1532 * Set media options. 1533 */ 1534 static int 1535 rl_ifmedia_upd(struct ifnet *ifp) 1536 { 1537 struct rl_softc *sc; 1538 struct mii_data *mii; 1539 1540 sc = ifp->if_softc; 1541 mii = device_get_softc(sc->rl_miibus); 1542 mii_mediachg(mii); 1543 1544 return(0); 1545 } 1546 1547 /* 1548 * Report current media status. 1549 */ 1550 static void 1551 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1552 { 1553 struct rl_softc *sc = ifp->if_softc; 1554 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1555 1556 mii_pollstat(mii); 1557 ifmr->ifm_active = mii->mii_media_active; 1558 ifmr->ifm_status = mii->mii_media_status; 1559 } 1560 1561 static int 1562 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1563 { 1564 struct rl_softc *sc = ifp->if_softc; 1565 struct ifreq *ifr = (struct ifreq *) data; 1566 struct mii_data *mii; 1567 int error = 0; 1568 1569 switch (command) { 1570 case SIOCSIFFLAGS: 1571 if (ifp->if_flags & IFF_UP) { 1572 rl_init(sc); 1573 } else { 1574 if (ifp->if_flags & IFF_RUNNING) 1575 rl_stop(sc); 1576 } 1577 error = 0; 1578 break; 1579 case SIOCADDMULTI: 1580 case SIOCDELMULTI: 1581 rl_setmulti(sc); 1582 error = 0; 1583 break; 1584 case SIOCGIFMEDIA: 1585 case SIOCSIFMEDIA: 1586 mii = device_get_softc(sc->rl_miibus); 1587 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1588 break; 1589 case SIOCSIFCAP: 1590 break; 1591 default: 1592 error = ether_ioctl(ifp, command, data); 1593 break; 1594 } 1595 1596 return(error); 1597 } 1598 1599 static void 1600 rl_watchdog(struct ifnet *ifp) 1601 { 1602 struct rl_softc *sc = ifp->if_softc; 1603 1604 device_printf(sc->rl_dev, "watchdog timeout\n"); 1605 1606 lwkt_serialize_enter(ifp->if_serializer); 1607 1608 ifp->if_oerrors++; 1609 1610 rl_txeof(sc); 1611 rl_rxeof(sc); 1612 rl_init(sc); 1613 1614 lwkt_serialize_exit(ifp->if_serializer); 1615 } 1616 1617 /* 1618 * Stop the adapter and free any mbufs allocated to the 1619 * RX and TX lists. 1620 */ 1621 static void 1622 rl_stop(struct rl_softc *sc) 1623 { 1624 struct ifnet *ifp = &sc->arpcom.ac_if; 1625 int i; 1626 1627 ifp->if_timer = 0; 1628 1629 callout_stop(&sc->rl_stat_timer); 1630 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1631 1632 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1633 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1634 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1635 1636 /* 1637 * Free the TX list buffers. 1638 */ 1639 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1640 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1641 bus_dmamap_unload(sc->rl_tag, 1642 sc->rl_cdata.rl_tx_dmamap[i]); 1643 bus_dmamap_destroy(sc->rl_tag, 1644 sc->rl_cdata.rl_tx_dmamap[i]); 1645 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1646 sc->rl_cdata.rl_tx_chain[i] = NULL; 1647 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1648 0x0000000); 1649 } 1650 } 1651 } 1652 1653 /* 1654 * Stop all chip I/O so that the kernel's probe routines don't 1655 * get confused by errant DMAs when rebooting. 1656 */ 1657 static void 1658 rl_shutdown(device_t dev) 1659 { 1660 struct rl_softc *sc; 1661 1662 sc = device_get_softc(dev); 1663 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1664 rl_stop(sc); 1665 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1666 } 1667 1668 /* 1669 * Device suspend routine. Stop the interface and save some PCI 1670 * settings in case the BIOS doesn't restore them properly on 1671 * resume. 1672 */ 1673 static int 1674 rl_suspend(device_t dev) 1675 { 1676 struct rl_softc *sc = device_get_softc(dev); 1677 int i; 1678 1679 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1680 rl_stop(sc); 1681 1682 for (i = 0; i < 5; i++) 1683 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1684 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1685 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1686 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1687 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1688 1689 sc->suspended = 1; 1690 1691 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1692 return (0); 1693 } 1694 1695 /* 1696 * Device resume routine. Restore some PCI settings in case the BIOS 1697 * doesn't, re-enable busmastering, and restart the interface if 1698 * appropriate. 1699 */ 1700 static int rl_resume(device_t dev) 1701 { 1702 struct rl_softc *sc = device_get_softc(dev); 1703 struct ifnet *ifp = &sc->arpcom.ac_if; 1704 int i; 1705 1706 lwkt_serialize_enter(ifp->if_serializer); 1707 1708 /* better way to do this? */ 1709 for (i = 0; i < 5; i++) 1710 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1711 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1712 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1713 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1714 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1715 1716 /* reenable busmastering */ 1717 pci_enable_busmaster(dev); 1718 pci_enable_io(dev, RL_RES); 1719 1720 /* reinitialize interface if necessary */ 1721 if (ifp->if_flags & IFF_UP) 1722 rl_init(sc); 1723 1724 sc->suspended = 0; 1725 lwkt_serialize_exit(ifp->if_serializer); 1726 return (0); 1727 } 1728