1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.25 2008/10/16 12:29:13 sephe Exp $ 37 */ 38 39 #define RE_RX_DESC_CNT_DEF 256 40 #define RE_TX_DESC_CNT_DEF 256 41 #define RE_RX_DESC_CNT_MAX 1024 42 #define RE_TX_DESC_CNT_MAX 1024 43 44 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc)) 45 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc)) 46 #define RE_RING_ALIGN 256 47 #define RE_IFQ_MAXLEN 512 48 #define RE_MAXSEGS 16 49 #define RE_TXDESC_SPARE 4 50 51 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt) 52 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt) 53 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 54 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 55 #define RE_PKTSZ(x) ((x)/* >> 3*/) 56 57 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 58 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 59 60 #define RE_JUMBO_FRAMELEN 7440 61 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 62 #define RE_FRAMELEN_2K 2048 63 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) 64 #define RE_SWCSUM_LIM_8169 2038 65 66 #define RE_TIMEOUT 1000 67 68 struct re_hwrev { 69 uint32_t re_hwrev; 70 uint32_t re_macver; /* see RE_MACVER_ */ 71 uint32_t re_caps; /* see RE_C_ */ 72 }; 73 74 #define RE_MACVER_UNKN 0 75 #define RE_MACVER_03 0x03 76 #define RE_MACVER_04 0x04 77 #define RE_MACVER_05 0x05 78 #define RE_MACVER_06 0x06 79 #define RE_MACVER_11 0x11 80 #define RE_MACVER_12 0x12 81 #define RE_MACVER_13 0x13 82 #define RE_MACVER_14 0x14 83 #define RE_MACVER_15 0x15 84 #define RE_MACVER_16 0x16 85 #define RE_MACVER_21 0x21 86 #define RE_MACVER_22 0x22 87 #define RE_MACVER_23 0x23 88 #define RE_MACVER_24 0x24 89 #define RE_MACVER_25 0x25 90 #define RE_MACVER_26 0x26 91 #define RE_MACVER_27 0x27 92 #define RE_MACVER_28 0x28 93 #define RE_MACVER_29 0x29 94 #define RE_MACVER_2A 0x2a 95 #define RE_MACVER_2B 0x2b 96 97 struct re_dmaload_arg { 98 int re_nsegs; 99 bus_dma_segment_t *re_segs; 100 }; 101 102 struct re_list_data { 103 struct mbuf **re_tx_mbuf; 104 struct mbuf **re_rx_mbuf; 105 bus_addr_t *re_rx_paddr; 106 int re_tx_prodidx; 107 int re_rx_prodidx; 108 int re_tx_considx; 109 int re_tx_free; 110 bus_dmamap_t *re_tx_dmamap; 111 bus_dmamap_t *re_rx_dmamap; 112 bus_dmamap_t re_rx_spare; 113 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 114 bus_dma_tag_t re_stag; /* stats mapping tag */ 115 bus_dmamap_t re_smap; /* stats map */ 116 struct re_stats *re_stats; 117 bus_addr_t re_stats_addr; 118 bus_dma_tag_t re_rx_list_tag; 119 bus_dmamap_t re_rx_list_map; 120 struct re_desc *re_rx_list; 121 bus_addr_t re_rx_list_addr; 122 bus_dma_tag_t re_tx_list_tag; 123 bus_dmamap_t re_tx_list_map; 124 struct re_desc *re_tx_list; 125 bus_addr_t re_tx_list_addr; 126 }; 127 128 struct re_softc { 129 struct arpcom arpcom; /* interface info */ 130 device_t re_dev; 131 bus_space_handle_t re_bhandle; /* bus space handle */ 132 bus_space_tag_t re_btag; /* bus space tag */ 133 struct resource *re_res; 134 struct resource *re_irq; 135 void *re_intrhand; 136 device_t re_miibus; 137 bus_dma_tag_t re_parent_tag; 138 bus_dma_tag_t re_tag; 139 int re_eecmd_read; 140 uint8_t re_stats_no_timeout; 141 int re_txthresh; 142 uint32_t re_hwrev; 143 struct re_list_data re_ldata; 144 struct callout re_timer; 145 struct mbuf *re_head; 146 struct mbuf *re_tail; 147 int re_drop_rxfrag; 148 uint32_t re_caps; /* see RE_C_ */ 149 uint32_t re_macver; /* see RE_MACVER_ */ 150 uint32_t re_rxlenmask; 151 int re_txstart; 152 int re_testmode; 153 int suspended; /* 0 = normal 1 = suspended */ 154 int re_link; 155 int re_eewidth; 156 int re_swcsum_lim; 157 int re_maxmtu; 158 int re_rx_desc_cnt; 159 int re_tx_desc_cnt; 160 int re_bus_speed; 161 int rxcycles; 162 163 uint32_t re_flags; /* see RE_F_ */ 164 165 struct sysctl_ctx_list re_sysctl_ctx; 166 struct sysctl_oid *re_sysctl_tree; 167 uint16_t re_intrs; 168 uint16_t re_tx_ack; 169 uint16_t re_rx_ack; 170 int re_tx_time; 171 int re_rx_time; 172 int re_sim_time; 173 int re_imtype; /* see RE_IMTYPE_ */ 174 175 uint32_t saved_maps[5]; /* pci data */ 176 uint32_t saved_biosaddr; 177 uint8_t saved_intline; 178 uint8_t saved_cachelnsz; 179 uint8_t saved_lattimer; 180 }; 181 182 #define RE_C_PCIE 0x1 /* PCI-E */ 183 #define RE_C_PCI64 0x2 /* PCI-X */ 184 #define RE_C_HWIM 0x4 /* hardware interrupt moderation */ 185 #define RE_C_HWCSUM 0x8 /* hardware csum offload */ 186 #define RE_C_JUMBO 0x10 /* jumbo frame */ 187 #define RE_C_8139CP 0x20 /* is 8139C+ */ 188 #define RE_C_MAC2 0x40 /* MAC style 2 */ 189 #define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */ 190 #define RE_C_8169 0x100 /* is 8110/8169 */ 191 #define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */ 192 193 #define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP) 194 195 /* Interrupt moderation types */ 196 #define RE_IMTYPE_NONE 0 197 #define RE_IMTYPE_SIM 1 /* simulated */ 198 #define RE_IMTYPE_HW 2 /* hardware based */ 199 200 #define RE_F_TIMER_INTR 0x1 201 202 /* 203 * register space access macros 204 */ 205 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 206 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 207 #define CSR_WRITE_4(sc, reg, val) \ 208 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 209 #define CSR_WRITE_2(sc, reg, val) \ 210 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 211 #define CSR_WRITE_1(sc, reg, val) \ 212 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 213 214 #define CSR_READ_4(sc, reg) \ 215 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 216 #define CSR_READ_2(sc, reg) \ 217 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 218 #define CSR_READ_1(sc, reg) \ 219 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 220 221 #define CSR_SETBIT_1(sc, reg, val) \ 222 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 223 #define CSR_CLRBIT_1(sc, reg, val) \ 224 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 225