1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.10 2008/10/05 01:53:41 sephe Exp $ 37 */ 38 39 #define RE_RX_DESC_CNT 64 40 #define RE_TX_DESC_CNT 64 41 #define RE_RX_LIST_SZ (RE_RX_DESC_CNT * sizeof(struct re_desc)) 42 #define RE_TX_LIST_SZ (RE_TX_DESC_CNT * sizeof(struct re_desc)) 43 #define RE_RING_ALIGN 256 44 #define RE_IFQ_MAXLEN 512 45 #define RE_MAXSEGS 16 46 #define RE_TXDESC_SPARE 4 47 48 #define RE_DESC_INC(x) (x = (x + 1) % RE_TX_DESC_CNT) 49 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 50 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 51 #define RE_PKTSZ(x) ((x)/* >> 3*/) 52 53 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 54 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 55 56 #define RE_JUMBO_FRAMELEN 7440 57 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 58 #define RE_FRAMELEN_2K 2048 59 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) 60 #define RE_SWCSUM_LIM_8169 2038 61 62 #define RE_TIMEOUT 1000 63 64 struct re_type { 65 uint16_t re_vid; 66 uint16_t re_did; 67 int re_basetype; 68 const char *re_name; 69 }; 70 71 struct re_hwrev { 72 uint32_t re_rev; 73 int re_type; /* RE_{8139CPLUS,8169} */ 74 uint32_t re_flags; /* see RE_F_ */ 75 int re_swcsum_lim; 76 int re_maxmtu; 77 }; 78 79 #define RE_8139CPLUS 3 80 #define RE_8169 4 81 82 struct re_dmaload_arg { 83 int re_nsegs; 84 bus_dma_segment_t *re_segs; 85 }; 86 87 struct re_list_data { 88 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT]; 89 struct mbuf *re_rx_mbuf[RE_RX_DESC_CNT]; 90 bus_addr_t re_rx_paddr[RE_RX_DESC_CNT]; 91 int re_tx_prodidx; 92 int re_rx_prodidx; 93 int re_tx_considx; 94 int re_tx_free; 95 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT]; 96 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT]; 97 bus_dmamap_t re_rx_spare; 98 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 99 bus_dma_tag_t re_stag; /* stats mapping tag */ 100 bus_dmamap_t re_smap; /* stats map */ 101 struct re_stats *re_stats; 102 bus_addr_t re_stats_addr; 103 bus_dma_tag_t re_rx_list_tag; 104 bus_dmamap_t re_rx_list_map; 105 struct re_desc *re_rx_list; 106 bus_addr_t re_rx_list_addr; 107 bus_dma_tag_t re_tx_list_tag; 108 bus_dmamap_t re_tx_list_map; 109 struct re_desc *re_tx_list; 110 bus_addr_t re_tx_list_addr; 111 }; 112 113 struct re_softc { 114 struct arpcom arpcom; /* interface info */ 115 #ifdef RE_DIAG 116 device_t re_dev; 117 #endif 118 bus_space_handle_t re_bhandle; /* bus space handle */ 119 bus_space_tag_t re_btag; /* bus space tag */ 120 struct resource *re_res; 121 struct resource *re_irq; 122 void *re_intrhand; 123 device_t re_miibus; 124 bus_dma_tag_t re_parent_tag; 125 bus_dma_tag_t re_tag; 126 uint8_t re_type; 127 int re_eecmd_read; 128 uint8_t re_stats_no_timeout; 129 int re_txthresh; 130 uint32_t re_hwrev; 131 struct re_list_data re_ldata; 132 struct callout re_timer; 133 struct mbuf *re_head; 134 struct mbuf *re_tail; 135 int re_drop_rxfrag; 136 uint32_t re_flags; /* see RE_F_ */ 137 uint32_t re_rxlenmask; 138 int re_txstart; 139 int re_testmode; 140 int suspended; /* 0 = normal 1 = suspended */ 141 int re_link; 142 int re_eewidth; 143 int re_swcsum_lim; 144 int re_maxmtu; 145 #ifdef DEVICE_POLLING 146 int rxcycles; 147 #endif 148 149 struct sysctl_ctx_list re_sysctl_ctx; 150 struct sysctl_oid *re_sysctl_tree; 151 uint16_t re_intrs; 152 uint16_t re_tx_ack; 153 154 #ifndef BURN_BRIDGES 155 uint32_t saved_maps[5]; /* pci data */ 156 uint32_t saved_biosaddr; 157 uint8_t saved_intline; 158 uint8_t saved_cachelnsz; 159 uint8_t saved_lattimer; 160 #endif 161 }; 162 163 #define RE_F_HASMPC 0x1 164 #define RE_F_PCIE 0x2 165 166 #define RE_TX_MODERATION_IS_ENABLED(sc) \ 167 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED) 168 169 #define RE_DISABLE_TX_MODERATION(sc) do { \ 170 (sc)->re_tx_ack = RE_ISR_TX_OK; \ 171 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \ 172 } while (0) 173 174 #define RE_ENABLE_TX_MODERATION(sc) do { \ 175 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \ 176 (sc)->re_intrs = RE_INTRS; \ 177 } while (0) 178 179 /* 180 * register space access macros 181 */ 182 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 183 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 184 #define CSR_WRITE_4(sc, reg, val) \ 185 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 186 #define CSR_WRITE_2(sc, reg, val) \ 187 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 188 #define CSR_WRITE_1(sc, reg, val) \ 189 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 190 191 #define CSR_READ_4(sc, reg) \ 192 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 193 #define CSR_READ_2(sc, reg) \ 194 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 195 #define CSR_READ_1(sc, reg) \ 196 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 197 198 #define CSR_SETBIT_1(sc, reg, val) \ 199 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 200 #define CSR_CLRBIT_1(sc, reg, val) \ 201 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 202