1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.13 2008/10/05 06:15:36 sephe Exp $ 37 */ 38 39 #define RE_RX_DESC_CNT_DEF 64 40 #define RE_TX_DESC_CNT_DEF 64 41 #define RE_RX_DESC_CNT_MAX 1024 42 #define RE_TX_DESC_CNT_MAX 1024 43 44 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc)) 45 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc)) 46 #define RE_RING_ALIGN 256 47 #define RE_IFQ_MAXLEN 512 48 #define RE_MAXSEGS 16 49 #define RE_TXDESC_SPARE 4 50 51 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt) 52 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt) 53 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 54 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 55 #define RE_PKTSZ(x) ((x)/* >> 3*/) 56 57 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 58 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 59 60 #define RE_JUMBO_FRAMELEN 7440 61 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 62 #define RE_FRAMELEN_2K 2048 63 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) 64 #define RE_SWCSUM_LIM_8169 2038 65 66 #define RE_TIMEOUT 1000 67 68 struct re_type { 69 uint16_t re_vid; 70 uint16_t re_did; 71 int re_basetype; 72 const char *re_name; 73 }; 74 75 struct re_hwrev { 76 uint32_t re_rev; 77 int re_type; /* RE_{8139CPLUS,8169} */ 78 uint32_t re_flags; /* see RE_F_ */ 79 int re_swcsum_lim; 80 int re_maxmtu; 81 }; 82 83 #define RE_8139CPLUS 3 84 #define RE_8169 4 85 86 struct re_dmaload_arg { 87 int re_nsegs; 88 bus_dma_segment_t *re_segs; 89 }; 90 91 struct re_list_data { 92 struct mbuf **re_tx_mbuf; 93 struct mbuf **re_rx_mbuf; 94 bus_addr_t *re_rx_paddr; 95 int re_tx_prodidx; 96 int re_rx_prodidx; 97 int re_tx_considx; 98 int re_tx_free; 99 bus_dmamap_t *re_tx_dmamap; 100 bus_dmamap_t *re_rx_dmamap; 101 bus_dmamap_t re_rx_spare; 102 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 103 bus_dma_tag_t re_stag; /* stats mapping tag */ 104 bus_dmamap_t re_smap; /* stats map */ 105 struct re_stats *re_stats; 106 bus_addr_t re_stats_addr; 107 bus_dma_tag_t re_rx_list_tag; 108 bus_dmamap_t re_rx_list_map; 109 struct re_desc *re_rx_list; 110 bus_addr_t re_rx_list_addr; 111 bus_dma_tag_t re_tx_list_tag; 112 bus_dmamap_t re_tx_list_map; 113 struct re_desc *re_tx_list; 114 bus_addr_t re_tx_list_addr; 115 }; 116 117 struct re_softc { 118 struct arpcom arpcom; /* interface info */ 119 #ifdef RE_DIAG 120 device_t re_dev; 121 #endif 122 bus_space_handle_t re_bhandle; /* bus space handle */ 123 bus_space_tag_t re_btag; /* bus space tag */ 124 struct resource *re_res; 125 struct resource *re_irq; 126 void *re_intrhand; 127 device_t re_miibus; 128 bus_dma_tag_t re_parent_tag; 129 bus_dma_tag_t re_tag; 130 uint8_t re_type; 131 int re_eecmd_read; 132 uint8_t re_stats_no_timeout; 133 int re_txthresh; 134 uint32_t re_hwrev; 135 struct re_list_data re_ldata; 136 struct callout re_timer; 137 struct mbuf *re_head; 138 struct mbuf *re_tail; 139 int re_drop_rxfrag; 140 uint32_t re_flags; /* see RE_F_ */ 141 uint32_t re_rxlenmask; 142 int re_txstart; 143 int re_testmode; 144 int suspended; /* 0 = normal 1 = suspended */ 145 int re_link; 146 int re_eewidth; 147 int re_swcsum_lim; 148 int re_maxmtu; 149 int re_rx_desc_cnt; 150 int re_tx_desc_cnt; 151 int re_bus_speed; 152 #ifdef DEVICE_POLLING 153 int rxcycles; 154 #endif 155 156 struct sysctl_ctx_list re_sysctl_ctx; 157 struct sysctl_oid *re_sysctl_tree; 158 uint16_t re_intrs; 159 uint16_t re_tx_ack; 160 161 #ifndef BURN_BRIDGES 162 uint32_t saved_maps[5]; /* pci data */ 163 uint32_t saved_biosaddr; 164 uint8_t saved_intline; 165 uint8_t saved_cachelnsz; 166 uint8_t saved_lattimer; 167 #endif 168 }; 169 170 #define RE_F_HASMPC 0x1 171 #define RE_F_PCIE 0x2 172 #define RE_F_PCI64 0x4 173 174 #define RE_TX_MODERATION_IS_ENABLED(sc) \ 175 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED) 176 177 #define RE_DISABLE_TX_MODERATION(sc) do { \ 178 (sc)->re_tx_ack = RE_ISR_TX_OK; \ 179 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \ 180 } while (0) 181 182 #define RE_ENABLE_TX_MODERATION(sc) do { \ 183 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \ 184 (sc)->re_intrs = RE_INTRS; \ 185 } while (0) 186 187 /* 188 * register space access macros 189 */ 190 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 191 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 192 #define CSR_WRITE_4(sc, reg, val) \ 193 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 194 #define CSR_WRITE_2(sc, reg, val) \ 195 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 196 #define CSR_WRITE_1(sc, reg, val) \ 197 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 198 199 #define CSR_READ_4(sc, reg) \ 200 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 201 #define CSR_READ_2(sc, reg) \ 202 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 203 #define CSR_READ_1(sc, reg) \ 204 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 205 206 #define CSR_SETBIT_1(sc, reg, val) \ 207 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 208 #define CSR_CLRBIT_1(sc, reg, val) \ 209 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 210