1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.1 2006/11/14 13:35:49 sephe Exp $ 37 */ 38 39 struct re_chain_data { 40 uint16_t cur_rx; 41 caddr_t re_rx_buf; 42 caddr_t re_rx_buf_ptr; 43 bus_dmamap_t re_rx_dmamap; 44 45 struct mbuf *re_tx_chain[RE_TX_LIST_CNT]; 46 bus_dmamap_t re_tx_dmamap[RE_TX_LIST_CNT]; 47 uint8_t last_tx; 48 uint8_t cur_tx; 49 }; 50 51 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT) 52 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0) 53 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0) 54 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx]) 55 #define RE_CUR_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.cur_tx]) 56 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0) 57 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0) 58 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx]) 59 #define RE_LAST_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.last_tx]) 60 61 struct re_type { 62 uint16_t re_vid; 63 uint16_t re_did; 64 int re_basetype; 65 const char *re_name; 66 }; 67 68 struct re_hwrev { 69 uint32_t re_rev; 70 int re_type; 71 const char *re_desc; 72 }; 73 74 #define RE_8139CPLUS 3 75 #define RE_8169 4 76 77 #define RE_ISCPLUS(x) ((x)->re_type == RE_8139CPLUS || \ 78 (x)->re_type == RE_8169) 79 80 struct re_softc; 81 82 struct re_dmaload_arg { 83 struct re_softc *sc; 84 int re_idx; 85 int re_maxsegs; 86 uint32_t re_flags; 87 struct re_desc *re_ring; 88 }; 89 90 struct re_list_data { 91 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT]; 92 struct mbuf *re_rx_mbuf[RE_TX_DESC_CNT]; 93 int re_tx_prodidx; 94 int re_rx_prodidx; 95 int re_tx_considx; 96 int re_tx_free; 97 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT]; 98 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT]; 99 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 100 bus_dma_tag_t re_stag; /* stats mapping tag */ 101 bus_dmamap_t re_smap; /* stats map */ 102 struct re_stats *re_stats; 103 bus_addr_t re_stats_addr; 104 bus_dma_tag_t re_rx_list_tag; 105 bus_dmamap_t re_rx_list_map; 106 struct re_desc *re_rx_list; 107 bus_addr_t re_rx_list_addr; 108 bus_dma_tag_t re_tx_list_tag; 109 bus_dmamap_t re_tx_list_map; 110 struct re_desc *re_tx_list; 111 bus_addr_t re_tx_list_addr; 112 }; 113 114 struct re_softc { 115 struct arpcom arpcom; /* interface info */ 116 #ifdef RE_DIAG 117 device_t re_dev; 118 #endif 119 bus_space_handle_t re_bhandle; /* bus space handle */ 120 bus_space_tag_t re_btag; /* bus space tag */ 121 struct resource *re_res; 122 struct resource *re_irq; 123 void *re_intrhand; 124 device_t re_miibus; 125 bus_dma_tag_t re_parent_tag; 126 bus_dma_tag_t re_tag; 127 uint8_t re_type; 128 int re_eecmd_read; 129 uint8_t re_stats_no_timeout; 130 int re_txthresh; 131 struct re_chain_data re_cdata; 132 struct re_list_data re_ldata; 133 struct callout re_timer; 134 struct mbuf *re_head; 135 struct mbuf *re_tail; 136 uint32_t re_hwrev; 137 uint32_t re_rxlenmask; 138 int re_txstart; 139 int re_testmode; 140 int suspended; /* 0 = normal 1 = suspended */ 141 int re_link; 142 int re_eewidth; 143 #ifdef DEVICE_POLLING 144 int rxcycles; 145 #endif 146 147 struct sysctl_ctx_list re_sysctl_ctx; 148 struct sysctl_oid *re_sysctl_tree; 149 uint16_t re_intrs; 150 uint16_t re_tx_ack; 151 152 #ifndef BURN_BRIDGES 153 uint32_t saved_maps[5]; /* pci data */ 154 uint32_t saved_biosaddr; 155 uint8_t saved_intline; 156 uint8_t saved_cachelnsz; 157 uint8_t saved_lattimer; 158 #endif 159 }; 160 161 #define RE_TX_MODERATION_IS_ENABLED(sc) \ 162 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED) 163 164 #define RE_DISABLE_TX_MODERATION(sc) do { \ 165 (sc)->re_tx_ack = RE_ISR_TX_OK; \ 166 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \ 167 } while (0) 168 169 #define RE_ENABLE_TX_MODERATION(sc) do { \ 170 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \ 171 (sc)->re_intrs = RE_INTRS; \ 172 } while (0) 173 174 /* 175 * register space access macros 176 */ 177 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 178 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 179 #define CSR_WRITE_4(sc, reg, val) \ 180 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 181 #define CSR_WRITE_2(sc, reg, val) \ 182 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 183 #define CSR_WRITE_1(sc, reg, val) \ 184 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 185 186 #define CSR_READ_4(sc, reg) \ 187 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 188 #define CSR_READ_2(sc, reg) \ 189 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 190 #define CSR_READ_1(sc, reg) \ 191 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 192 193 #define CSR_SETBIT_1(sc, reg, val) \ 194 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 195 #define CSR_CLRBIT_1(sc, reg, val) \ 196 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 197