1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.26 2008/10/16 12:46:40 sephe Exp $ 37 */ 38 39 #define RE_RX_DESC_CNT_8139CP 64 40 #define RE_TX_DESC_CNT_8139CP 64 41 42 #define RE_RX_DESC_CNT_DEF 256 43 #define RE_TX_DESC_CNT_DEF 256 44 #define RE_RX_DESC_CNT_MAX 1024 45 #define RE_TX_DESC_CNT_MAX 1024 46 47 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc)) 48 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc)) 49 #define RE_RING_ALIGN 256 50 #define RE_IFQ_MAXLEN 512 51 #define RE_MAXSEGS 16 52 #define RE_TXDESC_SPARE 4 53 54 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt) 55 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt) 56 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 57 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 58 #define RE_PKTSZ(x) ((x)/* >> 3*/) 59 60 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 61 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 62 63 #define RE_JUMBO_FRAMELEN 7440 64 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 65 #define RE_FRAMELEN_2K 2048 66 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) 67 #define RE_SWCSUM_LIM_8169 2038 68 69 #define RE_TIMEOUT 1000 70 71 struct re_hwrev { 72 uint32_t re_hwrev; 73 uint32_t re_macver; /* see RE_MACVER_ */ 74 uint32_t re_caps; /* see RE_C_ */ 75 }; 76 77 #define RE_MACVER_UNKN 0 78 #define RE_MACVER_03 0x03 79 #define RE_MACVER_04 0x04 80 #define RE_MACVER_05 0x05 81 #define RE_MACVER_06 0x06 82 #define RE_MACVER_11 0x11 83 #define RE_MACVER_12 0x12 84 #define RE_MACVER_13 0x13 85 #define RE_MACVER_14 0x14 86 #define RE_MACVER_15 0x15 87 #define RE_MACVER_16 0x16 88 #define RE_MACVER_21 0x21 89 #define RE_MACVER_22 0x22 90 #define RE_MACVER_23 0x23 91 #define RE_MACVER_24 0x24 92 #define RE_MACVER_25 0x25 93 #define RE_MACVER_26 0x26 94 #define RE_MACVER_27 0x27 95 #define RE_MACVER_28 0x28 96 #define RE_MACVER_29 0x29 97 #define RE_MACVER_2A 0x2a 98 #define RE_MACVER_2B 0x2b 99 100 struct re_dmaload_arg { 101 int re_nsegs; 102 bus_dma_segment_t *re_segs; 103 }; 104 105 struct re_list_data { 106 struct mbuf **re_tx_mbuf; 107 struct mbuf **re_rx_mbuf; 108 bus_addr_t *re_rx_paddr; 109 int re_tx_prodidx; 110 int re_rx_prodidx; 111 int re_tx_considx; 112 int re_tx_free; 113 bus_dmamap_t *re_tx_dmamap; 114 bus_dmamap_t *re_rx_dmamap; 115 bus_dmamap_t re_rx_spare; 116 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 117 bus_dma_tag_t re_stag; /* stats mapping tag */ 118 bus_dmamap_t re_smap; /* stats map */ 119 struct re_stats *re_stats; 120 bus_addr_t re_stats_addr; 121 bus_dma_tag_t re_rx_list_tag; 122 bus_dmamap_t re_rx_list_map; 123 struct re_desc *re_rx_list; 124 bus_addr_t re_rx_list_addr; 125 bus_dma_tag_t re_tx_list_tag; 126 bus_dmamap_t re_tx_list_map; 127 struct re_desc *re_tx_list; 128 bus_addr_t re_tx_list_addr; 129 }; 130 131 struct re_softc { 132 struct arpcom arpcom; /* interface info */ 133 device_t re_dev; 134 bus_space_handle_t re_bhandle; /* bus space handle */ 135 bus_space_tag_t re_btag; /* bus space tag */ 136 struct resource *re_res; 137 struct resource *re_irq; 138 void *re_intrhand; 139 device_t re_miibus; 140 bus_dma_tag_t re_parent_tag; 141 bus_dma_tag_t re_tag; 142 int re_eecmd_read; 143 uint8_t re_stats_no_timeout; 144 int re_txthresh; 145 uint32_t re_hwrev; 146 struct re_list_data re_ldata; 147 struct callout re_timer; 148 struct mbuf *re_head; 149 struct mbuf *re_tail; 150 int re_drop_rxfrag; 151 uint32_t re_caps; /* see RE_C_ */ 152 uint32_t re_macver; /* see RE_MACVER_ */ 153 uint32_t re_rxlenmask; 154 int re_txstart; 155 int re_testmode; 156 int suspended; /* 0 = normal 1 = suspended */ 157 int re_link; 158 int re_eewidth; 159 int re_swcsum_lim; 160 int re_maxmtu; 161 int re_rx_desc_cnt; 162 int re_tx_desc_cnt; 163 int re_bus_speed; 164 int rxcycles; 165 166 uint32_t re_flags; /* see RE_F_ */ 167 168 struct sysctl_ctx_list re_sysctl_ctx; 169 struct sysctl_oid *re_sysctl_tree; 170 uint16_t re_intrs; 171 uint16_t re_tx_ack; 172 uint16_t re_rx_ack; 173 int re_tx_time; 174 int re_rx_time; 175 int re_sim_time; 176 int re_imtype; /* see RE_IMTYPE_ */ 177 178 uint32_t saved_maps[5]; /* pci data */ 179 uint32_t saved_biosaddr; 180 uint8_t saved_intline; 181 uint8_t saved_cachelnsz; 182 uint8_t saved_lattimer; 183 }; 184 185 #define RE_C_PCIE 0x1 /* PCI-E */ 186 #define RE_C_PCI64 0x2 /* PCI-X */ 187 #define RE_C_HWIM 0x4 /* hardware interrupt moderation */ 188 #define RE_C_HWCSUM 0x8 /* hardware csum offload */ 189 #define RE_C_JUMBO 0x10 /* jumbo frame */ 190 #define RE_C_8139CP 0x20 /* is 8139C+ */ 191 #define RE_C_MAC2 0x40 /* MAC style 2 */ 192 #define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */ 193 #define RE_C_8169 0x100 /* is 8110/8169 */ 194 #define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */ 195 196 #define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP) 197 198 /* Interrupt moderation types */ 199 #define RE_IMTYPE_NONE 0 200 #define RE_IMTYPE_SIM 1 /* simulated */ 201 #define RE_IMTYPE_HW 2 /* hardware based */ 202 203 #define RE_F_TIMER_INTR 0x1 204 205 /* 206 * register space access macros 207 */ 208 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 209 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 210 #define CSR_WRITE_4(sc, reg, val) \ 211 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 212 #define CSR_WRITE_2(sc, reg, val) \ 213 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 214 #define CSR_WRITE_1(sc, reg, val) \ 215 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 216 217 #define CSR_READ_4(sc, reg) \ 218 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 219 #define CSR_READ_2(sc, reg) \ 220 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 221 #define CSR_READ_1(sc, reg) \ 222 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 223 224 #define CSR_SETBIT_1(sc, reg, val) \ 225 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 226 #define CSR_CLRBIT_1(sc, reg, val) \ 227 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 228