1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.11 2008/10/05 02:13:06 sephe Exp $ 37 */ 38 39 #define RE_RX_DESC_CNT 64 40 #define RE_TX_DESC_CNT 64 41 #define RE_RX_LIST_SZ (RE_RX_DESC_CNT * sizeof(struct re_desc)) 42 #define RE_TX_LIST_SZ (RE_TX_DESC_CNT * sizeof(struct re_desc)) 43 #define RE_RING_ALIGN 256 44 #define RE_IFQ_MAXLEN 512 45 #define RE_MAXSEGS 16 46 #define RE_TXDESC_SPARE 4 47 48 #define RE_RXDESC_INC(x) (x = (x + 1) % RE_RX_DESC_CNT) 49 #define RE_TXDESC_INC(x) (x = (x + 1) % RE_TX_DESC_CNT) 50 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 51 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 52 #define RE_PKTSZ(x) ((x)/* >> 3*/) 53 54 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 55 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 56 57 #define RE_JUMBO_FRAMELEN 7440 58 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 59 #define RE_FRAMELEN_2K 2048 60 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) 61 #define RE_SWCSUM_LIM_8169 2038 62 63 #define RE_TIMEOUT 1000 64 65 struct re_type { 66 uint16_t re_vid; 67 uint16_t re_did; 68 int re_basetype; 69 const char *re_name; 70 }; 71 72 struct re_hwrev { 73 uint32_t re_rev; 74 int re_type; /* RE_{8139CPLUS,8169} */ 75 uint32_t re_flags; /* see RE_F_ */ 76 int re_swcsum_lim; 77 int re_maxmtu; 78 }; 79 80 #define RE_8139CPLUS 3 81 #define RE_8169 4 82 83 struct re_dmaload_arg { 84 int re_nsegs; 85 bus_dma_segment_t *re_segs; 86 }; 87 88 struct re_list_data { 89 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT]; 90 struct mbuf *re_rx_mbuf[RE_RX_DESC_CNT]; 91 bus_addr_t re_rx_paddr[RE_RX_DESC_CNT]; 92 int re_tx_prodidx; 93 int re_rx_prodidx; 94 int re_tx_considx; 95 int re_tx_free; 96 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT]; 97 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT]; 98 bus_dmamap_t re_rx_spare; 99 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 100 bus_dma_tag_t re_stag; /* stats mapping tag */ 101 bus_dmamap_t re_smap; /* stats map */ 102 struct re_stats *re_stats; 103 bus_addr_t re_stats_addr; 104 bus_dma_tag_t re_rx_list_tag; 105 bus_dmamap_t re_rx_list_map; 106 struct re_desc *re_rx_list; 107 bus_addr_t re_rx_list_addr; 108 bus_dma_tag_t re_tx_list_tag; 109 bus_dmamap_t re_tx_list_map; 110 struct re_desc *re_tx_list; 111 bus_addr_t re_tx_list_addr; 112 }; 113 114 struct re_softc { 115 struct arpcom arpcom; /* interface info */ 116 #ifdef RE_DIAG 117 device_t re_dev; 118 #endif 119 bus_space_handle_t re_bhandle; /* bus space handle */ 120 bus_space_tag_t re_btag; /* bus space tag */ 121 struct resource *re_res; 122 struct resource *re_irq; 123 void *re_intrhand; 124 device_t re_miibus; 125 bus_dma_tag_t re_parent_tag; 126 bus_dma_tag_t re_tag; 127 uint8_t re_type; 128 int re_eecmd_read; 129 uint8_t re_stats_no_timeout; 130 int re_txthresh; 131 uint32_t re_hwrev; 132 struct re_list_data re_ldata; 133 struct callout re_timer; 134 struct mbuf *re_head; 135 struct mbuf *re_tail; 136 int re_drop_rxfrag; 137 uint32_t re_flags; /* see RE_F_ */ 138 uint32_t re_rxlenmask; 139 int re_txstart; 140 int re_testmode; 141 int suspended; /* 0 = normal 1 = suspended */ 142 int re_link; 143 int re_eewidth; 144 int re_swcsum_lim; 145 int re_maxmtu; 146 #ifdef DEVICE_POLLING 147 int rxcycles; 148 #endif 149 150 struct sysctl_ctx_list re_sysctl_ctx; 151 struct sysctl_oid *re_sysctl_tree; 152 uint16_t re_intrs; 153 uint16_t re_tx_ack; 154 155 #ifndef BURN_BRIDGES 156 uint32_t saved_maps[5]; /* pci data */ 157 uint32_t saved_biosaddr; 158 uint8_t saved_intline; 159 uint8_t saved_cachelnsz; 160 uint8_t saved_lattimer; 161 #endif 162 }; 163 164 #define RE_F_HASMPC 0x1 165 #define RE_F_PCIE 0x2 166 167 #define RE_TX_MODERATION_IS_ENABLED(sc) \ 168 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED) 169 170 #define RE_DISABLE_TX_MODERATION(sc) do { \ 171 (sc)->re_tx_ack = RE_ISR_TX_OK; \ 172 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \ 173 } while (0) 174 175 #define RE_ENABLE_TX_MODERATION(sc) do { \ 176 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \ 177 (sc)->re_intrs = RE_INTRS; \ 178 } while (0) 179 180 /* 181 * register space access macros 182 */ 183 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 184 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 185 #define CSR_WRITE_4(sc, reg, val) \ 186 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 187 #define CSR_WRITE_2(sc, reg, val) \ 188 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 189 #define CSR_WRITE_1(sc, reg, val) \ 190 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 191 192 #define CSR_READ_4(sc, reg) \ 193 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 194 #define CSR_READ_2(sc, reg) \ 195 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 196 #define CSR_READ_1(sc, reg) \ 197 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 198 199 #define CSR_SETBIT_1(sc, reg, val) \ 200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 201 #define CSR_CLRBIT_1(sc, reg, val) \ 202 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 203