1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_ifpoll.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_poll.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct re_type { 164 uint16_t re_vid; 165 uint16_t re_did; 166 const char *re_name; 167 } re_devs[] = { 168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 175 "RealTek 810x PCIe 10/100baseTX" }, 176 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 178 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 179 180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 181 "RealTek 8110/8169 Gigabit Ethernet" }, 182 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 187 "Corega CG-LAPCIGT Gigabit Ethernet" }, 188 189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" }, 191 192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 193 "US Robotics 997902 Gigabit Ethernet" }, 194 195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 196 "TTTech MC322 Gigabit Ethernet" }, 197 198 { 0, 0, NULL } 199 }; 200 201 static const struct re_hwrev re_hwrevs[] = { 202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 204 205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 206 RE_C_HWCSUM | RE_C_8169 }, 207 208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 209 RE_C_HWCSUM | RE_C_8169 }, 210 211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 212 RE_C_HWCSUM | RE_C_8169 }, 213 214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 216 217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 219 220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 222 223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 225 226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 228 229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 231 232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K, 245 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 246 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 247 248 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K, 249 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 250 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 251 252 { RE_HWREV_8168F, RE_MACVER_UNKN, RE_MTU_9K, 253 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 254 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 255 256 { RE_HWREV_8111F, RE_MACVER_UNKN, RE_MTU_9K, 257 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 258 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 259 260 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 261 RE_C_HWCSUM | RE_C_FASTE }, 262 263 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 264 RE_C_HWCSUM | RE_C_FASTE }, 265 266 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 267 RE_C_HWCSUM | RE_C_FASTE }, 268 269 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 270 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 271 RE_C_FASTE }, 272 273 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 274 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 275 RE_C_FASTE }, 276 277 { RE_HWREV_8105E, RE_MACVER_UNKN, ETHERMTU, 278 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 279 RE_C_STOP_RXTX | RE_C_FASTE }, 280 281 { RE_HWREV_NULL, 0, 0, 0 } 282 }; 283 284 static int re_probe(device_t); 285 static int re_attach(device_t); 286 static int re_detach(device_t); 287 static int re_suspend(device_t); 288 static int re_resume(device_t); 289 static void re_shutdown(device_t); 290 291 static int re_allocmem(device_t); 292 static void re_freemem(device_t); 293 static void re_freebufmem(struct re_softc *, int, int); 294 static int re_encap(struct re_softc *, struct mbuf **, int *); 295 static int re_newbuf_std(struct re_softc *, int, int); 296 static int re_newbuf_jumbo(struct re_softc *, int, int); 297 static void re_setup_rxdesc(struct re_softc *, int); 298 static int re_rx_list_init(struct re_softc *); 299 static int re_tx_list_init(struct re_softc *); 300 static int re_rxeof(struct re_softc *); 301 static int re_txeof(struct re_softc *); 302 static int re_tx_collect(struct re_softc *); 303 static void re_intr(void *); 304 static void re_tick(void *); 305 static void re_tick_serialized(void *); 306 307 static void re_start(struct ifnet *, struct ifaltq_subque *); 308 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 309 static void re_init(void *); 310 static void re_stop(struct re_softc *); 311 static void re_watchdog(struct ifnet *); 312 static int re_ifmedia_upd(struct ifnet *); 313 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 314 315 static void re_eeprom_putbyte(struct re_softc *, int); 316 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 317 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 318 static void re_get_eewidth(struct re_softc *); 319 320 static int re_gmii_readreg(device_t, int, int); 321 static int re_gmii_writereg(device_t, int, int, int); 322 323 static int re_miibus_readreg(device_t, int, int); 324 static int re_miibus_writereg(device_t, int, int, int); 325 static void re_miibus_statchg(device_t); 326 327 static void re_setmulti(struct re_softc *); 328 static void re_reset(struct re_softc *, int); 329 static void re_get_eaddr(struct re_softc *, uint8_t *); 330 331 static void re_setup_hw_im(struct re_softc *); 332 static void re_setup_sim_im(struct re_softc *); 333 static void re_disable_hw_im(struct re_softc *); 334 static void re_disable_sim_im(struct re_softc *); 335 static void re_config_imtype(struct re_softc *, int); 336 static void re_setup_intr(struct re_softc *, int, int); 337 338 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 339 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 340 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 341 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 342 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 343 344 static int re_jpool_alloc(struct re_softc *); 345 static void re_jpool_free(struct re_softc *); 346 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 347 static void re_jbuf_free(void *); 348 static void re_jbuf_ref(void *); 349 350 #ifdef RE_DIAG 351 static int re_diag(struct re_softc *); 352 #endif 353 354 #ifdef IFPOLL_ENABLE 355 static void re_npoll(struct ifnet *, struct ifpoll_info *); 356 static void re_npoll_compat(struct ifnet *, void *, int); 357 #endif 358 359 static device_method_t re_methods[] = { 360 /* Device interface */ 361 DEVMETHOD(device_probe, re_probe), 362 DEVMETHOD(device_attach, re_attach), 363 DEVMETHOD(device_detach, re_detach), 364 DEVMETHOD(device_suspend, re_suspend), 365 DEVMETHOD(device_resume, re_resume), 366 DEVMETHOD(device_shutdown, re_shutdown), 367 368 /* bus interface */ 369 DEVMETHOD(bus_print_child, bus_generic_print_child), 370 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 371 372 /* MII interface */ 373 DEVMETHOD(miibus_readreg, re_miibus_readreg), 374 DEVMETHOD(miibus_writereg, re_miibus_writereg), 375 DEVMETHOD(miibus_statchg, re_miibus_statchg), 376 377 DEVMETHOD_END 378 }; 379 380 static driver_t re_driver = { 381 "re", 382 re_methods, 383 sizeof(struct re_softc) 384 }; 385 386 static devclass_t re_devclass; 387 388 DECLARE_DUMMY_MODULE(if_re); 389 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 390 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 391 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 392 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 393 394 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 395 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 396 static int re_msi_enable = 1; 397 398 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 399 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 400 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 401 402 #define EE_SET(x) \ 403 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 404 405 #define EE_CLR(x) \ 406 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 407 408 static __inline void 409 re_free_rxchain(struct re_softc *sc) 410 { 411 if (sc->re_head != NULL) { 412 m_freem(sc->re_head); 413 sc->re_head = sc->re_tail = NULL; 414 } 415 } 416 417 /* 418 * Send a read command and address to the EEPROM, check for ACK. 419 */ 420 static void 421 re_eeprom_putbyte(struct re_softc *sc, int addr) 422 { 423 int d, i; 424 425 d = addr | (RE_9346_READ << sc->re_eewidth); 426 427 /* 428 * Feed in each bit and strobe the clock. 429 */ 430 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 431 if (d & i) 432 EE_SET(RE_EE_DATAIN); 433 else 434 EE_CLR(RE_EE_DATAIN); 435 DELAY(100); 436 EE_SET(RE_EE_CLK); 437 DELAY(150); 438 EE_CLR(RE_EE_CLK); 439 DELAY(100); 440 } 441 } 442 443 /* 444 * Read a word of data stored in the EEPROM at address 'addr.' 445 */ 446 static void 447 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 448 { 449 int i; 450 uint16_t word = 0; 451 452 /* 453 * Send address of word we want to read. 454 */ 455 re_eeprom_putbyte(sc, addr); 456 457 /* 458 * Start reading bits from EEPROM. 459 */ 460 for (i = 0x8000; i != 0; i >>= 1) { 461 EE_SET(RE_EE_CLK); 462 DELAY(100); 463 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 464 word |= i; 465 EE_CLR(RE_EE_CLK); 466 DELAY(100); 467 } 468 469 *dest = word; 470 } 471 472 /* 473 * Read a sequence of words from the EEPROM. 474 */ 475 static void 476 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 477 { 478 int i; 479 uint16_t word = 0, *ptr; 480 481 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 482 DELAY(100); 483 484 for (i = 0; i < cnt; i++) { 485 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 486 re_eeprom_getword(sc, off + i, &word); 487 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 488 ptr = (uint16_t *)(dest + (i * 2)); 489 *ptr = word; 490 } 491 492 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 493 } 494 495 static void 496 re_get_eewidth(struct re_softc *sc) 497 { 498 uint16_t re_did = 0; 499 500 sc->re_eewidth = 6; 501 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 502 if (re_did != 0x8129) 503 sc->re_eewidth = 8; 504 } 505 506 static int 507 re_gmii_readreg(device_t dev, int phy, int reg) 508 { 509 struct re_softc *sc = device_get_softc(dev); 510 u_int32_t rval; 511 int i; 512 513 if (phy != 1) 514 return(0); 515 516 /* Let the rgephy driver read the GMEDIASTAT register */ 517 518 if (reg == RE_GMEDIASTAT) 519 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 520 521 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 522 DELAY(1000); 523 524 for (i = 0; i < RE_TIMEOUT; i++) { 525 rval = CSR_READ_4(sc, RE_PHYAR); 526 if (rval & RE_PHYAR_BUSY) 527 break; 528 DELAY(100); 529 } 530 531 if (i == RE_TIMEOUT) { 532 device_printf(dev, "PHY read failed\n"); 533 return(0); 534 } 535 536 return(rval & RE_PHYAR_PHYDATA); 537 } 538 539 static int 540 re_gmii_writereg(device_t dev, int phy, int reg, int data) 541 { 542 struct re_softc *sc = device_get_softc(dev); 543 uint32_t rval; 544 int i; 545 546 CSR_WRITE_4(sc, RE_PHYAR, 547 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 548 DELAY(1000); 549 550 for (i = 0; i < RE_TIMEOUT; i++) { 551 rval = CSR_READ_4(sc, RE_PHYAR); 552 if ((rval & RE_PHYAR_BUSY) == 0) 553 break; 554 DELAY(100); 555 } 556 557 if (i == RE_TIMEOUT) 558 device_printf(dev, "PHY write failed\n"); 559 560 return(0); 561 } 562 563 static int 564 re_miibus_readreg(device_t dev, int phy, int reg) 565 { 566 struct re_softc *sc = device_get_softc(dev); 567 uint16_t rval = 0; 568 uint16_t re8139_reg = 0; 569 570 if (!RE_IS_8139CP(sc)) { 571 rval = re_gmii_readreg(dev, phy, reg); 572 return(rval); 573 } 574 575 /* Pretend the internal PHY is only at address 0 */ 576 if (phy) 577 return(0); 578 579 switch(reg) { 580 case MII_BMCR: 581 re8139_reg = RE_BMCR; 582 break; 583 case MII_BMSR: 584 re8139_reg = RE_BMSR; 585 break; 586 case MII_ANAR: 587 re8139_reg = RE_ANAR; 588 break; 589 case MII_ANER: 590 re8139_reg = RE_ANER; 591 break; 592 case MII_ANLPAR: 593 re8139_reg = RE_LPAR; 594 break; 595 case MII_PHYIDR1: 596 case MII_PHYIDR2: 597 return(0); 598 /* 599 * Allow the rlphy driver to read the media status 600 * register. If we have a link partner which does not 601 * support NWAY, this is the register which will tell 602 * us the results of parallel detection. 603 */ 604 case RE_MEDIASTAT: 605 return(CSR_READ_1(sc, RE_MEDIASTAT)); 606 default: 607 device_printf(dev, "bad phy register\n"); 608 return(0); 609 } 610 rval = CSR_READ_2(sc, re8139_reg); 611 if (re8139_reg == RE_BMCR) { 612 /* 8139C+ has different bit layout. */ 613 rval &= ~(BMCR_LOOP | BMCR_ISO); 614 } 615 return(rval); 616 } 617 618 static int 619 re_miibus_writereg(device_t dev, int phy, int reg, int data) 620 { 621 struct re_softc *sc= device_get_softc(dev); 622 u_int16_t re8139_reg = 0; 623 624 if (!RE_IS_8139CP(sc)) 625 return(re_gmii_writereg(dev, phy, reg, data)); 626 627 /* Pretend the internal PHY is only at address 0 */ 628 if (phy) 629 return(0); 630 631 switch(reg) { 632 case MII_BMCR: 633 re8139_reg = RE_BMCR; 634 /* 8139C+ has different bit layout. */ 635 data &= ~(BMCR_LOOP | BMCR_ISO); 636 break; 637 case MII_BMSR: 638 re8139_reg = RE_BMSR; 639 break; 640 case MII_ANAR: 641 re8139_reg = RE_ANAR; 642 break; 643 case MII_ANER: 644 re8139_reg = RE_ANER; 645 break; 646 case MII_ANLPAR: 647 re8139_reg = RE_LPAR; 648 break; 649 case MII_PHYIDR1: 650 case MII_PHYIDR2: 651 return(0); 652 default: 653 device_printf(dev, "bad phy register\n"); 654 return(0); 655 } 656 CSR_WRITE_2(sc, re8139_reg, data); 657 return(0); 658 } 659 660 static void 661 re_miibus_statchg(device_t dev) 662 { 663 } 664 665 /* 666 * Program the 64-bit multicast hash filter. 667 */ 668 static void 669 re_setmulti(struct re_softc *sc) 670 { 671 struct ifnet *ifp = &sc->arpcom.ac_if; 672 int h = 0; 673 uint32_t hashes[2] = { 0, 0 }; 674 struct ifmultiaddr *ifma; 675 uint32_t rxfilt; 676 int mcnt = 0; 677 678 rxfilt = CSR_READ_4(sc, RE_RXCFG); 679 680 /* Set the individual bit to receive frames for this host only. */ 681 rxfilt |= RE_RXCFG_RX_INDIV; 682 /* Set capture broadcast bit to capture broadcast frames. */ 683 rxfilt |= RE_RXCFG_RX_BROAD; 684 685 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 686 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 687 rxfilt |= RE_RXCFG_RX_MULTI; 688 689 /* If we want promiscuous mode, set the allframes bit. */ 690 if (ifp->if_flags & IFF_PROMISC) 691 rxfilt |= RE_RXCFG_RX_ALLPHYS; 692 693 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 694 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 695 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 696 return; 697 } 698 699 /* first, zot all the existing hash bits */ 700 CSR_WRITE_4(sc, RE_MAR0, 0); 701 CSR_WRITE_4(sc, RE_MAR4, 0); 702 703 /* now program new ones */ 704 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 705 if (ifma->ifma_addr->sa_family != AF_LINK) 706 continue; 707 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 708 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 709 if (h < 32) 710 hashes[0] |= (1 << h); 711 else 712 hashes[1] |= (1 << (h - 32)); 713 mcnt++; 714 } 715 716 if (mcnt) 717 rxfilt |= RE_RXCFG_RX_MULTI; 718 else 719 rxfilt &= ~RE_RXCFG_RX_MULTI; 720 721 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 722 723 /* 724 * For some unfathomable reason, RealTek decided to reverse 725 * the order of the multicast hash registers in the PCI Express 726 * parts. This means we have to write the hash pattern in reverse 727 * order for those devices. 728 */ 729 if (sc->re_caps & RE_C_PCIE) { 730 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 731 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 732 } else { 733 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 734 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 735 } 736 } 737 738 static void 739 re_reset(struct re_softc *sc, int running) 740 { 741 int i; 742 743 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 744 CSR_WRITE_1(sc, RE_COMMAND, 745 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 746 DELAY(100); 747 } 748 749 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 750 751 for (i = 0; i < RE_TIMEOUT; i++) { 752 DELAY(10); 753 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 754 break; 755 } 756 if (i == RE_TIMEOUT) 757 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 758 } 759 760 #ifdef RE_DIAG 761 /* 762 * The following routine is designed to test for a defect on some 763 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 764 * lines connected to the bus, however for a 32-bit only card, they 765 * should be pulled high. The result of this defect is that the 766 * NIC will not work right if you plug it into a 64-bit slot: DMA 767 * operations will be done with 64-bit transfers, which will fail 768 * because the 64-bit data lines aren't connected. 769 * 770 * There's no way to work around this (short of talking a soldering 771 * iron to the board), however we can detect it. The method we use 772 * here is to put the NIC into digital loopback mode, set the receiver 773 * to promiscuous mode, and then try to send a frame. We then compare 774 * the frame data we sent to what was received. If the data matches, 775 * then the NIC is working correctly, otherwise we know the user has 776 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 777 * slot. In the latter case, there's no way the NIC can work correctly, 778 * so we print out a message on the console and abort the device attach. 779 */ 780 781 static int 782 re_diag(struct re_softc *sc) 783 { 784 struct ifnet *ifp = &sc->arpcom.ac_if; 785 struct mbuf *m0; 786 struct ether_header *eh; 787 struct re_desc *cur_rx; 788 uint16_t status; 789 int total_len, i, error = 0, phyaddr; 790 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 791 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 792 char ethstr[2][ETHER_ADDRSTRLEN + 1]; 793 794 /* Allocate a single mbuf */ 795 796 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 797 if (m0 == NULL) 798 return(ENOBUFS); 799 800 /* 801 * Initialize the NIC in test mode. This sets the chip up 802 * so that it can send and receive frames, but performs the 803 * following special functions: 804 * - Puts receiver in promiscuous mode 805 * - Enables digital loopback mode 806 * - Leaves interrupts turned off 807 */ 808 809 ifp->if_flags |= IFF_PROMISC; 810 sc->re_flags |= RE_F_TESTMODE; 811 re_init(sc); 812 sc->re_flags |= RE_F_LINKED; 813 if (!RE_IS_8139CP(sc)) 814 phyaddr = 1; 815 else 816 phyaddr = 0; 817 818 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 819 for (i = 0; i < RE_TIMEOUT; i++) { 820 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 821 if (!(status & BMCR_RESET)) 822 break; 823 } 824 825 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 826 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 827 828 DELAY(100000); 829 830 /* Put some data in the mbuf */ 831 832 eh = mtod(m0, struct ether_header *); 833 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 834 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 835 eh->ether_type = htons(ETHERTYPE_IP); 836 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 837 838 /* 839 * Queue the packet, start transmission. 840 * Note: ifq_handoff() ultimately calls re_start() for us. 841 */ 842 843 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 844 error = ifq_handoff(ifp, m0, NULL); 845 if (error) { 846 m0 = NULL; 847 goto done; 848 } 849 m0 = NULL; 850 851 /* Wait for it to propagate through the chip */ 852 853 DELAY(100000); 854 for (i = 0; i < RE_TIMEOUT; i++) { 855 status = CSR_READ_2(sc, RE_ISR); 856 CSR_WRITE_2(sc, RE_ISR, status); 857 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 858 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 859 break; 860 DELAY(10); 861 } 862 863 if (i == RE_TIMEOUT) { 864 if_printf(ifp, "diagnostic failed to receive packet " 865 "in loopback mode\n"); 866 error = EIO; 867 goto done; 868 } 869 870 /* 871 * The packet should have been dumped into the first 872 * entry in the RX DMA ring. Grab it from there. 873 */ 874 875 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 876 BUS_DMASYNC_POSTREAD); 877 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 878 sc->re_ldata.re_rx_dmamap[0]); 879 880 m0 = sc->re_ldata.re_rx_mbuf[0]; 881 sc->re_ldata.re_rx_mbuf[0] = NULL; 882 eh = mtod(m0, struct ether_header *); 883 884 cur_rx = &sc->re_ldata.re_rx_list[0]; 885 total_len = RE_RXBYTES(cur_rx); 886 887 if (total_len != ETHER_MIN_LEN) { 888 if_printf(ifp, "diagnostic failed, received short packet\n"); 889 error = EIO; 890 goto done; 891 } 892 893 /* Test that the received packet data matches what we sent. */ 894 895 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 896 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 897 be16toh(eh->ether_type) != ETHERTYPE_IP) { 898 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 899 if_printf(ifp, "expected TX data: %s/%s/0x%x\n", 900 kether_ntoa(dst, ethstr[0]), kether_ntoa(src, ethstr[1]), ETHERTYPE_IP); 901 if_printf(ifp, "received RX data: %s/%s/0x%x\n", 902 kether_ntoa(eh->ether_dhost, ethstr[0]), 903 kether_ntoa(eh->ether_shost, ethstr[1]), 904 ntohs(eh->ether_type)); 905 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 906 "into a 64-bit PCI slot.\n"); 907 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 908 "for proper operation.\n"); 909 if_printf(ifp, "Read the re(4) man page for more details.\n"); 910 error = EIO; 911 } 912 913 done: 914 /* Turn interface off, release resources */ 915 916 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 917 ifp->if_flags &= ~IFF_PROMISC; 918 re_stop(sc); 919 if (m0 != NULL) 920 m_freem(m0); 921 922 return (error); 923 } 924 #endif /* RE_DIAG */ 925 926 /* 927 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 928 * IDs against our list and return a device name if we find a match. 929 */ 930 static int 931 re_probe(device_t dev) 932 { 933 const struct re_type *t; 934 const struct re_hwrev *hw_rev; 935 struct re_softc *sc; 936 int rid; 937 uint32_t hwrev, macmode, txcfg; 938 uint16_t vendor, product; 939 940 vendor = pci_get_vendor(dev); 941 product = pci_get_device(dev); 942 943 /* 944 * Only attach to rev.3 of the Linksys EG1032 adapter. 945 * Rev.2 is supported by sk(4). 946 */ 947 if (vendor == PCI_VENDOR_LINKSYS && 948 product == PCI_PRODUCT_LINKSYS_EG1032 && 949 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 950 return ENXIO; 951 952 if (vendor == PCI_VENDOR_REALTEK && 953 product == PCI_PRODUCT_REALTEK_RT8139 && 954 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 955 /* Poor 8139 */ 956 return ENXIO; 957 } 958 959 for (t = re_devs; t->re_name != NULL; t++) { 960 if (product == t->re_did && vendor == t->re_vid) 961 break; 962 } 963 964 /* 965 * Check if we found a RealTek device. 966 */ 967 if (t->re_name == NULL) 968 return ENXIO; 969 970 /* 971 * Temporarily map the I/O space so we can read the chip ID register. 972 */ 973 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 974 rid = RE_PCI_LOIO; 975 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 976 RF_ACTIVE); 977 if (sc->re_res == NULL) { 978 device_printf(dev, "couldn't map ports/memory\n"); 979 kfree(sc, M_TEMP); 980 return ENXIO; 981 } 982 983 sc->re_btag = rman_get_bustag(sc->re_res); 984 sc->re_bhandle = rman_get_bushandle(sc->re_res); 985 986 txcfg = CSR_READ_4(sc, RE_TXCFG); 987 hwrev = txcfg & RE_TXCFG_HWREV; 988 macmode = txcfg & RE_TXCFG_MACMODE; 989 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 990 kfree(sc, M_TEMP); 991 992 /* 993 * and continue matching for the specific chip... 994 */ 995 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 996 if (hw_rev->re_hwrev == hwrev) { 997 sc = device_get_softc(dev); 998 999 sc->re_hwrev = hw_rev->re_hwrev; 1000 sc->re_macver = hw_rev->re_macver; 1001 sc->re_caps = hw_rev->re_caps; 1002 sc->re_maxmtu = hw_rev->re_maxmtu; 1003 1004 /* 1005 * Apply chip property fixup 1006 */ 1007 switch (sc->re_hwrev) { 1008 case RE_HWREV_8101E1: 1009 case RE_HWREV_8101E2: 1010 if (macmode == 0) 1011 sc->re_macver = RE_MACVER_11; 1012 else if (macmode == 0x200000) 1013 sc->re_macver = RE_MACVER_12; 1014 break; 1015 case RE_HWREV_8102E: 1016 case RE_HWREV_8102EL: 1017 if (macmode == 0) 1018 sc->re_macver = RE_MACVER_13; 1019 else if (macmode == 0x100000) 1020 sc->re_macver = RE_MACVER_14; 1021 break; 1022 case RE_HWREV_8168B2: 1023 case RE_HWREV_8168B3: 1024 if (macmode == 0) 1025 sc->re_macver = RE_MACVER_22; 1026 break; 1027 case RE_HWREV_8168C: 1028 if (macmode == 0) 1029 sc->re_macver = RE_MACVER_24; 1030 else if (macmode == 0x200000) 1031 sc->re_macver = RE_MACVER_25; 1032 else if (macmode == 0x300000) 1033 sc->re_macver = RE_MACVER_27; 1034 break; 1035 case RE_HWREV_8168CP: 1036 if (macmode == 0) 1037 sc->re_macver = RE_MACVER_26; 1038 else if (macmode == 0x100000) 1039 sc->re_macver = RE_MACVER_28; 1040 break; 1041 case RE_HWREV_8168DP: 1042 if (macmode == 0) 1043 sc->re_macver = RE_MACVER_2B; 1044 else if (macmode == 0x200000) 1045 sc->re_macver = RE_MACVER_2C; 1046 break; 1047 case RE_HWREV_8168E: 1048 if (macmode == 0x100000) 1049 sc->re_macver = RE_MACVER_2E; 1050 else if (macmode == 0x200000) 1051 sc->re_macver = RE_MACVER_2F; 1052 break; 1053 case RE_HWREV_8168F: 1054 case RE_HWREV_8111F: 1055 if (macmode == 0x000000) 1056 sc->re_macver = RE_MACVER_30; 1057 else if (macmode == 0x100000) 1058 sc->re_macver = RE_MACVER_31; 1059 break; 1060 } 1061 if (pci_is_pcie(dev)) 1062 sc->re_caps |= RE_C_PCIE; 1063 1064 device_set_desc(dev, t->re_name); 1065 return 0; 1066 } 1067 } 1068 1069 if (bootverbose) { 1070 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1071 hwrev, macmode); 1072 } 1073 return ENXIO; 1074 } 1075 1076 static int 1077 re_allocmem(device_t dev) 1078 { 1079 struct re_softc *sc = device_get_softc(dev); 1080 bus_dmamem_t dmem; 1081 int error, i; 1082 1083 /* 1084 * Allocate list data 1085 */ 1086 sc->re_ldata.re_tx_mbuf = 1087 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1088 M_DEVBUF, M_ZERO | M_WAITOK); 1089 1090 sc->re_ldata.re_rx_mbuf = 1091 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1092 M_DEVBUF, M_ZERO | M_WAITOK); 1093 1094 sc->re_ldata.re_rx_paddr = 1095 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1096 M_DEVBUF, M_ZERO | M_WAITOK); 1097 1098 sc->re_ldata.re_tx_dmamap = 1099 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1100 M_DEVBUF, M_ZERO | M_WAITOK); 1101 1102 sc->re_ldata.re_rx_dmamap = 1103 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1104 M_DEVBUF, M_ZERO | M_WAITOK); 1105 1106 /* 1107 * Allocate the parent bus DMA tag appropriate for PCI. 1108 */ 1109 error = bus_dma_tag_create(NULL, /* parent */ 1110 1, 0, /* alignment, boundary */ 1111 BUS_SPACE_MAXADDR, /* lowaddr */ 1112 BUS_SPACE_MAXADDR, /* highaddr */ 1113 NULL, NULL, /* filter, filterarg */ 1114 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1115 0, /* nsegments */ 1116 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1117 0, /* flags */ 1118 &sc->re_parent_tag); 1119 if (error) { 1120 device_printf(dev, "could not allocate parent dma tag\n"); 1121 return error; 1122 } 1123 1124 /* Allocate TX descriptor list. */ 1125 error = bus_dmamem_coherent(sc->re_parent_tag, 1126 RE_RING_ALIGN, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1128 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1129 &dmem); 1130 if (error) { 1131 device_printf(dev, "could not allocate TX ring\n"); 1132 return error; 1133 } 1134 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1135 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1136 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1137 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1138 1139 /* Allocate RX descriptor list. */ 1140 error = bus_dmamem_coherent(sc->re_parent_tag, 1141 RE_RING_ALIGN, 0, 1142 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1143 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1144 &dmem); 1145 if (error) { 1146 device_printf(dev, "could not allocate RX ring\n"); 1147 return error; 1148 } 1149 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1150 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1151 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1152 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1153 1154 /* Allocate maps for TX mbufs. */ 1155 error = bus_dma_tag_create(sc->re_parent_tag, 1156 1, 0, 1157 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1158 NULL, NULL, 1159 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1160 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1161 &sc->re_ldata.re_tx_mtag); 1162 if (error) { 1163 device_printf(dev, "could not allocate TX buf dma tag\n"); 1164 return(error); 1165 } 1166 1167 /* Create DMA maps for TX buffers */ 1168 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1169 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1170 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1171 &sc->re_ldata.re_tx_dmamap[i]); 1172 if (error) { 1173 device_printf(dev, "can't create DMA map for TX buf\n"); 1174 re_freebufmem(sc, i, 0); 1175 return(error); 1176 } 1177 } 1178 1179 /* Allocate maps for RX mbufs. */ 1180 error = bus_dma_tag_create(sc->re_parent_tag, 1181 RE_RXBUF_ALIGN, 0, 1182 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1183 NULL, NULL, 1184 MCLBYTES, 1, MCLBYTES, 1185 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1186 &sc->re_ldata.re_rx_mtag); 1187 if (error) { 1188 device_printf(dev, "could not allocate RX buf dma tag\n"); 1189 return(error); 1190 } 1191 1192 /* Create spare DMA map for RX */ 1193 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1194 &sc->re_ldata.re_rx_spare); 1195 if (error) { 1196 device_printf(dev, "can't create spare DMA map for RX\n"); 1197 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1198 sc->re_ldata.re_rx_mtag = NULL; 1199 return error; 1200 } 1201 1202 /* Create DMA maps for RX buffers */ 1203 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1204 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1205 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1206 if (error) { 1207 device_printf(dev, "can't create DMA map for RX buf\n"); 1208 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1209 return(error); 1210 } 1211 } 1212 1213 /* Create jumbo buffer pool for RX if required */ 1214 if (sc->re_caps & RE_C_CONTIGRX) { 1215 error = re_jpool_alloc(sc); 1216 if (error) { 1217 re_jpool_free(sc); 1218 /* Disable jumbo frame support */ 1219 sc->re_maxmtu = ETHERMTU; 1220 } 1221 } 1222 return(0); 1223 } 1224 1225 static void 1226 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1227 { 1228 int i; 1229 1230 /* Destroy all the RX and TX buffer maps */ 1231 if (sc->re_ldata.re_tx_mtag) { 1232 for (i = 0; i < tx_cnt; i++) { 1233 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1234 sc->re_ldata.re_tx_dmamap[i]); 1235 } 1236 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1237 sc->re_ldata.re_tx_mtag = NULL; 1238 } 1239 1240 if (sc->re_ldata.re_rx_mtag) { 1241 for (i = 0; i < rx_cnt; i++) { 1242 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1243 sc->re_ldata.re_rx_dmamap[i]); 1244 } 1245 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1246 sc->re_ldata.re_rx_spare); 1247 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1248 sc->re_ldata.re_rx_mtag = NULL; 1249 } 1250 } 1251 1252 static void 1253 re_freemem(device_t dev) 1254 { 1255 struct re_softc *sc = device_get_softc(dev); 1256 1257 /* Unload and free the RX DMA ring memory and map */ 1258 if (sc->re_ldata.re_rx_list_tag) { 1259 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1260 sc->re_ldata.re_rx_list_map); 1261 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1262 sc->re_ldata.re_rx_list, 1263 sc->re_ldata.re_rx_list_map); 1264 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1265 } 1266 1267 /* Unload and free the TX DMA ring memory and map */ 1268 if (sc->re_ldata.re_tx_list_tag) { 1269 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1270 sc->re_ldata.re_tx_list_map); 1271 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1272 sc->re_ldata.re_tx_list, 1273 sc->re_ldata.re_tx_list_map); 1274 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1275 } 1276 1277 /* Free RX/TX buf DMA stuffs */ 1278 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1279 1280 /* Unload and free the stats buffer and map */ 1281 if (sc->re_ldata.re_stag) { 1282 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1283 bus_dmamem_free(sc->re_ldata.re_stag, 1284 sc->re_ldata.re_stats, 1285 sc->re_ldata.re_smap); 1286 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1287 } 1288 1289 if (sc->re_caps & RE_C_CONTIGRX) 1290 re_jpool_free(sc); 1291 1292 if (sc->re_parent_tag) 1293 bus_dma_tag_destroy(sc->re_parent_tag); 1294 1295 if (sc->re_ldata.re_tx_mbuf != NULL) 1296 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1297 if (sc->re_ldata.re_rx_mbuf != NULL) 1298 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1299 if (sc->re_ldata.re_rx_paddr != NULL) 1300 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1301 if (sc->re_ldata.re_tx_dmamap != NULL) 1302 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1303 if (sc->re_ldata.re_rx_dmamap != NULL) 1304 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1305 } 1306 1307 /* 1308 * Attach the interface. Allocate softc structures, do ifmedia 1309 * setup and ethernet/BPF attach. 1310 */ 1311 static int 1312 re_attach(device_t dev) 1313 { 1314 struct re_softc *sc = device_get_softc(dev); 1315 struct ifnet *ifp; 1316 uint8_t eaddr[ETHER_ADDR_LEN]; 1317 int error = 0, qlen, msi_enable; 1318 u_int irq_flags; 1319 1320 callout_init(&sc->re_timer); 1321 sc->re_dev = dev; 1322 1323 if (RE_IS_8139CP(sc)) { 1324 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1325 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1326 } else { 1327 sc->re_rx_desc_cnt = re_rx_desc_count; 1328 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1329 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1330 1331 sc->re_tx_desc_cnt = re_tx_desc_count; 1332 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1333 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1334 } 1335 1336 qlen = RE_IFQ_MAXLEN; 1337 if (sc->re_tx_desc_cnt > qlen) 1338 qlen = sc->re_tx_desc_cnt; 1339 1340 sc->re_rxbuf_size = MCLBYTES; 1341 sc->re_newbuf = re_newbuf_std; 1342 1343 sc->re_tx_time = 5; /* 125us */ 1344 sc->re_rx_time = 2; /* 50us */ 1345 if (sc->re_caps & RE_C_PCIE) 1346 sc->re_sim_time = 75; /* 75us */ 1347 else 1348 sc->re_sim_time = 125; /* 125us */ 1349 if (!RE_IS_8139CP(sc)) { 1350 /* simulated interrupt moderation */ 1351 sc->re_imtype = RE_IMTYPE_SIM; 1352 } else { 1353 sc->re_imtype = RE_IMTYPE_NONE; 1354 } 1355 re_config_imtype(sc, sc->re_imtype); 1356 1357 sysctl_ctx_init(&sc->re_sysctl_ctx); 1358 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1359 SYSCTL_STATIC_CHILDREN(_hw), 1360 OID_AUTO, 1361 device_get_nameunit(dev), 1362 CTLFLAG_RD, 0, ""); 1363 if (sc->re_sysctl_tree == NULL) { 1364 device_printf(dev, "can't add sysctl node\n"); 1365 error = ENXIO; 1366 goto fail; 1367 } 1368 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1369 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1370 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1371 0, "RX desc count"); 1372 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1373 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1374 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1375 0, "TX desc count"); 1376 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1377 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1378 OID_AUTO, "sim_time", 1379 CTLTYPE_INT | CTLFLAG_RW, 1380 sc, 0, re_sysctl_simtime, "I", 1381 "Simulated interrupt moderation time (usec)."); 1382 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1383 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1384 OID_AUTO, "imtype", 1385 CTLTYPE_INT | CTLFLAG_RW, 1386 sc, 0, re_sysctl_imtype, "I", 1387 "Interrupt moderation type -- " 1388 "0:disable, 1:simulated, " 1389 "2:hardware(if supported)"); 1390 if (sc->re_caps & RE_C_HWIM) { 1391 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1392 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1393 OID_AUTO, "hw_rxtime", 1394 CTLTYPE_INT | CTLFLAG_RW, 1395 sc, 0, re_sysctl_rxtime, "I", 1396 "Hardware interrupt moderation time " 1397 "(unit: 25usec)."); 1398 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1399 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1400 OID_AUTO, "hw_txtime", 1401 CTLTYPE_INT | CTLFLAG_RW, 1402 sc, 0, re_sysctl_txtime, "I", 1403 "Hardware interrupt moderation time " 1404 "(unit: 25usec)."); 1405 } 1406 1407 #ifndef BURN_BRIDGES 1408 /* 1409 * Handle power management nonsense. 1410 */ 1411 1412 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1413 uint32_t membase, irq; 1414 1415 /* Save important PCI config data. */ 1416 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1417 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1418 1419 /* Reset the power state. */ 1420 device_printf(dev, "chip is in D%d power mode " 1421 "-- setting to D0\n", pci_get_powerstate(dev)); 1422 1423 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1424 1425 /* Restore PCI config data. */ 1426 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1427 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1428 } 1429 #endif 1430 /* 1431 * Map control/status registers. 1432 */ 1433 pci_enable_busmaster(dev); 1434 1435 if (pci_is_pcie(dev)) { 1436 sc->re_res_rid = PCIR_BAR(2); 1437 sc->re_res_type = SYS_RES_MEMORY; 1438 } else { 1439 sc->re_res_rid = PCIR_BAR(0); 1440 sc->re_res_type = SYS_RES_IOPORT; 1441 } 1442 sc->re_res = bus_alloc_resource_any(dev, sc->re_res_type, 1443 &sc->re_res_rid, RF_ACTIVE); 1444 if (sc->re_res == NULL) { 1445 device_printf(dev, "couldn't map IO\n"); 1446 error = ENXIO; 1447 goto fail; 1448 } 1449 1450 sc->re_btag = rman_get_bustag(sc->re_res); 1451 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1452 1453 /* 1454 * Allocate interrupt 1455 */ 1456 if (pci_is_pcie(dev)) 1457 msi_enable = re_msi_enable; 1458 else 1459 msi_enable = 0; 1460 sc->re_irq_type = pci_alloc_1intr(dev, msi_enable, 1461 &sc->re_irq_rid, &irq_flags); 1462 1463 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1464 irq_flags); 1465 if (sc->re_irq == NULL) { 1466 device_printf(dev, "couldn't map interrupt\n"); 1467 error = ENXIO; 1468 goto fail; 1469 } 1470 1471 /* Reset the adapter. */ 1472 re_reset(sc, 0); 1473 1474 if (RE_IS_8139CP(sc)) { 1475 sc->re_bus_speed = 33; /* XXX */ 1476 } else if (sc->re_caps & RE_C_PCIE) { 1477 sc->re_bus_speed = 125; 1478 } else { 1479 uint8_t cfg2; 1480 1481 cfg2 = CSR_READ_1(sc, RE_CFG2); 1482 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1483 case RE_CFG2_PCICLK_33MHZ: 1484 sc->re_bus_speed = 33; 1485 break; 1486 case RE_CFG2_PCICLK_66MHZ: 1487 sc->re_bus_speed = 66; 1488 break; 1489 default: 1490 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1491 sc->re_bus_speed = 33; 1492 break; 1493 } 1494 if (cfg2 & RE_CFG2_PCI64) 1495 sc->re_caps |= RE_C_PCI64; 1496 } 1497 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1498 "PCI%s %dMHz\n", 1499 sc->re_hwrev, sc->re_macver, 1500 (sc->re_caps & RE_C_PCIE) ? 1501 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1502 sc->re_bus_speed); 1503 1504 /* 1505 * NOTE: 1506 * DO NOT try to adjust config1 and config5 which was spotted in 1507 * Realtek's Linux drivers. It will _permanently_ damage certain 1508 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1509 */ 1510 1511 re_get_eaddr(sc, eaddr); 1512 1513 if (!RE_IS_8139CP(sc)) { 1514 /* Set RX length mask */ 1515 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1516 sc->re_txstart = RE_GTXSTART; 1517 } else { 1518 /* Set RX length mask */ 1519 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1520 sc->re_txstart = RE_TXSTART; 1521 } 1522 1523 /* Allocate DMA stuffs */ 1524 error = re_allocmem(dev); 1525 if (error) 1526 goto fail; 1527 1528 /* 1529 * Apply some magic PCI settings from Realtek ... 1530 */ 1531 if (RE_IS_8169(sc)) { 1532 CSR_WRITE_1(sc, 0x82, 1); 1533 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1534 } 1535 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1536 1537 if (sc->re_caps & RE_C_MAC2) { 1538 /* 1539 * Following part is extracted from Realtek BSD driver v176. 1540 * However, this does _not_ make much/any sense: 1541 * 8168C's PCI Express device control is located at 0x78, 1542 * so the reading from 0x79 (higher part of 0x78) and setting 1543 * the 4~6bits intend to enlarge the "max read request size" 1544 * (we will do it). The content of the rest part of this 1545 * register is not meaningful to other PCI registers, so 1546 * writing the value to 0x54 could be completely wrong. 1547 * 0x80 is the lower part of PCI Express device status, non- 1548 * reserved bits are RW1C, writing 0 to them will not have 1549 * any effect at all. 1550 */ 1551 #ifdef foo 1552 uint8_t val; 1553 1554 val = pci_read_config(dev, 0x79, 1); 1555 val = (val & ~0x70) | 0x50; 1556 pci_write_config(dev, 0x54, val, 1); 1557 pci_write_config(dev, 0x80, 0, 1); 1558 #endif 1559 } 1560 1561 /* 1562 * Apply some PHY fixup from Realtek ... 1563 */ 1564 if (sc->re_hwrev == RE_HWREV_8110S) { 1565 CSR_WRITE_1(sc, 0x82, 1); 1566 re_miibus_writereg(dev, 1, 0xb, 0); 1567 } 1568 if (sc->re_caps & RE_C_PHYPMGT) { 1569 /* Power up PHY */ 1570 re_miibus_writereg(dev, 1, 0x1f, 0); 1571 re_miibus_writereg(dev, 1, 0xe, 0); 1572 } 1573 1574 /* Do MII setup */ 1575 if (mii_phy_probe(dev, &sc->re_miibus, 1576 re_ifmedia_upd, re_ifmedia_sts)) { 1577 device_printf(dev, "MII without any phy!\n"); 1578 error = ENXIO; 1579 goto fail; 1580 } 1581 1582 ifp = &sc->arpcom.ac_if; 1583 ifp->if_softc = sc; 1584 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1586 ifp->if_ioctl = re_ioctl; 1587 ifp->if_start = re_start; 1588 #ifdef IFPOLL_ENABLE 1589 ifp->if_npoll = re_npoll; 1590 #endif 1591 ifp->if_watchdog = re_watchdog; 1592 ifp->if_init = re_init; 1593 if (!RE_IS_8139CP(sc)) /* XXX */ 1594 ifp->if_baudrate = 1000000000; 1595 else 1596 ifp->if_baudrate = 100000000; 1597 ifq_set_maxlen(&ifp->if_snd, qlen); 1598 ifq_set_ready(&ifp->if_snd); 1599 1600 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1601 if (sc->re_caps & RE_C_HWCSUM) 1602 ifp->if_capabilities |= IFCAP_HWCSUM; 1603 1604 ifp->if_capenable = ifp->if_capabilities; 1605 if (ifp->if_capabilities & IFCAP_HWCSUM) 1606 ifp->if_hwassist = RE_CSUM_FEATURES; 1607 else 1608 ifp->if_hwassist = 0; 1609 1610 /* 1611 * Call MI attach routine. 1612 */ 1613 ether_ifattach(ifp, eaddr, NULL); 1614 1615 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 1616 1617 #ifdef IFPOLL_ENABLE 1618 ifpoll_compat_setup(&sc->re_npoll, 1619 &sc->re_sysctl_ctx, sc->re_sysctl_tree, device_get_unit(dev), 1620 ifp->if_serializer); 1621 #endif 1622 1623 #ifdef RE_DIAG 1624 /* 1625 * Perform hardware diagnostic on the original RTL8169. 1626 * Some 32-bit cards were incorrectly wired and would 1627 * malfunction if plugged into a 64-bit slot. 1628 */ 1629 if (sc->re_hwrev == RE_HWREV_8169) { 1630 lwkt_serialize_enter(ifp->if_serializer); 1631 error = re_diag(sc); 1632 lwkt_serialize_exit(ifp->if_serializer); 1633 1634 if (error) { 1635 device_printf(dev, "hardware diagnostic failure\n"); 1636 ether_ifdetach(ifp); 1637 goto fail; 1638 } 1639 } 1640 #endif /* RE_DIAG */ 1641 1642 /* Hook interrupt last to avoid having to lock softc */ 1643 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1644 &sc->re_intrhand, ifp->if_serializer); 1645 1646 if (error) { 1647 device_printf(dev, "couldn't set up irq\n"); 1648 ether_ifdetach(ifp); 1649 goto fail; 1650 } 1651 1652 fail: 1653 if (error) 1654 re_detach(dev); 1655 1656 return (error); 1657 } 1658 1659 /* 1660 * Shutdown hardware and free up resources. This can be called any 1661 * time after the mutex has been initialized. It is called in both 1662 * the error case in attach and the normal detach case so it needs 1663 * to be careful about only freeing resources that have actually been 1664 * allocated. 1665 */ 1666 static int 1667 re_detach(device_t dev) 1668 { 1669 struct re_softc *sc = device_get_softc(dev); 1670 struct ifnet *ifp = &sc->arpcom.ac_if; 1671 1672 /* These should only be active if attach succeeded */ 1673 if (device_is_attached(dev)) { 1674 lwkt_serialize_enter(ifp->if_serializer); 1675 re_stop(sc); 1676 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1677 lwkt_serialize_exit(ifp->if_serializer); 1678 1679 ether_ifdetach(ifp); 1680 } 1681 if (sc->re_miibus) 1682 device_delete_child(dev, sc->re_miibus); 1683 bus_generic_detach(dev); 1684 1685 if (sc->re_sysctl_tree != NULL) 1686 sysctl_ctx_free(&sc->re_sysctl_ctx); 1687 1688 if (sc->re_irq) 1689 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1690 sc->re_irq); 1691 1692 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1693 pci_release_msi(dev); 1694 1695 if (sc->re_res) { 1696 bus_release_resource(dev, sc->re_res_type, sc->re_res_rid, 1697 sc->re_res); 1698 } 1699 1700 /* Free DMA stuffs */ 1701 re_freemem(dev); 1702 1703 return(0); 1704 } 1705 1706 static void 1707 re_setup_rxdesc(struct re_softc *sc, int idx) 1708 { 1709 bus_addr_t paddr; 1710 uint32_t cmdstat; 1711 struct re_desc *d; 1712 1713 paddr = sc->re_ldata.re_rx_paddr[idx]; 1714 d = &sc->re_ldata.re_rx_list[idx]; 1715 1716 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1717 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1718 1719 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1720 if (idx == (sc->re_rx_desc_cnt - 1)) 1721 cmdstat |= RE_RDESC_CMD_EOR; 1722 d->re_cmdstat = htole32(cmdstat); 1723 } 1724 1725 static int 1726 re_newbuf_std(struct re_softc *sc, int idx, int init) 1727 { 1728 bus_dma_segment_t seg; 1729 bus_dmamap_t map; 1730 struct mbuf *m; 1731 int error, nsegs; 1732 1733 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1734 if (m == NULL) { 1735 error = ENOBUFS; 1736 1737 if (init) { 1738 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1739 return error; 1740 } else { 1741 goto back; 1742 } 1743 } 1744 m->m_len = m->m_pkthdr.len = MCLBYTES; 1745 1746 /* 1747 * NOTE: 1748 * re(4) chips need address of the receive buffer to be 8-byte 1749 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1750 */ 1751 1752 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1753 sc->re_ldata.re_rx_spare, m, 1754 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1755 if (error) { 1756 m_freem(m); 1757 if (init) { 1758 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1759 return error; 1760 } else { 1761 goto back; 1762 } 1763 } 1764 1765 if (!init) { 1766 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1767 sc->re_ldata.re_rx_dmamap[idx], 1768 BUS_DMASYNC_POSTREAD); 1769 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1770 sc->re_ldata.re_rx_dmamap[idx]); 1771 } 1772 sc->re_ldata.re_rx_mbuf[idx] = m; 1773 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1774 1775 map = sc->re_ldata.re_rx_dmamap[idx]; 1776 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1777 sc->re_ldata.re_rx_spare = map; 1778 back: 1779 re_setup_rxdesc(sc, idx); 1780 return error; 1781 } 1782 1783 static int 1784 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1785 { 1786 struct mbuf *m; 1787 struct re_jbuf *jbuf; 1788 int error = 0; 1789 1790 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1791 if (m == NULL) { 1792 error = ENOBUFS; 1793 if (init) { 1794 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1795 return error; 1796 } else { 1797 goto back; 1798 } 1799 } 1800 1801 jbuf = re_jbuf_alloc(sc); 1802 if (jbuf == NULL) { 1803 m_freem(m); 1804 1805 error = ENOBUFS; 1806 if (init) { 1807 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1808 return error; 1809 } else { 1810 goto back; 1811 } 1812 } 1813 1814 m->m_ext.ext_arg = jbuf; 1815 m->m_ext.ext_buf = jbuf->re_buf; 1816 m->m_ext.ext_free = re_jbuf_free; 1817 m->m_ext.ext_ref = re_jbuf_ref; 1818 m->m_ext.ext_size = sc->re_rxbuf_size; 1819 1820 m->m_data = m->m_ext.ext_buf; 1821 m->m_flags |= M_EXT; 1822 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1823 1824 /* 1825 * NOTE: 1826 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1827 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1828 */ 1829 1830 sc->re_ldata.re_rx_mbuf[idx] = m; 1831 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1832 back: 1833 re_setup_rxdesc(sc, idx); 1834 return error; 1835 } 1836 1837 static int 1838 re_tx_list_init(struct re_softc *sc) 1839 { 1840 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1841 1842 sc->re_ldata.re_tx_prodidx = 0; 1843 sc->re_ldata.re_tx_considx = 0; 1844 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1845 1846 return(0); 1847 } 1848 1849 static int 1850 re_rx_list_init(struct re_softc *sc) 1851 { 1852 int i, error; 1853 1854 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1855 1856 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1857 error = sc->re_newbuf(sc, i, 1); 1858 if (error) 1859 return(error); 1860 } 1861 1862 sc->re_ldata.re_rx_prodidx = 0; 1863 sc->re_head = sc->re_tail = NULL; 1864 1865 return(0); 1866 } 1867 1868 #define RE_IP4_PACKET 0x1 1869 #define RE_TCP_PACKET 0x2 1870 #define RE_UDP_PACKET 0x4 1871 1872 static __inline uint8_t 1873 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1874 { 1875 uint8_t packet_type = 0; 1876 1877 if (sc->re_caps & RE_C_MAC2) { 1878 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1879 packet_type |= RE_IP4_PACKET; 1880 } else { 1881 if (rxstat & RE_RDESC_STAT_PROTOID) 1882 packet_type |= RE_IP4_PACKET; 1883 } 1884 if (RE_TCPPKT(rxstat)) 1885 packet_type |= RE_TCP_PACKET; 1886 else if (RE_UDPPKT(rxstat)) 1887 packet_type |= RE_UDP_PACKET; 1888 return packet_type; 1889 } 1890 1891 /* 1892 * RX handler for C+ and 8169. For the gigE chips, we support 1893 * the reception of jumbo frames that have been fragmented 1894 * across multiple 2K mbuf cluster buffers. 1895 */ 1896 static int 1897 re_rxeof(struct re_softc *sc) 1898 { 1899 struct ifnet *ifp = &sc->arpcom.ac_if; 1900 struct mbuf *m; 1901 struct re_desc *cur_rx; 1902 uint32_t rxstat, rxctrl; 1903 int i, total_len, rx = 0; 1904 1905 for (i = sc->re_ldata.re_rx_prodidx; 1906 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1907 cur_rx = &sc->re_ldata.re_rx_list[i]; 1908 m = sc->re_ldata.re_rx_mbuf[i]; 1909 total_len = RE_RXBYTES(cur_rx); 1910 rxstat = le32toh(cur_rx->re_cmdstat); 1911 rxctrl = le32toh(cur_rx->re_control); 1912 1913 rx = 1; 1914 1915 #ifdef INVARIANTS 1916 if (sc->re_flags & RE_F_USE_JPOOL) 1917 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1918 #endif 1919 1920 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1921 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1922 re_setup_rxdesc(sc, i); 1923 continue; 1924 } 1925 1926 if (sc->re_newbuf(sc, i, 0)) { 1927 /* Drop upcoming fragments */ 1928 sc->re_flags |= RE_F_DROP_RXFRAG; 1929 continue; 1930 } 1931 1932 m->m_len = MCLBYTES; 1933 if (sc->re_head == NULL) { 1934 sc->re_head = sc->re_tail = m; 1935 } else { 1936 sc->re_tail->m_next = m; 1937 sc->re_tail = m; 1938 } 1939 continue; 1940 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1941 /* 1942 * Last fragment of a multi-fragment packet. 1943 * 1944 * Since error already happened, this fragment 1945 * must be dropped as well as the fragment chain. 1946 */ 1947 re_setup_rxdesc(sc, i); 1948 re_free_rxchain(sc); 1949 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1950 continue; 1951 } 1952 1953 /* 1954 * NOTE: for the 8139C+, the frame length field 1955 * is always 12 bits in size, but for the gigE chips, 1956 * it is 13 bits (since the max RX frame length is 16K). 1957 * Unfortunately, all 32 bits in the status word 1958 * were already used, so to make room for the extra 1959 * length bit, RealTek took out the 'frame alignment 1960 * error' bit and shifted the other status bits 1961 * over one slot. The OWN, EOR, FS and LS bits are 1962 * still in the same places. We have already extracted 1963 * the frame length and checked the OWN bit, so rather 1964 * than using an alternate bit mapping, we shift the 1965 * status bits one space to the right so we can evaluate 1966 * them using the 8169 status as though it was in the 1967 * same format as that of the 8139C+. 1968 */ 1969 if (!RE_IS_8139CP(sc)) 1970 rxstat >>= 1; 1971 1972 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1973 IFNET_STAT_INC(ifp, ierrors, 1); 1974 /* 1975 * If this is part of a multi-fragment packet, 1976 * discard all the pieces. 1977 */ 1978 re_free_rxchain(sc); 1979 re_setup_rxdesc(sc, i); 1980 continue; 1981 } 1982 1983 /* 1984 * If allocating a replacement mbuf fails, 1985 * reload the current one. 1986 */ 1987 1988 if (sc->re_newbuf(sc, i, 0)) { 1989 IFNET_STAT_INC(ifp, ierrors, 1); 1990 continue; 1991 } 1992 1993 if (sc->re_head != NULL) { 1994 m->m_len = total_len % MCLBYTES; 1995 /* 1996 * Special case: if there's 4 bytes or less 1997 * in this buffer, the mbuf can be discarded: 1998 * the last 4 bytes is the CRC, which we don't 1999 * care about anyway. 2000 */ 2001 if (m->m_len <= ETHER_CRC_LEN) { 2002 sc->re_tail->m_len -= 2003 (ETHER_CRC_LEN - m->m_len); 2004 m_freem(m); 2005 } else { 2006 m->m_len -= ETHER_CRC_LEN; 2007 sc->re_tail->m_next = m; 2008 } 2009 m = sc->re_head; 2010 sc->re_head = sc->re_tail = NULL; 2011 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2012 } else { 2013 m->m_pkthdr.len = m->m_len = 2014 (total_len - ETHER_CRC_LEN); 2015 } 2016 2017 IFNET_STAT_INC(ifp, ipackets, 1); 2018 m->m_pkthdr.rcvif = ifp; 2019 2020 /* Do RX checksumming if enabled */ 2021 2022 if (ifp->if_capenable & IFCAP_RXCSUM) { 2023 uint8_t packet_type; 2024 2025 packet_type = re_packet_type(sc, rxstat, rxctrl); 2026 2027 /* Check IP header checksum */ 2028 if (packet_type & RE_IP4_PACKET) { 2029 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2030 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2031 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2032 } 2033 2034 /* Check TCP/UDP checksum */ 2035 if (((packet_type & RE_TCP_PACKET) && 2036 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2037 ((packet_type & RE_UDP_PACKET) && 2038 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2039 m->m_pkthdr.csum_flags |= 2040 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2041 CSUM_FRAG_NOT_CHECKED; 2042 m->m_pkthdr.csum_data = 0xffff; 2043 } 2044 } 2045 2046 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2047 m->m_flags |= M_VLANTAG; 2048 m->m_pkthdr.ether_vlantag = 2049 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2050 } 2051 ifp->if_input(ifp, m); 2052 } 2053 2054 sc->re_ldata.re_rx_prodidx = i; 2055 2056 return rx; 2057 } 2058 2059 #undef RE_IP4_PACKET 2060 #undef RE_TCP_PACKET 2061 #undef RE_UDP_PACKET 2062 2063 static int 2064 re_tx_collect(struct re_softc *sc) 2065 { 2066 struct ifnet *ifp = &sc->arpcom.ac_if; 2067 uint32_t txstat; 2068 int idx, tx = 0; 2069 2070 for (idx = sc->re_ldata.re_tx_considx; 2071 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2072 RE_TXDESC_INC(sc, idx)) { 2073 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2074 if (txstat & RE_TDESC_CMD_OWN) 2075 break; 2076 2077 tx = 1; 2078 2079 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2080 2081 /* 2082 * We only stash mbufs in the last descriptor 2083 * in a fragment chain, which also happens to 2084 * be the only place where the TX status bits 2085 * are valid. 2086 */ 2087 if (txstat & RE_TDESC_CMD_EOF) { 2088 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2089 sc->re_ldata.re_tx_dmamap[idx]); 2090 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2091 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2092 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2093 RE_TDESC_STAT_COLCNT)) 2094 IFNET_STAT_INC(ifp, collisions, 1); 2095 if (txstat & RE_TDESC_STAT_TXERRSUM) 2096 IFNET_STAT_INC(ifp, oerrors, 1); 2097 else 2098 IFNET_STAT_INC(ifp, opackets, 1); 2099 } 2100 sc->re_ldata.re_tx_free++; 2101 } 2102 sc->re_ldata.re_tx_considx = idx; 2103 2104 return tx; 2105 } 2106 2107 static int 2108 re_txeof(struct re_softc *sc) 2109 { 2110 struct ifnet *ifp = &sc->arpcom.ac_if; 2111 int tx; 2112 2113 tx = re_tx_collect(sc); 2114 2115 /* There is enough free TX descs */ 2116 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2117 ifq_clr_oactive(&ifp->if_snd); 2118 2119 /* 2120 * Some chips will ignore a second TX request issued while an 2121 * existing transmission is in progress. If the transmitter goes 2122 * idle but there are still packets waiting to be sent, we need 2123 * to restart the channel here to flush them out. This only seems 2124 * to be required with the PCIe devices. 2125 */ 2126 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2127 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2128 else 2129 ifp->if_timer = 0; 2130 2131 return tx; 2132 } 2133 2134 static void 2135 re_tick(void *xsc) 2136 { 2137 struct re_softc *sc = xsc; 2138 2139 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2140 re_tick_serialized(xsc); 2141 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2142 } 2143 2144 static void 2145 re_tick_serialized(void *xsc) 2146 { 2147 struct re_softc *sc = xsc; 2148 struct ifnet *ifp = &sc->arpcom.ac_if; 2149 struct mii_data *mii; 2150 2151 ASSERT_SERIALIZED(ifp->if_serializer); 2152 2153 mii = device_get_softc(sc->re_miibus); 2154 mii_tick(mii); 2155 if (sc->re_flags & RE_F_LINKED) { 2156 if (!(mii->mii_media_status & IFM_ACTIVE)) 2157 sc->re_flags &= ~RE_F_LINKED; 2158 } else { 2159 if (mii->mii_media_status & IFM_ACTIVE && 2160 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2161 sc->re_flags |= RE_F_LINKED; 2162 if (!ifq_is_empty(&ifp->if_snd)) 2163 if_devstart(ifp); 2164 } 2165 } 2166 2167 callout_reset(&sc->re_timer, hz, re_tick, sc); 2168 } 2169 2170 #ifdef IFPOLL_ENABLE 2171 2172 static void 2173 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2174 { 2175 struct re_softc *sc = ifp->if_softc; 2176 2177 ASSERT_SERIALIZED(ifp->if_serializer); 2178 2179 if (sc->re_npoll.ifpc_stcount-- == 0) { 2180 uint16_t status; 2181 2182 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac; 2183 2184 status = CSR_READ_2(sc, RE_ISR); 2185 if (status == 0xffff) 2186 return; 2187 if (status) 2188 CSR_WRITE_2(sc, RE_ISR, status); 2189 2190 /* 2191 * XXX check behaviour on receiver stalls. 2192 */ 2193 2194 if (status & RE_ISR_SYSTEM_ERR) 2195 re_init(sc); 2196 } 2197 2198 sc->rxcycles = count; 2199 re_rxeof(sc); 2200 re_txeof(sc); 2201 2202 if (!ifq_is_empty(&ifp->if_snd)) 2203 if_devstart(ifp); 2204 } 2205 2206 static void 2207 re_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2208 { 2209 struct re_softc *sc = ifp->if_softc; 2210 2211 ASSERT_SERIALIZED(ifp->if_serializer); 2212 2213 if (info != NULL) { 2214 int cpuid = sc->re_npoll.ifpc_cpuid; 2215 2216 info->ifpi_rx[cpuid].poll_func = re_npoll_compat; 2217 info->ifpi_rx[cpuid].arg = NULL; 2218 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2219 2220 if (ifp->if_flags & IFF_RUNNING) 2221 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2222 ifq_set_cpuid(&ifp->if_snd, cpuid); 2223 } else { 2224 if (ifp->if_flags & IFF_RUNNING) 2225 re_setup_intr(sc, 1, sc->re_imtype); 2226 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 2227 } 2228 } 2229 #endif /* IFPOLL_ENABLE */ 2230 2231 static void 2232 re_intr(void *arg) 2233 { 2234 struct re_softc *sc = arg; 2235 struct ifnet *ifp = &sc->arpcom.ac_if; 2236 uint16_t status; 2237 int rx, tx; 2238 2239 ASSERT_SERIALIZED(ifp->if_serializer); 2240 2241 if ((sc->re_flags & RE_F_SUSPENDED) || 2242 (ifp->if_flags & IFF_RUNNING) == 0) 2243 return; 2244 2245 rx = tx = 0; 2246 2247 status = CSR_READ_2(sc, RE_ISR); 2248 /* If the card has gone away the read returns 0xffff. */ 2249 if (status == 0xffff) 2250 goto reload; 2251 if (status) 2252 CSR_WRITE_2(sc, RE_ISR, status); 2253 2254 if ((status & sc->re_intrs) == 0) 2255 goto reload; 2256 2257 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2258 rx |= re_rxeof(sc); 2259 2260 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2261 tx |= re_txeof(sc); 2262 2263 if (status & RE_ISR_SYSTEM_ERR) 2264 re_init(sc); 2265 2266 if (status & RE_ISR_LINKCHG) { 2267 callout_stop(&sc->re_timer); 2268 re_tick_serialized(sc); 2269 } 2270 2271 reload: 2272 if (sc->re_imtype == RE_IMTYPE_SIM) { 2273 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2274 if ((tx | rx) == 0) { 2275 /* 2276 * Nothing needs to be processed, fallback 2277 * to use TX/RX interrupts. 2278 */ 2279 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2280 2281 /* 2282 * Recollect, mainly to avoid the possible 2283 * race introduced by changing interrupt 2284 * masks. 2285 */ 2286 re_rxeof(sc); 2287 tx = re_txeof(sc); 2288 } else { 2289 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2290 } 2291 } else if (tx | rx) { 2292 /* 2293 * Assume that using simulated interrupt moderation 2294 * (hardware timer based) could reduce the interript 2295 * rate. 2296 */ 2297 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2298 } 2299 } 2300 2301 if (tx && !ifq_is_empty(&ifp->if_snd)) 2302 if_devstart(ifp); 2303 } 2304 2305 static int 2306 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2307 { 2308 struct mbuf *m = *m_head; 2309 bus_dma_segment_t segs[RE_MAXSEGS]; 2310 bus_dmamap_t map; 2311 int error, maxsegs, idx, i, nsegs; 2312 struct re_desc *d, *tx_ring; 2313 uint32_t cmd_csum, ctl_csum, vlantag; 2314 2315 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2316 ("not enough free TX desc")); 2317 2318 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2319 2320 /* 2321 * Set up checksum offload. Note: checksum offload bits must 2322 * appear in all descriptors of a multi-descriptor transmit 2323 * attempt. (This is according to testing done with an 8169 2324 * chip. I'm not sure if this is a requirement or a bug.) 2325 */ 2326 cmd_csum = ctl_csum = 0; 2327 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2328 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2329 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2330 } 2331 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2332 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2333 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2334 } 2335 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2336 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2337 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2338 } 2339 2340 /* For MAC2 chips, csum flags are set on re_control */ 2341 if (sc->re_caps & RE_C_MAC2) 2342 cmd_csum = 0; 2343 else 2344 ctl_csum = 0; 2345 2346 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2347 /* 2348 * With some of the RealTek chips, using the checksum offload 2349 * support in conjunction with the autopadding feature results 2350 * in the transmission of corrupt frames. For example, if we 2351 * need to send a really small IP fragment that's less than 60 2352 * bytes in size, and IP header checksumming is enabled, the 2353 * resulting ethernet frame that appears on the wire will 2354 * have garbled payload. To work around this, if TX checksum 2355 * offload is enabled, we always manually pad short frames out 2356 * to the minimum ethernet frame size. 2357 * 2358 * Note: this appears unnecessary for TCP, and doing it for TCP 2359 * with PCIe adapters seems to result in bad checksums. 2360 */ 2361 if ((m->m_pkthdr.csum_flags & 2362 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2363 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2364 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2365 error = m_devpad(m, RE_MIN_FRAMELEN); 2366 if (error) 2367 goto back; 2368 } 2369 } 2370 2371 vlantag = 0; 2372 if (m->m_flags & M_VLANTAG) { 2373 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2374 RE_TDESC_CTL_INSTAG; 2375 } 2376 2377 maxsegs = sc->re_ldata.re_tx_free; 2378 if (maxsegs > RE_MAXSEGS) 2379 maxsegs = RE_MAXSEGS; 2380 2381 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2382 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2383 if (error) 2384 goto back; 2385 2386 m = *m_head; 2387 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2388 2389 /* 2390 * Map the segment array into descriptors. We also keep track 2391 * of the end of the ring and set the end-of-ring bits as needed, 2392 * and we set the ownership bits in all except the very first 2393 * descriptor, whose ownership bits will be turned on later. 2394 */ 2395 tx_ring = sc->re_ldata.re_tx_list; 2396 idx = *idx0; 2397 i = 0; 2398 for (;;) { 2399 uint32_t cmdstat; 2400 2401 d = &tx_ring[idx]; 2402 2403 cmdstat = segs[i].ds_len; 2404 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2405 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2406 if (i == 0) 2407 cmdstat |= RE_TDESC_CMD_SOF; 2408 else 2409 cmdstat |= RE_TDESC_CMD_OWN; 2410 if (idx == (sc->re_tx_desc_cnt - 1)) 2411 cmdstat |= RE_TDESC_CMD_EOR; 2412 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2413 d->re_control = htole32(ctl_csum | vlantag); 2414 2415 i++; 2416 if (i == nsegs) 2417 break; 2418 RE_TXDESC_INC(sc, idx); 2419 } 2420 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2421 2422 /* Transfer ownership of packet to the chip. */ 2423 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2424 if (*idx0 != idx) 2425 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2426 2427 /* 2428 * Insure that the map for this transmission 2429 * is placed at the array index of the last descriptor 2430 * in this chain. 2431 */ 2432 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2433 sc->re_ldata.re_tx_dmamap[idx] = map; 2434 2435 sc->re_ldata.re_tx_mbuf[idx] = m; 2436 sc->re_ldata.re_tx_free -= nsegs; 2437 2438 RE_TXDESC_INC(sc, idx); 2439 *idx0 = idx; 2440 back: 2441 if (error) { 2442 m_freem(*m_head); 2443 *m_head = NULL; 2444 } 2445 return error; 2446 } 2447 2448 /* 2449 * Main transmit routine for C+ and gigE NICs. 2450 */ 2451 2452 static void 2453 re_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2454 { 2455 struct re_softc *sc = ifp->if_softc; 2456 struct mbuf *m_head; 2457 int idx, need_trans, oactive, error; 2458 2459 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2460 ASSERT_SERIALIZED(ifp->if_serializer); 2461 2462 if ((sc->re_flags & RE_F_LINKED) == 0) { 2463 ifq_purge(&ifp->if_snd); 2464 return; 2465 } 2466 2467 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2468 return; 2469 2470 idx = sc->re_ldata.re_tx_prodidx; 2471 2472 need_trans = 0; 2473 oactive = 0; 2474 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2475 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2476 if (!oactive) { 2477 if (re_tx_collect(sc)) { 2478 oactive = 1; 2479 continue; 2480 } 2481 } 2482 ifq_set_oactive(&ifp->if_snd); 2483 break; 2484 } 2485 2486 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2487 if (m_head == NULL) 2488 break; 2489 2490 error = re_encap(sc, &m_head, &idx); 2491 if (error) { 2492 /* m_head is freed by re_encap(), if we reach here */ 2493 IFNET_STAT_INC(ifp, oerrors, 1); 2494 2495 if (error == EFBIG && !oactive) { 2496 if (re_tx_collect(sc)) { 2497 oactive = 1; 2498 continue; 2499 } 2500 } 2501 ifq_set_oactive(&ifp->if_snd); 2502 break; 2503 } 2504 2505 oactive = 0; 2506 need_trans = 1; 2507 2508 /* 2509 * If there's a BPF listener, bounce a copy of this frame 2510 * to him. 2511 */ 2512 ETHER_BPF_MTAP(ifp, m_head); 2513 } 2514 2515 /* 2516 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2517 * for OACTIVE to not be properly set when we also do not 2518 * have sufficient free tx descriptors, leaving packet in 2519 * ifp->if_snd. This can cause if_start_dispatch() to loop 2520 * infinitely so make sure OACTIVE is set properly. 2521 */ 2522 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2523 if (!ifq_is_oactive(&ifp->if_snd)) { 2524 if_printf(ifp, "Debug: OACTIVE was not set when " 2525 "re_tx_free was below minimum!\n"); 2526 ifq_set_oactive(&ifp->if_snd); 2527 } 2528 } 2529 if (!need_trans) 2530 return; 2531 2532 sc->re_ldata.re_tx_prodidx = idx; 2533 2534 /* 2535 * RealTek put the TX poll request register in a different 2536 * location on the 8169 gigE chip. I don't know why. 2537 */ 2538 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2539 2540 /* 2541 * Set a timeout in case the chip goes out to lunch. 2542 */ 2543 ifp->if_timer = 5; 2544 } 2545 2546 static void 2547 re_init(void *xsc) 2548 { 2549 struct re_softc *sc = xsc; 2550 struct ifnet *ifp = &sc->arpcom.ac_if; 2551 struct mii_data *mii; 2552 int error, framelen; 2553 2554 ASSERT_SERIALIZED(ifp->if_serializer); 2555 2556 mii = device_get_softc(sc->re_miibus); 2557 2558 /* 2559 * Cancel pending I/O and free all RX/TX buffers. 2560 */ 2561 re_stop(sc); 2562 2563 if (sc->re_caps & RE_C_CONTIGRX) { 2564 if (ifp->if_mtu > ETHERMTU) { 2565 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2566 sc->re_flags |= RE_F_USE_JPOOL; 2567 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2568 sc->re_newbuf = re_newbuf_jumbo; 2569 } else { 2570 sc->re_flags &= ~RE_F_USE_JPOOL; 2571 sc->re_rxbuf_size = MCLBYTES; 2572 sc->re_newbuf = re_newbuf_std; 2573 } 2574 } 2575 2576 /* 2577 * Adjust max read request size according to MTU; mainly to 2578 * improve TX performance for common case (ETHERMTU) on GigE 2579 * NICs. However, this could _not_ be done on 10/100 only 2580 * NICs; their DMA engines will malfunction using non-default 2581 * max read request size. 2582 */ 2583 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2584 if (ifp->if_mtu > ETHERMTU) { 2585 /* 2586 * 512 seems to be the only value that works 2587 * reliably with jumbo frame 2588 */ 2589 pcie_set_max_readrq(sc->re_dev, 2590 PCIEM_DEVCTL_MAX_READRQ_512); 2591 } else { 2592 pcie_set_max_readrq(sc->re_dev, 2593 PCIEM_DEVCTL_MAX_READRQ_4096); 2594 } 2595 } 2596 2597 /* 2598 * Enable C+ RX and TX mode, as well as VLAN stripping and 2599 * RX checksum offload. We must configure the C+ register 2600 * before all others. 2601 */ 2602 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2603 RE_CPLUSCMD_PCI_MRW | 2604 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2605 RE_CPLUSCMD_VLANSTRIP : 0) | 2606 (ifp->if_capenable & IFCAP_RXCSUM ? 2607 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2608 2609 /* 2610 * Init our MAC address. Even though the chipset 2611 * documentation doesn't mention it, we need to enter "Config 2612 * register write enable" mode to modify the ID registers. 2613 */ 2614 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2615 CSR_WRITE_4(sc, RE_IDR0, 2616 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2617 CSR_WRITE_2(sc, RE_IDR4, 2618 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2619 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2620 2621 /* 2622 * For C+ mode, initialize the RX descriptors and mbufs. 2623 */ 2624 error = re_rx_list_init(sc); 2625 if (error) { 2626 re_stop(sc); 2627 return; 2628 } 2629 error = re_tx_list_init(sc); 2630 if (error) { 2631 re_stop(sc); 2632 return; 2633 } 2634 2635 /* 2636 * Load the addresses of the RX and TX lists into the chip. 2637 */ 2638 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2639 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2640 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2641 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2642 2643 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2644 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2645 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2646 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2647 2648 /* 2649 * Enable transmit and receive. 2650 */ 2651 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2652 2653 /* 2654 * Set the initial TX and RX configuration. 2655 */ 2656 if (sc->re_flags & RE_F_TESTMODE) { 2657 if (!RE_IS_8139CP(sc)) 2658 CSR_WRITE_4(sc, RE_TXCFG, 2659 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2660 else 2661 CSR_WRITE_4(sc, RE_TXCFG, 2662 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2663 } else 2664 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2665 2666 framelen = RE_FRAMELEN(ifp->if_mtu); 2667 if (framelen < MCLBYTES) 2668 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2669 else 2670 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2671 2672 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2673 2674 /* 2675 * Program the multicast filter, if necessary. 2676 */ 2677 re_setmulti(sc); 2678 2679 #ifdef IFPOLL_ENABLE 2680 /* 2681 * Disable interrupts if we are polling. 2682 */ 2683 if (ifp->if_flags & IFF_NPOLLING) 2684 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2685 else /* otherwise ... */ 2686 #endif /* IFPOLL_ENABLE */ 2687 /* 2688 * Enable interrupts. 2689 */ 2690 if (sc->re_flags & RE_F_TESTMODE) 2691 CSR_WRITE_2(sc, RE_IMR, 0); 2692 else 2693 re_setup_intr(sc, 1, sc->re_imtype); 2694 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2695 2696 /* Start RX/TX process. */ 2697 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2698 2699 #ifdef notdef 2700 /* Enable receiver and transmitter. */ 2701 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2702 #endif 2703 2704 /* 2705 * For 8169 gigE NICs, set the max allowed RX packet 2706 * size so we can receive jumbo frames. 2707 */ 2708 if (!RE_IS_8139CP(sc)) { 2709 if (sc->re_caps & RE_C_CONTIGRX) 2710 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2711 else 2712 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2713 } 2714 2715 if (sc->re_flags & RE_F_TESTMODE) 2716 return; 2717 2718 mii_mediachg(mii); 2719 2720 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2721 2722 ifp->if_flags |= IFF_RUNNING; 2723 ifq_clr_oactive(&ifp->if_snd); 2724 2725 callout_reset(&sc->re_timer, hz, re_tick, sc); 2726 } 2727 2728 /* 2729 * Set media options. 2730 */ 2731 static int 2732 re_ifmedia_upd(struct ifnet *ifp) 2733 { 2734 struct re_softc *sc = ifp->if_softc; 2735 struct mii_data *mii; 2736 2737 ASSERT_SERIALIZED(ifp->if_serializer); 2738 2739 mii = device_get_softc(sc->re_miibus); 2740 mii_mediachg(mii); 2741 2742 return(0); 2743 } 2744 2745 /* 2746 * Report current media status. 2747 */ 2748 static void 2749 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2750 { 2751 struct re_softc *sc = ifp->if_softc; 2752 struct mii_data *mii; 2753 2754 ASSERT_SERIALIZED(ifp->if_serializer); 2755 2756 mii = device_get_softc(sc->re_miibus); 2757 2758 mii_pollstat(mii); 2759 ifmr->ifm_active = mii->mii_media_active; 2760 ifmr->ifm_status = mii->mii_media_status; 2761 } 2762 2763 static int 2764 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2765 { 2766 struct re_softc *sc = ifp->if_softc; 2767 struct ifreq *ifr = (struct ifreq *) data; 2768 struct mii_data *mii; 2769 int error = 0, mask; 2770 2771 ASSERT_SERIALIZED(ifp->if_serializer); 2772 2773 switch(command) { 2774 case SIOCSIFMTU: 2775 if (ifr->ifr_mtu > sc->re_maxmtu) { 2776 error = EINVAL; 2777 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2778 ifp->if_mtu = ifr->ifr_mtu; 2779 if (ifp->if_flags & IFF_RUNNING) 2780 ifp->if_init(sc); 2781 } 2782 break; 2783 2784 case SIOCSIFFLAGS: 2785 if (ifp->if_flags & IFF_UP) { 2786 if (ifp->if_flags & IFF_RUNNING) { 2787 if ((ifp->if_flags ^ sc->re_if_flags) & 2788 (IFF_PROMISC | IFF_ALLMULTI)) 2789 re_setmulti(sc); 2790 } else { 2791 re_init(sc); 2792 } 2793 } else if (ifp->if_flags & IFF_RUNNING) { 2794 re_stop(sc); 2795 } 2796 sc->re_if_flags = ifp->if_flags; 2797 break; 2798 2799 case SIOCADDMULTI: 2800 case SIOCDELMULTI: 2801 re_setmulti(sc); 2802 break; 2803 2804 case SIOCGIFMEDIA: 2805 case SIOCSIFMEDIA: 2806 mii = device_get_softc(sc->re_miibus); 2807 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2808 break; 2809 2810 case SIOCSIFCAP: 2811 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2812 ifp->if_capabilities; 2813 ifp->if_capenable ^= mask; 2814 2815 if (mask & IFCAP_HWCSUM) { 2816 if (ifp->if_capenable & IFCAP_TXCSUM) 2817 ifp->if_hwassist = RE_CSUM_FEATURES; 2818 else 2819 ifp->if_hwassist = 0; 2820 } 2821 if (mask && (ifp->if_flags & IFF_RUNNING)) 2822 re_init(sc); 2823 break; 2824 2825 default: 2826 error = ether_ioctl(ifp, command, data); 2827 break; 2828 } 2829 return(error); 2830 } 2831 2832 static void 2833 re_watchdog(struct ifnet *ifp) 2834 { 2835 struct re_softc *sc = ifp->if_softc; 2836 2837 ASSERT_SERIALIZED(ifp->if_serializer); 2838 2839 if_printf(ifp, "watchdog timeout\n"); 2840 2841 IFNET_STAT_INC(ifp, oerrors, 1); 2842 2843 re_txeof(sc); 2844 re_rxeof(sc); 2845 2846 re_init(sc); 2847 2848 if (!ifq_is_empty(&ifp->if_snd)) 2849 if_devstart(ifp); 2850 } 2851 2852 /* 2853 * Stop the adapter and free any mbufs allocated to the 2854 * RX and TX lists. 2855 */ 2856 static void 2857 re_stop(struct re_softc *sc) 2858 { 2859 struct ifnet *ifp = &sc->arpcom.ac_if; 2860 int i; 2861 2862 ASSERT_SERIALIZED(ifp->if_serializer); 2863 2864 /* Reset the adapter. */ 2865 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2866 2867 ifp->if_timer = 0; 2868 callout_stop(&sc->re_timer); 2869 2870 ifp->if_flags &= ~IFF_RUNNING; 2871 ifq_clr_oactive(&ifp->if_snd); 2872 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2873 2874 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2875 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2876 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2877 2878 re_free_rxchain(sc); 2879 2880 /* Free the TX list buffers. */ 2881 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2882 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2883 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2884 sc->re_ldata.re_tx_dmamap[i]); 2885 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2886 sc->re_ldata.re_tx_mbuf[i] = NULL; 2887 } 2888 } 2889 2890 /* Free the RX list buffers. */ 2891 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2892 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2893 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2894 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2895 sc->re_ldata.re_rx_dmamap[i]); 2896 } 2897 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2898 sc->re_ldata.re_rx_mbuf[i] = NULL; 2899 } 2900 } 2901 } 2902 2903 /* 2904 * Device suspend routine. Stop the interface and save some PCI 2905 * settings in case the BIOS doesn't restore them properly on 2906 * resume. 2907 */ 2908 static int 2909 re_suspend(device_t dev) 2910 { 2911 #ifndef BURN_BRIDGES 2912 int i; 2913 #endif 2914 struct re_softc *sc = device_get_softc(dev); 2915 struct ifnet *ifp = &sc->arpcom.ac_if; 2916 2917 lwkt_serialize_enter(ifp->if_serializer); 2918 2919 re_stop(sc); 2920 2921 #ifndef BURN_BRIDGES 2922 for (i = 0; i < 5; i++) 2923 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2924 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2925 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2926 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2927 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2928 #endif 2929 2930 sc->re_flags |= RE_F_SUSPENDED; 2931 2932 lwkt_serialize_exit(ifp->if_serializer); 2933 2934 return (0); 2935 } 2936 2937 /* 2938 * Device resume routine. Restore some PCI settings in case the BIOS 2939 * doesn't, re-enable busmastering, and restart the interface if 2940 * appropriate. 2941 */ 2942 static int 2943 re_resume(device_t dev) 2944 { 2945 struct re_softc *sc = device_get_softc(dev); 2946 struct ifnet *ifp = &sc->arpcom.ac_if; 2947 #ifndef BURN_BRIDGES 2948 int i; 2949 #endif 2950 2951 lwkt_serialize_enter(ifp->if_serializer); 2952 2953 #ifndef BURN_BRIDGES 2954 /* better way to do this? */ 2955 for (i = 0; i < 5; i++) 2956 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2957 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2958 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2959 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2960 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2961 2962 /* reenable busmastering */ 2963 pci_enable_busmaster(dev); 2964 pci_enable_io(dev, SYS_RES_IOPORT); 2965 #endif 2966 2967 /* reinitialize interface if necessary */ 2968 if (ifp->if_flags & IFF_UP) 2969 re_init(sc); 2970 2971 sc->re_flags &= ~RE_F_SUSPENDED; 2972 2973 lwkt_serialize_exit(ifp->if_serializer); 2974 2975 return (0); 2976 } 2977 2978 /* 2979 * Stop all chip I/O so that the kernel's probe routines don't 2980 * get confused by errant DMAs when rebooting. 2981 */ 2982 static void 2983 re_shutdown(device_t dev) 2984 { 2985 struct re_softc *sc = device_get_softc(dev); 2986 struct ifnet *ifp = &sc->arpcom.ac_if; 2987 2988 lwkt_serialize_enter(ifp->if_serializer); 2989 re_stop(sc); 2990 lwkt_serialize_exit(ifp->if_serializer); 2991 } 2992 2993 static int 2994 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 2995 { 2996 struct re_softc *sc = arg1; 2997 2998 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 2999 } 3000 3001 static int 3002 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 3003 { 3004 struct re_softc *sc = arg1; 3005 3006 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 3007 } 3008 3009 static int 3010 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 3011 { 3012 struct re_softc *sc = arg1; 3013 struct ifnet *ifp = &sc->arpcom.ac_if; 3014 int error, v; 3015 3016 lwkt_serialize_enter(ifp->if_serializer); 3017 3018 v = *hwtime; 3019 error = sysctl_handle_int(oidp, &v, 0, req); 3020 if (error || req->newptr == NULL) 3021 goto back; 3022 3023 if (v <= 0) { 3024 error = EINVAL; 3025 goto back; 3026 } 3027 3028 if (v != *hwtime) { 3029 *hwtime = v; 3030 3031 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3032 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3033 re_setup_hw_im(sc); 3034 } 3035 back: 3036 lwkt_serialize_exit(ifp->if_serializer); 3037 return error; 3038 } 3039 3040 static int 3041 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3042 { 3043 struct re_softc *sc = arg1; 3044 struct ifnet *ifp = &sc->arpcom.ac_if; 3045 int error, v; 3046 3047 lwkt_serialize_enter(ifp->if_serializer); 3048 3049 v = sc->re_sim_time; 3050 error = sysctl_handle_int(oidp, &v, 0, req); 3051 if (error || req->newptr == NULL) 3052 goto back; 3053 3054 if (v <= 0) { 3055 error = EINVAL; 3056 goto back; 3057 } 3058 3059 if (v != sc->re_sim_time) { 3060 sc->re_sim_time = v; 3061 3062 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3063 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3064 #ifdef foo 3065 int reg; 3066 3067 /* 3068 * Following code causes various strange 3069 * performance problems. Hmm ... 3070 */ 3071 CSR_WRITE_2(sc, RE_IMR, 0); 3072 if (!RE_IS_8139CP(sc)) 3073 reg = RE_TIMERINT_8169; 3074 else 3075 reg = RE_TIMERINT; 3076 CSR_WRITE_4(sc, reg, 0); 3077 CSR_READ_4(sc, reg); /* flush */ 3078 3079 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3080 re_setup_sim_im(sc); 3081 #else 3082 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3083 DELAY(10); 3084 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3085 #endif 3086 } 3087 } 3088 back: 3089 lwkt_serialize_exit(ifp->if_serializer); 3090 return error; 3091 } 3092 3093 static int 3094 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3095 { 3096 struct re_softc *sc = arg1; 3097 struct ifnet *ifp = &sc->arpcom.ac_if; 3098 int error, v; 3099 3100 lwkt_serialize_enter(ifp->if_serializer); 3101 3102 v = sc->re_imtype; 3103 error = sysctl_handle_int(oidp, &v, 0, req); 3104 if (error || req->newptr == NULL) 3105 goto back; 3106 3107 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3108 error = EINVAL; 3109 goto back; 3110 } 3111 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3112 /* Can't do hardware interrupt moderation */ 3113 error = EOPNOTSUPP; 3114 goto back; 3115 } 3116 3117 if (v != sc->re_imtype) { 3118 sc->re_imtype = v; 3119 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3120 IFF_RUNNING) 3121 re_setup_intr(sc, 1, sc->re_imtype); 3122 } 3123 back: 3124 lwkt_serialize_exit(ifp->if_serializer); 3125 return error; 3126 } 3127 3128 static void 3129 re_setup_hw_im(struct re_softc *sc) 3130 { 3131 KKASSERT(sc->re_caps & RE_C_HWIM); 3132 3133 /* 3134 * Interrupt moderation 3135 * 3136 * 0xABCD 3137 * A - unknown (maybe TX related) 3138 * B - TX timer (unit: 25us) 3139 * C - unknown (maybe RX related) 3140 * D - RX timer (unit: 25us) 3141 * 3142 * 3143 * re(4)'s interrupt moderation is actually controlled by 3144 * two variables, like most other NICs (bge, bce etc.) 3145 * o timer 3146 * o number of packets [P] 3147 * 3148 * The logic relationship between these two variables is 3149 * similar to other NICs too: 3150 * if (timer expire || packets > [P]) 3151 * Interrupt is delivered 3152 * 3153 * Currently we only know how to set 'timer', but not 3154 * 'number of packets', which should be ~30, as far as I 3155 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3156 */ 3157 CSR_WRITE_2(sc, RE_IM, 3158 RE_IM_RXTIME(sc->re_rx_time) | 3159 RE_IM_TXTIME(sc->re_tx_time) | 3160 RE_IM_MAGIC); 3161 } 3162 3163 static void 3164 re_disable_hw_im(struct re_softc *sc) 3165 { 3166 if (sc->re_caps & RE_C_HWIM) 3167 CSR_WRITE_2(sc, RE_IM, 0); 3168 } 3169 3170 static void 3171 re_setup_sim_im(struct re_softc *sc) 3172 { 3173 if (!RE_IS_8139CP(sc)) { 3174 uint32_t ticks; 3175 3176 /* 3177 * Datasheet says tick decreases at bus speed, 3178 * but it seems the clock runs a little bit 3179 * faster, so we do some compensation here. 3180 */ 3181 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3182 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3183 } else { 3184 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3185 } 3186 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3187 sc->re_flags |= RE_F_TIMER_INTR; 3188 } 3189 3190 static void 3191 re_disable_sim_im(struct re_softc *sc) 3192 { 3193 if (!RE_IS_8139CP(sc)) 3194 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3195 else 3196 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3197 sc->re_flags &= ~RE_F_TIMER_INTR; 3198 } 3199 3200 static void 3201 re_config_imtype(struct re_softc *sc, int imtype) 3202 { 3203 switch (imtype) { 3204 case RE_IMTYPE_HW: 3205 KKASSERT(sc->re_caps & RE_C_HWIM); 3206 /* FALL THROUGH */ 3207 case RE_IMTYPE_NONE: 3208 sc->re_intrs = RE_INTRS; 3209 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3210 RE_ISR_RX_OVERRUN; 3211 sc->re_tx_ack = RE_ISR_TX_OK; 3212 break; 3213 3214 case RE_IMTYPE_SIM: 3215 sc->re_intrs = RE_INTRS_TIMER; 3216 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3217 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3218 break; 3219 3220 default: 3221 panic("%s: unknown imtype %d", 3222 sc->arpcom.ac_if.if_xname, imtype); 3223 } 3224 } 3225 3226 static void 3227 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3228 { 3229 re_config_imtype(sc, imtype); 3230 3231 if (enable_intrs) 3232 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3233 else 3234 CSR_WRITE_2(sc, RE_IMR, 0); 3235 3236 sc->re_npoll.ifpc_stcount = 0; 3237 3238 switch (imtype) { 3239 case RE_IMTYPE_NONE: 3240 re_disable_sim_im(sc); 3241 re_disable_hw_im(sc); 3242 break; 3243 3244 case RE_IMTYPE_HW: 3245 KKASSERT(sc->re_caps & RE_C_HWIM); 3246 re_disable_sim_im(sc); 3247 re_setup_hw_im(sc); 3248 break; 3249 3250 case RE_IMTYPE_SIM: 3251 re_disable_hw_im(sc); 3252 re_setup_sim_im(sc); 3253 break; 3254 3255 default: 3256 panic("%s: unknown imtype %d", 3257 sc->arpcom.ac_if.if_xname, imtype); 3258 } 3259 } 3260 3261 static void 3262 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3263 { 3264 int i; 3265 3266 if (sc->re_macver == RE_MACVER_11 || 3267 sc->re_macver == RE_MACVER_12 || 3268 sc->re_macver == RE_MACVER_30 || 3269 sc->re_macver == RE_MACVER_31) { 3270 uint16_t re_did; 3271 3272 re_get_eewidth(sc); 3273 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3274 if (re_did == 0x8128) { 3275 uint16_t as[ETHER_ADDR_LEN / 2]; 3276 int eaddr_off; 3277 3278 if (sc->re_macver == RE_MACVER_30 || 3279 sc->re_macver == RE_MACVER_31) 3280 eaddr_off = RE_EE_EADDR1; 3281 else 3282 eaddr_off = RE_EE_EADDR0; 3283 3284 /* 3285 * Get station address from the EEPROM. 3286 */ 3287 re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3); 3288 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3289 as[i] = le16toh(as[i]); 3290 bcopy(as, eaddr, ETHER_ADDR_LEN); 3291 return; 3292 } 3293 } 3294 3295 /* 3296 * Get station address from IDRx. 3297 */ 3298 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3299 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3300 } 3301 3302 static int 3303 re_jpool_alloc(struct re_softc *sc) 3304 { 3305 struct re_list_data *ldata = &sc->re_ldata; 3306 struct re_jbuf *jbuf; 3307 bus_addr_t paddr; 3308 bus_size_t jpool_size; 3309 bus_dmamem_t dmem; 3310 caddr_t buf; 3311 int i, error; 3312 3313 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3314 3315 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3316 M_DEVBUF, M_WAITOK | M_ZERO); 3317 3318 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3319 3320 error = bus_dmamem_coherent(sc->re_parent_tag, 3321 RE_RXBUF_ALIGN, 0, 3322 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3323 jpool_size, BUS_DMA_WAITOK, &dmem); 3324 if (error) { 3325 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3326 return error; 3327 } 3328 ldata->re_jpool_tag = dmem.dmem_tag; 3329 ldata->re_jpool_map = dmem.dmem_map; 3330 ldata->re_jpool = dmem.dmem_addr; 3331 paddr = dmem.dmem_busaddr; 3332 3333 /* ..and split it into 9KB chunks */ 3334 SLIST_INIT(&ldata->re_jbuf_free); 3335 3336 buf = ldata->re_jpool; 3337 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3338 jbuf = &ldata->re_jbuf[i]; 3339 3340 jbuf->re_sc = sc; 3341 jbuf->re_inuse = 0; 3342 jbuf->re_slot = i; 3343 jbuf->re_buf = buf; 3344 jbuf->re_paddr = paddr; 3345 3346 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3347 3348 buf += RE_JBUF_SIZE; 3349 paddr += RE_JBUF_SIZE; 3350 } 3351 return 0; 3352 } 3353 3354 static void 3355 re_jpool_free(struct re_softc *sc) 3356 { 3357 struct re_list_data *ldata = &sc->re_ldata; 3358 3359 if (ldata->re_jpool_tag != NULL) { 3360 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3361 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3362 ldata->re_jpool_map); 3363 bus_dma_tag_destroy(ldata->re_jpool_tag); 3364 ldata->re_jpool_tag = NULL; 3365 } 3366 3367 if (ldata->re_jbuf != NULL) { 3368 kfree(ldata->re_jbuf, M_DEVBUF); 3369 ldata->re_jbuf = NULL; 3370 } 3371 } 3372 3373 static struct re_jbuf * 3374 re_jbuf_alloc(struct re_softc *sc) 3375 { 3376 struct re_list_data *ldata = &sc->re_ldata; 3377 struct re_jbuf *jbuf; 3378 3379 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3380 3381 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3382 if (jbuf != NULL) { 3383 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3384 jbuf->re_inuse = 1; 3385 } 3386 3387 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3388 3389 return jbuf; 3390 } 3391 3392 static void 3393 re_jbuf_free(void *arg) 3394 { 3395 struct re_jbuf *jbuf = arg; 3396 struct re_softc *sc = jbuf->re_sc; 3397 struct re_list_data *ldata = &sc->re_ldata; 3398 3399 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3400 panic("%s: free wrong jumbo buffer", 3401 sc->arpcom.ac_if.if_xname); 3402 } else if (jbuf->re_inuse == 0) { 3403 panic("%s: jumbo buffer already freed", 3404 sc->arpcom.ac_if.if_xname); 3405 } 3406 3407 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3408 atomic_subtract_int(&jbuf->re_inuse, 1); 3409 if (jbuf->re_inuse == 0) 3410 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3411 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3412 } 3413 3414 static void 3415 re_jbuf_ref(void *arg) 3416 { 3417 struct re_jbuf *jbuf = arg; 3418 struct re_softc *sc = jbuf->re_sc; 3419 struct re_list_data *ldata = &sc->re_ldata; 3420 3421 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3422 panic("%s: ref wrong jumbo buffer", 3423 sc->arpcom.ac_if.if_xname); 3424 } else if (jbuf->re_inuse == 0) { 3425 panic("%s: jumbo buffer already freed", 3426 sc->arpcom.ac_if.if_xname); 3427 } 3428 atomic_add_int(&jbuf->re_inuse, 1); 3429 } 3430