1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #define _IP_VHL 115 116 #include "opt_polling.h" 117 118 #include <sys/param.h> 119 #include <sys/bus.h> 120 #include <sys/endian.h> 121 #include <sys/kernel.h> 122 #include <sys/in_cksum.h> 123 #include <sys/interrupt.h> 124 #include <sys/malloc.h> 125 #include <sys/mbuf.h> 126 #include <sys/rman.h> 127 #include <sys/serialize.h> 128 #include <sys/socket.h> 129 #include <sys/sockio.h> 130 #include <sys/sysctl.h> 131 132 #include <net/bpf.h> 133 #include <net/ethernet.h> 134 #include <net/if.h> 135 #include <net/ifq_var.h> 136 #include <net/if_arp.h> 137 #include <net/if_dl.h> 138 #include <net/if_media.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct re_type { 164 uint16_t re_vid; 165 uint16_t re_did; 166 const char *re_name; 167 } re_devs[] = { 168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 175 "RealTek 810x PCIe 10/100baseTX" }, 176 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 178 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 179 180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 181 "RealTek 8110/8169 Gigabit Ethernet" }, 182 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 187 "Corega CG-LAPCIGT Gigabit Ethernet" }, 188 189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" }, 191 192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 193 "US Robotics 997902 Gigabit Ethernet" }, 194 195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 196 "TTTech MC322 Gigabit Ethernet" }, 197 198 { 0, 0, NULL } 199 }; 200 201 static const struct re_hwrev re_hwrevs[] = { 202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 204 205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 206 RE_C_HWCSUM | RE_C_8169 }, 207 208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 209 RE_C_HWCSUM | RE_C_8169 }, 210 211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 212 RE_C_HWCSUM | RE_C_8169 }, 213 214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 216 217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 219 220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 222 223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 225 226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 228 229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 231 232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 245 RE_C_HWCSUM | RE_C_FASTE }, 246 247 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 248 RE_C_HWCSUM | RE_C_FASTE }, 249 250 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 251 RE_C_HWCSUM | RE_C_FASTE }, 252 253 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 254 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 255 RE_C_FASTE }, 256 257 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 258 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 259 RE_C_FASTE }, 260 261 { RE_HWREV_NULL, 0, 0, 0 } 262 }; 263 264 static int re_probe(device_t); 265 static int re_attach(device_t); 266 static int re_detach(device_t); 267 static int re_suspend(device_t); 268 static int re_resume(device_t); 269 static void re_shutdown(device_t); 270 271 static int re_allocmem(device_t); 272 static void re_freemem(device_t); 273 static void re_freebufmem(struct re_softc *, int, int); 274 static int re_encap(struct re_softc *, struct mbuf **, int *); 275 static int re_newbuf_std(struct re_softc *, int, int); 276 static int re_newbuf_jumbo(struct re_softc *, int, int); 277 static void re_setup_rxdesc(struct re_softc *, int); 278 static int re_rx_list_init(struct re_softc *); 279 static int re_tx_list_init(struct re_softc *); 280 static int re_rxeof(struct re_softc *); 281 static int re_txeof(struct re_softc *); 282 static int re_tx_collect(struct re_softc *); 283 static void re_intr(void *); 284 static void re_tick(void *); 285 static void re_tick_serialized(void *); 286 287 static void re_start(struct ifnet *); 288 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 289 static void re_init(void *); 290 static void re_stop(struct re_softc *); 291 static void re_watchdog(struct ifnet *); 292 static int re_ifmedia_upd(struct ifnet *); 293 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 294 295 static void re_eeprom_putbyte(struct re_softc *, int); 296 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 297 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 298 static void re_get_eewidth(struct re_softc *); 299 300 static int re_gmii_readreg(device_t, int, int); 301 static int re_gmii_writereg(device_t, int, int, int); 302 303 static int re_miibus_readreg(device_t, int, int); 304 static int re_miibus_writereg(device_t, int, int, int); 305 static void re_miibus_statchg(device_t); 306 307 static void re_setmulti(struct re_softc *); 308 static void re_reset(struct re_softc *, int); 309 static void re_get_eaddr(struct re_softc *, uint8_t *); 310 311 static void re_setup_hw_im(struct re_softc *); 312 static void re_setup_sim_im(struct re_softc *); 313 static void re_disable_hw_im(struct re_softc *); 314 static void re_disable_sim_im(struct re_softc *); 315 static void re_config_imtype(struct re_softc *, int); 316 static void re_setup_intr(struct re_softc *, int, int); 317 318 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 319 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 320 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 321 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 322 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 323 324 static int re_jpool_alloc(struct re_softc *); 325 static void re_jpool_free(struct re_softc *); 326 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 327 static void re_jbuf_free(void *); 328 static void re_jbuf_ref(void *); 329 330 #ifdef RE_DIAG 331 static int re_diag(struct re_softc *); 332 #endif 333 334 #ifdef DEVICE_POLLING 335 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 336 #endif 337 338 static device_method_t re_methods[] = { 339 /* Device interface */ 340 DEVMETHOD(device_probe, re_probe), 341 DEVMETHOD(device_attach, re_attach), 342 DEVMETHOD(device_detach, re_detach), 343 DEVMETHOD(device_suspend, re_suspend), 344 DEVMETHOD(device_resume, re_resume), 345 DEVMETHOD(device_shutdown, re_shutdown), 346 347 /* bus interface */ 348 DEVMETHOD(bus_print_child, bus_generic_print_child), 349 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 350 351 /* MII interface */ 352 DEVMETHOD(miibus_readreg, re_miibus_readreg), 353 DEVMETHOD(miibus_writereg, re_miibus_writereg), 354 DEVMETHOD(miibus_statchg, re_miibus_statchg), 355 356 { 0, 0 } 357 }; 358 359 static driver_t re_driver = { 360 "re", 361 re_methods, 362 sizeof(struct re_softc) 363 }; 364 365 static devclass_t re_devclass; 366 367 DECLARE_DUMMY_MODULE(if_re); 368 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 369 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 370 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 371 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 372 373 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 374 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 375 376 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 377 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 378 379 #define EE_SET(x) \ 380 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 381 382 #define EE_CLR(x) \ 383 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 384 385 static __inline void 386 re_free_rxchain(struct re_softc *sc) 387 { 388 if (sc->re_head != NULL) { 389 m_freem(sc->re_head); 390 sc->re_head = sc->re_tail = NULL; 391 } 392 } 393 394 /* 395 * Send a read command and address to the EEPROM, check for ACK. 396 */ 397 static void 398 re_eeprom_putbyte(struct re_softc *sc, int addr) 399 { 400 int d, i; 401 402 d = addr | (RE_9346_READ << sc->re_eewidth); 403 404 /* 405 * Feed in each bit and strobe the clock. 406 */ 407 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 408 if (d & i) 409 EE_SET(RE_EE_DATAIN); 410 else 411 EE_CLR(RE_EE_DATAIN); 412 DELAY(100); 413 EE_SET(RE_EE_CLK); 414 DELAY(150); 415 EE_CLR(RE_EE_CLK); 416 DELAY(100); 417 } 418 } 419 420 /* 421 * Read a word of data stored in the EEPROM at address 'addr.' 422 */ 423 static void 424 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 425 { 426 int i; 427 uint16_t word = 0; 428 429 /* 430 * Send address of word we want to read. 431 */ 432 re_eeprom_putbyte(sc, addr); 433 434 /* 435 * Start reading bits from EEPROM. 436 */ 437 for (i = 0x8000; i != 0; i >>= 1) { 438 EE_SET(RE_EE_CLK); 439 DELAY(100); 440 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 441 word |= i; 442 EE_CLR(RE_EE_CLK); 443 DELAY(100); 444 } 445 446 *dest = word; 447 } 448 449 /* 450 * Read a sequence of words from the EEPROM. 451 */ 452 static void 453 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 454 { 455 int i; 456 uint16_t word = 0, *ptr; 457 458 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 459 DELAY(100); 460 461 for (i = 0; i < cnt; i++) { 462 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 463 re_eeprom_getword(sc, off + i, &word); 464 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 465 ptr = (uint16_t *)(dest + (i * 2)); 466 *ptr = word; 467 } 468 469 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 470 } 471 472 static void 473 re_get_eewidth(struct re_softc *sc) 474 { 475 uint16_t re_did = 0; 476 477 sc->re_eewidth = 6; 478 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 479 if (re_did != 0x8129) 480 sc->re_eewidth = 8; 481 } 482 483 static int 484 re_gmii_readreg(device_t dev, int phy, int reg) 485 { 486 struct re_softc *sc = device_get_softc(dev); 487 u_int32_t rval; 488 int i; 489 490 if (phy != 1) 491 return(0); 492 493 /* Let the rgephy driver read the GMEDIASTAT register */ 494 495 if (reg == RE_GMEDIASTAT) 496 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 497 498 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 499 DELAY(1000); 500 501 for (i = 0; i < RE_TIMEOUT; i++) { 502 rval = CSR_READ_4(sc, RE_PHYAR); 503 if (rval & RE_PHYAR_BUSY) 504 break; 505 DELAY(100); 506 } 507 508 if (i == RE_TIMEOUT) { 509 device_printf(dev, "PHY read failed\n"); 510 return(0); 511 } 512 513 return(rval & RE_PHYAR_PHYDATA); 514 } 515 516 static int 517 re_gmii_writereg(device_t dev, int phy, int reg, int data) 518 { 519 struct re_softc *sc = device_get_softc(dev); 520 uint32_t rval; 521 int i; 522 523 CSR_WRITE_4(sc, RE_PHYAR, 524 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 525 DELAY(1000); 526 527 for (i = 0; i < RE_TIMEOUT; i++) { 528 rval = CSR_READ_4(sc, RE_PHYAR); 529 if ((rval & RE_PHYAR_BUSY) == 0) 530 break; 531 DELAY(100); 532 } 533 534 if (i == RE_TIMEOUT) 535 device_printf(dev, "PHY write failed\n"); 536 537 return(0); 538 } 539 540 static int 541 re_miibus_readreg(device_t dev, int phy, int reg) 542 { 543 struct re_softc *sc = device_get_softc(dev); 544 uint16_t rval = 0; 545 uint16_t re8139_reg = 0; 546 547 if (!RE_IS_8139CP(sc)) { 548 rval = re_gmii_readreg(dev, phy, reg); 549 return(rval); 550 } 551 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return(0); 555 556 switch(reg) { 557 case MII_BMCR: 558 re8139_reg = RE_BMCR; 559 break; 560 case MII_BMSR: 561 re8139_reg = RE_BMSR; 562 break; 563 case MII_ANAR: 564 re8139_reg = RE_ANAR; 565 break; 566 case MII_ANER: 567 re8139_reg = RE_ANER; 568 break; 569 case MII_ANLPAR: 570 re8139_reg = RE_LPAR; 571 break; 572 case MII_PHYIDR1: 573 case MII_PHYIDR2: 574 return(0); 575 /* 576 * Allow the rlphy driver to read the media status 577 * register. If we have a link partner which does not 578 * support NWAY, this is the register which will tell 579 * us the results of parallel detection. 580 */ 581 case RE_MEDIASTAT: 582 return(CSR_READ_1(sc, RE_MEDIASTAT)); 583 default: 584 device_printf(dev, "bad phy register\n"); 585 return(0); 586 } 587 rval = CSR_READ_2(sc, re8139_reg); 588 if (re8139_reg == RE_BMCR) { 589 /* 8139C+ has different bit layout. */ 590 rval &= ~(BMCR_LOOP | BMCR_ISO); 591 } 592 return(rval); 593 } 594 595 static int 596 re_miibus_writereg(device_t dev, int phy, int reg, int data) 597 { 598 struct re_softc *sc= device_get_softc(dev); 599 u_int16_t re8139_reg = 0; 600 601 if (!RE_IS_8139CP(sc)) 602 return(re_gmii_writereg(dev, phy, reg, data)); 603 604 /* Pretend the internal PHY is only at address 0 */ 605 if (phy) 606 return(0); 607 608 switch(reg) { 609 case MII_BMCR: 610 re8139_reg = RE_BMCR; 611 /* 8139C+ has different bit layout. */ 612 data &= ~(BMCR_LOOP | BMCR_ISO); 613 break; 614 case MII_BMSR: 615 re8139_reg = RE_BMSR; 616 break; 617 case MII_ANAR: 618 re8139_reg = RE_ANAR; 619 break; 620 case MII_ANER: 621 re8139_reg = RE_ANER; 622 break; 623 case MII_ANLPAR: 624 re8139_reg = RE_LPAR; 625 break; 626 case MII_PHYIDR1: 627 case MII_PHYIDR2: 628 return(0); 629 default: 630 device_printf(dev, "bad phy register\n"); 631 return(0); 632 } 633 CSR_WRITE_2(sc, re8139_reg, data); 634 return(0); 635 } 636 637 static void 638 re_miibus_statchg(device_t dev) 639 { 640 } 641 642 /* 643 * Program the 64-bit multicast hash filter. 644 */ 645 static void 646 re_setmulti(struct re_softc *sc) 647 { 648 struct ifnet *ifp = &sc->arpcom.ac_if; 649 int h = 0; 650 uint32_t hashes[2] = { 0, 0 }; 651 struct ifmultiaddr *ifma; 652 uint32_t rxfilt; 653 int mcnt = 0; 654 655 rxfilt = CSR_READ_4(sc, RE_RXCFG); 656 657 /* Set the individual bit to receive frames for this host only. */ 658 rxfilt |= RE_RXCFG_RX_INDIV; 659 /* Set capture broadcast bit to capture broadcast frames. */ 660 rxfilt |= RE_RXCFG_RX_BROAD; 661 662 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 663 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 664 rxfilt |= RE_RXCFG_RX_MULTI; 665 666 /* If we want promiscuous mode, set the allframes bit. */ 667 if (ifp->if_flags & IFF_PROMISC) 668 rxfilt |= RE_RXCFG_RX_ALLPHYS; 669 670 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 671 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 672 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 673 return; 674 } 675 676 /* first, zot all the existing hash bits */ 677 CSR_WRITE_4(sc, RE_MAR0, 0); 678 CSR_WRITE_4(sc, RE_MAR4, 0); 679 680 /* now program new ones */ 681 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 682 if (ifma->ifma_addr->sa_family != AF_LINK) 683 continue; 684 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 685 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 686 if (h < 32) 687 hashes[0] |= (1 << h); 688 else 689 hashes[1] |= (1 << (h - 32)); 690 mcnt++; 691 } 692 693 if (mcnt) 694 rxfilt |= RE_RXCFG_RX_MULTI; 695 else 696 rxfilt &= ~RE_RXCFG_RX_MULTI; 697 698 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 699 700 /* 701 * For some unfathomable reason, RealTek decided to reverse 702 * the order of the multicast hash registers in the PCI Express 703 * parts. This means we have to write the hash pattern in reverse 704 * order for those devices. 705 */ 706 if (sc->re_caps & RE_C_PCIE) { 707 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); 708 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); 709 } else { 710 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 711 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 712 } 713 } 714 715 static void 716 re_reset(struct re_softc *sc, int running) 717 { 718 int i; 719 720 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 721 CSR_WRITE_1(sc, RE_COMMAND, 722 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 723 DELAY(100); 724 } 725 726 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 727 728 for (i = 0; i < RE_TIMEOUT; i++) { 729 DELAY(10); 730 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 731 break; 732 } 733 if (i == RE_TIMEOUT) 734 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 735 } 736 737 #ifdef RE_DIAG 738 /* 739 * The following routine is designed to test for a defect on some 740 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 741 * lines connected to the bus, however for a 32-bit only card, they 742 * should be pulled high. The result of this defect is that the 743 * NIC will not work right if you plug it into a 64-bit slot: DMA 744 * operations will be done with 64-bit transfers, which will fail 745 * because the 64-bit data lines aren't connected. 746 * 747 * There's no way to work around this (short of talking a soldering 748 * iron to the board), however we can detect it. The method we use 749 * here is to put the NIC into digital loopback mode, set the receiver 750 * to promiscuous mode, and then try to send a frame. We then compare 751 * the frame data we sent to what was received. If the data matches, 752 * then the NIC is working correctly, otherwise we know the user has 753 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 754 * slot. In the latter case, there's no way the NIC can work correctly, 755 * so we print out a message on the console and abort the device attach. 756 */ 757 758 static int 759 re_diag(struct re_softc *sc) 760 { 761 struct ifnet *ifp = &sc->arpcom.ac_if; 762 struct mbuf *m0; 763 struct ether_header *eh; 764 struct re_desc *cur_rx; 765 uint16_t status; 766 uint32_t rxstat; 767 int total_len, i, error = 0, phyaddr; 768 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 769 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 770 771 /* Allocate a single mbuf */ 772 773 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 774 if (m0 == NULL) 775 return(ENOBUFS); 776 777 /* 778 * Initialize the NIC in test mode. This sets the chip up 779 * so that it can send and receive frames, but performs the 780 * following special functions: 781 * - Puts receiver in promiscuous mode 782 * - Enables digital loopback mode 783 * - Leaves interrupts turned off 784 */ 785 786 ifp->if_flags |= IFF_PROMISC; 787 sc->re_flags |= RE_F_TESTMODE; 788 re_init(sc); 789 sc->re_flags |= RE_F_LINKED; 790 if (!RE_IS_8139CP(sc)) 791 phyaddr = 1; 792 else 793 phyaddr = 0; 794 795 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 796 for (i = 0; i < RE_TIMEOUT; i++) { 797 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 798 if (!(status & BMCR_RESET)) 799 break; 800 } 801 802 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 803 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 804 805 DELAY(100000); 806 807 /* Put some data in the mbuf */ 808 809 eh = mtod(m0, struct ether_header *); 810 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 811 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 812 eh->ether_type = htons(ETHERTYPE_IP); 813 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 814 815 /* 816 * Queue the packet, start transmission. 817 * Note: ifq_handoff() ultimately calls re_start() for us. 818 */ 819 820 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 821 error = ifq_handoff(ifp, m0, NULL); 822 if (error) { 823 m0 = NULL; 824 goto done; 825 } 826 m0 = NULL; 827 828 /* Wait for it to propagate through the chip */ 829 830 DELAY(100000); 831 for (i = 0; i < RE_TIMEOUT; i++) { 832 status = CSR_READ_2(sc, RE_ISR); 833 CSR_WRITE_2(sc, RE_ISR, status); 834 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 835 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 836 break; 837 DELAY(10); 838 } 839 840 if (i == RE_TIMEOUT) { 841 if_printf(ifp, "diagnostic failed to receive packet " 842 "in loopback mode\n"); 843 error = EIO; 844 goto done; 845 } 846 847 /* 848 * The packet should have been dumped into the first 849 * entry in the RX DMA ring. Grab it from there. 850 */ 851 852 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 853 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 854 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 857 sc->re_ldata.re_rx_dmamap[0]); 858 859 m0 = sc->re_ldata.re_rx_mbuf[0]; 860 sc->re_ldata.re_rx_mbuf[0] = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->re_ldata.re_rx_list[0]; 864 total_len = RE_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->re_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 if_printf(ifp, "diagnostic failed, received short packet\n"); 869 error = EIO; 870 goto done; 871 } 872 873 /* Test that the received packet data matches what we sent. */ 874 875 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 876 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 877 be16toh(eh->ether_type) != ETHERTYPE_IP) { 878 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 879 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 880 dst, ":", src, ":", ETHERTYPE_IP); 881 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 882 eh->ether_dhost, ":", eh->ether_shost, ":", 883 ntohs(eh->ether_type)); 884 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 885 "into a 64-bit PCI slot.\n"); 886 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 887 "for proper operation.\n"); 888 if_printf(ifp, "Read the re(4) man page for more details.\n"); 889 error = EIO; 890 } 891 892 done: 893 /* Turn interface off, release resources */ 894 895 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 896 ifp->if_flags &= ~IFF_PROMISC; 897 re_stop(sc); 898 if (m0 != NULL) 899 m_freem(m0); 900 901 return (error); 902 } 903 #endif /* RE_DIAG */ 904 905 /* 906 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 907 * IDs against our list and return a device name if we find a match. 908 */ 909 static int 910 re_probe(device_t dev) 911 { 912 const struct re_type *t; 913 const struct re_hwrev *hw_rev; 914 struct re_softc *sc; 915 int rid; 916 uint32_t hwrev, macmode, txcfg; 917 uint16_t vendor, product; 918 919 vendor = pci_get_vendor(dev); 920 product = pci_get_device(dev); 921 922 /* 923 * Only attach to rev.3 of the Linksys EG1032 adapter. 924 * Rev.2 is supported by sk(4). 925 */ 926 if (vendor == PCI_VENDOR_LINKSYS && 927 product == PCI_PRODUCT_LINKSYS_EG1032 && 928 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 929 return ENXIO; 930 931 if (vendor == PCI_VENDOR_REALTEK && 932 product == PCI_PRODUCT_REALTEK_RT8139 && 933 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 934 /* Poor 8139 */ 935 return ENXIO; 936 } 937 938 for (t = re_devs; t->re_name != NULL; t++) { 939 if (product == t->re_did && vendor == t->re_vid) 940 break; 941 } 942 943 /* 944 * Check if we found a RealTek device. 945 */ 946 if (t->re_name == NULL) 947 return ENXIO; 948 949 /* 950 * Temporarily map the I/O space so we can read the chip ID register. 951 */ 952 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 953 rid = RE_PCI_LOIO; 954 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 955 RF_ACTIVE); 956 if (sc->re_res == NULL) { 957 device_printf(dev, "couldn't map ports/memory\n"); 958 kfree(sc, M_TEMP); 959 return ENXIO; 960 } 961 962 sc->re_btag = rman_get_bustag(sc->re_res); 963 sc->re_bhandle = rman_get_bushandle(sc->re_res); 964 965 txcfg = CSR_READ_4(sc, RE_TXCFG); 966 hwrev = txcfg & RE_TXCFG_HWREV; 967 macmode = txcfg & RE_TXCFG_MACMODE; 968 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 969 kfree(sc, M_TEMP); 970 971 /* 972 * and continue matching for the specific chip... 973 */ 974 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 975 if (hw_rev->re_hwrev == hwrev) { 976 sc = device_get_softc(dev); 977 978 sc->re_hwrev = hw_rev->re_hwrev; 979 sc->re_macver = hw_rev->re_macver; 980 sc->re_caps = hw_rev->re_caps; 981 sc->re_maxmtu = hw_rev->re_maxmtu; 982 983 /* 984 * Apply chip property fixup 985 */ 986 switch (sc->re_hwrev) { 987 case RE_HWREV_8101E1: 988 case RE_HWREV_8101E2: 989 if (macmode == 0) 990 sc->re_macver = RE_MACVER_11; 991 else if (macmode == 0x200000) 992 sc->re_macver = RE_MACVER_12; 993 break; 994 case RE_HWREV_8102E: 995 case RE_HWREV_8102EL: 996 if (macmode == 0) 997 sc->re_macver = RE_MACVER_13; 998 else if (macmode == 0x100000) 999 sc->re_macver = RE_MACVER_14; 1000 break; 1001 case RE_HWREV_8168B2: 1002 case RE_HWREV_8168B3: 1003 if (macmode == 0) 1004 sc->re_macver = RE_MACVER_22; 1005 break; 1006 case RE_HWREV_8168C: 1007 if (macmode == 0) 1008 sc->re_macver = RE_MACVER_24; 1009 else if (macmode == 0x200000) 1010 sc->re_macver = RE_MACVER_25; 1011 else if (macmode == 0x300000) 1012 sc->re_macver = RE_MACVER_27; 1013 break; 1014 case RE_HWREV_8168CP: 1015 if (macmode == 0) 1016 sc->re_macver = RE_MACVER_26; 1017 else if (macmode == 0x100000) 1018 sc->re_macver = RE_MACVER_28; 1019 break; 1020 } 1021 if (pci_is_pcie(dev)) 1022 sc->re_caps |= RE_C_PCIE; 1023 1024 device_set_desc(dev, t->re_name); 1025 return 0; 1026 } 1027 } 1028 1029 if (bootverbose) { 1030 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1031 hwrev, macmode); 1032 } 1033 return ENXIO; 1034 } 1035 1036 static int 1037 re_allocmem(device_t dev) 1038 { 1039 struct re_softc *sc = device_get_softc(dev); 1040 bus_dmamem_t dmem; 1041 int error, i; 1042 1043 /* 1044 * Allocate list data 1045 */ 1046 sc->re_ldata.re_tx_mbuf = 1047 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1048 M_DEVBUF, M_ZERO | M_WAITOK); 1049 1050 sc->re_ldata.re_rx_mbuf = 1051 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1052 M_DEVBUF, M_ZERO | M_WAITOK); 1053 1054 sc->re_ldata.re_rx_paddr = 1055 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1056 M_DEVBUF, M_ZERO | M_WAITOK); 1057 1058 sc->re_ldata.re_tx_dmamap = 1059 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1060 M_DEVBUF, M_ZERO | M_WAITOK); 1061 1062 sc->re_ldata.re_rx_dmamap = 1063 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1064 M_DEVBUF, M_ZERO | M_WAITOK); 1065 1066 /* 1067 * Allocate the parent bus DMA tag appropriate for PCI. 1068 */ 1069 error = bus_dma_tag_create(NULL, /* parent */ 1070 1, 0, /* alignment, boundary */ 1071 BUS_SPACE_MAXADDR, /* lowaddr */ 1072 BUS_SPACE_MAXADDR, /* highaddr */ 1073 NULL, NULL, /* filter, filterarg */ 1074 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1075 0, /* nsegments */ 1076 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1077 0, /* flags */ 1078 &sc->re_parent_tag); 1079 if (error) { 1080 device_printf(dev, "could not allocate parent dma tag\n"); 1081 return error; 1082 } 1083 1084 /* Allocate TX descriptor list. */ 1085 error = bus_dmamem_coherent(sc->re_parent_tag, 1086 RE_RING_ALIGN, 0, 1087 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1088 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1089 &dmem); 1090 if (error) { 1091 device_printf(dev, "could not allocate TX ring\n"); 1092 return error; 1093 } 1094 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1095 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1096 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1097 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1098 1099 /* Allocate RX descriptor list. */ 1100 error = bus_dmamem_coherent(sc->re_parent_tag, 1101 RE_RING_ALIGN, 0, 1102 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1103 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1104 &dmem); 1105 if (error) { 1106 device_printf(dev, "could not allocate RX ring\n"); 1107 return error; 1108 } 1109 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1110 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1111 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1112 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1113 1114 /* Allocate maps for TX mbufs. */ 1115 error = bus_dma_tag_create(sc->re_parent_tag, 1116 1, 0, 1117 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1118 NULL, NULL, 1119 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1120 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1121 &sc->re_ldata.re_tx_mtag); 1122 if (error) { 1123 device_printf(dev, "could not allocate TX buf dma tag\n"); 1124 return(error); 1125 } 1126 1127 /* Create DMA maps for TX buffers */ 1128 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1129 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1130 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1131 &sc->re_ldata.re_tx_dmamap[i]); 1132 if (error) { 1133 device_printf(dev, "can't create DMA map for TX buf\n"); 1134 re_freebufmem(sc, i, 0); 1135 return(error); 1136 } 1137 } 1138 1139 /* Allocate maps for RX mbufs. */ 1140 error = bus_dma_tag_create(sc->re_parent_tag, 1141 RE_RXBUF_ALIGN, 0, 1142 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1143 NULL, NULL, 1144 MCLBYTES, 1, MCLBYTES, 1145 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1146 &sc->re_ldata.re_rx_mtag); 1147 if (error) { 1148 device_printf(dev, "could not allocate RX buf dma tag\n"); 1149 return(error); 1150 } 1151 1152 /* Create spare DMA map for RX */ 1153 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1154 &sc->re_ldata.re_rx_spare); 1155 if (error) { 1156 device_printf(dev, "can't create spare DMA map for RX\n"); 1157 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1158 sc->re_ldata.re_rx_mtag = NULL; 1159 return error; 1160 } 1161 1162 /* Create DMA maps for RX buffers */ 1163 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1164 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1165 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1166 if (error) { 1167 device_printf(dev, "can't create DMA map for RX buf\n"); 1168 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1169 return(error); 1170 } 1171 } 1172 1173 /* Create jumbo buffer pool for RX if required */ 1174 if (sc->re_caps & RE_C_CONTIGRX) { 1175 error = re_jpool_alloc(sc); 1176 if (error) { 1177 re_jpool_free(sc); 1178 /* Disable jumbo frame support */ 1179 sc->re_maxmtu = ETHERMTU; 1180 } 1181 } 1182 return(0); 1183 } 1184 1185 static void 1186 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1187 { 1188 int i; 1189 1190 /* Destroy all the RX and TX buffer maps */ 1191 if (sc->re_ldata.re_tx_mtag) { 1192 for (i = 0; i < tx_cnt; i++) { 1193 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1194 sc->re_ldata.re_tx_dmamap[i]); 1195 } 1196 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1197 sc->re_ldata.re_tx_mtag = NULL; 1198 } 1199 1200 if (sc->re_ldata.re_rx_mtag) { 1201 for (i = 0; i < rx_cnt; i++) { 1202 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1203 sc->re_ldata.re_rx_dmamap[i]); 1204 } 1205 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1206 sc->re_ldata.re_rx_spare); 1207 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1208 sc->re_ldata.re_rx_mtag = NULL; 1209 } 1210 } 1211 1212 static void 1213 re_freemem(device_t dev) 1214 { 1215 struct re_softc *sc = device_get_softc(dev); 1216 1217 /* Unload and free the RX DMA ring memory and map */ 1218 if (sc->re_ldata.re_rx_list_tag) { 1219 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1220 sc->re_ldata.re_rx_list_map); 1221 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1222 sc->re_ldata.re_rx_list, 1223 sc->re_ldata.re_rx_list_map); 1224 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1225 } 1226 1227 /* Unload and free the TX DMA ring memory and map */ 1228 if (sc->re_ldata.re_tx_list_tag) { 1229 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1230 sc->re_ldata.re_tx_list_map); 1231 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1232 sc->re_ldata.re_tx_list, 1233 sc->re_ldata.re_tx_list_map); 1234 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1235 } 1236 1237 /* Free RX/TX buf DMA stuffs */ 1238 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1239 1240 /* Unload and free the stats buffer and map */ 1241 if (sc->re_ldata.re_stag) { 1242 bus_dmamap_unload(sc->re_ldata.re_stag, 1243 sc->re_ldata.re_rx_list_map); 1244 bus_dmamem_free(sc->re_ldata.re_stag, 1245 sc->re_ldata.re_stats, 1246 sc->re_ldata.re_smap); 1247 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1248 } 1249 1250 if (sc->re_caps & RE_C_CONTIGRX) 1251 re_jpool_free(sc); 1252 1253 if (sc->re_parent_tag) 1254 bus_dma_tag_destroy(sc->re_parent_tag); 1255 1256 if (sc->re_ldata.re_tx_mbuf != NULL) 1257 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1258 if (sc->re_ldata.re_rx_mbuf != NULL) 1259 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1260 if (sc->re_ldata.re_rx_paddr != NULL) 1261 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1262 if (sc->re_ldata.re_tx_dmamap != NULL) 1263 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1264 if (sc->re_ldata.re_rx_dmamap != NULL) 1265 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1266 } 1267 1268 /* 1269 * Attach the interface. Allocate softc structures, do ifmedia 1270 * setup and ethernet/BPF attach. 1271 */ 1272 static int 1273 re_attach(device_t dev) 1274 { 1275 struct re_softc *sc = device_get_softc(dev); 1276 struct ifnet *ifp; 1277 uint8_t eaddr[ETHER_ADDR_LEN]; 1278 int error = 0, rid, qlen; 1279 1280 callout_init(&sc->re_timer); 1281 sc->re_dev = dev; 1282 1283 if (RE_IS_8139CP(sc)) { 1284 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1285 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1286 } else { 1287 sc->re_rx_desc_cnt = re_rx_desc_count; 1288 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1289 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1290 1291 sc->re_tx_desc_cnt = re_tx_desc_count; 1292 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1293 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1294 } 1295 1296 qlen = RE_IFQ_MAXLEN; 1297 if (sc->re_tx_desc_cnt > qlen) 1298 qlen = sc->re_tx_desc_cnt; 1299 1300 sc->re_rxbuf_size = MCLBYTES; 1301 sc->re_newbuf = re_newbuf_std; 1302 1303 sc->re_tx_time = 5; /* 125us */ 1304 sc->re_rx_time = 2; /* 50us */ 1305 if (sc->re_caps & RE_C_PCIE) 1306 sc->re_sim_time = 75; /* 75us */ 1307 else 1308 sc->re_sim_time = 125; /* 125us */ 1309 if (!RE_IS_8139CP(sc)) { 1310 /* simulated interrupt moderation */ 1311 sc->re_imtype = RE_IMTYPE_SIM; 1312 } else { 1313 sc->re_imtype = RE_IMTYPE_NONE; 1314 } 1315 re_config_imtype(sc, sc->re_imtype); 1316 1317 sysctl_ctx_init(&sc->re_sysctl_ctx); 1318 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1319 SYSCTL_STATIC_CHILDREN(_hw), 1320 OID_AUTO, 1321 device_get_nameunit(dev), 1322 CTLFLAG_RD, 0, ""); 1323 if (sc->re_sysctl_tree == NULL) { 1324 device_printf(dev, "can't add sysctl node\n"); 1325 error = ENXIO; 1326 goto fail; 1327 } 1328 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1329 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1330 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1331 0, "RX desc count"); 1332 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1333 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1334 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1335 0, "TX desc count"); 1336 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1337 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1338 OID_AUTO, "sim_time", 1339 CTLTYPE_INT | CTLFLAG_RW, 1340 sc, 0, re_sysctl_simtime, "I", 1341 "Simulated interrupt moderation time (usec)."); 1342 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1343 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1344 OID_AUTO, "imtype", 1345 CTLTYPE_INT | CTLFLAG_RW, 1346 sc, 0, re_sysctl_imtype, "I", 1347 "Interrupt moderation type -- " 1348 "0:disable, 1:simulated, " 1349 "2:hardware(if supported)"); 1350 if (sc->re_caps & RE_C_HWIM) { 1351 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1352 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1353 OID_AUTO, "hw_rxtime", 1354 CTLTYPE_INT | CTLFLAG_RW, 1355 sc, 0, re_sysctl_rxtime, "I", 1356 "Hardware interrupt moderation time " 1357 "(unit: 25usec)."); 1358 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1359 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1360 OID_AUTO, "hw_txtime", 1361 CTLTYPE_INT | CTLFLAG_RW, 1362 sc, 0, re_sysctl_txtime, "I", 1363 "Hardware interrupt moderation time " 1364 "(unit: 25usec)."); 1365 } 1366 1367 #ifndef BURN_BRIDGES 1368 /* 1369 * Handle power management nonsense. 1370 */ 1371 1372 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1373 uint32_t membase, irq; 1374 1375 /* Save important PCI config data. */ 1376 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1377 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1378 1379 /* Reset the power state. */ 1380 device_printf(dev, "chip is in D%d power mode " 1381 "-- setting to D0\n", pci_get_powerstate(dev)); 1382 1383 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1384 1385 /* Restore PCI config data. */ 1386 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1387 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1388 } 1389 #endif 1390 /* 1391 * Map control/status registers. 1392 */ 1393 pci_enable_busmaster(dev); 1394 1395 rid = RE_PCI_LOIO; 1396 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1397 RF_ACTIVE); 1398 1399 if (sc->re_res == NULL) { 1400 device_printf(dev, "couldn't map ports\n"); 1401 error = ENXIO; 1402 goto fail; 1403 } 1404 1405 sc->re_btag = rman_get_bustag(sc->re_res); 1406 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1407 1408 /* Allocate interrupt */ 1409 rid = 0; 1410 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1411 RF_SHAREABLE | RF_ACTIVE); 1412 1413 if (sc->re_irq == NULL) { 1414 device_printf(dev, "couldn't map interrupt\n"); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 /* Reset the adapter. */ 1420 re_reset(sc, 0); 1421 1422 if (RE_IS_8139CP(sc)) { 1423 sc->re_bus_speed = 33; /* XXX */ 1424 } else if (sc->re_caps & RE_C_PCIE) { 1425 sc->re_bus_speed = 125; 1426 } else { 1427 uint8_t cfg2; 1428 1429 cfg2 = CSR_READ_1(sc, RE_CFG2); 1430 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1431 case RE_CFG2_PCICLK_33MHZ: 1432 sc->re_bus_speed = 33; 1433 break; 1434 case RE_CFG2_PCICLK_66MHZ: 1435 sc->re_bus_speed = 66; 1436 break; 1437 default: 1438 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1439 sc->re_bus_speed = 33; 1440 break; 1441 } 1442 if (cfg2 & RE_CFG2_PCI64) 1443 sc->re_caps |= RE_C_PCI64; 1444 } 1445 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1446 "PCI%s %dMHz\n", 1447 sc->re_hwrev, sc->re_macver, 1448 (sc->re_caps & RE_C_PCIE) ? 1449 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1450 sc->re_bus_speed); 1451 1452 /* 1453 * NOTE: 1454 * DO NOT try to adjust config1 and config5 which was spotted in 1455 * Realtek's Linux drivers. It will _permanently_ damage certain 1456 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1457 */ 1458 1459 re_get_eaddr(sc, eaddr); 1460 1461 if (!RE_IS_8139CP(sc)) { 1462 /* Set RX length mask */ 1463 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1464 sc->re_txstart = RE_GTXSTART; 1465 } else { 1466 /* Set RX length mask */ 1467 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1468 sc->re_txstart = RE_TXSTART; 1469 } 1470 1471 /* Allocate DMA stuffs */ 1472 error = re_allocmem(dev); 1473 if (error) 1474 goto fail; 1475 1476 /* 1477 * Apply some magic PCI settings from Realtek ... 1478 */ 1479 if (RE_IS_8169(sc)) { 1480 CSR_WRITE_1(sc, 0x82, 1); 1481 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1482 } 1483 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1484 1485 if (sc->re_caps & RE_C_MAC2) { 1486 /* 1487 * Following part is extracted from Realtek BSD driver v176. 1488 * However, this does _not_ make much/any sense: 1489 * 8168C's PCI Express device control is located at 0x78, 1490 * so the reading from 0x79 (higher part of 0x78) and setting 1491 * the 4~6bits intend to enlarge the "max read request size" 1492 * (we will do it). The content of the rest part of this 1493 * register is not meaningful to other PCI registers, so 1494 * writing the value to 0x54 could be completely wrong. 1495 * 0x80 is the lower part of PCI Express device status, non- 1496 * reserved bits are RW1C, writing 0 to them will not have 1497 * any effect at all. 1498 */ 1499 #ifdef foo 1500 uint8_t val; 1501 1502 val = pci_read_config(dev, 0x79, 1); 1503 val = (val & ~0x70) | 0x50; 1504 pci_write_config(dev, 0x54, val, 1); 1505 pci_write_config(dev, 0x80, 0, 1); 1506 #endif 1507 } 1508 1509 /* 1510 * Apply some PHY fixup from Realtek ... 1511 */ 1512 if (sc->re_hwrev == RE_HWREV_8110S) { 1513 CSR_WRITE_1(sc, 0x82, 1); 1514 re_miibus_writereg(dev, 1, 0xb, 0); 1515 } 1516 if (sc->re_caps & RE_C_PHYPMGT) { 1517 /* Power up PHY */ 1518 re_miibus_writereg(dev, 1, 0x1f, 0); 1519 re_miibus_writereg(dev, 1, 0xe, 0); 1520 } 1521 1522 /* Do MII setup */ 1523 if (mii_phy_probe(dev, &sc->re_miibus, 1524 re_ifmedia_upd, re_ifmedia_sts)) { 1525 device_printf(dev, "MII without any phy!\n"); 1526 error = ENXIO; 1527 goto fail; 1528 } 1529 1530 ifp = &sc->arpcom.ac_if; 1531 ifp->if_softc = sc; 1532 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1533 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1534 ifp->if_ioctl = re_ioctl; 1535 ifp->if_start = re_start; 1536 #ifdef DEVICE_POLLING 1537 ifp->if_poll = re_poll; 1538 #endif 1539 ifp->if_watchdog = re_watchdog; 1540 ifp->if_init = re_init; 1541 if (!RE_IS_8139CP(sc)) /* XXX */ 1542 ifp->if_baudrate = 1000000000; 1543 else 1544 ifp->if_baudrate = 100000000; 1545 ifq_set_maxlen(&ifp->if_snd, qlen); 1546 ifq_set_ready(&ifp->if_snd); 1547 1548 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1549 if (sc->re_caps & RE_C_HWCSUM) 1550 ifp->if_capabilities |= IFCAP_HWCSUM; 1551 1552 ifp->if_capenable = ifp->if_capabilities; 1553 if (ifp->if_capabilities & IFCAP_HWCSUM) 1554 ifp->if_hwassist = RE_CSUM_FEATURES; 1555 else 1556 ifp->if_hwassist = 0; 1557 1558 /* 1559 * Call MI attach routine. 1560 */ 1561 ether_ifattach(ifp, eaddr, NULL); 1562 1563 #ifdef RE_DIAG 1564 /* 1565 * Perform hardware diagnostic on the original RTL8169. 1566 * Some 32-bit cards were incorrectly wired and would 1567 * malfunction if plugged into a 64-bit slot. 1568 */ 1569 if (sc->re_hwrev == RE_HWREV_8169) { 1570 lwkt_serialize_enter(ifp->if_serializer); 1571 error = re_diag(sc); 1572 lwkt_serialize_exit(ifp->if_serializer); 1573 1574 if (error) { 1575 device_printf(dev, "hardware diagnostic failure\n"); 1576 ether_ifdetach(ifp); 1577 goto fail; 1578 } 1579 } 1580 #endif /* RE_DIAG */ 1581 1582 /* Hook interrupt last to avoid having to lock softc */ 1583 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1584 &sc->re_intrhand, ifp->if_serializer); 1585 1586 if (error) { 1587 device_printf(dev, "couldn't set up irq\n"); 1588 ether_ifdetach(ifp); 1589 goto fail; 1590 } 1591 1592 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); 1593 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1594 1595 fail: 1596 if (error) 1597 re_detach(dev); 1598 1599 return (error); 1600 } 1601 1602 /* 1603 * Shutdown hardware and free up resources. This can be called any 1604 * time after the mutex has been initialized. It is called in both 1605 * the error case in attach and the normal detach case so it needs 1606 * to be careful about only freeing resources that have actually been 1607 * allocated. 1608 */ 1609 static int 1610 re_detach(device_t dev) 1611 { 1612 struct re_softc *sc = device_get_softc(dev); 1613 struct ifnet *ifp = &sc->arpcom.ac_if; 1614 1615 /* These should only be active if attach succeeded */ 1616 if (device_is_attached(dev)) { 1617 lwkt_serialize_enter(ifp->if_serializer); 1618 re_stop(sc); 1619 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1620 lwkt_serialize_exit(ifp->if_serializer); 1621 1622 ether_ifdetach(ifp); 1623 } 1624 if (sc->re_miibus) 1625 device_delete_child(dev, sc->re_miibus); 1626 bus_generic_detach(dev); 1627 1628 if (sc->re_sysctl_tree != NULL) 1629 sysctl_ctx_free(&sc->re_sysctl_ctx); 1630 1631 if (sc->re_irq) 1632 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1633 if (sc->re_res) { 1634 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1635 sc->re_res); 1636 } 1637 1638 /* Free DMA stuffs */ 1639 re_freemem(dev); 1640 1641 return(0); 1642 } 1643 1644 static void 1645 re_setup_rxdesc(struct re_softc *sc, int idx) 1646 { 1647 bus_addr_t paddr; 1648 uint32_t cmdstat; 1649 struct re_desc *d; 1650 1651 paddr = sc->re_ldata.re_rx_paddr[idx]; 1652 d = &sc->re_ldata.re_rx_list[idx]; 1653 1654 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1655 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1656 1657 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1658 if (idx == (sc->re_rx_desc_cnt - 1)) 1659 cmdstat |= RE_RDESC_CMD_EOR; 1660 d->re_cmdstat = htole32(cmdstat); 1661 } 1662 1663 static int 1664 re_newbuf_std(struct re_softc *sc, int idx, int init) 1665 { 1666 bus_dma_segment_t seg; 1667 bus_dmamap_t map; 1668 struct mbuf *m; 1669 int error, nsegs; 1670 1671 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1672 if (m == NULL) { 1673 error = ENOBUFS; 1674 1675 if (init) { 1676 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1677 return error; 1678 } else { 1679 goto back; 1680 } 1681 } 1682 m->m_len = m->m_pkthdr.len = MCLBYTES; 1683 1684 /* 1685 * NOTE: 1686 * re(4) chips need address of the receive buffer to be 8-byte 1687 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1688 */ 1689 1690 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1691 sc->re_ldata.re_rx_spare, m, 1692 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1693 if (error) { 1694 m_freem(m); 1695 if (init) { 1696 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1697 return error; 1698 } else { 1699 goto back; 1700 } 1701 } 1702 1703 if (!init) { 1704 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1705 sc->re_ldata.re_rx_dmamap[idx], 1706 BUS_DMASYNC_POSTREAD); 1707 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1708 sc->re_ldata.re_rx_dmamap[idx]); 1709 } 1710 sc->re_ldata.re_rx_mbuf[idx] = m; 1711 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1712 1713 map = sc->re_ldata.re_rx_dmamap[idx]; 1714 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1715 sc->re_ldata.re_rx_spare = map; 1716 back: 1717 re_setup_rxdesc(sc, idx); 1718 return error; 1719 } 1720 1721 static int 1722 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1723 { 1724 struct mbuf *m; 1725 struct re_jbuf *jbuf; 1726 int error = 0; 1727 1728 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1729 if (m == NULL) { 1730 error = ENOBUFS; 1731 if (init) { 1732 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1733 return error; 1734 } else { 1735 goto back; 1736 } 1737 } 1738 1739 jbuf = re_jbuf_alloc(sc); 1740 if (jbuf == NULL) { 1741 m_freem(m); 1742 1743 error = ENOBUFS; 1744 if (init) { 1745 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1746 return error; 1747 } else { 1748 goto back; 1749 } 1750 } 1751 1752 m->m_ext.ext_arg = jbuf; 1753 m->m_ext.ext_buf = jbuf->re_buf; 1754 m->m_ext.ext_free = re_jbuf_free; 1755 m->m_ext.ext_ref = re_jbuf_ref; 1756 m->m_ext.ext_size = sc->re_rxbuf_size; 1757 1758 m->m_data = m->m_ext.ext_buf; 1759 m->m_flags |= M_EXT; 1760 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1761 1762 /* 1763 * NOTE: 1764 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1765 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1766 */ 1767 1768 sc->re_ldata.re_rx_mbuf[idx] = m; 1769 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1770 back: 1771 re_setup_rxdesc(sc, idx); 1772 return error; 1773 } 1774 1775 static int 1776 re_tx_list_init(struct re_softc *sc) 1777 { 1778 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1779 1780 /* Flush the TX descriptors */ 1781 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1782 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1783 1784 sc->re_ldata.re_tx_prodidx = 0; 1785 sc->re_ldata.re_tx_considx = 0; 1786 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1787 1788 return(0); 1789 } 1790 1791 static int 1792 re_rx_list_init(struct re_softc *sc) 1793 { 1794 int i, error; 1795 1796 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1797 1798 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1799 error = sc->re_newbuf(sc, i, 1); 1800 if (error) 1801 return(error); 1802 } 1803 1804 /* Flush the RX descriptors */ 1805 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1806 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1807 1808 sc->re_ldata.re_rx_prodidx = 0; 1809 sc->re_head = sc->re_tail = NULL; 1810 1811 return(0); 1812 } 1813 1814 #define RE_IP4_PACKET 0x1 1815 #define RE_TCP_PACKET 0x2 1816 #define RE_UDP_PACKET 0x4 1817 1818 static __inline uint8_t 1819 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1820 { 1821 uint8_t packet_type = 0; 1822 1823 if (sc->re_caps & RE_C_MAC2) { 1824 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1825 packet_type |= RE_IP4_PACKET; 1826 } else { 1827 if (rxstat & RE_RDESC_STAT_PROTOID) 1828 packet_type |= RE_IP4_PACKET; 1829 } 1830 if (RE_TCPPKT(rxstat)) 1831 packet_type |= RE_TCP_PACKET; 1832 else if (RE_UDPPKT(rxstat)) 1833 packet_type |= RE_UDP_PACKET; 1834 return packet_type; 1835 } 1836 1837 /* 1838 * RX handler for C+ and 8169. For the gigE chips, we support 1839 * the reception of jumbo frames that have been fragmented 1840 * across multiple 2K mbuf cluster buffers. 1841 */ 1842 static int 1843 re_rxeof(struct re_softc *sc) 1844 { 1845 struct ifnet *ifp = &sc->arpcom.ac_if; 1846 struct mbuf *m; 1847 struct re_desc *cur_rx; 1848 uint32_t rxstat, rxctrl; 1849 int i, total_len, rx = 0; 1850 struct mbuf_chain chain[MAXCPU]; 1851 1852 /* Invalidate the descriptor memory */ 1853 1854 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1855 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1856 1857 ether_input_chain_init(chain); 1858 1859 for (i = sc->re_ldata.re_rx_prodidx; 1860 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1861 cur_rx = &sc->re_ldata.re_rx_list[i]; 1862 m = sc->re_ldata.re_rx_mbuf[i]; 1863 total_len = RE_RXBYTES(cur_rx); 1864 rxstat = le32toh(cur_rx->re_cmdstat); 1865 rxctrl = le32toh(cur_rx->re_control); 1866 1867 rx = 1; 1868 1869 #ifdef INVARIANTS 1870 if (sc->re_flags & RE_F_USE_JPOOL) 1871 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1872 #endif 1873 1874 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1875 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1876 re_setup_rxdesc(sc, i); 1877 continue; 1878 } 1879 1880 if (sc->re_newbuf(sc, i, 0)) { 1881 /* Drop upcoming fragments */ 1882 sc->re_flags |= RE_F_DROP_RXFRAG; 1883 continue; 1884 } 1885 1886 m->m_len = MCLBYTES; 1887 if (sc->re_head == NULL) { 1888 sc->re_head = sc->re_tail = m; 1889 } else { 1890 sc->re_tail->m_next = m; 1891 sc->re_tail = m; 1892 } 1893 continue; 1894 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1895 /* 1896 * Last fragment of a multi-fragment packet. 1897 * 1898 * Since error already happened, this fragment 1899 * must be dropped as well as the fragment chain. 1900 */ 1901 re_setup_rxdesc(sc, i); 1902 re_free_rxchain(sc); 1903 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1904 continue; 1905 } 1906 1907 /* 1908 * NOTE: for the 8139C+, the frame length field 1909 * is always 12 bits in size, but for the gigE chips, 1910 * it is 13 bits (since the max RX frame length is 16K). 1911 * Unfortunately, all 32 bits in the status word 1912 * were already used, so to make room for the extra 1913 * length bit, RealTek took out the 'frame alignment 1914 * error' bit and shifted the other status bits 1915 * over one slot. The OWN, EOR, FS and LS bits are 1916 * still in the same places. We have already extracted 1917 * the frame length and checked the OWN bit, so rather 1918 * than using an alternate bit mapping, we shift the 1919 * status bits one space to the right so we can evaluate 1920 * them using the 8169 status as though it was in the 1921 * same format as that of the 8139C+. 1922 */ 1923 if (!RE_IS_8139CP(sc)) 1924 rxstat >>= 1; 1925 1926 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1927 ifp->if_ierrors++; 1928 /* 1929 * If this is part of a multi-fragment packet, 1930 * discard all the pieces. 1931 */ 1932 re_free_rxchain(sc); 1933 re_setup_rxdesc(sc, i); 1934 continue; 1935 } 1936 1937 /* 1938 * If allocating a replacement mbuf fails, 1939 * reload the current one. 1940 */ 1941 1942 if (sc->re_newbuf(sc, i, 0)) { 1943 ifp->if_ierrors++; 1944 continue; 1945 } 1946 1947 if (sc->re_head != NULL) { 1948 m->m_len = total_len % MCLBYTES; 1949 /* 1950 * Special case: if there's 4 bytes or less 1951 * in this buffer, the mbuf can be discarded: 1952 * the last 4 bytes is the CRC, which we don't 1953 * care about anyway. 1954 */ 1955 if (m->m_len <= ETHER_CRC_LEN) { 1956 sc->re_tail->m_len -= 1957 (ETHER_CRC_LEN - m->m_len); 1958 m_freem(m); 1959 } else { 1960 m->m_len -= ETHER_CRC_LEN; 1961 sc->re_tail->m_next = m; 1962 } 1963 m = sc->re_head; 1964 sc->re_head = sc->re_tail = NULL; 1965 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1966 } else { 1967 m->m_pkthdr.len = m->m_len = 1968 (total_len - ETHER_CRC_LEN); 1969 } 1970 1971 ifp->if_ipackets++; 1972 m->m_pkthdr.rcvif = ifp; 1973 1974 /* Do RX checksumming if enabled */ 1975 1976 if (ifp->if_capenable & IFCAP_RXCSUM) { 1977 uint8_t packet_type; 1978 1979 packet_type = re_packet_type(sc, rxstat, rxctrl); 1980 1981 /* Check IP header checksum */ 1982 if (packet_type & RE_IP4_PACKET) { 1983 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1984 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1985 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1986 } 1987 1988 /* Check TCP/UDP checksum */ 1989 if (((packet_type & RE_TCP_PACKET) && 1990 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1991 ((packet_type & RE_UDP_PACKET) && 1992 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 1993 m->m_pkthdr.csum_flags |= 1994 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1995 CSUM_FRAG_NOT_CHECKED; 1996 m->m_pkthdr.csum_data = 0xffff; 1997 } 1998 } 1999 2000 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2001 m->m_flags |= M_VLANTAG; 2002 m->m_pkthdr.ether_vlantag = 2003 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2004 } 2005 ether_input_chain(ifp, m, chain); 2006 } 2007 2008 ether_input_dispatch(chain); 2009 2010 /* Flush the RX DMA ring */ 2011 2012 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 2013 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 2014 2015 sc->re_ldata.re_rx_prodidx = i; 2016 2017 return rx; 2018 } 2019 2020 #undef RE_IP4_PACKET 2021 #undef RE_TCP_PACKET 2022 #undef RE_UDP_PACKET 2023 2024 static int 2025 re_tx_collect(struct re_softc *sc) 2026 { 2027 struct ifnet *ifp = &sc->arpcom.ac_if; 2028 uint32_t txstat; 2029 int idx, tx = 0; 2030 2031 /* Invalidate the TX descriptor list */ 2032 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2033 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 2034 2035 for (idx = sc->re_ldata.re_tx_considx; 2036 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2037 RE_TXDESC_INC(sc, idx)) { 2038 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2039 if (txstat & RE_TDESC_CMD_OWN) 2040 break; 2041 2042 tx = 1; 2043 2044 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2045 2046 /* 2047 * We only stash mbufs in the last descriptor 2048 * in a fragment chain, which also happens to 2049 * be the only place where the TX status bits 2050 * are valid. 2051 */ 2052 if (txstat & RE_TDESC_CMD_EOF) { 2053 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2054 sc->re_ldata.re_tx_dmamap[idx]); 2055 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2056 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2057 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2058 RE_TDESC_STAT_COLCNT)) 2059 ifp->if_collisions++; 2060 if (txstat & RE_TDESC_STAT_TXERRSUM) 2061 ifp->if_oerrors++; 2062 else 2063 ifp->if_opackets++; 2064 } 2065 sc->re_ldata.re_tx_free++; 2066 } 2067 sc->re_ldata.re_tx_considx = idx; 2068 2069 return tx; 2070 } 2071 2072 static int 2073 re_txeof(struct re_softc *sc) 2074 { 2075 struct ifnet *ifp = &sc->arpcom.ac_if; 2076 int tx; 2077 2078 tx = re_tx_collect(sc); 2079 2080 /* There is enough free TX descs */ 2081 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2082 ifp->if_flags &= ~IFF_OACTIVE; 2083 2084 /* 2085 * Some chips will ignore a second TX request issued while an 2086 * existing transmission is in progress. If the transmitter goes 2087 * idle but there are still packets waiting to be sent, we need 2088 * to restart the channel here to flush them out. This only seems 2089 * to be required with the PCIe devices. 2090 */ 2091 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2092 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2093 else 2094 ifp->if_timer = 0; 2095 2096 return tx; 2097 } 2098 2099 static void 2100 re_tick(void *xsc) 2101 { 2102 struct re_softc *sc = xsc; 2103 2104 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2105 re_tick_serialized(xsc); 2106 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2107 } 2108 2109 static void 2110 re_tick_serialized(void *xsc) 2111 { 2112 struct re_softc *sc = xsc; 2113 struct ifnet *ifp = &sc->arpcom.ac_if; 2114 struct mii_data *mii; 2115 2116 ASSERT_SERIALIZED(ifp->if_serializer); 2117 2118 mii = device_get_softc(sc->re_miibus); 2119 mii_tick(mii); 2120 if (sc->re_flags & RE_F_LINKED) { 2121 if (!(mii->mii_media_status & IFM_ACTIVE)) 2122 sc->re_flags &= ~RE_F_LINKED; 2123 } else { 2124 if (mii->mii_media_status & IFM_ACTIVE && 2125 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2126 sc->re_flags |= RE_F_LINKED; 2127 if (!ifq_is_empty(&ifp->if_snd)) 2128 if_devstart(ifp); 2129 } 2130 } 2131 2132 callout_reset(&sc->re_timer, hz, re_tick, sc); 2133 } 2134 2135 #ifdef DEVICE_POLLING 2136 2137 static void 2138 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2139 { 2140 struct re_softc *sc = ifp->if_softc; 2141 2142 ASSERT_SERIALIZED(ifp->if_serializer); 2143 2144 switch(cmd) { 2145 case POLL_REGISTER: 2146 /* disable interrupts */ 2147 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2148 break; 2149 2150 case POLL_DEREGISTER: 2151 /* enable interrupts */ 2152 re_setup_intr(sc, 1, sc->re_imtype); 2153 break; 2154 2155 default: 2156 sc->rxcycles = count; 2157 re_rxeof(sc); 2158 re_txeof(sc); 2159 2160 if (!ifq_is_empty(&ifp->if_snd)) 2161 if_devstart(ifp); 2162 2163 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2164 uint16_t status; 2165 2166 status = CSR_READ_2(sc, RE_ISR); 2167 if (status == 0xffff) 2168 return; 2169 if (status) 2170 CSR_WRITE_2(sc, RE_ISR, status); 2171 2172 /* 2173 * XXX check behaviour on receiver stalls. 2174 */ 2175 2176 if (status & RE_ISR_SYSTEM_ERR) 2177 re_init(sc); 2178 } 2179 break; 2180 } 2181 } 2182 #endif /* DEVICE_POLLING */ 2183 2184 static void 2185 re_intr(void *arg) 2186 { 2187 struct re_softc *sc = arg; 2188 struct ifnet *ifp = &sc->arpcom.ac_if; 2189 uint16_t status; 2190 int rx, tx; 2191 2192 ASSERT_SERIALIZED(ifp->if_serializer); 2193 2194 if ((sc->re_flags & RE_F_SUSPENDED) || 2195 (ifp->if_flags & IFF_RUNNING) == 0) 2196 return; 2197 2198 rx = tx = 0; 2199 for (;;) { 2200 status = CSR_READ_2(sc, RE_ISR); 2201 /* If the card has gone away the read returns 0xffff. */ 2202 if (status == 0xffff) 2203 break; 2204 if (status) 2205 CSR_WRITE_2(sc, RE_ISR, status); 2206 2207 if ((status & sc->re_intrs) == 0) 2208 break; 2209 2210 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2211 rx |= re_rxeof(sc); 2212 2213 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2214 tx |= re_txeof(sc); 2215 2216 if (status & RE_ISR_SYSTEM_ERR) 2217 re_init(sc); 2218 2219 if (status & RE_ISR_LINKCHG) { 2220 callout_stop(&sc->re_timer); 2221 re_tick_serialized(sc); 2222 } 2223 } 2224 2225 if (sc->re_imtype == RE_IMTYPE_SIM) { 2226 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2227 if ((tx | rx) == 0) { 2228 /* 2229 * Nothing needs to be processed, fallback 2230 * to use TX/RX interrupts. 2231 */ 2232 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2233 2234 /* 2235 * Recollect, mainly to avoid the possible 2236 * race introduced by changing interrupt 2237 * masks. 2238 */ 2239 re_rxeof(sc); 2240 tx = re_txeof(sc); 2241 } else { 2242 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2243 } 2244 } else if (tx | rx) { 2245 /* 2246 * Assume that using simulated interrupt moderation 2247 * (hardware timer based) could reduce the interript 2248 * rate. 2249 */ 2250 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2251 } 2252 } 2253 2254 if (tx && !ifq_is_empty(&ifp->if_snd)) 2255 if_devstart(ifp); 2256 } 2257 2258 static int 2259 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2260 { 2261 struct mbuf *m = *m_head; 2262 bus_dma_segment_t segs[RE_MAXSEGS]; 2263 bus_dmamap_t map; 2264 int error, maxsegs, idx, i, nsegs; 2265 struct re_desc *d, *tx_ring; 2266 uint32_t cmd_csum, ctl_csum, vlantag; 2267 2268 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2269 ("not enough free TX desc\n")); 2270 2271 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2272 2273 /* 2274 * Set up checksum offload. Note: checksum offload bits must 2275 * appear in all descriptors of a multi-descriptor transmit 2276 * attempt. (This is according to testing done with an 8169 2277 * chip. I'm not sure if this is a requirement or a bug.) 2278 */ 2279 cmd_csum = ctl_csum = 0; 2280 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2281 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2282 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2283 } 2284 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2285 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2286 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2287 } 2288 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2289 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2290 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2291 } 2292 2293 /* For MAC2 chips, csum flags are set on re_control */ 2294 if (sc->re_caps & RE_C_MAC2) 2295 cmd_csum = 0; 2296 else 2297 ctl_csum = 0; 2298 2299 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2300 /* 2301 * With some of the RealTek chips, using the checksum offload 2302 * support in conjunction with the autopadding feature results 2303 * in the transmission of corrupt frames. For example, if we 2304 * need to send a really small IP fragment that's less than 60 2305 * bytes in size, and IP header checksumming is enabled, the 2306 * resulting ethernet frame that appears on the wire will 2307 * have garbled payload. To work around this, if TX checksum 2308 * offload is enabled, we always manually pad short frames out 2309 * to the minimum ethernet frame size. 2310 * 2311 * Note: this appears unnecessary for TCP, and doing it for TCP 2312 * with PCIe adapters seems to result in bad checksums. 2313 */ 2314 if ((m->m_pkthdr.csum_flags & 2315 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2316 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2317 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2318 error = m_devpad(m, RE_MIN_FRAMELEN); 2319 if (error) 2320 goto back; 2321 } 2322 } 2323 2324 vlantag = 0; 2325 if (m->m_flags & M_VLANTAG) { 2326 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2327 RE_TDESC_CTL_INSTAG; 2328 } 2329 2330 maxsegs = sc->re_ldata.re_tx_free; 2331 if (maxsegs > RE_MAXSEGS) 2332 maxsegs = RE_MAXSEGS; 2333 2334 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2335 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2336 if (error) 2337 goto back; 2338 2339 m = *m_head; 2340 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2341 2342 /* 2343 * Map the segment array into descriptors. We also keep track 2344 * of the end of the ring and set the end-of-ring bits as needed, 2345 * and we set the ownership bits in all except the very first 2346 * descriptor, whose ownership bits will be turned on later. 2347 */ 2348 tx_ring = sc->re_ldata.re_tx_list; 2349 idx = *idx0; 2350 i = 0; 2351 for (;;) { 2352 uint32_t cmdstat; 2353 2354 d = &tx_ring[idx]; 2355 2356 cmdstat = segs[i].ds_len; 2357 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2358 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2359 if (i == 0) 2360 cmdstat |= RE_TDESC_CMD_SOF; 2361 else 2362 cmdstat |= RE_TDESC_CMD_OWN; 2363 if (idx == (sc->re_tx_desc_cnt - 1)) 2364 cmdstat |= RE_TDESC_CMD_EOR; 2365 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2366 d->re_control = htole32(ctl_csum | vlantag); 2367 2368 i++; 2369 if (i == nsegs) 2370 break; 2371 RE_TXDESC_INC(sc, idx); 2372 } 2373 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2374 2375 /* Transfer ownership of packet to the chip. */ 2376 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2377 if (*idx0 != idx) 2378 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2379 2380 /* 2381 * Insure that the map for this transmission 2382 * is placed at the array index of the last descriptor 2383 * in this chain. 2384 */ 2385 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2386 sc->re_ldata.re_tx_dmamap[idx] = map; 2387 2388 sc->re_ldata.re_tx_mbuf[idx] = m; 2389 sc->re_ldata.re_tx_free -= nsegs; 2390 2391 RE_TXDESC_INC(sc, idx); 2392 *idx0 = idx; 2393 back: 2394 if (error) { 2395 m_freem(*m_head); 2396 *m_head = NULL; 2397 } 2398 return error; 2399 } 2400 2401 /* 2402 * Main transmit routine for C+ and gigE NICs. 2403 */ 2404 2405 static void 2406 re_start(struct ifnet *ifp) 2407 { 2408 struct re_softc *sc = ifp->if_softc; 2409 struct mbuf *m_head; 2410 int idx, need_trans, oactive, error; 2411 2412 ASSERT_SERIALIZED(ifp->if_serializer); 2413 2414 if ((sc->re_flags & RE_F_LINKED) == 0) { 2415 ifq_purge(&ifp->if_snd); 2416 return; 2417 } 2418 2419 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2420 return; 2421 2422 idx = sc->re_ldata.re_tx_prodidx; 2423 2424 need_trans = 0; 2425 oactive = 0; 2426 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2427 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2428 if (!oactive) { 2429 if (re_tx_collect(sc)) { 2430 oactive = 1; 2431 continue; 2432 } 2433 } 2434 ifp->if_flags |= IFF_OACTIVE; 2435 break; 2436 } 2437 2438 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2439 if (m_head == NULL) 2440 break; 2441 2442 error = re_encap(sc, &m_head, &idx); 2443 if (error) { 2444 /* m_head is freed by re_encap(), if we reach here */ 2445 ifp->if_oerrors++; 2446 2447 if (error == EFBIG && !oactive) { 2448 if (re_tx_collect(sc)) { 2449 oactive = 1; 2450 continue; 2451 } 2452 } 2453 ifp->if_flags |= IFF_OACTIVE; 2454 break; 2455 } 2456 2457 oactive = 0; 2458 need_trans = 1; 2459 2460 /* 2461 * If there's a BPF listener, bounce a copy of this frame 2462 * to him. 2463 */ 2464 ETHER_BPF_MTAP(ifp, m_head); 2465 } 2466 2467 if (!need_trans) 2468 return; 2469 2470 /* Flush the TX descriptors */ 2471 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2472 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2473 2474 sc->re_ldata.re_tx_prodidx = idx; 2475 2476 /* 2477 * RealTek put the TX poll request register in a different 2478 * location on the 8169 gigE chip. I don't know why. 2479 */ 2480 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2481 2482 /* 2483 * Set a timeout in case the chip goes out to lunch. 2484 */ 2485 ifp->if_timer = 5; 2486 } 2487 2488 static void 2489 re_init(void *xsc) 2490 { 2491 struct re_softc *sc = xsc; 2492 struct ifnet *ifp = &sc->arpcom.ac_if; 2493 struct mii_data *mii; 2494 int error, framelen; 2495 2496 ASSERT_SERIALIZED(ifp->if_serializer); 2497 2498 mii = device_get_softc(sc->re_miibus); 2499 2500 /* 2501 * Cancel pending I/O and free all RX/TX buffers. 2502 */ 2503 re_stop(sc); 2504 2505 if (sc->re_caps & RE_C_CONTIGRX) { 2506 if (ifp->if_mtu > ETHERMTU) { 2507 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2508 sc->re_flags |= RE_F_USE_JPOOL; 2509 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2510 sc->re_newbuf = re_newbuf_jumbo; 2511 } else { 2512 sc->re_flags &= ~RE_F_USE_JPOOL; 2513 sc->re_rxbuf_size = MCLBYTES; 2514 sc->re_newbuf = re_newbuf_std; 2515 } 2516 } 2517 2518 /* 2519 * Adjust max read request size according to MTU; mainly to 2520 * improve TX performance for common case (ETHERMTU) on GigE 2521 * NICs. However, this could _not_ be done on 10/100 only 2522 * NICs; their DMA engines will malfunction using non-default 2523 * max read request size. 2524 */ 2525 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2526 if (ifp->if_mtu > ETHERMTU) { 2527 /* 2528 * 512 seems to be the only value that works 2529 * reliably with jumbo frame 2530 */ 2531 pcie_set_max_readrq(sc->re_dev, 2532 PCIEM_DEVCTL_MAX_READRQ_512); 2533 } else { 2534 pcie_set_max_readrq(sc->re_dev, 2535 PCIEM_DEVCTL_MAX_READRQ_4096); 2536 } 2537 } 2538 2539 /* 2540 * Enable C+ RX and TX mode, as well as VLAN stripping and 2541 * RX checksum offload. We must configure the C+ register 2542 * before all others. 2543 */ 2544 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2545 RE_CPLUSCMD_PCI_MRW | 2546 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2547 RE_CPLUSCMD_VLANSTRIP : 0) | 2548 (ifp->if_capenable & IFCAP_RXCSUM ? 2549 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2550 2551 /* 2552 * Init our MAC address. Even though the chipset 2553 * documentation doesn't mention it, we need to enter "Config 2554 * register write enable" mode to modify the ID registers. 2555 */ 2556 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2557 CSR_WRITE_4(sc, RE_IDR0, 2558 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2559 CSR_WRITE_2(sc, RE_IDR4, 2560 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2561 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2562 2563 /* 2564 * For C+ mode, initialize the RX descriptors and mbufs. 2565 */ 2566 error = re_rx_list_init(sc); 2567 if (error) { 2568 re_stop(sc); 2569 return; 2570 } 2571 error = re_tx_list_init(sc); 2572 if (error) { 2573 re_stop(sc); 2574 return; 2575 } 2576 2577 /* 2578 * Load the addresses of the RX and TX lists into the chip. 2579 */ 2580 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2581 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2582 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2583 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2584 2585 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2586 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2587 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2588 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2589 2590 /* 2591 * Enable transmit and receive. 2592 */ 2593 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2594 2595 /* 2596 * Set the initial TX and RX configuration. 2597 */ 2598 if (sc->re_flags & RE_F_TESTMODE) { 2599 if (!RE_IS_8139CP(sc)) 2600 CSR_WRITE_4(sc, RE_TXCFG, 2601 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2602 else 2603 CSR_WRITE_4(sc, RE_TXCFG, 2604 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2605 } else 2606 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2607 2608 framelen = RE_FRAMELEN(ifp->if_mtu); 2609 if (framelen < MCLBYTES) 2610 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2611 else 2612 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2613 2614 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2615 2616 /* 2617 * Program the multicast filter, if necessary. 2618 */ 2619 re_setmulti(sc); 2620 2621 #ifdef DEVICE_POLLING 2622 /* 2623 * Disable interrupts if we are polling. 2624 */ 2625 if (ifp->if_flags & IFF_POLLING) 2626 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2627 else /* otherwise ... */ 2628 #endif /* DEVICE_POLLING */ 2629 /* 2630 * Enable interrupts. 2631 */ 2632 if (sc->re_flags & RE_F_TESTMODE) 2633 CSR_WRITE_2(sc, RE_IMR, 0); 2634 else 2635 re_setup_intr(sc, 1, sc->re_imtype); 2636 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2637 2638 /* Start RX/TX process. */ 2639 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2640 2641 #ifdef notdef 2642 /* Enable receiver and transmitter. */ 2643 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2644 #endif 2645 2646 /* 2647 * For 8169 gigE NICs, set the max allowed RX packet 2648 * size so we can receive jumbo frames. 2649 */ 2650 if (!RE_IS_8139CP(sc)) { 2651 if (sc->re_caps & RE_C_CONTIGRX) 2652 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2653 else 2654 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2655 } 2656 2657 if (sc->re_flags & RE_F_TESTMODE) 2658 return; 2659 2660 mii_mediachg(mii); 2661 2662 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2663 2664 ifp->if_flags |= IFF_RUNNING; 2665 ifp->if_flags &= ~IFF_OACTIVE; 2666 2667 callout_reset(&sc->re_timer, hz, re_tick, sc); 2668 } 2669 2670 /* 2671 * Set media options. 2672 */ 2673 static int 2674 re_ifmedia_upd(struct ifnet *ifp) 2675 { 2676 struct re_softc *sc = ifp->if_softc; 2677 struct mii_data *mii; 2678 2679 ASSERT_SERIALIZED(ifp->if_serializer); 2680 2681 mii = device_get_softc(sc->re_miibus); 2682 mii_mediachg(mii); 2683 2684 return(0); 2685 } 2686 2687 /* 2688 * Report current media status. 2689 */ 2690 static void 2691 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2692 { 2693 struct re_softc *sc = ifp->if_softc; 2694 struct mii_data *mii; 2695 2696 ASSERT_SERIALIZED(ifp->if_serializer); 2697 2698 mii = device_get_softc(sc->re_miibus); 2699 2700 mii_pollstat(mii); 2701 ifmr->ifm_active = mii->mii_media_active; 2702 ifmr->ifm_status = mii->mii_media_status; 2703 } 2704 2705 static int 2706 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2707 { 2708 struct re_softc *sc = ifp->if_softc; 2709 struct ifreq *ifr = (struct ifreq *) data; 2710 struct mii_data *mii; 2711 int error = 0, mask; 2712 2713 ASSERT_SERIALIZED(ifp->if_serializer); 2714 2715 switch(command) { 2716 case SIOCSIFMTU: 2717 if (ifr->ifr_mtu > sc->re_maxmtu) { 2718 error = EINVAL; 2719 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2720 ifp->if_mtu = ifr->ifr_mtu; 2721 if (ifp->if_flags & IFF_RUNNING) 2722 ifp->if_init(sc); 2723 } 2724 break; 2725 2726 case SIOCSIFFLAGS: 2727 if (ifp->if_flags & IFF_UP) { 2728 if (ifp->if_flags & IFF_RUNNING) { 2729 if ((ifp->if_flags ^ sc->re_if_flags) & 2730 (IFF_PROMISC | IFF_ALLMULTI)) 2731 re_setmulti(sc); 2732 } else { 2733 re_init(sc); 2734 } 2735 } else if (ifp->if_flags & IFF_RUNNING) { 2736 re_stop(sc); 2737 } 2738 sc->re_if_flags = ifp->if_flags; 2739 break; 2740 2741 case SIOCADDMULTI: 2742 case SIOCDELMULTI: 2743 re_setmulti(sc); 2744 break; 2745 2746 case SIOCGIFMEDIA: 2747 case SIOCSIFMEDIA: 2748 mii = device_get_softc(sc->re_miibus); 2749 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2750 break; 2751 2752 case SIOCSIFCAP: 2753 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2754 ifp->if_capabilities; 2755 ifp->if_capenable ^= mask; 2756 2757 if (mask & IFCAP_HWCSUM) { 2758 if (ifp->if_capenable & IFCAP_TXCSUM) 2759 ifp->if_hwassist = RE_CSUM_FEATURES; 2760 else 2761 ifp->if_hwassist = 0; 2762 } 2763 if (mask && (ifp->if_flags & IFF_RUNNING)) 2764 re_init(sc); 2765 break; 2766 2767 default: 2768 error = ether_ioctl(ifp, command, data); 2769 break; 2770 } 2771 return(error); 2772 } 2773 2774 static void 2775 re_watchdog(struct ifnet *ifp) 2776 { 2777 struct re_softc *sc = ifp->if_softc; 2778 2779 ASSERT_SERIALIZED(ifp->if_serializer); 2780 2781 if_printf(ifp, "watchdog timeout\n"); 2782 2783 ifp->if_oerrors++; 2784 2785 re_txeof(sc); 2786 re_rxeof(sc); 2787 2788 re_init(sc); 2789 2790 if (!ifq_is_empty(&ifp->if_snd)) 2791 if_devstart(ifp); 2792 } 2793 2794 /* 2795 * Stop the adapter and free any mbufs allocated to the 2796 * RX and TX lists. 2797 */ 2798 static void 2799 re_stop(struct re_softc *sc) 2800 { 2801 struct ifnet *ifp = &sc->arpcom.ac_if; 2802 int i; 2803 2804 ASSERT_SERIALIZED(ifp->if_serializer); 2805 2806 /* Reset the adapter. */ 2807 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2808 2809 ifp->if_timer = 0; 2810 callout_stop(&sc->re_timer); 2811 2812 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2813 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2814 2815 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2816 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2817 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2818 2819 re_free_rxchain(sc); 2820 2821 /* Free the TX list buffers. */ 2822 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2823 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2824 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2825 sc->re_ldata.re_tx_dmamap[i]); 2826 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2827 sc->re_ldata.re_tx_mbuf[i] = NULL; 2828 } 2829 } 2830 2831 /* Free the RX list buffers. */ 2832 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2833 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2834 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2835 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2836 sc->re_ldata.re_rx_dmamap[i]); 2837 } 2838 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2839 sc->re_ldata.re_rx_mbuf[i] = NULL; 2840 } 2841 } 2842 } 2843 2844 /* 2845 * Device suspend routine. Stop the interface and save some PCI 2846 * settings in case the BIOS doesn't restore them properly on 2847 * resume. 2848 */ 2849 static int 2850 re_suspend(device_t dev) 2851 { 2852 #ifndef BURN_BRIDGES 2853 int i; 2854 #endif 2855 struct re_softc *sc = device_get_softc(dev); 2856 struct ifnet *ifp = &sc->arpcom.ac_if; 2857 2858 lwkt_serialize_enter(ifp->if_serializer); 2859 2860 re_stop(sc); 2861 2862 #ifndef BURN_BRIDGES 2863 for (i = 0; i < 5; i++) 2864 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2865 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2866 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2867 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2868 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2869 #endif 2870 2871 sc->re_flags |= RE_F_SUSPENDED; 2872 2873 lwkt_serialize_exit(ifp->if_serializer); 2874 2875 return (0); 2876 } 2877 2878 /* 2879 * Device resume routine. Restore some PCI settings in case the BIOS 2880 * doesn't, re-enable busmastering, and restart the interface if 2881 * appropriate. 2882 */ 2883 static int 2884 re_resume(device_t dev) 2885 { 2886 struct re_softc *sc = device_get_softc(dev); 2887 struct ifnet *ifp = &sc->arpcom.ac_if; 2888 #ifndef BURN_BRIDGES 2889 int i; 2890 #endif 2891 2892 lwkt_serialize_enter(ifp->if_serializer); 2893 2894 #ifndef BURN_BRIDGES 2895 /* better way to do this? */ 2896 for (i = 0; i < 5; i++) 2897 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2898 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2899 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2900 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2901 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2902 2903 /* reenable busmastering */ 2904 pci_enable_busmaster(dev); 2905 pci_enable_io(dev, SYS_RES_IOPORT); 2906 #endif 2907 2908 /* reinitialize interface if necessary */ 2909 if (ifp->if_flags & IFF_UP) 2910 re_init(sc); 2911 2912 sc->re_flags &= ~RE_F_SUSPENDED; 2913 2914 lwkt_serialize_exit(ifp->if_serializer); 2915 2916 return (0); 2917 } 2918 2919 /* 2920 * Stop all chip I/O so that the kernel's probe routines don't 2921 * get confused by errant DMAs when rebooting. 2922 */ 2923 static void 2924 re_shutdown(device_t dev) 2925 { 2926 struct re_softc *sc = device_get_softc(dev); 2927 struct ifnet *ifp = &sc->arpcom.ac_if; 2928 2929 lwkt_serialize_enter(ifp->if_serializer); 2930 re_stop(sc); 2931 lwkt_serialize_exit(ifp->if_serializer); 2932 } 2933 2934 static int 2935 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 2936 { 2937 struct re_softc *sc = arg1; 2938 2939 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 2940 } 2941 2942 static int 2943 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 2944 { 2945 struct re_softc *sc = arg1; 2946 2947 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 2948 } 2949 2950 static int 2951 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 2952 { 2953 struct re_softc *sc = arg1; 2954 struct ifnet *ifp = &sc->arpcom.ac_if; 2955 int error, v; 2956 2957 lwkt_serialize_enter(ifp->if_serializer); 2958 2959 v = *hwtime; 2960 error = sysctl_handle_int(oidp, &v, 0, req); 2961 if (error || req->newptr == NULL) 2962 goto back; 2963 2964 if (v <= 0) { 2965 error = EINVAL; 2966 goto back; 2967 } 2968 2969 if (v != *hwtime) { 2970 *hwtime = v; 2971 2972 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 2973 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 2974 re_setup_hw_im(sc); 2975 } 2976 back: 2977 lwkt_serialize_exit(ifp->if_serializer); 2978 return error; 2979 } 2980 2981 static int 2982 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 2983 { 2984 struct re_softc *sc = arg1; 2985 struct ifnet *ifp = &sc->arpcom.ac_if; 2986 int error, v; 2987 2988 lwkt_serialize_enter(ifp->if_serializer); 2989 2990 v = sc->re_sim_time; 2991 error = sysctl_handle_int(oidp, &v, 0, req); 2992 if (error || req->newptr == NULL) 2993 goto back; 2994 2995 if (v <= 0) { 2996 error = EINVAL; 2997 goto back; 2998 } 2999 3000 if (v != sc->re_sim_time) { 3001 sc->re_sim_time = v; 3002 3003 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3004 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3005 #ifdef foo 3006 int reg; 3007 3008 /* 3009 * Following code causes various strange 3010 * performance problems. Hmm ... 3011 */ 3012 CSR_WRITE_2(sc, RE_IMR, 0); 3013 if (!RE_IS_8139CP(sc)) 3014 reg = RE_TIMERINT_8169; 3015 else 3016 reg = RE_TIMERINT; 3017 CSR_WRITE_4(sc, reg, 0); 3018 CSR_READ_4(sc, reg); /* flush */ 3019 3020 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3021 re_setup_sim_im(sc); 3022 #else 3023 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3024 DELAY(10); 3025 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3026 #endif 3027 } 3028 } 3029 back: 3030 lwkt_serialize_exit(ifp->if_serializer); 3031 return error; 3032 } 3033 3034 static int 3035 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3036 { 3037 struct re_softc *sc = arg1; 3038 struct ifnet *ifp = &sc->arpcom.ac_if; 3039 int error, v; 3040 3041 lwkt_serialize_enter(ifp->if_serializer); 3042 3043 v = sc->re_imtype; 3044 error = sysctl_handle_int(oidp, &v, 0, req); 3045 if (error || req->newptr == NULL) 3046 goto back; 3047 3048 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3049 error = EINVAL; 3050 goto back; 3051 } 3052 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3053 /* Can't do hardware interrupt moderation */ 3054 error = EOPNOTSUPP; 3055 goto back; 3056 } 3057 3058 if (v != sc->re_imtype) { 3059 sc->re_imtype = v; 3060 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3061 IFF_RUNNING) 3062 re_setup_intr(sc, 1, sc->re_imtype); 3063 } 3064 back: 3065 lwkt_serialize_exit(ifp->if_serializer); 3066 return error; 3067 } 3068 3069 static void 3070 re_setup_hw_im(struct re_softc *sc) 3071 { 3072 KKASSERT(sc->re_caps & RE_C_HWIM); 3073 3074 /* 3075 * Interrupt moderation 3076 * 3077 * 0xABCD 3078 * A - unknown (maybe TX related) 3079 * B - TX timer (unit: 25us) 3080 * C - unknown (maybe RX related) 3081 * D - RX timer (unit: 25us) 3082 * 3083 * 3084 * re(4)'s interrupt moderation is actually controlled by 3085 * two variables, like most other NICs (bge, bce etc.) 3086 * o timer 3087 * o number of packets [P] 3088 * 3089 * The logic relationship between these two variables is 3090 * similar to other NICs too: 3091 * if (timer expire || packets > [P]) 3092 * Interrupt is delivered 3093 * 3094 * Currently we only know how to set 'timer', but not 3095 * 'number of packets', which should be ~30, as far as I 3096 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3097 */ 3098 CSR_WRITE_2(sc, RE_IM, 3099 RE_IM_RXTIME(sc->re_rx_time) | 3100 RE_IM_TXTIME(sc->re_tx_time) | 3101 RE_IM_MAGIC); 3102 } 3103 3104 static void 3105 re_disable_hw_im(struct re_softc *sc) 3106 { 3107 if (sc->re_caps & RE_C_HWIM) 3108 CSR_WRITE_2(sc, RE_IM, 0); 3109 } 3110 3111 static void 3112 re_setup_sim_im(struct re_softc *sc) 3113 { 3114 if (!RE_IS_8139CP(sc)) { 3115 uint32_t ticks; 3116 3117 /* 3118 * Datasheet says tick decreases at bus speed, 3119 * but it seems the clock runs a little bit 3120 * faster, so we do some compensation here. 3121 */ 3122 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3123 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3124 } else { 3125 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3126 } 3127 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3128 sc->re_flags |= RE_F_TIMER_INTR; 3129 } 3130 3131 static void 3132 re_disable_sim_im(struct re_softc *sc) 3133 { 3134 if (!RE_IS_8139CP(sc)) 3135 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3136 else 3137 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3138 sc->re_flags &= ~RE_F_TIMER_INTR; 3139 } 3140 3141 static void 3142 re_config_imtype(struct re_softc *sc, int imtype) 3143 { 3144 switch (imtype) { 3145 case RE_IMTYPE_HW: 3146 KKASSERT(sc->re_caps & RE_C_HWIM); 3147 /* FALL THROUGH */ 3148 case RE_IMTYPE_NONE: 3149 sc->re_intrs = RE_INTRS; 3150 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3151 RE_ISR_RX_OVERRUN; 3152 sc->re_tx_ack = RE_ISR_TX_OK; 3153 break; 3154 3155 case RE_IMTYPE_SIM: 3156 sc->re_intrs = RE_INTRS_TIMER; 3157 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3158 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3159 break; 3160 3161 default: 3162 panic("%s: unknown imtype %d\n", 3163 sc->arpcom.ac_if.if_xname, imtype); 3164 } 3165 } 3166 3167 static void 3168 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3169 { 3170 re_config_imtype(sc, imtype); 3171 3172 if (enable_intrs) 3173 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3174 else 3175 CSR_WRITE_2(sc, RE_IMR, 0); 3176 3177 switch (imtype) { 3178 case RE_IMTYPE_NONE: 3179 re_disable_sim_im(sc); 3180 re_disable_hw_im(sc); 3181 break; 3182 3183 case RE_IMTYPE_HW: 3184 KKASSERT(sc->re_caps & RE_C_HWIM); 3185 re_disable_sim_im(sc); 3186 re_setup_hw_im(sc); 3187 break; 3188 3189 case RE_IMTYPE_SIM: 3190 re_disable_hw_im(sc); 3191 re_setup_sim_im(sc); 3192 break; 3193 3194 default: 3195 panic("%s: unknown imtype %d\n", 3196 sc->arpcom.ac_if.if_xname, imtype); 3197 } 3198 } 3199 3200 static void 3201 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3202 { 3203 int i; 3204 3205 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) { 3206 uint16_t re_did; 3207 3208 re_get_eewidth(sc); 3209 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3210 if (re_did == 0x8128) { 3211 uint16_t as[ETHER_ADDR_LEN / 2]; 3212 3213 /* 3214 * Get station address from the EEPROM. 3215 */ 3216 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 3217 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3218 as[i] = le16toh(as[i]); 3219 bcopy(as, eaddr, sizeof(eaddr)); 3220 return; 3221 } 3222 } 3223 3224 /* 3225 * Get station address from IDRx. 3226 */ 3227 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3228 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3229 } 3230 3231 static int 3232 re_jpool_alloc(struct re_softc *sc) 3233 { 3234 struct re_list_data *ldata = &sc->re_ldata; 3235 struct re_jbuf *jbuf; 3236 bus_addr_t paddr; 3237 bus_size_t jpool_size; 3238 bus_dmamem_t dmem; 3239 caddr_t buf; 3240 int i, error; 3241 3242 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3243 3244 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3245 M_DEVBUF, M_WAITOK | M_ZERO); 3246 3247 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3248 3249 error = bus_dmamem_coherent(sc->re_parent_tag, 3250 RE_RXBUF_ALIGN, 0, 3251 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3252 jpool_size, BUS_DMA_WAITOK, &dmem); 3253 if (error) { 3254 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3255 return error; 3256 } 3257 ldata->re_jpool_tag = dmem.dmem_tag; 3258 ldata->re_jpool_map = dmem.dmem_map; 3259 ldata->re_jpool = dmem.dmem_addr; 3260 paddr = dmem.dmem_busaddr; 3261 3262 /* ..and split it into 9KB chunks */ 3263 SLIST_INIT(&ldata->re_jbuf_free); 3264 3265 buf = ldata->re_jpool; 3266 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3267 jbuf = &ldata->re_jbuf[i]; 3268 3269 jbuf->re_sc = sc; 3270 jbuf->re_inuse = 0; 3271 jbuf->re_slot = i; 3272 jbuf->re_buf = buf; 3273 jbuf->re_paddr = paddr; 3274 3275 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3276 3277 buf += RE_JBUF_SIZE; 3278 paddr += RE_JBUF_SIZE; 3279 } 3280 return 0; 3281 } 3282 3283 static void 3284 re_jpool_free(struct re_softc *sc) 3285 { 3286 struct re_list_data *ldata = &sc->re_ldata; 3287 3288 if (ldata->re_jpool_tag != NULL) { 3289 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3290 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3291 ldata->re_jpool_map); 3292 bus_dma_tag_destroy(ldata->re_jpool_tag); 3293 ldata->re_jpool_tag = NULL; 3294 } 3295 3296 if (ldata->re_jbuf != NULL) { 3297 kfree(ldata->re_jbuf, M_DEVBUF); 3298 ldata->re_jbuf = NULL; 3299 } 3300 } 3301 3302 static struct re_jbuf * 3303 re_jbuf_alloc(struct re_softc *sc) 3304 { 3305 struct re_list_data *ldata = &sc->re_ldata; 3306 struct re_jbuf *jbuf; 3307 3308 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3309 3310 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3311 if (jbuf != NULL) { 3312 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3313 jbuf->re_inuse = 1; 3314 } 3315 3316 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3317 3318 return jbuf; 3319 } 3320 3321 static void 3322 re_jbuf_free(void *arg) 3323 { 3324 struct re_jbuf *jbuf = arg; 3325 struct re_softc *sc = jbuf->re_sc; 3326 struct re_list_data *ldata = &sc->re_ldata; 3327 3328 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3329 panic("%s: free wrong jumbo buffer\n", 3330 sc->arpcom.ac_if.if_xname); 3331 } else if (jbuf->re_inuse == 0) { 3332 panic("%s: jumbo buffer already freed\n", 3333 sc->arpcom.ac_if.if_xname); 3334 } 3335 3336 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3337 atomic_subtract_int(&jbuf->re_inuse, 1); 3338 if (jbuf->re_inuse == 0) 3339 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3340 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3341 } 3342 3343 static void 3344 re_jbuf_ref(void *arg) 3345 { 3346 struct re_jbuf *jbuf = arg; 3347 struct re_softc *sc = jbuf->re_sc; 3348 struct re_list_data *ldata = &sc->re_ldata; 3349 3350 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3351 panic("%s: ref wrong jumbo buffer\n", 3352 sc->arpcom.ac_if.if_xname); 3353 } else if (jbuf->re_inuse == 0) { 3354 panic("%s: jumbo buffer already freed\n", 3355 sc->arpcom.ac_if.if_xname); 3356 } 3357 atomic_add_int(&jbuf->re_inuse, 1); 3358 } 3359