1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_polling.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_types.h> 139 #include <net/vlan/if_vlan_var.h> 140 #include <net/vlan/if_vlan_ether.h> 141 142 #include <netinet/ip.h> 143 144 #include <dev/netif/mii_layer/mii.h> 145 #include <dev/netif/mii_layer/miivar.h> 146 147 #include <bus/pci/pcidevs.h> 148 #include <bus/pci/pcireg.h> 149 #include <bus/pci/pcivar.h> 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 #include <dev/netif/re/if_rereg.h> 155 #include <dev/netif/re/if_revar.h> 156 157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static const struct re_type { 163 uint16_t re_vid; 164 uint16_t re_did; 165 const char *re_name; 166 } re_devs[] = { 167 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 168 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 169 170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 174 "RealTek 810x PCIe 10/100baseTX" }, 175 176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 177 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 178 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 180 "RealTek 8110/8169 Gigabit Ethernet" }, 181 182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 183 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 184 185 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 186 "Corega CG-LAPCIGT Gigabit Ethernet" }, 187 188 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 189 "Linksys EG1032 Gigabit Ethernet" }, 190 191 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 192 "US Robotics 997902 Gigabit Ethernet" }, 193 194 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 195 "TTTech MC322 Gigabit Ethernet" }, 196 197 { 0, 0, NULL } 198 }; 199 200 static const struct re_hwrev re_hwrevs[] = { 201 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 202 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 203 204 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 205 RE_C_HWCSUM | RE_C_8169 }, 206 207 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 208 RE_C_HWCSUM | RE_C_8169 }, 209 210 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 211 RE_C_HWCSUM | RE_C_8169 }, 212 213 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 214 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 215 216 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 217 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 218 219 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 220 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 221 222 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 223 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 224 225 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 226 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 227 228 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 229 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 230 231 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 232 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 233 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 234 235 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 236 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 237 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 238 239 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 240 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 241 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 242 243 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K, 244 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 245 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 246 247 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K, 248 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 249 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 250 251 { RE_HWREV_8168F, RE_MACVER_UNKN, RE_MTU_9K, 252 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 253 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 254 255 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 256 RE_C_HWCSUM | RE_C_FASTE }, 257 258 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 259 RE_C_HWCSUM | RE_C_FASTE }, 260 261 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 262 RE_C_HWCSUM | RE_C_FASTE }, 263 264 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 265 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 266 RE_C_FASTE }, 267 268 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 269 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 270 RE_C_FASTE }, 271 272 { RE_HWREV_8105E, RE_MACVER_UNKN, ETHERMTU, 273 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 274 RE_C_STOP_RXTX | RE_C_FASTE }, 275 276 { RE_HWREV_NULL, 0, 0, 0 } 277 }; 278 279 static int re_probe(device_t); 280 static int re_attach(device_t); 281 static int re_detach(device_t); 282 static int re_suspend(device_t); 283 static int re_resume(device_t); 284 static void re_shutdown(device_t); 285 286 static int re_allocmem(device_t); 287 static void re_freemem(device_t); 288 static void re_freebufmem(struct re_softc *, int, int); 289 static int re_encap(struct re_softc *, struct mbuf **, int *); 290 static int re_newbuf_std(struct re_softc *, int, int); 291 static int re_newbuf_jumbo(struct re_softc *, int, int); 292 static void re_setup_rxdesc(struct re_softc *, int); 293 static int re_rx_list_init(struct re_softc *); 294 static int re_tx_list_init(struct re_softc *); 295 static int re_rxeof(struct re_softc *); 296 static int re_txeof(struct re_softc *); 297 static int re_tx_collect(struct re_softc *); 298 static void re_intr(void *); 299 static void re_tick(void *); 300 static void re_tick_serialized(void *); 301 302 static void re_start(struct ifnet *); 303 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 304 static void re_init(void *); 305 static void re_stop(struct re_softc *); 306 static void re_watchdog(struct ifnet *); 307 static int re_ifmedia_upd(struct ifnet *); 308 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 309 310 static void re_eeprom_putbyte(struct re_softc *, int); 311 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 312 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 313 static void re_get_eewidth(struct re_softc *); 314 315 static int re_gmii_readreg(device_t, int, int); 316 static int re_gmii_writereg(device_t, int, int, int); 317 318 static int re_miibus_readreg(device_t, int, int); 319 static int re_miibus_writereg(device_t, int, int, int); 320 static void re_miibus_statchg(device_t); 321 322 static void re_setmulti(struct re_softc *); 323 static void re_reset(struct re_softc *, int); 324 static void re_get_eaddr(struct re_softc *, uint8_t *); 325 326 static void re_setup_hw_im(struct re_softc *); 327 static void re_setup_sim_im(struct re_softc *); 328 static void re_disable_hw_im(struct re_softc *); 329 static void re_disable_sim_im(struct re_softc *); 330 static void re_config_imtype(struct re_softc *, int); 331 static void re_setup_intr(struct re_softc *, int, int); 332 333 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 334 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 335 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 336 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 337 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 338 339 static int re_jpool_alloc(struct re_softc *); 340 static void re_jpool_free(struct re_softc *); 341 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 342 static void re_jbuf_free(void *); 343 static void re_jbuf_ref(void *); 344 345 #ifdef RE_DIAG 346 static int re_diag(struct re_softc *); 347 #endif 348 349 #ifdef DEVICE_POLLING 350 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 351 #endif 352 353 static device_method_t re_methods[] = { 354 /* Device interface */ 355 DEVMETHOD(device_probe, re_probe), 356 DEVMETHOD(device_attach, re_attach), 357 DEVMETHOD(device_detach, re_detach), 358 DEVMETHOD(device_suspend, re_suspend), 359 DEVMETHOD(device_resume, re_resume), 360 DEVMETHOD(device_shutdown, re_shutdown), 361 362 /* bus interface */ 363 DEVMETHOD(bus_print_child, bus_generic_print_child), 364 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 365 366 /* MII interface */ 367 DEVMETHOD(miibus_readreg, re_miibus_readreg), 368 DEVMETHOD(miibus_writereg, re_miibus_writereg), 369 DEVMETHOD(miibus_statchg, re_miibus_statchg), 370 371 { 0, 0 } 372 }; 373 374 static driver_t re_driver = { 375 "re", 376 re_methods, 377 sizeof(struct re_softc) 378 }; 379 380 static devclass_t re_devclass; 381 382 DECLARE_DUMMY_MODULE(if_re); 383 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 384 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 385 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 386 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 387 388 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 389 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 390 static int re_msi_enable = 0; 391 392 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 393 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 394 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 395 396 #define EE_SET(x) \ 397 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 398 399 #define EE_CLR(x) \ 400 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 401 402 static __inline void 403 re_free_rxchain(struct re_softc *sc) 404 { 405 if (sc->re_head != NULL) { 406 m_freem(sc->re_head); 407 sc->re_head = sc->re_tail = NULL; 408 } 409 } 410 411 /* 412 * Send a read command and address to the EEPROM, check for ACK. 413 */ 414 static void 415 re_eeprom_putbyte(struct re_softc *sc, int addr) 416 { 417 int d, i; 418 419 d = addr | (RE_9346_READ << sc->re_eewidth); 420 421 /* 422 * Feed in each bit and strobe the clock. 423 */ 424 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 425 if (d & i) 426 EE_SET(RE_EE_DATAIN); 427 else 428 EE_CLR(RE_EE_DATAIN); 429 DELAY(100); 430 EE_SET(RE_EE_CLK); 431 DELAY(150); 432 EE_CLR(RE_EE_CLK); 433 DELAY(100); 434 } 435 } 436 437 /* 438 * Read a word of data stored in the EEPROM at address 'addr.' 439 */ 440 static void 441 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 442 { 443 int i; 444 uint16_t word = 0; 445 446 /* 447 * Send address of word we want to read. 448 */ 449 re_eeprom_putbyte(sc, addr); 450 451 /* 452 * Start reading bits from EEPROM. 453 */ 454 for (i = 0x8000; i != 0; i >>= 1) { 455 EE_SET(RE_EE_CLK); 456 DELAY(100); 457 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 458 word |= i; 459 EE_CLR(RE_EE_CLK); 460 DELAY(100); 461 } 462 463 *dest = word; 464 } 465 466 /* 467 * Read a sequence of words from the EEPROM. 468 */ 469 static void 470 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 471 { 472 int i; 473 uint16_t word = 0, *ptr; 474 475 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 476 DELAY(100); 477 478 for (i = 0; i < cnt; i++) { 479 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 480 re_eeprom_getword(sc, off + i, &word); 481 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 482 ptr = (uint16_t *)(dest + (i * 2)); 483 *ptr = word; 484 } 485 486 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 487 } 488 489 static void 490 re_get_eewidth(struct re_softc *sc) 491 { 492 uint16_t re_did = 0; 493 494 sc->re_eewidth = 6; 495 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 496 if (re_did != 0x8129) 497 sc->re_eewidth = 8; 498 } 499 500 static int 501 re_gmii_readreg(device_t dev, int phy, int reg) 502 { 503 struct re_softc *sc = device_get_softc(dev); 504 u_int32_t rval; 505 int i; 506 507 if (phy != 1) 508 return(0); 509 510 /* Let the rgephy driver read the GMEDIASTAT register */ 511 512 if (reg == RE_GMEDIASTAT) 513 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 514 515 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 516 DELAY(1000); 517 518 for (i = 0; i < RE_TIMEOUT; i++) { 519 rval = CSR_READ_4(sc, RE_PHYAR); 520 if (rval & RE_PHYAR_BUSY) 521 break; 522 DELAY(100); 523 } 524 525 if (i == RE_TIMEOUT) { 526 device_printf(dev, "PHY read failed\n"); 527 return(0); 528 } 529 530 return(rval & RE_PHYAR_PHYDATA); 531 } 532 533 static int 534 re_gmii_writereg(device_t dev, int phy, int reg, int data) 535 { 536 struct re_softc *sc = device_get_softc(dev); 537 uint32_t rval; 538 int i; 539 540 CSR_WRITE_4(sc, RE_PHYAR, 541 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 542 DELAY(1000); 543 544 for (i = 0; i < RE_TIMEOUT; i++) { 545 rval = CSR_READ_4(sc, RE_PHYAR); 546 if ((rval & RE_PHYAR_BUSY) == 0) 547 break; 548 DELAY(100); 549 } 550 551 if (i == RE_TIMEOUT) 552 device_printf(dev, "PHY write failed\n"); 553 554 return(0); 555 } 556 557 static int 558 re_miibus_readreg(device_t dev, int phy, int reg) 559 { 560 struct re_softc *sc = device_get_softc(dev); 561 uint16_t rval = 0; 562 uint16_t re8139_reg = 0; 563 564 if (!RE_IS_8139CP(sc)) { 565 rval = re_gmii_readreg(dev, phy, reg); 566 return(rval); 567 } 568 569 /* Pretend the internal PHY is only at address 0 */ 570 if (phy) 571 return(0); 572 573 switch(reg) { 574 case MII_BMCR: 575 re8139_reg = RE_BMCR; 576 break; 577 case MII_BMSR: 578 re8139_reg = RE_BMSR; 579 break; 580 case MII_ANAR: 581 re8139_reg = RE_ANAR; 582 break; 583 case MII_ANER: 584 re8139_reg = RE_ANER; 585 break; 586 case MII_ANLPAR: 587 re8139_reg = RE_LPAR; 588 break; 589 case MII_PHYIDR1: 590 case MII_PHYIDR2: 591 return(0); 592 /* 593 * Allow the rlphy driver to read the media status 594 * register. If we have a link partner which does not 595 * support NWAY, this is the register which will tell 596 * us the results of parallel detection. 597 */ 598 case RE_MEDIASTAT: 599 return(CSR_READ_1(sc, RE_MEDIASTAT)); 600 default: 601 device_printf(dev, "bad phy register\n"); 602 return(0); 603 } 604 rval = CSR_READ_2(sc, re8139_reg); 605 if (re8139_reg == RE_BMCR) { 606 /* 8139C+ has different bit layout. */ 607 rval &= ~(BMCR_LOOP | BMCR_ISO); 608 } 609 return(rval); 610 } 611 612 static int 613 re_miibus_writereg(device_t dev, int phy, int reg, int data) 614 { 615 struct re_softc *sc= device_get_softc(dev); 616 u_int16_t re8139_reg = 0; 617 618 if (!RE_IS_8139CP(sc)) 619 return(re_gmii_writereg(dev, phy, reg, data)); 620 621 /* Pretend the internal PHY is only at address 0 */ 622 if (phy) 623 return(0); 624 625 switch(reg) { 626 case MII_BMCR: 627 re8139_reg = RE_BMCR; 628 /* 8139C+ has different bit layout. */ 629 data &= ~(BMCR_LOOP | BMCR_ISO); 630 break; 631 case MII_BMSR: 632 re8139_reg = RE_BMSR; 633 break; 634 case MII_ANAR: 635 re8139_reg = RE_ANAR; 636 break; 637 case MII_ANER: 638 re8139_reg = RE_ANER; 639 break; 640 case MII_ANLPAR: 641 re8139_reg = RE_LPAR; 642 break; 643 case MII_PHYIDR1: 644 case MII_PHYIDR2: 645 return(0); 646 default: 647 device_printf(dev, "bad phy register\n"); 648 return(0); 649 } 650 CSR_WRITE_2(sc, re8139_reg, data); 651 return(0); 652 } 653 654 static void 655 re_miibus_statchg(device_t dev) 656 { 657 } 658 659 /* 660 * Program the 64-bit multicast hash filter. 661 */ 662 static void 663 re_setmulti(struct re_softc *sc) 664 { 665 struct ifnet *ifp = &sc->arpcom.ac_if; 666 int h = 0; 667 uint32_t hashes[2] = { 0, 0 }; 668 struct ifmultiaddr *ifma; 669 uint32_t rxfilt; 670 int mcnt = 0; 671 672 rxfilt = CSR_READ_4(sc, RE_RXCFG); 673 674 /* Set the individual bit to receive frames for this host only. */ 675 rxfilt |= RE_RXCFG_RX_INDIV; 676 /* Set capture broadcast bit to capture broadcast frames. */ 677 rxfilt |= RE_RXCFG_RX_BROAD; 678 679 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 680 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 681 rxfilt |= RE_RXCFG_RX_MULTI; 682 683 /* If we want promiscuous mode, set the allframes bit. */ 684 if (ifp->if_flags & IFF_PROMISC) 685 rxfilt |= RE_RXCFG_RX_ALLPHYS; 686 687 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 688 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 689 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 690 return; 691 } 692 693 /* first, zot all the existing hash bits */ 694 CSR_WRITE_4(sc, RE_MAR0, 0); 695 CSR_WRITE_4(sc, RE_MAR4, 0); 696 697 /* now program new ones */ 698 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 699 if (ifma->ifma_addr->sa_family != AF_LINK) 700 continue; 701 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 702 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 703 if (h < 32) 704 hashes[0] |= (1 << h); 705 else 706 hashes[1] |= (1 << (h - 32)); 707 mcnt++; 708 } 709 710 if (mcnt) 711 rxfilt |= RE_RXCFG_RX_MULTI; 712 else 713 rxfilt &= ~RE_RXCFG_RX_MULTI; 714 715 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 716 717 /* 718 * For some unfathomable reason, RealTek decided to reverse 719 * the order of the multicast hash registers in the PCI Express 720 * parts. This means we have to write the hash pattern in reverse 721 * order for those devices. 722 */ 723 if (sc->re_caps & RE_C_PCIE) { 724 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 725 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 726 } else { 727 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 728 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 729 } 730 } 731 732 static void 733 re_reset(struct re_softc *sc, int running) 734 { 735 int i; 736 737 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 738 CSR_WRITE_1(sc, RE_COMMAND, 739 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 740 DELAY(100); 741 } 742 743 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 744 745 for (i = 0; i < RE_TIMEOUT; i++) { 746 DELAY(10); 747 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 748 break; 749 } 750 if (i == RE_TIMEOUT) 751 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 752 } 753 754 #ifdef RE_DIAG 755 /* 756 * The following routine is designed to test for a defect on some 757 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 758 * lines connected to the bus, however for a 32-bit only card, they 759 * should be pulled high. The result of this defect is that the 760 * NIC will not work right if you plug it into a 64-bit slot: DMA 761 * operations will be done with 64-bit transfers, which will fail 762 * because the 64-bit data lines aren't connected. 763 * 764 * There's no way to work around this (short of talking a soldering 765 * iron to the board), however we can detect it. The method we use 766 * here is to put the NIC into digital loopback mode, set the receiver 767 * to promiscuous mode, and then try to send a frame. We then compare 768 * the frame data we sent to what was received. If the data matches, 769 * then the NIC is working correctly, otherwise we know the user has 770 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 771 * slot. In the latter case, there's no way the NIC can work correctly, 772 * so we print out a message on the console and abort the device attach. 773 */ 774 775 static int 776 re_diag(struct re_softc *sc) 777 { 778 struct ifnet *ifp = &sc->arpcom.ac_if; 779 struct mbuf *m0; 780 struct ether_header *eh; 781 struct re_desc *cur_rx; 782 uint16_t status; 783 uint32_t rxstat; 784 int total_len, i, error = 0, phyaddr; 785 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 786 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 787 788 /* Allocate a single mbuf */ 789 790 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 791 if (m0 == NULL) 792 return(ENOBUFS); 793 794 /* 795 * Initialize the NIC in test mode. This sets the chip up 796 * so that it can send and receive frames, but performs the 797 * following special functions: 798 * - Puts receiver in promiscuous mode 799 * - Enables digital loopback mode 800 * - Leaves interrupts turned off 801 */ 802 803 ifp->if_flags |= IFF_PROMISC; 804 sc->re_flags |= RE_F_TESTMODE; 805 re_init(sc); 806 sc->re_flags |= RE_F_LINKED; 807 if (!RE_IS_8139CP(sc)) 808 phyaddr = 1; 809 else 810 phyaddr = 0; 811 812 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 813 for (i = 0; i < RE_TIMEOUT; i++) { 814 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 815 if (!(status & BMCR_RESET)) 816 break; 817 } 818 819 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 820 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 821 822 DELAY(100000); 823 824 /* Put some data in the mbuf */ 825 826 eh = mtod(m0, struct ether_header *); 827 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 828 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 829 eh->ether_type = htons(ETHERTYPE_IP); 830 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 831 832 /* 833 * Queue the packet, start transmission. 834 * Note: ifq_handoff() ultimately calls re_start() for us. 835 */ 836 837 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 838 error = ifq_handoff(ifp, m0, NULL); 839 if (error) { 840 m0 = NULL; 841 goto done; 842 } 843 m0 = NULL; 844 845 /* Wait for it to propagate through the chip */ 846 847 DELAY(100000); 848 for (i = 0; i < RE_TIMEOUT; i++) { 849 status = CSR_READ_2(sc, RE_ISR); 850 CSR_WRITE_2(sc, RE_ISR, status); 851 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 852 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 853 break; 854 DELAY(10); 855 } 856 857 if (i == RE_TIMEOUT) { 858 if_printf(ifp, "diagnostic failed to receive packet " 859 "in loopback mode\n"); 860 error = EIO; 861 goto done; 862 } 863 864 /* 865 * The packet should have been dumped into the first 866 * entry in the RX DMA ring. Grab it from there. 867 */ 868 869 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 870 BUS_DMASYNC_POSTREAD); 871 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 872 sc->re_ldata.re_rx_dmamap[0]); 873 874 m0 = sc->re_ldata.re_rx_mbuf[0]; 875 sc->re_ldata.re_rx_mbuf[0] = NULL; 876 eh = mtod(m0, struct ether_header *); 877 878 cur_rx = &sc->re_ldata.re_rx_list[0]; 879 total_len = RE_RXBYTES(cur_rx); 880 rxstat = le32toh(cur_rx->re_cmdstat); 881 882 if (total_len != ETHER_MIN_LEN) { 883 if_printf(ifp, "diagnostic failed, received short packet\n"); 884 error = EIO; 885 goto done; 886 } 887 888 /* Test that the received packet data matches what we sent. */ 889 890 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 891 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 892 be16toh(eh->ether_type) != ETHERTYPE_IP) { 893 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 894 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 895 dst, ":", src, ":", ETHERTYPE_IP); 896 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 897 eh->ether_dhost, ":", eh->ether_shost, ":", 898 ntohs(eh->ether_type)); 899 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 900 "into a 64-bit PCI slot.\n"); 901 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 902 "for proper operation.\n"); 903 if_printf(ifp, "Read the re(4) man page for more details.\n"); 904 error = EIO; 905 } 906 907 done: 908 /* Turn interface off, release resources */ 909 910 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 911 ifp->if_flags &= ~IFF_PROMISC; 912 re_stop(sc); 913 if (m0 != NULL) 914 m_freem(m0); 915 916 return (error); 917 } 918 #endif /* RE_DIAG */ 919 920 /* 921 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 922 * IDs against our list and return a device name if we find a match. 923 */ 924 static int 925 re_probe(device_t dev) 926 { 927 const struct re_type *t; 928 const struct re_hwrev *hw_rev; 929 struct re_softc *sc; 930 int rid; 931 uint32_t hwrev, macmode, txcfg; 932 uint16_t vendor, product; 933 934 vendor = pci_get_vendor(dev); 935 product = pci_get_device(dev); 936 937 /* 938 * Only attach to rev.3 of the Linksys EG1032 adapter. 939 * Rev.2 is supported by sk(4). 940 */ 941 if (vendor == PCI_VENDOR_LINKSYS && 942 product == PCI_PRODUCT_LINKSYS_EG1032 && 943 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 944 return ENXIO; 945 946 if (vendor == PCI_VENDOR_REALTEK && 947 product == PCI_PRODUCT_REALTEK_RT8139 && 948 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 949 /* Poor 8139 */ 950 return ENXIO; 951 } 952 953 for (t = re_devs; t->re_name != NULL; t++) { 954 if (product == t->re_did && vendor == t->re_vid) 955 break; 956 } 957 958 /* 959 * Check if we found a RealTek device. 960 */ 961 if (t->re_name == NULL) 962 return ENXIO; 963 964 /* 965 * Temporarily map the I/O space so we can read the chip ID register. 966 */ 967 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 968 rid = RE_PCI_LOIO; 969 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 970 RF_ACTIVE); 971 if (sc->re_res == NULL) { 972 device_printf(dev, "couldn't map ports/memory\n"); 973 kfree(sc, M_TEMP); 974 return ENXIO; 975 } 976 977 sc->re_btag = rman_get_bustag(sc->re_res); 978 sc->re_bhandle = rman_get_bushandle(sc->re_res); 979 980 txcfg = CSR_READ_4(sc, RE_TXCFG); 981 hwrev = txcfg & RE_TXCFG_HWREV; 982 macmode = txcfg & RE_TXCFG_MACMODE; 983 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 984 kfree(sc, M_TEMP); 985 986 /* 987 * and continue matching for the specific chip... 988 */ 989 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 990 if (hw_rev->re_hwrev == hwrev) { 991 sc = device_get_softc(dev); 992 993 sc->re_hwrev = hw_rev->re_hwrev; 994 sc->re_macver = hw_rev->re_macver; 995 sc->re_caps = hw_rev->re_caps; 996 sc->re_maxmtu = hw_rev->re_maxmtu; 997 998 /* 999 * Apply chip property fixup 1000 */ 1001 switch (sc->re_hwrev) { 1002 case RE_HWREV_8101E1: 1003 case RE_HWREV_8101E2: 1004 if (macmode == 0) 1005 sc->re_macver = RE_MACVER_11; 1006 else if (macmode == 0x200000) 1007 sc->re_macver = RE_MACVER_12; 1008 break; 1009 case RE_HWREV_8102E: 1010 case RE_HWREV_8102EL: 1011 if (macmode == 0) 1012 sc->re_macver = RE_MACVER_13; 1013 else if (macmode == 0x100000) 1014 sc->re_macver = RE_MACVER_14; 1015 break; 1016 case RE_HWREV_8168B2: 1017 case RE_HWREV_8168B3: 1018 if (macmode == 0) 1019 sc->re_macver = RE_MACVER_22; 1020 break; 1021 case RE_HWREV_8168C: 1022 if (macmode == 0) 1023 sc->re_macver = RE_MACVER_24; 1024 else if (macmode == 0x200000) 1025 sc->re_macver = RE_MACVER_25; 1026 else if (macmode == 0x300000) 1027 sc->re_macver = RE_MACVER_27; 1028 break; 1029 case RE_HWREV_8168CP: 1030 if (macmode == 0) 1031 sc->re_macver = RE_MACVER_26; 1032 else if (macmode == 0x100000) 1033 sc->re_macver = RE_MACVER_28; 1034 break; 1035 case RE_HWREV_8168DP: 1036 if (macmode == 0) 1037 sc->re_macver = RE_MACVER_2B; 1038 else if (macmode == 0x200000) 1039 sc->re_macver = RE_MACVER_2C; 1040 break; 1041 case RE_HWREV_8168E: 1042 if (macmode == 0x100000) 1043 sc->re_macver = RE_MACVER_2E; 1044 else if (macmode == 0x200000) 1045 sc->re_macver = RE_MACVER_2F; 1046 break; 1047 case RE_HWREV_8168F: 1048 if (macmode == 0x000000) 1049 sc->re_macver = RE_MACVER_30; 1050 else if (macmode == 0x100000) 1051 sc->re_macver = RE_MACVER_31; 1052 break; 1053 } 1054 if (pci_is_pcie(dev)) 1055 sc->re_caps |= RE_C_PCIE; 1056 1057 device_set_desc(dev, t->re_name); 1058 return 0; 1059 } 1060 } 1061 1062 if (bootverbose) { 1063 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1064 hwrev, macmode); 1065 } 1066 return ENXIO; 1067 } 1068 1069 static int 1070 re_allocmem(device_t dev) 1071 { 1072 struct re_softc *sc = device_get_softc(dev); 1073 bus_dmamem_t dmem; 1074 int error, i; 1075 1076 /* 1077 * Allocate list data 1078 */ 1079 sc->re_ldata.re_tx_mbuf = 1080 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1081 M_DEVBUF, M_ZERO | M_WAITOK); 1082 1083 sc->re_ldata.re_rx_mbuf = 1084 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1085 M_DEVBUF, M_ZERO | M_WAITOK); 1086 1087 sc->re_ldata.re_rx_paddr = 1088 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1089 M_DEVBUF, M_ZERO | M_WAITOK); 1090 1091 sc->re_ldata.re_tx_dmamap = 1092 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1093 M_DEVBUF, M_ZERO | M_WAITOK); 1094 1095 sc->re_ldata.re_rx_dmamap = 1096 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1097 M_DEVBUF, M_ZERO | M_WAITOK); 1098 1099 /* 1100 * Allocate the parent bus DMA tag appropriate for PCI. 1101 */ 1102 error = bus_dma_tag_create(NULL, /* parent */ 1103 1, 0, /* alignment, boundary */ 1104 BUS_SPACE_MAXADDR, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, NULL, /* filter, filterarg */ 1107 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1108 0, /* nsegments */ 1109 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1110 0, /* flags */ 1111 &sc->re_parent_tag); 1112 if (error) { 1113 device_printf(dev, "could not allocate parent dma tag\n"); 1114 return error; 1115 } 1116 1117 /* Allocate TX descriptor list. */ 1118 error = bus_dmamem_coherent(sc->re_parent_tag, 1119 RE_RING_ALIGN, 0, 1120 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1121 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1122 &dmem); 1123 if (error) { 1124 device_printf(dev, "could not allocate TX ring\n"); 1125 return error; 1126 } 1127 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1128 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1129 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1130 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1131 1132 /* Allocate RX descriptor list. */ 1133 error = bus_dmamem_coherent(sc->re_parent_tag, 1134 RE_RING_ALIGN, 0, 1135 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1136 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1137 &dmem); 1138 if (error) { 1139 device_printf(dev, "could not allocate RX ring\n"); 1140 return error; 1141 } 1142 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1143 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1144 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1145 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1146 1147 /* Allocate maps for TX mbufs. */ 1148 error = bus_dma_tag_create(sc->re_parent_tag, 1149 1, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1151 NULL, NULL, 1152 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1153 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1154 &sc->re_ldata.re_tx_mtag); 1155 if (error) { 1156 device_printf(dev, "could not allocate TX buf dma tag\n"); 1157 return(error); 1158 } 1159 1160 /* Create DMA maps for TX buffers */ 1161 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1162 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1163 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1164 &sc->re_ldata.re_tx_dmamap[i]); 1165 if (error) { 1166 device_printf(dev, "can't create DMA map for TX buf\n"); 1167 re_freebufmem(sc, i, 0); 1168 return(error); 1169 } 1170 } 1171 1172 /* Allocate maps for RX mbufs. */ 1173 error = bus_dma_tag_create(sc->re_parent_tag, 1174 RE_RXBUF_ALIGN, 0, 1175 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1176 NULL, NULL, 1177 MCLBYTES, 1, MCLBYTES, 1178 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1179 &sc->re_ldata.re_rx_mtag); 1180 if (error) { 1181 device_printf(dev, "could not allocate RX buf dma tag\n"); 1182 return(error); 1183 } 1184 1185 /* Create spare DMA map for RX */ 1186 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1187 &sc->re_ldata.re_rx_spare); 1188 if (error) { 1189 device_printf(dev, "can't create spare DMA map for RX\n"); 1190 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1191 sc->re_ldata.re_rx_mtag = NULL; 1192 return error; 1193 } 1194 1195 /* Create DMA maps for RX buffers */ 1196 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1197 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1198 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1199 if (error) { 1200 device_printf(dev, "can't create DMA map for RX buf\n"); 1201 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1202 return(error); 1203 } 1204 } 1205 1206 /* Create jumbo buffer pool for RX if required */ 1207 if (sc->re_caps & RE_C_CONTIGRX) { 1208 error = re_jpool_alloc(sc); 1209 if (error) { 1210 re_jpool_free(sc); 1211 /* Disable jumbo frame support */ 1212 sc->re_maxmtu = ETHERMTU; 1213 } 1214 } 1215 return(0); 1216 } 1217 1218 static void 1219 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1220 { 1221 int i; 1222 1223 /* Destroy all the RX and TX buffer maps */ 1224 if (sc->re_ldata.re_tx_mtag) { 1225 for (i = 0; i < tx_cnt; i++) { 1226 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1227 sc->re_ldata.re_tx_dmamap[i]); 1228 } 1229 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1230 sc->re_ldata.re_tx_mtag = NULL; 1231 } 1232 1233 if (sc->re_ldata.re_rx_mtag) { 1234 for (i = 0; i < rx_cnt; i++) { 1235 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1236 sc->re_ldata.re_rx_dmamap[i]); 1237 } 1238 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1239 sc->re_ldata.re_rx_spare); 1240 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1241 sc->re_ldata.re_rx_mtag = NULL; 1242 } 1243 } 1244 1245 static void 1246 re_freemem(device_t dev) 1247 { 1248 struct re_softc *sc = device_get_softc(dev); 1249 1250 /* Unload and free the RX DMA ring memory and map */ 1251 if (sc->re_ldata.re_rx_list_tag) { 1252 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1253 sc->re_ldata.re_rx_list_map); 1254 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1255 sc->re_ldata.re_rx_list, 1256 sc->re_ldata.re_rx_list_map); 1257 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1258 } 1259 1260 /* Unload and free the TX DMA ring memory and map */ 1261 if (sc->re_ldata.re_tx_list_tag) { 1262 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1263 sc->re_ldata.re_tx_list_map); 1264 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1265 sc->re_ldata.re_tx_list, 1266 sc->re_ldata.re_tx_list_map); 1267 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1268 } 1269 1270 /* Free RX/TX buf DMA stuffs */ 1271 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1272 1273 /* Unload and free the stats buffer and map */ 1274 if (sc->re_ldata.re_stag) { 1275 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1276 bus_dmamem_free(sc->re_ldata.re_stag, 1277 sc->re_ldata.re_stats, 1278 sc->re_ldata.re_smap); 1279 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1280 } 1281 1282 if (sc->re_caps & RE_C_CONTIGRX) 1283 re_jpool_free(sc); 1284 1285 if (sc->re_parent_tag) 1286 bus_dma_tag_destroy(sc->re_parent_tag); 1287 1288 if (sc->re_ldata.re_tx_mbuf != NULL) 1289 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1290 if (sc->re_ldata.re_rx_mbuf != NULL) 1291 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1292 if (sc->re_ldata.re_rx_paddr != NULL) 1293 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1294 if (sc->re_ldata.re_tx_dmamap != NULL) 1295 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1296 if (sc->re_ldata.re_rx_dmamap != NULL) 1297 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1298 } 1299 1300 /* 1301 * Attach the interface. Allocate softc structures, do ifmedia 1302 * setup and ethernet/BPF attach. 1303 */ 1304 static int 1305 re_attach(device_t dev) 1306 { 1307 struct re_softc *sc = device_get_softc(dev); 1308 struct ifnet *ifp; 1309 uint8_t eaddr[ETHER_ADDR_LEN]; 1310 int error = 0, rid, qlen; 1311 u_int irq_flags; 1312 1313 callout_init(&sc->re_timer); 1314 sc->re_dev = dev; 1315 1316 if (RE_IS_8139CP(sc)) { 1317 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1318 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1319 } else { 1320 sc->re_rx_desc_cnt = re_rx_desc_count; 1321 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1322 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1323 1324 sc->re_tx_desc_cnt = re_tx_desc_count; 1325 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1326 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1327 } 1328 1329 qlen = RE_IFQ_MAXLEN; 1330 if (sc->re_tx_desc_cnt > qlen) 1331 qlen = sc->re_tx_desc_cnt; 1332 1333 sc->re_rxbuf_size = MCLBYTES; 1334 sc->re_newbuf = re_newbuf_std; 1335 1336 sc->re_tx_time = 5; /* 125us */ 1337 sc->re_rx_time = 2; /* 50us */ 1338 if (sc->re_caps & RE_C_PCIE) 1339 sc->re_sim_time = 75; /* 75us */ 1340 else 1341 sc->re_sim_time = 125; /* 125us */ 1342 if (!RE_IS_8139CP(sc)) { 1343 /* simulated interrupt moderation */ 1344 sc->re_imtype = RE_IMTYPE_SIM; 1345 } else { 1346 sc->re_imtype = RE_IMTYPE_NONE; 1347 } 1348 re_config_imtype(sc, sc->re_imtype); 1349 1350 sysctl_ctx_init(&sc->re_sysctl_ctx); 1351 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1352 SYSCTL_STATIC_CHILDREN(_hw), 1353 OID_AUTO, 1354 device_get_nameunit(dev), 1355 CTLFLAG_RD, 0, ""); 1356 if (sc->re_sysctl_tree == NULL) { 1357 device_printf(dev, "can't add sysctl node\n"); 1358 error = ENXIO; 1359 goto fail; 1360 } 1361 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1362 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1363 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1364 0, "RX desc count"); 1365 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1366 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1367 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1368 0, "TX desc count"); 1369 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1370 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1371 OID_AUTO, "sim_time", 1372 CTLTYPE_INT | CTLFLAG_RW, 1373 sc, 0, re_sysctl_simtime, "I", 1374 "Simulated interrupt moderation time (usec)."); 1375 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1376 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1377 OID_AUTO, "imtype", 1378 CTLTYPE_INT | CTLFLAG_RW, 1379 sc, 0, re_sysctl_imtype, "I", 1380 "Interrupt moderation type -- " 1381 "0:disable, 1:simulated, " 1382 "2:hardware(if supported)"); 1383 if (sc->re_caps & RE_C_HWIM) { 1384 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1385 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1386 OID_AUTO, "hw_rxtime", 1387 CTLTYPE_INT | CTLFLAG_RW, 1388 sc, 0, re_sysctl_rxtime, "I", 1389 "Hardware interrupt moderation time " 1390 "(unit: 25usec)."); 1391 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1392 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1393 OID_AUTO, "hw_txtime", 1394 CTLTYPE_INT | CTLFLAG_RW, 1395 sc, 0, re_sysctl_txtime, "I", 1396 "Hardware interrupt moderation time " 1397 "(unit: 25usec)."); 1398 } 1399 1400 #ifndef BURN_BRIDGES 1401 /* 1402 * Handle power management nonsense. 1403 */ 1404 1405 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1406 uint32_t membase, irq; 1407 1408 /* Save important PCI config data. */ 1409 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1410 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1411 1412 /* Reset the power state. */ 1413 device_printf(dev, "chip is in D%d power mode " 1414 "-- setting to D0\n", pci_get_powerstate(dev)); 1415 1416 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1417 1418 /* Restore PCI config data. */ 1419 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1420 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1421 } 1422 #endif 1423 /* 1424 * Map control/status registers. 1425 */ 1426 pci_enable_busmaster(dev); 1427 1428 rid = RE_PCI_LOIO; 1429 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1430 RF_ACTIVE); 1431 1432 if (sc->re_res == NULL) { 1433 device_printf(dev, "couldn't map ports\n"); 1434 error = ENXIO; 1435 goto fail; 1436 } 1437 1438 sc->re_btag = rman_get_bustag(sc->re_res); 1439 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1440 1441 /* Allocate interrupt */ 1442 sc->re_irq_type = pci_alloc_1intr(dev, re_msi_enable, 1443 &sc->re_irq_rid, &irq_flags); 1444 1445 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1446 irq_flags); 1447 if (sc->re_irq == NULL) { 1448 device_printf(dev, "couldn't map interrupt\n"); 1449 error = ENXIO; 1450 goto fail; 1451 } 1452 1453 /* Reset the adapter. */ 1454 re_reset(sc, 0); 1455 1456 if (RE_IS_8139CP(sc)) { 1457 sc->re_bus_speed = 33; /* XXX */ 1458 } else if (sc->re_caps & RE_C_PCIE) { 1459 sc->re_bus_speed = 125; 1460 } else { 1461 uint8_t cfg2; 1462 1463 cfg2 = CSR_READ_1(sc, RE_CFG2); 1464 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1465 case RE_CFG2_PCICLK_33MHZ: 1466 sc->re_bus_speed = 33; 1467 break; 1468 case RE_CFG2_PCICLK_66MHZ: 1469 sc->re_bus_speed = 66; 1470 break; 1471 default: 1472 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1473 sc->re_bus_speed = 33; 1474 break; 1475 } 1476 if (cfg2 & RE_CFG2_PCI64) 1477 sc->re_caps |= RE_C_PCI64; 1478 } 1479 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1480 "PCI%s %dMHz\n", 1481 sc->re_hwrev, sc->re_macver, 1482 (sc->re_caps & RE_C_PCIE) ? 1483 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1484 sc->re_bus_speed); 1485 1486 /* 1487 * NOTE: 1488 * DO NOT try to adjust config1 and config5 which was spotted in 1489 * Realtek's Linux drivers. It will _permanently_ damage certain 1490 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1491 */ 1492 1493 re_get_eaddr(sc, eaddr); 1494 1495 if (!RE_IS_8139CP(sc)) { 1496 /* Set RX length mask */ 1497 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1498 sc->re_txstart = RE_GTXSTART; 1499 } else { 1500 /* Set RX length mask */ 1501 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1502 sc->re_txstart = RE_TXSTART; 1503 } 1504 1505 /* Allocate DMA stuffs */ 1506 error = re_allocmem(dev); 1507 if (error) 1508 goto fail; 1509 1510 /* 1511 * Apply some magic PCI settings from Realtek ... 1512 */ 1513 if (RE_IS_8169(sc)) { 1514 CSR_WRITE_1(sc, 0x82, 1); 1515 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1516 } 1517 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1518 1519 if (sc->re_caps & RE_C_MAC2) { 1520 /* 1521 * Following part is extracted from Realtek BSD driver v176. 1522 * However, this does _not_ make much/any sense: 1523 * 8168C's PCI Express device control is located at 0x78, 1524 * so the reading from 0x79 (higher part of 0x78) and setting 1525 * the 4~6bits intend to enlarge the "max read request size" 1526 * (we will do it). The content of the rest part of this 1527 * register is not meaningful to other PCI registers, so 1528 * writing the value to 0x54 could be completely wrong. 1529 * 0x80 is the lower part of PCI Express device status, non- 1530 * reserved bits are RW1C, writing 0 to them will not have 1531 * any effect at all. 1532 */ 1533 #ifdef foo 1534 uint8_t val; 1535 1536 val = pci_read_config(dev, 0x79, 1); 1537 val = (val & ~0x70) | 0x50; 1538 pci_write_config(dev, 0x54, val, 1); 1539 pci_write_config(dev, 0x80, 0, 1); 1540 #endif 1541 } 1542 1543 /* 1544 * Apply some PHY fixup from Realtek ... 1545 */ 1546 if (sc->re_hwrev == RE_HWREV_8110S) { 1547 CSR_WRITE_1(sc, 0x82, 1); 1548 re_miibus_writereg(dev, 1, 0xb, 0); 1549 } 1550 if (sc->re_caps & RE_C_PHYPMGT) { 1551 /* Power up PHY */ 1552 re_miibus_writereg(dev, 1, 0x1f, 0); 1553 re_miibus_writereg(dev, 1, 0xe, 0); 1554 } 1555 1556 /* Do MII setup */ 1557 if (mii_phy_probe(dev, &sc->re_miibus, 1558 re_ifmedia_upd, re_ifmedia_sts)) { 1559 device_printf(dev, "MII without any phy!\n"); 1560 error = ENXIO; 1561 goto fail; 1562 } 1563 1564 ifp = &sc->arpcom.ac_if; 1565 ifp->if_softc = sc; 1566 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1567 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1568 ifp->if_ioctl = re_ioctl; 1569 ifp->if_start = re_start; 1570 #ifdef DEVICE_POLLING 1571 ifp->if_poll = re_poll; 1572 #endif 1573 ifp->if_watchdog = re_watchdog; 1574 ifp->if_init = re_init; 1575 if (!RE_IS_8139CP(sc)) /* XXX */ 1576 ifp->if_baudrate = 1000000000; 1577 else 1578 ifp->if_baudrate = 100000000; 1579 ifq_set_maxlen(&ifp->if_snd, qlen); 1580 ifq_set_ready(&ifp->if_snd); 1581 1582 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1583 if (sc->re_caps & RE_C_HWCSUM) 1584 ifp->if_capabilities |= IFCAP_HWCSUM; 1585 1586 ifp->if_capenable = ifp->if_capabilities; 1587 if (ifp->if_capabilities & IFCAP_HWCSUM) 1588 ifp->if_hwassist = RE_CSUM_FEATURES; 1589 else 1590 ifp->if_hwassist = 0; 1591 1592 /* 1593 * Call MI attach routine. 1594 */ 1595 ether_ifattach(ifp, eaddr, NULL); 1596 1597 #ifdef RE_DIAG 1598 /* 1599 * Perform hardware diagnostic on the original RTL8169. 1600 * Some 32-bit cards were incorrectly wired and would 1601 * malfunction if plugged into a 64-bit slot. 1602 */ 1603 if (sc->re_hwrev == RE_HWREV_8169) { 1604 lwkt_serialize_enter(ifp->if_serializer); 1605 error = re_diag(sc); 1606 lwkt_serialize_exit(ifp->if_serializer); 1607 1608 if (error) { 1609 device_printf(dev, "hardware diagnostic failure\n"); 1610 ether_ifdetach(ifp); 1611 goto fail; 1612 } 1613 } 1614 #endif /* RE_DIAG */ 1615 1616 /* Hook interrupt last to avoid having to lock softc */ 1617 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1618 &sc->re_intrhand, ifp->if_serializer); 1619 1620 if (error) { 1621 device_printf(dev, "couldn't set up irq\n"); 1622 ether_ifdetach(ifp); 1623 goto fail; 1624 } 1625 1626 ifp->if_cpuid = rman_get_cpuid(sc->re_irq); 1627 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1628 1629 fail: 1630 if (error) 1631 re_detach(dev); 1632 1633 return (error); 1634 } 1635 1636 /* 1637 * Shutdown hardware and free up resources. This can be called any 1638 * time after the mutex has been initialized. It is called in both 1639 * the error case in attach and the normal detach case so it needs 1640 * to be careful about only freeing resources that have actually been 1641 * allocated. 1642 */ 1643 static int 1644 re_detach(device_t dev) 1645 { 1646 struct re_softc *sc = device_get_softc(dev); 1647 struct ifnet *ifp = &sc->arpcom.ac_if; 1648 1649 /* These should only be active if attach succeeded */ 1650 if (device_is_attached(dev)) { 1651 lwkt_serialize_enter(ifp->if_serializer); 1652 re_stop(sc); 1653 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1654 lwkt_serialize_exit(ifp->if_serializer); 1655 1656 ether_ifdetach(ifp); 1657 } 1658 if (sc->re_miibus) 1659 device_delete_child(dev, sc->re_miibus); 1660 bus_generic_detach(dev); 1661 1662 if (sc->re_sysctl_tree != NULL) 1663 sysctl_ctx_free(&sc->re_sysctl_ctx); 1664 1665 if (sc->re_irq) 1666 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1667 sc->re_irq); 1668 1669 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1670 pci_release_msi(dev); 1671 1672 if (sc->re_res) { 1673 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1674 sc->re_res); 1675 } 1676 1677 /* Free DMA stuffs */ 1678 re_freemem(dev); 1679 1680 return(0); 1681 } 1682 1683 static void 1684 re_setup_rxdesc(struct re_softc *sc, int idx) 1685 { 1686 bus_addr_t paddr; 1687 uint32_t cmdstat; 1688 struct re_desc *d; 1689 1690 paddr = sc->re_ldata.re_rx_paddr[idx]; 1691 d = &sc->re_ldata.re_rx_list[idx]; 1692 1693 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1694 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1695 1696 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1697 if (idx == (sc->re_rx_desc_cnt - 1)) 1698 cmdstat |= RE_RDESC_CMD_EOR; 1699 d->re_cmdstat = htole32(cmdstat); 1700 } 1701 1702 static int 1703 re_newbuf_std(struct re_softc *sc, int idx, int init) 1704 { 1705 bus_dma_segment_t seg; 1706 bus_dmamap_t map; 1707 struct mbuf *m; 1708 int error, nsegs; 1709 1710 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1711 if (m == NULL) { 1712 error = ENOBUFS; 1713 1714 if (init) { 1715 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1716 return error; 1717 } else { 1718 goto back; 1719 } 1720 } 1721 m->m_len = m->m_pkthdr.len = MCLBYTES; 1722 1723 /* 1724 * NOTE: 1725 * re(4) chips need address of the receive buffer to be 8-byte 1726 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1727 */ 1728 1729 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1730 sc->re_ldata.re_rx_spare, m, 1731 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1732 if (error) { 1733 m_freem(m); 1734 if (init) { 1735 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1736 return error; 1737 } else { 1738 goto back; 1739 } 1740 } 1741 1742 if (!init) { 1743 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1744 sc->re_ldata.re_rx_dmamap[idx], 1745 BUS_DMASYNC_POSTREAD); 1746 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1747 sc->re_ldata.re_rx_dmamap[idx]); 1748 } 1749 sc->re_ldata.re_rx_mbuf[idx] = m; 1750 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1751 1752 map = sc->re_ldata.re_rx_dmamap[idx]; 1753 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1754 sc->re_ldata.re_rx_spare = map; 1755 back: 1756 re_setup_rxdesc(sc, idx); 1757 return error; 1758 } 1759 1760 static int 1761 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1762 { 1763 struct mbuf *m; 1764 struct re_jbuf *jbuf; 1765 int error = 0; 1766 1767 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1768 if (m == NULL) { 1769 error = ENOBUFS; 1770 if (init) { 1771 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1772 return error; 1773 } else { 1774 goto back; 1775 } 1776 } 1777 1778 jbuf = re_jbuf_alloc(sc); 1779 if (jbuf == NULL) { 1780 m_freem(m); 1781 1782 error = ENOBUFS; 1783 if (init) { 1784 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1785 return error; 1786 } else { 1787 goto back; 1788 } 1789 } 1790 1791 m->m_ext.ext_arg = jbuf; 1792 m->m_ext.ext_buf = jbuf->re_buf; 1793 m->m_ext.ext_free = re_jbuf_free; 1794 m->m_ext.ext_ref = re_jbuf_ref; 1795 m->m_ext.ext_size = sc->re_rxbuf_size; 1796 1797 m->m_data = m->m_ext.ext_buf; 1798 m->m_flags |= M_EXT; 1799 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1800 1801 /* 1802 * NOTE: 1803 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1804 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1805 */ 1806 1807 sc->re_ldata.re_rx_mbuf[idx] = m; 1808 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1809 back: 1810 re_setup_rxdesc(sc, idx); 1811 return error; 1812 } 1813 1814 static int 1815 re_tx_list_init(struct re_softc *sc) 1816 { 1817 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1818 1819 sc->re_ldata.re_tx_prodidx = 0; 1820 sc->re_ldata.re_tx_considx = 0; 1821 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1822 1823 return(0); 1824 } 1825 1826 static int 1827 re_rx_list_init(struct re_softc *sc) 1828 { 1829 int i, error; 1830 1831 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1832 1833 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1834 error = sc->re_newbuf(sc, i, 1); 1835 if (error) 1836 return(error); 1837 } 1838 1839 sc->re_ldata.re_rx_prodidx = 0; 1840 sc->re_head = sc->re_tail = NULL; 1841 1842 return(0); 1843 } 1844 1845 #define RE_IP4_PACKET 0x1 1846 #define RE_TCP_PACKET 0x2 1847 #define RE_UDP_PACKET 0x4 1848 1849 static __inline uint8_t 1850 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1851 { 1852 uint8_t packet_type = 0; 1853 1854 if (sc->re_caps & RE_C_MAC2) { 1855 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1856 packet_type |= RE_IP4_PACKET; 1857 } else { 1858 if (rxstat & RE_RDESC_STAT_PROTOID) 1859 packet_type |= RE_IP4_PACKET; 1860 } 1861 if (RE_TCPPKT(rxstat)) 1862 packet_type |= RE_TCP_PACKET; 1863 else if (RE_UDPPKT(rxstat)) 1864 packet_type |= RE_UDP_PACKET; 1865 return packet_type; 1866 } 1867 1868 /* 1869 * RX handler for C+ and 8169. For the gigE chips, we support 1870 * the reception of jumbo frames that have been fragmented 1871 * across multiple 2K mbuf cluster buffers. 1872 */ 1873 static int 1874 re_rxeof(struct re_softc *sc) 1875 { 1876 struct ifnet *ifp = &sc->arpcom.ac_if; 1877 struct mbuf *m; 1878 struct re_desc *cur_rx; 1879 uint32_t rxstat, rxctrl; 1880 int i, total_len, rx = 0; 1881 1882 for (i = sc->re_ldata.re_rx_prodidx; 1883 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1884 cur_rx = &sc->re_ldata.re_rx_list[i]; 1885 m = sc->re_ldata.re_rx_mbuf[i]; 1886 total_len = RE_RXBYTES(cur_rx); 1887 rxstat = le32toh(cur_rx->re_cmdstat); 1888 rxctrl = le32toh(cur_rx->re_control); 1889 1890 rx = 1; 1891 1892 #ifdef INVARIANTS 1893 if (sc->re_flags & RE_F_USE_JPOOL) 1894 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1895 #endif 1896 1897 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1898 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1899 re_setup_rxdesc(sc, i); 1900 continue; 1901 } 1902 1903 if (sc->re_newbuf(sc, i, 0)) { 1904 /* Drop upcoming fragments */ 1905 sc->re_flags |= RE_F_DROP_RXFRAG; 1906 continue; 1907 } 1908 1909 m->m_len = MCLBYTES; 1910 if (sc->re_head == NULL) { 1911 sc->re_head = sc->re_tail = m; 1912 } else { 1913 sc->re_tail->m_next = m; 1914 sc->re_tail = m; 1915 } 1916 continue; 1917 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1918 /* 1919 * Last fragment of a multi-fragment packet. 1920 * 1921 * Since error already happened, this fragment 1922 * must be dropped as well as the fragment chain. 1923 */ 1924 re_setup_rxdesc(sc, i); 1925 re_free_rxchain(sc); 1926 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1927 continue; 1928 } 1929 1930 /* 1931 * NOTE: for the 8139C+, the frame length field 1932 * is always 12 bits in size, but for the gigE chips, 1933 * it is 13 bits (since the max RX frame length is 16K). 1934 * Unfortunately, all 32 bits in the status word 1935 * were already used, so to make room for the extra 1936 * length bit, RealTek took out the 'frame alignment 1937 * error' bit and shifted the other status bits 1938 * over one slot. The OWN, EOR, FS and LS bits are 1939 * still in the same places. We have already extracted 1940 * the frame length and checked the OWN bit, so rather 1941 * than using an alternate bit mapping, we shift the 1942 * status bits one space to the right so we can evaluate 1943 * them using the 8169 status as though it was in the 1944 * same format as that of the 8139C+. 1945 */ 1946 if (!RE_IS_8139CP(sc)) 1947 rxstat >>= 1; 1948 1949 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1950 ifp->if_ierrors++; 1951 /* 1952 * If this is part of a multi-fragment packet, 1953 * discard all the pieces. 1954 */ 1955 re_free_rxchain(sc); 1956 re_setup_rxdesc(sc, i); 1957 continue; 1958 } 1959 1960 /* 1961 * If allocating a replacement mbuf fails, 1962 * reload the current one. 1963 */ 1964 1965 if (sc->re_newbuf(sc, i, 0)) { 1966 ifp->if_ierrors++; 1967 continue; 1968 } 1969 1970 if (sc->re_head != NULL) { 1971 m->m_len = total_len % MCLBYTES; 1972 /* 1973 * Special case: if there's 4 bytes or less 1974 * in this buffer, the mbuf can be discarded: 1975 * the last 4 bytes is the CRC, which we don't 1976 * care about anyway. 1977 */ 1978 if (m->m_len <= ETHER_CRC_LEN) { 1979 sc->re_tail->m_len -= 1980 (ETHER_CRC_LEN - m->m_len); 1981 m_freem(m); 1982 } else { 1983 m->m_len -= ETHER_CRC_LEN; 1984 sc->re_tail->m_next = m; 1985 } 1986 m = sc->re_head; 1987 sc->re_head = sc->re_tail = NULL; 1988 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1989 } else { 1990 m->m_pkthdr.len = m->m_len = 1991 (total_len - ETHER_CRC_LEN); 1992 } 1993 1994 ifp->if_ipackets++; 1995 m->m_pkthdr.rcvif = ifp; 1996 1997 /* Do RX checksumming if enabled */ 1998 1999 if (ifp->if_capenable & IFCAP_RXCSUM) { 2000 uint8_t packet_type; 2001 2002 packet_type = re_packet_type(sc, rxstat, rxctrl); 2003 2004 /* Check IP header checksum */ 2005 if (packet_type & RE_IP4_PACKET) { 2006 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2007 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2008 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2009 } 2010 2011 /* Check TCP/UDP checksum */ 2012 if (((packet_type & RE_TCP_PACKET) && 2013 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2014 ((packet_type & RE_UDP_PACKET) && 2015 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2016 m->m_pkthdr.csum_flags |= 2017 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2018 CSUM_FRAG_NOT_CHECKED; 2019 m->m_pkthdr.csum_data = 0xffff; 2020 } 2021 } 2022 2023 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2024 m->m_flags |= M_VLANTAG; 2025 m->m_pkthdr.ether_vlantag = 2026 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2027 } 2028 ifp->if_input(ifp, m); 2029 } 2030 2031 sc->re_ldata.re_rx_prodidx = i; 2032 2033 return rx; 2034 } 2035 2036 #undef RE_IP4_PACKET 2037 #undef RE_TCP_PACKET 2038 #undef RE_UDP_PACKET 2039 2040 static int 2041 re_tx_collect(struct re_softc *sc) 2042 { 2043 struct ifnet *ifp = &sc->arpcom.ac_if; 2044 uint32_t txstat; 2045 int idx, tx = 0; 2046 2047 for (idx = sc->re_ldata.re_tx_considx; 2048 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2049 RE_TXDESC_INC(sc, idx)) { 2050 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2051 if (txstat & RE_TDESC_CMD_OWN) 2052 break; 2053 2054 tx = 1; 2055 2056 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2057 2058 /* 2059 * We only stash mbufs in the last descriptor 2060 * in a fragment chain, which also happens to 2061 * be the only place where the TX status bits 2062 * are valid. 2063 */ 2064 if (txstat & RE_TDESC_CMD_EOF) { 2065 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2066 sc->re_ldata.re_tx_dmamap[idx]); 2067 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2068 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2069 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2070 RE_TDESC_STAT_COLCNT)) 2071 ifp->if_collisions++; 2072 if (txstat & RE_TDESC_STAT_TXERRSUM) 2073 ifp->if_oerrors++; 2074 else 2075 ifp->if_opackets++; 2076 } 2077 sc->re_ldata.re_tx_free++; 2078 } 2079 sc->re_ldata.re_tx_considx = idx; 2080 2081 return tx; 2082 } 2083 2084 static int 2085 re_txeof(struct re_softc *sc) 2086 { 2087 struct ifnet *ifp = &sc->arpcom.ac_if; 2088 int tx; 2089 2090 tx = re_tx_collect(sc); 2091 2092 /* There is enough free TX descs */ 2093 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2094 ifp->if_flags &= ~IFF_OACTIVE; 2095 2096 /* 2097 * Some chips will ignore a second TX request issued while an 2098 * existing transmission is in progress. If the transmitter goes 2099 * idle but there are still packets waiting to be sent, we need 2100 * to restart the channel here to flush them out. This only seems 2101 * to be required with the PCIe devices. 2102 */ 2103 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2104 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2105 else 2106 ifp->if_timer = 0; 2107 2108 return tx; 2109 } 2110 2111 static void 2112 re_tick(void *xsc) 2113 { 2114 struct re_softc *sc = xsc; 2115 2116 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2117 re_tick_serialized(xsc); 2118 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2119 } 2120 2121 static void 2122 re_tick_serialized(void *xsc) 2123 { 2124 struct re_softc *sc = xsc; 2125 struct ifnet *ifp = &sc->arpcom.ac_if; 2126 struct mii_data *mii; 2127 2128 ASSERT_SERIALIZED(ifp->if_serializer); 2129 2130 mii = device_get_softc(sc->re_miibus); 2131 mii_tick(mii); 2132 if (sc->re_flags & RE_F_LINKED) { 2133 if (!(mii->mii_media_status & IFM_ACTIVE)) 2134 sc->re_flags &= ~RE_F_LINKED; 2135 } else { 2136 if (mii->mii_media_status & IFM_ACTIVE && 2137 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2138 sc->re_flags |= RE_F_LINKED; 2139 if (!ifq_is_empty(&ifp->if_snd)) 2140 if_devstart(ifp); 2141 } 2142 } 2143 2144 callout_reset(&sc->re_timer, hz, re_tick, sc); 2145 } 2146 2147 #ifdef DEVICE_POLLING 2148 2149 static void 2150 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2151 { 2152 struct re_softc *sc = ifp->if_softc; 2153 2154 ASSERT_SERIALIZED(ifp->if_serializer); 2155 2156 switch(cmd) { 2157 case POLL_REGISTER: 2158 /* disable interrupts */ 2159 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2160 break; 2161 2162 case POLL_DEREGISTER: 2163 /* enable interrupts */ 2164 re_setup_intr(sc, 1, sc->re_imtype); 2165 break; 2166 2167 default: 2168 sc->rxcycles = count; 2169 re_rxeof(sc); 2170 re_txeof(sc); 2171 2172 if (!ifq_is_empty(&ifp->if_snd)) 2173 if_devstart(ifp); 2174 2175 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2176 uint16_t status; 2177 2178 status = CSR_READ_2(sc, RE_ISR); 2179 if (status == 0xffff) 2180 return; 2181 if (status) 2182 CSR_WRITE_2(sc, RE_ISR, status); 2183 2184 /* 2185 * XXX check behaviour on receiver stalls. 2186 */ 2187 2188 if (status & RE_ISR_SYSTEM_ERR) 2189 re_init(sc); 2190 } 2191 break; 2192 } 2193 } 2194 #endif /* DEVICE_POLLING */ 2195 2196 static void 2197 re_intr(void *arg) 2198 { 2199 struct re_softc *sc = arg; 2200 struct ifnet *ifp = &sc->arpcom.ac_if; 2201 uint16_t status; 2202 int rx, tx; 2203 2204 ASSERT_SERIALIZED(ifp->if_serializer); 2205 2206 if ((sc->re_flags & RE_F_SUSPENDED) || 2207 (ifp->if_flags & IFF_RUNNING) == 0) 2208 return; 2209 2210 rx = tx = 0; 2211 for (;;) { 2212 status = CSR_READ_2(sc, RE_ISR); 2213 /* If the card has gone away the read returns 0xffff. */ 2214 if (status == 0xffff) 2215 break; 2216 if (status) 2217 CSR_WRITE_2(sc, RE_ISR, status); 2218 2219 if ((status & sc->re_intrs) == 0) 2220 break; 2221 2222 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2223 rx |= re_rxeof(sc); 2224 2225 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2226 tx |= re_txeof(sc); 2227 2228 if (status & RE_ISR_SYSTEM_ERR) 2229 re_init(sc); 2230 2231 if (status & RE_ISR_LINKCHG) { 2232 callout_stop(&sc->re_timer); 2233 re_tick_serialized(sc); 2234 } 2235 } 2236 2237 if (sc->re_imtype == RE_IMTYPE_SIM) { 2238 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2239 if ((tx | rx) == 0) { 2240 /* 2241 * Nothing needs to be processed, fallback 2242 * to use TX/RX interrupts. 2243 */ 2244 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2245 2246 /* 2247 * Recollect, mainly to avoid the possible 2248 * race introduced by changing interrupt 2249 * masks. 2250 */ 2251 re_rxeof(sc); 2252 tx = re_txeof(sc); 2253 } else { 2254 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2255 } 2256 } else if (tx | rx) { 2257 /* 2258 * Assume that using simulated interrupt moderation 2259 * (hardware timer based) could reduce the interript 2260 * rate. 2261 */ 2262 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2263 } 2264 } 2265 2266 if (tx && !ifq_is_empty(&ifp->if_snd)) 2267 if_devstart(ifp); 2268 } 2269 2270 static int 2271 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2272 { 2273 struct mbuf *m = *m_head; 2274 bus_dma_segment_t segs[RE_MAXSEGS]; 2275 bus_dmamap_t map; 2276 int error, maxsegs, idx, i, nsegs; 2277 struct re_desc *d, *tx_ring; 2278 uint32_t cmd_csum, ctl_csum, vlantag; 2279 2280 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2281 ("not enough free TX desc")); 2282 2283 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2284 2285 /* 2286 * Set up checksum offload. Note: checksum offload bits must 2287 * appear in all descriptors of a multi-descriptor transmit 2288 * attempt. (This is according to testing done with an 8169 2289 * chip. I'm not sure if this is a requirement or a bug.) 2290 */ 2291 cmd_csum = ctl_csum = 0; 2292 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2293 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2294 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2295 } 2296 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2297 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2298 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2299 } 2300 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2301 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2302 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2303 } 2304 2305 /* For MAC2 chips, csum flags are set on re_control */ 2306 if (sc->re_caps & RE_C_MAC2) 2307 cmd_csum = 0; 2308 else 2309 ctl_csum = 0; 2310 2311 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2312 /* 2313 * With some of the RealTek chips, using the checksum offload 2314 * support in conjunction with the autopadding feature results 2315 * in the transmission of corrupt frames. For example, if we 2316 * need to send a really small IP fragment that's less than 60 2317 * bytes in size, and IP header checksumming is enabled, the 2318 * resulting ethernet frame that appears on the wire will 2319 * have garbled payload. To work around this, if TX checksum 2320 * offload is enabled, we always manually pad short frames out 2321 * to the minimum ethernet frame size. 2322 * 2323 * Note: this appears unnecessary for TCP, and doing it for TCP 2324 * with PCIe adapters seems to result in bad checksums. 2325 */ 2326 if ((m->m_pkthdr.csum_flags & 2327 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2328 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2329 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2330 error = m_devpad(m, RE_MIN_FRAMELEN); 2331 if (error) 2332 goto back; 2333 } 2334 } 2335 2336 vlantag = 0; 2337 if (m->m_flags & M_VLANTAG) { 2338 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2339 RE_TDESC_CTL_INSTAG; 2340 } 2341 2342 maxsegs = sc->re_ldata.re_tx_free; 2343 if (maxsegs > RE_MAXSEGS) 2344 maxsegs = RE_MAXSEGS; 2345 2346 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2347 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2348 if (error) 2349 goto back; 2350 2351 m = *m_head; 2352 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2353 2354 /* 2355 * Map the segment array into descriptors. We also keep track 2356 * of the end of the ring and set the end-of-ring bits as needed, 2357 * and we set the ownership bits in all except the very first 2358 * descriptor, whose ownership bits will be turned on later. 2359 */ 2360 tx_ring = sc->re_ldata.re_tx_list; 2361 idx = *idx0; 2362 i = 0; 2363 for (;;) { 2364 uint32_t cmdstat; 2365 2366 d = &tx_ring[idx]; 2367 2368 cmdstat = segs[i].ds_len; 2369 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2370 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2371 if (i == 0) 2372 cmdstat |= RE_TDESC_CMD_SOF; 2373 else 2374 cmdstat |= RE_TDESC_CMD_OWN; 2375 if (idx == (sc->re_tx_desc_cnt - 1)) 2376 cmdstat |= RE_TDESC_CMD_EOR; 2377 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2378 d->re_control = htole32(ctl_csum | vlantag); 2379 2380 i++; 2381 if (i == nsegs) 2382 break; 2383 RE_TXDESC_INC(sc, idx); 2384 } 2385 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2386 2387 /* Transfer ownership of packet to the chip. */ 2388 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2389 if (*idx0 != idx) 2390 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2391 2392 /* 2393 * Insure that the map for this transmission 2394 * is placed at the array index of the last descriptor 2395 * in this chain. 2396 */ 2397 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2398 sc->re_ldata.re_tx_dmamap[idx] = map; 2399 2400 sc->re_ldata.re_tx_mbuf[idx] = m; 2401 sc->re_ldata.re_tx_free -= nsegs; 2402 2403 RE_TXDESC_INC(sc, idx); 2404 *idx0 = idx; 2405 back: 2406 if (error) { 2407 m_freem(*m_head); 2408 *m_head = NULL; 2409 } 2410 return error; 2411 } 2412 2413 /* 2414 * Main transmit routine for C+ and gigE NICs. 2415 */ 2416 2417 static void 2418 re_start(struct ifnet *ifp) 2419 { 2420 struct re_softc *sc = ifp->if_softc; 2421 struct mbuf *m_head; 2422 int idx, need_trans, oactive, error; 2423 2424 ASSERT_SERIALIZED(ifp->if_serializer); 2425 2426 if ((sc->re_flags & RE_F_LINKED) == 0) { 2427 ifq_purge(&ifp->if_snd); 2428 return; 2429 } 2430 2431 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2432 return; 2433 2434 idx = sc->re_ldata.re_tx_prodidx; 2435 2436 need_trans = 0; 2437 oactive = 0; 2438 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2439 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2440 if (!oactive) { 2441 if (re_tx_collect(sc)) { 2442 oactive = 1; 2443 continue; 2444 } 2445 } 2446 ifp->if_flags |= IFF_OACTIVE; 2447 break; 2448 } 2449 2450 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2451 if (m_head == NULL) 2452 break; 2453 2454 error = re_encap(sc, &m_head, &idx); 2455 if (error) { 2456 /* m_head is freed by re_encap(), if we reach here */ 2457 ifp->if_oerrors++; 2458 2459 if (error == EFBIG && !oactive) { 2460 if (re_tx_collect(sc)) { 2461 oactive = 1; 2462 continue; 2463 } 2464 } 2465 ifp->if_flags |= IFF_OACTIVE; 2466 break; 2467 } 2468 2469 oactive = 0; 2470 need_trans = 1; 2471 2472 /* 2473 * If there's a BPF listener, bounce a copy of this frame 2474 * to him. 2475 */ 2476 ETHER_BPF_MTAP(ifp, m_head); 2477 } 2478 2479 /* 2480 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2481 * for IFF_OACTIVE to not be properly set when we also do not 2482 * have sufficient free tx descriptors, leaving packet in 2483 * ifp->if_send. This can cause if_start_dispatch() to loop 2484 * infinitely so make sure IFF_OACTIVE is set properly. 2485 */ 2486 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2487 if ((ifp->if_flags & IFF_OACTIVE) == 0) { 2488 device_printf(sc->re_dev, 2489 "Debug: IFF_OACTIVE was not set when" 2490 " re_tx_free was below minimum!\n"); 2491 ifp->if_flags |= IFF_OACTIVE; 2492 } 2493 } 2494 if (!need_trans) 2495 return; 2496 2497 sc->re_ldata.re_tx_prodidx = idx; 2498 2499 /* 2500 * RealTek put the TX poll request register in a different 2501 * location on the 8169 gigE chip. I don't know why. 2502 */ 2503 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2504 2505 /* 2506 * Set a timeout in case the chip goes out to lunch. 2507 */ 2508 ifp->if_timer = 5; 2509 } 2510 2511 static void 2512 re_init(void *xsc) 2513 { 2514 struct re_softc *sc = xsc; 2515 struct ifnet *ifp = &sc->arpcom.ac_if; 2516 struct mii_data *mii; 2517 int error, framelen; 2518 2519 ASSERT_SERIALIZED(ifp->if_serializer); 2520 2521 mii = device_get_softc(sc->re_miibus); 2522 2523 /* 2524 * Cancel pending I/O and free all RX/TX buffers. 2525 */ 2526 re_stop(sc); 2527 2528 if (sc->re_caps & RE_C_CONTIGRX) { 2529 if (ifp->if_mtu > ETHERMTU) { 2530 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2531 sc->re_flags |= RE_F_USE_JPOOL; 2532 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2533 sc->re_newbuf = re_newbuf_jumbo; 2534 } else { 2535 sc->re_flags &= ~RE_F_USE_JPOOL; 2536 sc->re_rxbuf_size = MCLBYTES; 2537 sc->re_newbuf = re_newbuf_std; 2538 } 2539 } 2540 2541 /* 2542 * Adjust max read request size according to MTU; mainly to 2543 * improve TX performance for common case (ETHERMTU) on GigE 2544 * NICs. However, this could _not_ be done on 10/100 only 2545 * NICs; their DMA engines will malfunction using non-default 2546 * max read request size. 2547 */ 2548 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2549 if (ifp->if_mtu > ETHERMTU) { 2550 /* 2551 * 512 seems to be the only value that works 2552 * reliably with jumbo frame 2553 */ 2554 pcie_set_max_readrq(sc->re_dev, 2555 PCIEM_DEVCTL_MAX_READRQ_512); 2556 } else { 2557 pcie_set_max_readrq(sc->re_dev, 2558 PCIEM_DEVCTL_MAX_READRQ_4096); 2559 } 2560 } 2561 2562 /* 2563 * Enable C+ RX and TX mode, as well as VLAN stripping and 2564 * RX checksum offload. We must configure the C+ register 2565 * before all others. 2566 */ 2567 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2568 RE_CPLUSCMD_PCI_MRW | 2569 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2570 RE_CPLUSCMD_VLANSTRIP : 0) | 2571 (ifp->if_capenable & IFCAP_RXCSUM ? 2572 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2573 2574 /* 2575 * Init our MAC address. Even though the chipset 2576 * documentation doesn't mention it, we need to enter "Config 2577 * register write enable" mode to modify the ID registers. 2578 */ 2579 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2580 CSR_WRITE_4(sc, RE_IDR0, 2581 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2582 CSR_WRITE_2(sc, RE_IDR4, 2583 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2584 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2585 2586 /* 2587 * For C+ mode, initialize the RX descriptors and mbufs. 2588 */ 2589 error = re_rx_list_init(sc); 2590 if (error) { 2591 re_stop(sc); 2592 return; 2593 } 2594 error = re_tx_list_init(sc); 2595 if (error) { 2596 re_stop(sc); 2597 return; 2598 } 2599 2600 /* 2601 * Load the addresses of the RX and TX lists into the chip. 2602 */ 2603 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2604 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2605 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2606 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2607 2608 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2609 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2610 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2611 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2612 2613 /* 2614 * Enable transmit and receive. 2615 */ 2616 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2617 2618 /* 2619 * Set the initial TX and RX configuration. 2620 */ 2621 if (sc->re_flags & RE_F_TESTMODE) { 2622 if (!RE_IS_8139CP(sc)) 2623 CSR_WRITE_4(sc, RE_TXCFG, 2624 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2625 else 2626 CSR_WRITE_4(sc, RE_TXCFG, 2627 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2628 } else 2629 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2630 2631 framelen = RE_FRAMELEN(ifp->if_mtu); 2632 if (framelen < MCLBYTES) 2633 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2634 else 2635 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2636 2637 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2638 2639 /* 2640 * Program the multicast filter, if necessary. 2641 */ 2642 re_setmulti(sc); 2643 2644 #ifdef DEVICE_POLLING 2645 /* 2646 * Disable interrupts if we are polling. 2647 */ 2648 if (ifp->if_flags & IFF_POLLING) 2649 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2650 else /* otherwise ... */ 2651 #endif /* DEVICE_POLLING */ 2652 /* 2653 * Enable interrupts. 2654 */ 2655 if (sc->re_flags & RE_F_TESTMODE) 2656 CSR_WRITE_2(sc, RE_IMR, 0); 2657 else 2658 re_setup_intr(sc, 1, sc->re_imtype); 2659 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2660 2661 /* Start RX/TX process. */ 2662 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2663 2664 #ifdef notdef 2665 /* Enable receiver and transmitter. */ 2666 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2667 #endif 2668 2669 /* 2670 * For 8169 gigE NICs, set the max allowed RX packet 2671 * size so we can receive jumbo frames. 2672 */ 2673 if (!RE_IS_8139CP(sc)) { 2674 if (sc->re_caps & RE_C_CONTIGRX) 2675 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2676 else 2677 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2678 } 2679 2680 if (sc->re_flags & RE_F_TESTMODE) 2681 return; 2682 2683 mii_mediachg(mii); 2684 2685 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2686 2687 ifp->if_flags |= IFF_RUNNING; 2688 ifp->if_flags &= ~IFF_OACTIVE; 2689 2690 callout_reset(&sc->re_timer, hz, re_tick, sc); 2691 } 2692 2693 /* 2694 * Set media options. 2695 */ 2696 static int 2697 re_ifmedia_upd(struct ifnet *ifp) 2698 { 2699 struct re_softc *sc = ifp->if_softc; 2700 struct mii_data *mii; 2701 2702 ASSERT_SERIALIZED(ifp->if_serializer); 2703 2704 mii = device_get_softc(sc->re_miibus); 2705 mii_mediachg(mii); 2706 2707 return(0); 2708 } 2709 2710 /* 2711 * Report current media status. 2712 */ 2713 static void 2714 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2715 { 2716 struct re_softc *sc = ifp->if_softc; 2717 struct mii_data *mii; 2718 2719 ASSERT_SERIALIZED(ifp->if_serializer); 2720 2721 mii = device_get_softc(sc->re_miibus); 2722 2723 mii_pollstat(mii); 2724 ifmr->ifm_active = mii->mii_media_active; 2725 ifmr->ifm_status = mii->mii_media_status; 2726 } 2727 2728 static int 2729 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2730 { 2731 struct re_softc *sc = ifp->if_softc; 2732 struct ifreq *ifr = (struct ifreq *) data; 2733 struct mii_data *mii; 2734 int error = 0, mask; 2735 2736 ASSERT_SERIALIZED(ifp->if_serializer); 2737 2738 switch(command) { 2739 case SIOCSIFMTU: 2740 if (ifr->ifr_mtu > sc->re_maxmtu) { 2741 error = EINVAL; 2742 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2743 ifp->if_mtu = ifr->ifr_mtu; 2744 if (ifp->if_flags & IFF_RUNNING) 2745 ifp->if_init(sc); 2746 } 2747 break; 2748 2749 case SIOCSIFFLAGS: 2750 if (ifp->if_flags & IFF_UP) { 2751 if (ifp->if_flags & IFF_RUNNING) { 2752 if ((ifp->if_flags ^ sc->re_if_flags) & 2753 (IFF_PROMISC | IFF_ALLMULTI)) 2754 re_setmulti(sc); 2755 } else { 2756 re_init(sc); 2757 } 2758 } else if (ifp->if_flags & IFF_RUNNING) { 2759 re_stop(sc); 2760 } 2761 sc->re_if_flags = ifp->if_flags; 2762 break; 2763 2764 case SIOCADDMULTI: 2765 case SIOCDELMULTI: 2766 re_setmulti(sc); 2767 break; 2768 2769 case SIOCGIFMEDIA: 2770 case SIOCSIFMEDIA: 2771 mii = device_get_softc(sc->re_miibus); 2772 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2773 break; 2774 2775 case SIOCSIFCAP: 2776 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2777 ifp->if_capabilities; 2778 ifp->if_capenable ^= mask; 2779 2780 if (mask & IFCAP_HWCSUM) { 2781 if (ifp->if_capenable & IFCAP_TXCSUM) 2782 ifp->if_hwassist = RE_CSUM_FEATURES; 2783 else 2784 ifp->if_hwassist = 0; 2785 } 2786 if (mask && (ifp->if_flags & IFF_RUNNING)) 2787 re_init(sc); 2788 break; 2789 2790 default: 2791 error = ether_ioctl(ifp, command, data); 2792 break; 2793 } 2794 return(error); 2795 } 2796 2797 static void 2798 re_watchdog(struct ifnet *ifp) 2799 { 2800 struct re_softc *sc = ifp->if_softc; 2801 2802 ASSERT_SERIALIZED(ifp->if_serializer); 2803 2804 if_printf(ifp, "watchdog timeout\n"); 2805 2806 ifp->if_oerrors++; 2807 2808 re_txeof(sc); 2809 re_rxeof(sc); 2810 2811 re_init(sc); 2812 2813 if (!ifq_is_empty(&ifp->if_snd)) 2814 if_devstart(ifp); 2815 } 2816 2817 /* 2818 * Stop the adapter and free any mbufs allocated to the 2819 * RX and TX lists. 2820 */ 2821 static void 2822 re_stop(struct re_softc *sc) 2823 { 2824 struct ifnet *ifp = &sc->arpcom.ac_if; 2825 int i; 2826 2827 ASSERT_SERIALIZED(ifp->if_serializer); 2828 2829 /* Reset the adapter. */ 2830 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2831 2832 ifp->if_timer = 0; 2833 callout_stop(&sc->re_timer); 2834 2835 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2836 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2837 2838 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2839 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2840 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2841 2842 re_free_rxchain(sc); 2843 2844 /* Free the TX list buffers. */ 2845 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2846 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2847 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2848 sc->re_ldata.re_tx_dmamap[i]); 2849 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2850 sc->re_ldata.re_tx_mbuf[i] = NULL; 2851 } 2852 } 2853 2854 /* Free the RX list buffers. */ 2855 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2856 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2857 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2858 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2859 sc->re_ldata.re_rx_dmamap[i]); 2860 } 2861 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2862 sc->re_ldata.re_rx_mbuf[i] = NULL; 2863 } 2864 } 2865 } 2866 2867 /* 2868 * Device suspend routine. Stop the interface and save some PCI 2869 * settings in case the BIOS doesn't restore them properly on 2870 * resume. 2871 */ 2872 static int 2873 re_suspend(device_t dev) 2874 { 2875 #ifndef BURN_BRIDGES 2876 int i; 2877 #endif 2878 struct re_softc *sc = device_get_softc(dev); 2879 struct ifnet *ifp = &sc->arpcom.ac_if; 2880 2881 lwkt_serialize_enter(ifp->if_serializer); 2882 2883 re_stop(sc); 2884 2885 #ifndef BURN_BRIDGES 2886 for (i = 0; i < 5; i++) 2887 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2888 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2889 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2890 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2891 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2892 #endif 2893 2894 sc->re_flags |= RE_F_SUSPENDED; 2895 2896 lwkt_serialize_exit(ifp->if_serializer); 2897 2898 return (0); 2899 } 2900 2901 /* 2902 * Device resume routine. Restore some PCI settings in case the BIOS 2903 * doesn't, re-enable busmastering, and restart the interface if 2904 * appropriate. 2905 */ 2906 static int 2907 re_resume(device_t dev) 2908 { 2909 struct re_softc *sc = device_get_softc(dev); 2910 struct ifnet *ifp = &sc->arpcom.ac_if; 2911 #ifndef BURN_BRIDGES 2912 int i; 2913 #endif 2914 2915 lwkt_serialize_enter(ifp->if_serializer); 2916 2917 #ifndef BURN_BRIDGES 2918 /* better way to do this? */ 2919 for (i = 0; i < 5; i++) 2920 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2921 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2922 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2923 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2924 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2925 2926 /* reenable busmastering */ 2927 pci_enable_busmaster(dev); 2928 pci_enable_io(dev, SYS_RES_IOPORT); 2929 #endif 2930 2931 /* reinitialize interface if necessary */ 2932 if (ifp->if_flags & IFF_UP) 2933 re_init(sc); 2934 2935 sc->re_flags &= ~RE_F_SUSPENDED; 2936 2937 lwkt_serialize_exit(ifp->if_serializer); 2938 2939 return (0); 2940 } 2941 2942 /* 2943 * Stop all chip I/O so that the kernel's probe routines don't 2944 * get confused by errant DMAs when rebooting. 2945 */ 2946 static void 2947 re_shutdown(device_t dev) 2948 { 2949 struct re_softc *sc = device_get_softc(dev); 2950 struct ifnet *ifp = &sc->arpcom.ac_if; 2951 2952 lwkt_serialize_enter(ifp->if_serializer); 2953 re_stop(sc); 2954 lwkt_serialize_exit(ifp->if_serializer); 2955 } 2956 2957 static int 2958 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 2959 { 2960 struct re_softc *sc = arg1; 2961 2962 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 2963 } 2964 2965 static int 2966 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 2967 { 2968 struct re_softc *sc = arg1; 2969 2970 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 2971 } 2972 2973 static int 2974 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 2975 { 2976 struct re_softc *sc = arg1; 2977 struct ifnet *ifp = &sc->arpcom.ac_if; 2978 int error, v; 2979 2980 lwkt_serialize_enter(ifp->if_serializer); 2981 2982 v = *hwtime; 2983 error = sysctl_handle_int(oidp, &v, 0, req); 2984 if (error || req->newptr == NULL) 2985 goto back; 2986 2987 if (v <= 0) { 2988 error = EINVAL; 2989 goto back; 2990 } 2991 2992 if (v != *hwtime) { 2993 *hwtime = v; 2994 2995 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 2996 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 2997 re_setup_hw_im(sc); 2998 } 2999 back: 3000 lwkt_serialize_exit(ifp->if_serializer); 3001 return error; 3002 } 3003 3004 static int 3005 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3006 { 3007 struct re_softc *sc = arg1; 3008 struct ifnet *ifp = &sc->arpcom.ac_if; 3009 int error, v; 3010 3011 lwkt_serialize_enter(ifp->if_serializer); 3012 3013 v = sc->re_sim_time; 3014 error = sysctl_handle_int(oidp, &v, 0, req); 3015 if (error || req->newptr == NULL) 3016 goto back; 3017 3018 if (v <= 0) { 3019 error = EINVAL; 3020 goto back; 3021 } 3022 3023 if (v != sc->re_sim_time) { 3024 sc->re_sim_time = v; 3025 3026 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3027 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3028 #ifdef foo 3029 int reg; 3030 3031 /* 3032 * Following code causes various strange 3033 * performance problems. Hmm ... 3034 */ 3035 CSR_WRITE_2(sc, RE_IMR, 0); 3036 if (!RE_IS_8139CP(sc)) 3037 reg = RE_TIMERINT_8169; 3038 else 3039 reg = RE_TIMERINT; 3040 CSR_WRITE_4(sc, reg, 0); 3041 CSR_READ_4(sc, reg); /* flush */ 3042 3043 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3044 re_setup_sim_im(sc); 3045 #else 3046 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3047 DELAY(10); 3048 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3049 #endif 3050 } 3051 } 3052 back: 3053 lwkt_serialize_exit(ifp->if_serializer); 3054 return error; 3055 } 3056 3057 static int 3058 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3059 { 3060 struct re_softc *sc = arg1; 3061 struct ifnet *ifp = &sc->arpcom.ac_if; 3062 int error, v; 3063 3064 lwkt_serialize_enter(ifp->if_serializer); 3065 3066 v = sc->re_imtype; 3067 error = sysctl_handle_int(oidp, &v, 0, req); 3068 if (error || req->newptr == NULL) 3069 goto back; 3070 3071 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3072 error = EINVAL; 3073 goto back; 3074 } 3075 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3076 /* Can't do hardware interrupt moderation */ 3077 error = EOPNOTSUPP; 3078 goto back; 3079 } 3080 3081 if (v != sc->re_imtype) { 3082 sc->re_imtype = v; 3083 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3084 IFF_RUNNING) 3085 re_setup_intr(sc, 1, sc->re_imtype); 3086 } 3087 back: 3088 lwkt_serialize_exit(ifp->if_serializer); 3089 return error; 3090 } 3091 3092 static void 3093 re_setup_hw_im(struct re_softc *sc) 3094 { 3095 KKASSERT(sc->re_caps & RE_C_HWIM); 3096 3097 /* 3098 * Interrupt moderation 3099 * 3100 * 0xABCD 3101 * A - unknown (maybe TX related) 3102 * B - TX timer (unit: 25us) 3103 * C - unknown (maybe RX related) 3104 * D - RX timer (unit: 25us) 3105 * 3106 * 3107 * re(4)'s interrupt moderation is actually controlled by 3108 * two variables, like most other NICs (bge, bce etc.) 3109 * o timer 3110 * o number of packets [P] 3111 * 3112 * The logic relationship between these two variables is 3113 * similar to other NICs too: 3114 * if (timer expire || packets > [P]) 3115 * Interrupt is delivered 3116 * 3117 * Currently we only know how to set 'timer', but not 3118 * 'number of packets', which should be ~30, as far as I 3119 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3120 */ 3121 CSR_WRITE_2(sc, RE_IM, 3122 RE_IM_RXTIME(sc->re_rx_time) | 3123 RE_IM_TXTIME(sc->re_tx_time) | 3124 RE_IM_MAGIC); 3125 } 3126 3127 static void 3128 re_disable_hw_im(struct re_softc *sc) 3129 { 3130 if (sc->re_caps & RE_C_HWIM) 3131 CSR_WRITE_2(sc, RE_IM, 0); 3132 } 3133 3134 static void 3135 re_setup_sim_im(struct re_softc *sc) 3136 { 3137 if (!RE_IS_8139CP(sc)) { 3138 uint32_t ticks; 3139 3140 /* 3141 * Datasheet says tick decreases at bus speed, 3142 * but it seems the clock runs a little bit 3143 * faster, so we do some compensation here. 3144 */ 3145 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3146 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3147 } else { 3148 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3149 } 3150 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3151 sc->re_flags |= RE_F_TIMER_INTR; 3152 } 3153 3154 static void 3155 re_disable_sim_im(struct re_softc *sc) 3156 { 3157 if (!RE_IS_8139CP(sc)) 3158 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3159 else 3160 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3161 sc->re_flags &= ~RE_F_TIMER_INTR; 3162 } 3163 3164 static void 3165 re_config_imtype(struct re_softc *sc, int imtype) 3166 { 3167 switch (imtype) { 3168 case RE_IMTYPE_HW: 3169 KKASSERT(sc->re_caps & RE_C_HWIM); 3170 /* FALL THROUGH */ 3171 case RE_IMTYPE_NONE: 3172 sc->re_intrs = RE_INTRS; 3173 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3174 RE_ISR_RX_OVERRUN; 3175 sc->re_tx_ack = RE_ISR_TX_OK; 3176 break; 3177 3178 case RE_IMTYPE_SIM: 3179 sc->re_intrs = RE_INTRS_TIMER; 3180 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3181 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3182 break; 3183 3184 default: 3185 panic("%s: unknown imtype %d", 3186 sc->arpcom.ac_if.if_xname, imtype); 3187 } 3188 } 3189 3190 static void 3191 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3192 { 3193 re_config_imtype(sc, imtype); 3194 3195 if (enable_intrs) 3196 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3197 else 3198 CSR_WRITE_2(sc, RE_IMR, 0); 3199 3200 switch (imtype) { 3201 case RE_IMTYPE_NONE: 3202 re_disable_sim_im(sc); 3203 re_disable_hw_im(sc); 3204 break; 3205 3206 case RE_IMTYPE_HW: 3207 KKASSERT(sc->re_caps & RE_C_HWIM); 3208 re_disable_sim_im(sc); 3209 re_setup_hw_im(sc); 3210 break; 3211 3212 case RE_IMTYPE_SIM: 3213 re_disable_hw_im(sc); 3214 re_setup_sim_im(sc); 3215 break; 3216 3217 default: 3218 panic("%s: unknown imtype %d", 3219 sc->arpcom.ac_if.if_xname, imtype); 3220 } 3221 } 3222 3223 static void 3224 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3225 { 3226 int i; 3227 3228 if (sc->re_macver == RE_MACVER_11 || 3229 sc->re_macver == RE_MACVER_12 || 3230 sc->re_macver == RE_MACVER_30 || 3231 sc->re_macver == RE_MACVER_31) { 3232 uint16_t re_did; 3233 3234 re_get_eewidth(sc); 3235 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3236 if (re_did == 0x8128) { 3237 uint16_t as[ETHER_ADDR_LEN / 2]; 3238 int eaddr_off; 3239 3240 if (sc->re_macver == RE_MACVER_30 || 3241 sc->re_macver == RE_MACVER_31) 3242 eaddr_off = RE_EE_EADDR1; 3243 else 3244 eaddr_off = RE_EE_EADDR0; 3245 3246 /* 3247 * Get station address from the EEPROM. 3248 */ 3249 re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3); 3250 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3251 as[i] = le16toh(as[i]); 3252 bcopy(as, eaddr, ETHER_ADDR_LEN); 3253 return; 3254 } 3255 } 3256 3257 /* 3258 * Get station address from IDRx. 3259 */ 3260 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3261 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3262 } 3263 3264 static int 3265 re_jpool_alloc(struct re_softc *sc) 3266 { 3267 struct re_list_data *ldata = &sc->re_ldata; 3268 struct re_jbuf *jbuf; 3269 bus_addr_t paddr; 3270 bus_size_t jpool_size; 3271 bus_dmamem_t dmem; 3272 caddr_t buf; 3273 int i, error; 3274 3275 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3276 3277 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3278 M_DEVBUF, M_WAITOK | M_ZERO); 3279 3280 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3281 3282 error = bus_dmamem_coherent(sc->re_parent_tag, 3283 RE_RXBUF_ALIGN, 0, 3284 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3285 jpool_size, BUS_DMA_WAITOK, &dmem); 3286 if (error) { 3287 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3288 return error; 3289 } 3290 ldata->re_jpool_tag = dmem.dmem_tag; 3291 ldata->re_jpool_map = dmem.dmem_map; 3292 ldata->re_jpool = dmem.dmem_addr; 3293 paddr = dmem.dmem_busaddr; 3294 3295 /* ..and split it into 9KB chunks */ 3296 SLIST_INIT(&ldata->re_jbuf_free); 3297 3298 buf = ldata->re_jpool; 3299 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3300 jbuf = &ldata->re_jbuf[i]; 3301 3302 jbuf->re_sc = sc; 3303 jbuf->re_inuse = 0; 3304 jbuf->re_slot = i; 3305 jbuf->re_buf = buf; 3306 jbuf->re_paddr = paddr; 3307 3308 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3309 3310 buf += RE_JBUF_SIZE; 3311 paddr += RE_JBUF_SIZE; 3312 } 3313 return 0; 3314 } 3315 3316 static void 3317 re_jpool_free(struct re_softc *sc) 3318 { 3319 struct re_list_data *ldata = &sc->re_ldata; 3320 3321 if (ldata->re_jpool_tag != NULL) { 3322 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3323 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3324 ldata->re_jpool_map); 3325 bus_dma_tag_destroy(ldata->re_jpool_tag); 3326 ldata->re_jpool_tag = NULL; 3327 } 3328 3329 if (ldata->re_jbuf != NULL) { 3330 kfree(ldata->re_jbuf, M_DEVBUF); 3331 ldata->re_jbuf = NULL; 3332 } 3333 } 3334 3335 static struct re_jbuf * 3336 re_jbuf_alloc(struct re_softc *sc) 3337 { 3338 struct re_list_data *ldata = &sc->re_ldata; 3339 struct re_jbuf *jbuf; 3340 3341 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3342 3343 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3344 if (jbuf != NULL) { 3345 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3346 jbuf->re_inuse = 1; 3347 } 3348 3349 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3350 3351 return jbuf; 3352 } 3353 3354 static void 3355 re_jbuf_free(void *arg) 3356 { 3357 struct re_jbuf *jbuf = arg; 3358 struct re_softc *sc = jbuf->re_sc; 3359 struct re_list_data *ldata = &sc->re_ldata; 3360 3361 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3362 panic("%s: free wrong jumbo buffer", 3363 sc->arpcom.ac_if.if_xname); 3364 } else if (jbuf->re_inuse == 0) { 3365 panic("%s: jumbo buffer already freed", 3366 sc->arpcom.ac_if.if_xname); 3367 } 3368 3369 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3370 atomic_subtract_int(&jbuf->re_inuse, 1); 3371 if (jbuf->re_inuse == 0) 3372 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3373 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3374 } 3375 3376 static void 3377 re_jbuf_ref(void *arg) 3378 { 3379 struct re_jbuf *jbuf = arg; 3380 struct re_softc *sc = jbuf->re_sc; 3381 struct re_list_data *ldata = &sc->re_ldata; 3382 3383 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3384 panic("%s: ref wrong jumbo buffer", 3385 sc->arpcom.ac_if.if_xname); 3386 } else if (jbuf->re_inuse == 0) { 3387 panic("%s: jumbo buffer already freed", 3388 sc->arpcom.ac_if.if_xname); 3389 } 3390 atomic_add_int(&jbuf->re_inuse, 1); 3391 } 3392