1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.12 2005/05/25 01:44:27 dillon Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include <sys/param.h> 115 #include <sys/endian.h> 116 #include <sys/systm.h> 117 #include <sys/sockio.h> 118 #include <sys/mbuf.h> 119 #include <sys/malloc.h> 120 #include <sys/module.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 124 #include <net/if.h> 125 #include <net/ifq_var.h> 126 #include <net/if_arp.h> 127 #include <net/ethernet.h> 128 #include <net/if_dl.h> 129 #include <net/if_media.h> 130 #include <net/if_types.h> 131 #include <net/vlan/if_vlan_var.h> 132 133 #include <net/bpf.h> 134 135 #include <machine/bus_pio.h> 136 #include <machine/bus_memio.h> 137 #include <machine/bus.h> 138 #include <machine/resource.h> 139 #include <sys/bus.h> 140 #include <sys/rman.h> 141 142 #include <dev/netif/mii_layer/mii.h> 143 #include <dev/netif/mii_layer/miivar.h> 144 145 #include <bus/pci/pcireg.h> 146 #include <bus/pci/pcivar.h> 147 148 /* "controller miibus0" required. See GENERIC if you get errors here. */ 149 #include "miibus_if.h" 150 151 #include <dev/netif/re/if_rereg.h> 152 153 /* 154 * The hardware supports checksumming but, as usual, some chipsets screw it 155 * all up and produce bogus packets, so we disable it by default. 156 */ 157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #define RE_DISABLE_HWCSUM 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static struct re_type re_devs[] = { 164 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS, 165 "RealTek 8139C+ 10/100BaseTX" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169, 167 "RealTek 8169 Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S, 169 "RealTek 8169S Single-chip Gigabit Ethernet" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S, 171 "RealTek 8110S Single-chip Gigabit Ethernet" }, 172 { 0, 0, 0, NULL } 173 }; 174 175 static struct re_hwrev re_hwrevs[] = { 176 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"}, 177 { RE_HWREV_8169, RE_8169, "8169"}, 178 { RE_HWREV_8169S, RE_8169, "8169S"}, 179 { RE_HWREV_8110S, RE_8169, "8110S"}, 180 { 0, 0, NULL } 181 }; 182 183 static int re_probe(device_t); 184 static int re_attach(device_t); 185 static int re_detach(device_t); 186 187 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 188 189 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 190 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 191 bus_size_t, int); 192 static int re_allocmem(device_t, struct re_softc *); 193 static int re_newbuf(struct re_softc *, int, struct mbuf *); 194 static int re_rx_list_init(struct re_softc *); 195 static int re_tx_list_init(struct re_softc *); 196 static void re_rxeof(struct re_softc *); 197 static void re_txeof(struct re_softc *); 198 static void re_intr(void *); 199 static void re_tick(void *); 200 static void re_start(struct ifnet *); 201 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 202 static void re_init(void *); 203 static void re_stop(struct re_softc *); 204 static void re_watchdog(struct ifnet *); 205 static int re_suspend(device_t); 206 static int re_resume(device_t); 207 static void re_shutdown(device_t); 208 static int re_ifmedia_upd(struct ifnet *); 209 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 210 211 static void re_eeprom_putbyte(struct re_softc *, int); 212 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 213 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int); 214 static int re_gmii_readreg(device_t, int, int); 215 static int re_gmii_writereg(device_t, int, int, int); 216 217 static int re_miibus_readreg(device_t, int, int); 218 static int re_miibus_writereg(device_t, int, int, int); 219 static void re_miibus_statchg(device_t); 220 221 static void re_setmulti(struct re_softc *); 222 static void re_reset(struct re_softc *); 223 224 static int re_diag(struct re_softc *); 225 #ifdef DEVICE_POLLING 226 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 227 #endif 228 229 static device_method_t re_methods[] = { 230 /* Device interface */ 231 DEVMETHOD(device_probe, re_probe), 232 DEVMETHOD(device_attach, re_attach), 233 DEVMETHOD(device_detach, re_detach), 234 DEVMETHOD(device_suspend, re_suspend), 235 DEVMETHOD(device_resume, re_resume), 236 DEVMETHOD(device_shutdown, re_shutdown), 237 238 /* bus interface */ 239 DEVMETHOD(bus_print_child, bus_generic_print_child), 240 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 241 242 /* MII interface */ 243 DEVMETHOD(miibus_readreg, re_miibus_readreg), 244 DEVMETHOD(miibus_writereg, re_miibus_writereg), 245 DEVMETHOD(miibus_statchg, re_miibus_statchg), 246 247 { 0, 0 } 248 }; 249 250 static driver_t re_driver = { 251 "re", 252 re_methods, 253 sizeof(struct re_softc) 254 }; 255 256 static devclass_t re_devclass; 257 258 DECLARE_DUMMY_MODULE(if_re); 259 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 260 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 261 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 262 263 #define EE_SET(x) \ 264 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 265 266 #define EE_CLR(x) \ 267 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 268 269 /* 270 * Send a read command and address to the EEPROM, check for ACK. 271 */ 272 static void 273 re_eeprom_putbyte(struct re_softc *sc, int addr) 274 { 275 int d, i; 276 277 d = addr | sc->re_eecmd_read; 278 279 /* 280 * Feed in each bit and strobe the clock. 281 */ 282 for (i = 0x400; i != 0; i >>= 1) { 283 if (d & i) 284 EE_SET(RE_EE_DATAIN); 285 else 286 EE_CLR(RE_EE_DATAIN); 287 DELAY(100); 288 EE_SET(RE_EE_CLK); 289 DELAY(150); 290 EE_CLR(RE_EE_CLK); 291 DELAY(100); 292 } 293 } 294 295 /* 296 * Read a word of data stored in the EEPROM at address 'addr.' 297 */ 298 static void 299 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 300 { 301 int i; 302 uint16_t word = 0; 303 304 /* Enter EEPROM access mode. */ 305 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 306 307 /* 308 * Send address of word we want to read. 309 */ 310 re_eeprom_putbyte(sc, addr); 311 312 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 313 314 /* 315 * Start reading bits from EEPROM. 316 */ 317 for (i = 0x8000; i != 0; i >>= 1) { 318 EE_SET(RE_EE_CLK); 319 DELAY(100); 320 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 321 word |= i; 322 EE_CLR(RE_EE_CLK); 323 DELAY(100); 324 } 325 326 /* Turn off EEPROM access mode. */ 327 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 328 329 *dest = word; 330 } 331 332 /* 333 * Read a sequence of words from the EEPROM. 334 */ 335 static void 336 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap) 337 { 338 int i; 339 uint16_t word = 0, *ptr; 340 341 for (i = 0; i < cnt; i++) { 342 re_eeprom_getword(sc, off + i, &word); 343 ptr = (u_int16_t *)(dest + (i * 2)); 344 if (swap) 345 *ptr = be16toh(word); 346 else 347 *ptr = word; 348 } 349 } 350 351 static int 352 re_gmii_readreg(device_t dev, int phy, int reg) 353 { 354 struct re_softc *sc = device_get_softc(dev); 355 u_int32_t rval; 356 int i; 357 358 if (phy != 1) 359 return(0); 360 361 /* Let the rgephy driver read the GMEDIASTAT register */ 362 363 if (reg == RE_GMEDIASTAT) 364 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 365 366 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 367 DELAY(1000); 368 369 for (i = 0; i < RE_TIMEOUT; i++) { 370 rval = CSR_READ_4(sc, RE_PHYAR); 371 if (rval & RE_PHYAR_BUSY) 372 break; 373 DELAY(100); 374 } 375 376 if (i == RE_TIMEOUT) { 377 device_printf(dev, "PHY read failed\n"); 378 return(0); 379 } 380 381 return(rval & RE_PHYAR_PHYDATA); 382 } 383 384 static int 385 re_gmii_writereg(device_t dev, int phy, int reg, int data) 386 { 387 struct re_softc *sc = device_get_softc(dev); 388 uint32_t rval; 389 int i; 390 391 CSR_WRITE_4(sc, RE_PHYAR, 392 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 393 DELAY(1000); 394 395 for (i = 0; i < RE_TIMEOUT; i++) { 396 rval = CSR_READ_4(sc, RE_PHYAR); 397 if ((rval & RE_PHYAR_BUSY) == 0) 398 break; 399 DELAY(100); 400 } 401 402 if (i == RE_TIMEOUT) 403 device_printf(dev, "PHY write failed\n"); 404 405 return(0); 406 } 407 408 static int 409 re_miibus_readreg(device_t dev, int phy, int reg) 410 { 411 struct re_softc *sc = device_get_softc(dev); 412 uint16_t rval = 0; 413 uint16_t re8139_reg = 0; 414 415 if (sc->re_type == RE_8169) { 416 rval = re_gmii_readreg(dev, phy, reg); 417 return(rval); 418 } 419 420 /* Pretend the internal PHY is only at address 0 */ 421 if (phy) 422 return(0); 423 424 switch(reg) { 425 case MII_BMCR: 426 re8139_reg = RE_BMCR; 427 break; 428 case MII_BMSR: 429 re8139_reg = RE_BMSR; 430 break; 431 case MII_ANAR: 432 re8139_reg = RE_ANAR; 433 break; 434 case MII_ANER: 435 re8139_reg = RE_ANER; 436 break; 437 case MII_ANLPAR: 438 re8139_reg = RE_LPAR; 439 break; 440 case MII_PHYIDR1: 441 case MII_PHYIDR2: 442 return(0); 443 /* 444 * Allow the rlphy driver to read the media status 445 * register. If we have a link partner which does not 446 * support NWAY, this is the register which will tell 447 * us the results of parallel detection. 448 */ 449 case RE_MEDIASTAT: 450 return(CSR_READ_1(sc, RE_MEDIASTAT)); 451 default: 452 device_printf(dev, "bad phy register\n"); 453 return(0); 454 } 455 rval = CSR_READ_2(sc, re8139_reg); 456 return(rval); 457 } 458 459 static int 460 re_miibus_writereg(device_t dev, int phy, int reg, int data) 461 { 462 struct re_softc *sc= device_get_softc(dev); 463 u_int16_t re8139_reg = 0; 464 465 if (sc->re_type == RE_8169) 466 return(re_gmii_writereg(dev, phy, reg, data)); 467 468 /* Pretend the internal PHY is only at address 0 */ 469 if (phy) 470 return(0); 471 472 switch(reg) { 473 case MII_BMCR: 474 re8139_reg = RE_BMCR; 475 break; 476 case MII_BMSR: 477 re8139_reg = RE_BMSR; 478 break; 479 case MII_ANAR: 480 re8139_reg = RE_ANAR; 481 break; 482 case MII_ANER: 483 re8139_reg = RE_ANER; 484 break; 485 case MII_ANLPAR: 486 re8139_reg = RE_LPAR; 487 break; 488 case MII_PHYIDR1: 489 case MII_PHYIDR2: 490 return(0); 491 default: 492 device_printf(dev, "bad phy register\n"); 493 return(0); 494 } 495 CSR_WRITE_2(sc, re8139_reg, data); 496 return(0); 497 } 498 499 static void 500 re_miibus_statchg(device_t dev) 501 { 502 } 503 504 /* 505 * Program the 64-bit multicast hash filter. 506 */ 507 static void 508 re_setmulti(struct re_softc *sc) 509 { 510 struct ifnet *ifp = &sc->arpcom.ac_if; 511 int h = 0; 512 uint32_t hashes[2] = { 0, 0 }; 513 struct ifmultiaddr *ifma; 514 uint32_t rxfilt; 515 int mcnt = 0; 516 517 rxfilt = CSR_READ_4(sc, RE_RXCFG); 518 519 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 520 rxfilt |= RE_RXCFG_RX_MULTI; 521 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 522 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 523 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 524 return; 525 } 526 527 /* first, zot all the existing hash bits */ 528 CSR_WRITE_4(sc, RE_MAR0, 0); 529 CSR_WRITE_4(sc, RE_MAR4, 0); 530 531 /* now program new ones */ 532 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 533 if (ifma->ifma_addr->sa_family != AF_LINK) 534 continue; 535 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 536 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 537 if (h < 32) 538 hashes[0] |= (1 << h); 539 else 540 hashes[1] |= (1 << (h - 32)); 541 mcnt++; 542 } 543 544 if (mcnt) 545 rxfilt |= RE_RXCFG_RX_MULTI; 546 else 547 rxfilt &= ~RE_RXCFG_RX_MULTI; 548 549 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 550 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 551 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 552 } 553 554 static void 555 re_reset(struct re_softc *sc) 556 { 557 int i; 558 559 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 560 561 for (i = 0; i < RE_TIMEOUT; i++) { 562 DELAY(10); 563 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 564 break; 565 } 566 if (i == RE_TIMEOUT) 567 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 568 569 CSR_WRITE_1(sc, 0x82, 1); 570 } 571 572 /* 573 * The following routine is designed to test for a defect on some 574 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 575 * lines connected to the bus, however for a 32-bit only card, they 576 * should be pulled high. The result of this defect is that the 577 * NIC will not work right if you plug it into a 64-bit slot: DMA 578 * operations will be done with 64-bit transfers, which will fail 579 * because the 64-bit data lines aren't connected. 580 * 581 * There's no way to work around this (short of talking a soldering 582 * iron to the board), however we can detect it. The method we use 583 * here is to put the NIC into digital loopback mode, set the receiver 584 * to promiscuous mode, and then try to send a frame. We then compare 585 * the frame data we sent to what was received. If the data matches, 586 * then the NIC is working correctly, otherwise we know the user has 587 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 588 * slot. In the latter case, there's no way the NIC can work correctly, 589 * so we print out a message on the console and abort the device attach. 590 */ 591 592 static int 593 re_diag(struct re_softc *sc) 594 { 595 struct ifnet *ifp = &sc->arpcom.ac_if; 596 struct mbuf *m0; 597 struct ether_header *eh; 598 struct re_desc *cur_rx; 599 uint16_t status; 600 uint32_t rxstat; 601 int total_len, i, error = 0; 602 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 603 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 604 605 /* Allocate a single mbuf */ 606 607 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 608 if (m0 == NULL) 609 return(ENOBUFS); 610 611 /* 612 * Initialize the NIC in test mode. This sets the chip up 613 * so that it can send and receive frames, but performs the 614 * following special functions: 615 * - Puts receiver in promiscuous mode 616 * - Enables digital loopback mode 617 * - Leaves interrupts turned off 618 */ 619 620 ifp->if_flags |= IFF_PROMISC; 621 sc->re_testmode = 1; 622 re_init(sc); 623 re_stop(sc); 624 DELAY(100000); 625 re_init(sc); 626 627 /* Put some data in the mbuf */ 628 629 eh = mtod(m0, struct ether_header *); 630 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 631 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 632 eh->ether_type = htons(ETHERTYPE_IP); 633 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 634 635 /* 636 * Queue the packet, start transmission. 637 * Note: ifq_handoff() ultimately calls re_start() for us. 638 */ 639 640 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 641 error = ifq_handoff(ifp, m0, NULL); 642 if (error) { 643 m0 = NULL; 644 goto done; 645 } 646 m0 = NULL; 647 648 /* Wait for it to propagate through the chip */ 649 650 DELAY(100000); 651 for (i = 0; i < RE_TIMEOUT; i++) { 652 status = CSR_READ_2(sc, RE_ISR); 653 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 654 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 655 break; 656 DELAY(10); 657 } 658 659 if (i == RE_TIMEOUT) { 660 if_printf(ifp, "diagnostic failed to receive packet " 661 "in loopback mode\n"); 662 error = EIO; 663 goto done; 664 } 665 666 /* 667 * The packet should have been dumped into the first 668 * entry in the RX DMA ring. Grab it from there. 669 */ 670 671 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 672 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 673 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 674 BUS_DMASYNC_POSTWRITE); 675 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 676 677 m0 = sc->re_ldata.re_rx_mbuf[0]; 678 sc->re_ldata.re_rx_mbuf[0] = NULL; 679 eh = mtod(m0, struct ether_header *); 680 681 cur_rx = &sc->re_ldata.re_rx_list[0]; 682 total_len = RE_RXBYTES(cur_rx); 683 rxstat = le32toh(cur_rx->re_cmdstat); 684 685 if (total_len != ETHER_MIN_LEN) { 686 if_printf(ifp, "diagnostic failed, received short packet\n"); 687 error = EIO; 688 goto done; 689 } 690 691 /* Test that the received packet data matches what we sent. */ 692 693 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 694 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 695 be16toh(eh->ether_type) != ETHERTYPE_IP) { 696 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 697 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 698 dst, ":", src, ":", ETHERTYPE_IP); 699 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 700 eh->ether_dhost, ":", eh->ether_shost, ":", 701 ntohs(eh->ether_type)); 702 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 703 "into a 64-bit PCI slot.\n"); 704 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 705 "for proper operation.\n"); 706 if_printf(ifp, "Read the re(4) man page for more details.\n"); 707 error = EIO; 708 } 709 710 done: 711 /* Turn interface off, release resources */ 712 713 sc->re_testmode = 0; 714 ifp->if_flags &= ~IFF_PROMISC; 715 re_stop(sc); 716 if (m0 != NULL) 717 m_freem(m0); 718 719 return (error); 720 } 721 722 /* 723 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 724 * IDs against our list and return a device name if we find a match. 725 */ 726 static int 727 re_probe(device_t dev) 728 { 729 struct re_type *t; 730 struct re_softc *sc; 731 int rid; 732 uint32_t hwrev; 733 uint16_t vendor, product; 734 735 t = re_devs; 736 737 vendor = pci_get_vendor(dev); 738 product = pci_get_device(dev); 739 740 for (t = re_devs; t->re_name != NULL; t++) { 741 if (product == t->re_did && vendor == t->re_vid) 742 break; 743 } 744 745 /* 746 * Check if we found a RealTek device. 747 */ 748 if (t->re_name == NULL) 749 return(ENXIO); 750 751 /* 752 * Temporarily map the I/O space so we can read the chip ID register. 753 */ 754 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 755 rid = RE_PCI_LOIO; 756 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 757 RF_ACTIVE); 758 if (sc->re_res == NULL) { 759 device_printf(dev, "couldn't map ports/memory\n"); 760 free(sc, M_TEMP); 761 return(ENXIO); 762 } 763 764 sc->re_btag = rman_get_bustag(sc->re_res); 765 sc->re_bhandle = rman_get_bushandle(sc->re_res); 766 767 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 768 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 769 free(sc, M_TEMP); 770 771 /* 772 * and continue matching for the specific chip... 773 */ 774 for (; t->re_name != NULL; t++) { 775 if (product == t->re_did && vendor == t->re_vid && 776 t->re_basetype == hwrev) { 777 device_set_desc(dev, t->re_name); 778 return(0); 779 } 780 } 781 return(ENXIO); 782 } 783 784 /* 785 * This routine takes the segment list provided as the result of 786 * a bus_dma_map_load() operation and assigns the addresses/lengths 787 * to RealTek DMA descriptors. This can be called either by the RX 788 * code or the TX code. In the RX case, we'll probably wind up mapping 789 * at most one segment. For the TX case, there could be any number of 790 * segments since TX packets may span multiple mbufs. In either case, 791 * if the number of segments is larger than the re_maxsegs limit 792 * specified by the caller, we abort the mapping operation. Sadly, 793 * whoever designed the buffer mapping API did not provide a way to 794 * return an error from here, so we have to fake it a bit. 795 */ 796 797 static void 798 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 799 bus_size_t mapsize, int error) 800 { 801 struct re_dmaload_arg *ctx; 802 struct re_desc *d = NULL; 803 int i = 0, idx; 804 uint32_t cmdstat; 805 806 if (error) 807 return; 808 809 ctx = arg; 810 811 /* Signal error to caller if there's too many segments */ 812 if (nseg > ctx->re_maxsegs) { 813 ctx->re_maxsegs = 0; 814 return; 815 } 816 817 /* 818 * Map the segment array into descriptors. Note that we set the 819 * start-of-frame and end-of-frame markers for either TX or RX, but 820 * they really only have meaning in the TX case. (In the RX case, 821 * it's the chip that tells us where packets begin and end.) 822 * We also keep track of the end of the ring and set the 823 * end-of-ring bits as needed, and we set the ownership bits 824 * in all except the very first descriptor. (The caller will 825 * set this descriptor later when it start transmission or 826 * reception.) 827 */ 828 idx = ctx->re_idx; 829 for (;;) { 830 d = &ctx->re_ring[idx]; 831 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 832 ctx->re_maxsegs = 0; 833 return; 834 } 835 cmdstat = segs[i].ds_len; 836 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 837 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 838 if (i == 0) 839 cmdstat |= RE_TDESC_CMD_SOF; 840 else 841 cmdstat |= RE_TDESC_CMD_OWN; 842 if (idx == (RE_RX_DESC_CNT - 1)) 843 cmdstat |= RE_TDESC_CMD_EOR; 844 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 845 i++; 846 if (i == nseg) 847 break; 848 RE_DESC_INC(idx); 849 } 850 851 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 852 ctx->re_maxsegs = nseg; 853 ctx->re_idx = idx; 854 } 855 856 /* 857 * Map a single buffer address. 858 */ 859 860 static void 861 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 862 { 863 uint32_t *addr; 864 865 if (error) 866 return; 867 868 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 869 addr = arg; 870 *addr = segs->ds_addr; 871 } 872 873 static int 874 re_allocmem(device_t dev, struct re_softc *sc) 875 { 876 int error, i, nseg; 877 878 /* 879 * Allocate map for RX mbufs. 880 */ 881 nseg = 32; 882 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 883 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 884 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 885 &sc->re_ldata.re_mtag); 886 if (error) { 887 device_printf(dev, "could not allocate dma tag\n"); 888 return(error); 889 } 890 891 /* 892 * Allocate map for TX descriptor list. 893 */ 894 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 895 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 896 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 897 &sc->re_ldata.re_tx_list_tag); 898 if (error) { 899 device_printf(dev, "could not allocate dma tag\n"); 900 return(error); 901 } 902 903 /* Allocate DMA'able memory for the TX ring */ 904 905 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 906 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 907 &sc->re_ldata.re_tx_list_map); 908 if (error) { 909 device_printf(dev, "could not allocate TX ring\n"); 910 return(error); 911 } 912 913 /* Load the map for the TX ring. */ 914 915 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 916 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 917 RE_TX_LIST_SZ, re_dma_map_addr, 918 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 919 if (error) { 920 device_printf(dev, "could not get addres of TX ring\n"); 921 return(error); 922 } 923 924 /* Create DMA maps for TX buffers */ 925 926 for (i = 0; i < RE_TX_DESC_CNT; i++) { 927 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 928 &sc->re_ldata.re_tx_dmamap[i]); 929 if (error) { 930 device_printf(dev, "can't create DMA map for TX\n"); 931 return(error); 932 } 933 } 934 935 /* 936 * Allocate map for RX descriptor list. 937 */ 938 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 939 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 940 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 941 &sc->re_ldata.re_rx_list_tag); 942 if (error) { 943 device_printf(dev, "could not allocate dma tag\n"); 944 return(error); 945 } 946 947 /* Allocate DMA'able memory for the RX ring */ 948 949 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 950 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 951 &sc->re_ldata.re_rx_list_map); 952 if (error) { 953 device_printf(dev, "could not allocate RX ring\n"); 954 return(error); 955 } 956 957 /* Load the map for the RX ring. */ 958 959 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 960 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 961 RE_TX_LIST_SZ, re_dma_map_addr, 962 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 963 if (error) { 964 device_printf(dev, "could not get address of RX ring\n"); 965 return(error); 966 } 967 968 /* Create DMA maps for RX buffers */ 969 970 for (i = 0; i < RE_RX_DESC_CNT; i++) { 971 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 972 &sc->re_ldata.re_rx_dmamap[i]); 973 if (error) { 974 device_printf(dev, "can't create DMA map for RX\n"); 975 return(ENOMEM); 976 } 977 } 978 979 return(0); 980 } 981 982 /* 983 * Attach the interface. Allocate softc structures, do ifmedia 984 * setup and ethernet/BPF attach. 985 */ 986 static int 987 re_attach(device_t dev) 988 { 989 struct re_softc *sc = device_get_softc(dev); 990 struct ifnet *ifp; 991 struct re_hwrev *hw_rev; 992 uint8_t eaddr[ETHER_ADDR_LEN]; 993 int hwrev; 994 u_int16_t re_did = 0; 995 int error = 0, rid, i; 996 997 callout_init(&sc->re_timer); 998 999 #ifndef BURN_BRIDGES 1000 /* 1001 * Handle power management nonsense. 1002 */ 1003 1004 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1005 uint32_t membase, irq; 1006 1007 /* Save important PCI config data. */ 1008 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1009 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1010 1011 /* Reset the power state. */ 1012 device_printf(dev, "chip is is in D%d power mode " 1013 "-- setting to D0\n", pci_get_powerstate(dev)); 1014 1015 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1016 1017 /* Restore PCI config data. */ 1018 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1019 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1020 } 1021 #endif 1022 /* 1023 * Map control/status registers. 1024 */ 1025 pci_enable_busmaster(dev); 1026 1027 rid = RE_PCI_LOIO; 1028 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1029 RF_ACTIVE); 1030 1031 if (sc->re_res == NULL) { 1032 device_printf(dev, "couldn't map ports/memory\n"); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 sc->re_btag = rman_get_bustag(sc->re_res); 1038 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1039 1040 /* Allocate interrupt */ 1041 rid = 0; 1042 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1043 RF_SHAREABLE | RF_ACTIVE); 1044 1045 if (sc->re_irq == NULL) { 1046 device_printf(dev, "couldn't map interrupt\n"); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 /* Reset the adapter. */ 1052 re_reset(sc); 1053 1054 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1055 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1056 if (hw_rev->re_rev == hwrev) { 1057 sc->re_type = hw_rev->re_type; 1058 break; 1059 } 1060 } 1061 1062 if (sc->re_type == RE_8169) { 1063 /* Set RX length mask */ 1064 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1065 1066 /* Force station address autoload from the EEPROM */ 1067 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD); 1068 for (i = 0; i < RE_TIMEOUT; i++) { 1069 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0) 1070 break; 1071 DELAY(100); 1072 } 1073 if (i == RE_TIMEOUT) 1074 device_printf(dev, "eeprom autoload timed out\n"); 1075 1076 for (i = 0; i < ETHER_ADDR_LEN; i++) 1077 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 1078 } else { 1079 uint16_t as[3]; 1080 1081 /* Set RX length mask */ 1082 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1083 1084 sc->re_eecmd_read = RE_EECMD_READ_6BIT; 1085 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1086 if (re_did != 0x8129) 1087 sc->re_eecmd_read = RE_EECMD_READ_8BIT; 1088 1089 /* 1090 * Get station address from the EEPROM. 1091 */ 1092 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0); 1093 for (i = 0; i < 3; i++) { 1094 eaddr[(i * 2) + 0] = as[i] & 0xff; 1095 eaddr[(i * 2) + 1] = as[i] >> 8; 1096 } 1097 } 1098 1099 /* 1100 * Allocate the parent bus DMA tag appropriate for PCI. 1101 */ 1102 #define RE_NSEG_NEW 32 1103 error = bus_dma_tag_create(NULL, /* parent */ 1104 1, 0, /* alignment, boundary */ 1105 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1106 BUS_SPACE_MAXADDR, /* highaddr */ 1107 NULL, NULL, /* filter, filterarg */ 1108 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1109 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1110 BUS_DMA_ALLOCNOW, /* flags */ 1111 &sc->re_parent_tag); 1112 if (error) 1113 goto fail; 1114 1115 error = re_allocmem(dev, sc); 1116 1117 if (error) 1118 goto fail; 1119 1120 /* Do MII setup */ 1121 if (mii_phy_probe(dev, &sc->re_miibus, 1122 re_ifmedia_upd, re_ifmedia_sts)) { 1123 device_printf(dev, "MII without any phy!\n"); 1124 error = ENXIO; 1125 goto fail; 1126 } 1127 1128 ifp = &sc->arpcom.ac_if; 1129 ifp->if_softc = sc; 1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1131 ifp->if_mtu = ETHERMTU; 1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1133 ifp->if_ioctl = re_ioctl; 1134 ifp->if_capabilities = IFCAP_VLAN_MTU; 1135 ifp->if_start = re_start; 1136 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1137 #ifdef DEVICE_POLLING 1138 ifp->if_poll = re_poll; 1139 #endif 1140 ifp->if_watchdog = re_watchdog; 1141 ifp->if_init = re_init; 1142 if (sc->re_type == RE_8169) 1143 ifp->if_baudrate = 1000000000; 1144 else 1145 ifp->if_baudrate = 100000000; 1146 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1147 ifq_set_ready(&ifp->if_snd); 1148 #ifdef RE_DISABLE_HWCSUM 1149 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1150 ifp->if_hwassist = 0; 1151 #else 1152 ifp->if_capenable = ifp->if_capabilities; 1153 ifp->if_hwassist = RE_CSUM_FEATURES; 1154 #endif 1155 1156 /* 1157 * Call MI attach routine. 1158 */ 1159 ether_ifattach(ifp, eaddr); 1160 1161 /* Perform hardware diagnostic. */ 1162 error = re_diag(sc); 1163 1164 if (error) { 1165 device_printf(dev, "hardware diagnostic failure\n"); 1166 ether_ifdetach(ifp); 1167 goto fail; 1168 } 1169 1170 /* Hook interrupt last to avoid having to lock softc */ 1171 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc, 1172 &sc->re_intrhand, NULL); 1173 1174 if (error) { 1175 device_printf(dev, "couldn't set up irq\n"); 1176 ether_ifdetach(ifp); 1177 goto fail; 1178 } 1179 1180 fail: 1181 if (error) 1182 re_detach(dev); 1183 1184 return (error); 1185 } 1186 1187 /* 1188 * Shutdown hardware and free up resources. This can be called any 1189 * time after the mutex has been initialized. It is called in both 1190 * the error case in attach and the normal detach case so it needs 1191 * to be careful about only freeing resources that have actually been 1192 * allocated. 1193 */ 1194 static int 1195 re_detach(device_t dev) 1196 { 1197 struct re_softc *sc = device_get_softc(dev); 1198 struct ifnet *ifp = &sc->arpcom.ac_if; 1199 int i, s; 1200 1201 s = splimp(); 1202 1203 /* These should only be active if attach succeeded */ 1204 if (device_is_attached(dev)) { 1205 re_stop(sc); 1206 ether_ifdetach(ifp); 1207 } 1208 if (sc->re_miibus) 1209 device_delete_child(dev, sc->re_miibus); 1210 bus_generic_detach(dev); 1211 1212 if (sc->re_intrhand) 1213 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1214 if (sc->re_irq) 1215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1216 if (sc->re_res) 1217 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1218 sc->re_res); 1219 1220 /* Unload and free the RX DMA ring memory and map */ 1221 1222 if (sc->re_ldata.re_rx_list_tag) { 1223 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1224 sc->re_ldata.re_rx_list_map); 1225 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1226 sc->re_ldata.re_rx_list, 1227 sc->re_ldata.re_rx_list_map); 1228 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1229 } 1230 1231 /* Unload and free the TX DMA ring memory and map */ 1232 1233 if (sc->re_ldata.re_tx_list_tag) { 1234 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1235 sc->re_ldata.re_tx_list_map); 1236 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1237 sc->re_ldata.re_tx_list, 1238 sc->re_ldata.re_tx_list_map); 1239 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1240 } 1241 1242 /* Destroy all the RX and TX buffer maps */ 1243 1244 if (sc->re_ldata.re_mtag) { 1245 for (i = 0; i < RE_TX_DESC_CNT; i++) 1246 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1247 sc->re_ldata.re_tx_dmamap[i]); 1248 for (i = 0; i < RE_RX_DESC_CNT; i++) 1249 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1250 sc->re_ldata.re_rx_dmamap[i]); 1251 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1252 } 1253 1254 /* Unload and free the stats buffer and map */ 1255 1256 if (sc->re_ldata.re_stag) { 1257 bus_dmamap_unload(sc->re_ldata.re_stag, 1258 sc->re_ldata.re_rx_list_map); 1259 bus_dmamem_free(sc->re_ldata.re_stag, 1260 sc->re_ldata.re_stats, 1261 sc->re_ldata.re_smap); 1262 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1263 } 1264 1265 if (sc->re_parent_tag) 1266 bus_dma_tag_destroy(sc->re_parent_tag); 1267 1268 splx(s); 1269 1270 return(0); 1271 } 1272 1273 static int 1274 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1275 { 1276 struct re_dmaload_arg arg; 1277 struct mbuf *n = NULL; 1278 int error; 1279 1280 if (m == NULL) { 1281 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1282 if (n == NULL) 1283 return(ENOBUFS); 1284 m = n; 1285 } else 1286 m->m_data = m->m_ext.ext_buf; 1287 1288 /* 1289 * Initialize mbuf length fields and fixup 1290 * alignment so that the frame payload is 1291 * longword aligned. 1292 */ 1293 m->m_len = m->m_pkthdr.len = MCLBYTES; 1294 m_adj(m, ETHER_ALIGN); 1295 1296 arg.sc = sc; 1297 arg.re_idx = idx; 1298 arg.re_maxsegs = 1; 1299 arg.re_flags = 0; 1300 arg.re_ring = sc->re_ldata.re_rx_list; 1301 1302 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1303 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1304 &arg, BUS_DMA_NOWAIT); 1305 if (error || arg.re_maxsegs != 1) { 1306 if (n != NULL) 1307 m_freem(n); 1308 return (ENOMEM); 1309 } 1310 1311 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1312 sc->re_ldata.re_rx_mbuf[idx] = m; 1313 1314 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1315 BUS_DMASYNC_PREREAD); 1316 1317 return(0); 1318 } 1319 1320 static int 1321 re_tx_list_init(struct re_softc *sc) 1322 { 1323 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1324 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1325 1326 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1327 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1328 sc->re_ldata.re_tx_prodidx = 0; 1329 sc->re_ldata.re_tx_considx = 0; 1330 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1331 1332 return(0); 1333 } 1334 1335 static int 1336 re_rx_list_init(struct re_softc *sc) 1337 { 1338 int i, error; 1339 1340 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1341 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1342 1343 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1344 error = re_newbuf(sc, i, NULL); 1345 if (error) 1346 return(error); 1347 } 1348 1349 /* Flush the RX descriptors */ 1350 1351 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1352 sc->re_ldata.re_rx_list_map, 1353 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1354 1355 sc->re_ldata.re_rx_prodidx = 0; 1356 sc->re_head = sc->re_tail = NULL; 1357 1358 return(0); 1359 } 1360 1361 /* 1362 * RX handler for C+ and 8169. For the gigE chips, we support 1363 * the reception of jumbo frames that have been fragmented 1364 * across multiple 2K mbuf cluster buffers. 1365 */ 1366 static void 1367 re_rxeof(struct re_softc *sc) 1368 { 1369 struct ifnet *ifp = &sc->arpcom.ac_if; 1370 struct mbuf *m; 1371 struct re_desc *cur_rx; 1372 uint32_t rxstat, rxvlan; 1373 int i, total_len; 1374 1375 /* Invalidate the descriptor memory */ 1376 1377 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1378 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1379 1380 for (i = sc->re_ldata.re_rx_prodidx; 1381 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1382 cur_rx = &sc->re_ldata.re_rx_list[i]; 1383 m = sc->re_ldata.re_rx_mbuf[i]; 1384 total_len = RE_RXBYTES(cur_rx); 1385 rxstat = le32toh(cur_rx->re_cmdstat); 1386 rxvlan = le32toh(cur_rx->re_vlanctl); 1387 1388 /* Invalidate the RX mbuf and unload its map */ 1389 1390 bus_dmamap_sync(sc->re_ldata.re_mtag, 1391 sc->re_ldata.re_rx_dmamap[i], 1392 BUS_DMASYNC_POSTWRITE); 1393 bus_dmamap_unload(sc->re_ldata.re_mtag, 1394 sc->re_ldata.re_rx_dmamap[i]); 1395 1396 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1397 m->m_len = MCLBYTES - ETHER_ALIGN; 1398 if (sc->re_head == NULL) { 1399 sc->re_head = sc->re_tail = m; 1400 } else { 1401 m->m_flags &= ~M_PKTHDR; 1402 sc->re_tail->m_next = m; 1403 sc->re_tail = m; 1404 } 1405 re_newbuf(sc, i, NULL); 1406 continue; 1407 } 1408 1409 /* 1410 * NOTE: for the 8139C+, the frame length field 1411 * is always 12 bits in size, but for the gigE chips, 1412 * it is 13 bits (since the max RX frame length is 16K). 1413 * Unfortunately, all 32 bits in the status word 1414 * were already used, so to make room for the extra 1415 * length bit, RealTek took out the 'frame alignment 1416 * error' bit and shifted the other status bits 1417 * over one slot. The OWN, EOR, FS and LS bits are 1418 * still in the same places. We have already extracted 1419 * the frame length and checked the OWN bit, so rather 1420 * than using an alternate bit mapping, we shift the 1421 * status bits one space to the right so we can evaluate 1422 * them using the 8169 status as though it was in the 1423 * same format as that of the 8139C+. 1424 */ 1425 if (sc->re_type == RE_8169) 1426 rxstat >>= 1; 1427 1428 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1429 ifp->if_ierrors++; 1430 /* 1431 * If this is part of a multi-fragment packet, 1432 * discard all the pieces. 1433 */ 1434 if (sc->re_head != NULL) { 1435 m_freem(sc->re_head); 1436 sc->re_head = sc->re_tail = NULL; 1437 } 1438 re_newbuf(sc, i, m); 1439 continue; 1440 } 1441 1442 /* 1443 * If allocating a replacement mbuf fails, 1444 * reload the current one. 1445 */ 1446 1447 if (re_newbuf(sc, i, NULL)) { 1448 ifp->if_ierrors++; 1449 if (sc->re_head != NULL) { 1450 m_freem(sc->re_head); 1451 sc->re_head = sc->re_tail = NULL; 1452 } 1453 re_newbuf(sc, i, m); 1454 continue; 1455 } 1456 1457 if (sc->re_head != NULL) { 1458 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1459 /* 1460 * Special case: if there's 4 bytes or less 1461 * in this buffer, the mbuf can be discarded: 1462 * the last 4 bytes is the CRC, which we don't 1463 * care about anyway. 1464 */ 1465 if (m->m_len <= ETHER_CRC_LEN) { 1466 sc->re_tail->m_len -= 1467 (ETHER_CRC_LEN - m->m_len); 1468 m_freem(m); 1469 } else { 1470 m->m_len -= ETHER_CRC_LEN; 1471 m->m_flags &= ~M_PKTHDR; 1472 sc->re_tail->m_next = m; 1473 } 1474 m = sc->re_head; 1475 sc->re_head = sc->re_tail = NULL; 1476 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1477 } else 1478 m->m_pkthdr.len = m->m_len = 1479 (total_len - ETHER_CRC_LEN); 1480 1481 ifp->if_ipackets++; 1482 m->m_pkthdr.rcvif = ifp; 1483 1484 /* Do RX checksumming if enabled */ 1485 1486 if (ifp->if_capenable & IFCAP_RXCSUM) { 1487 1488 /* Check IP header checksum */ 1489 if (rxstat & RE_RDESC_STAT_PROTOID) 1490 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1491 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1492 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1493 1494 /* Check TCP/UDP checksum */ 1495 if ((RE_TCPPKT(rxstat) && 1496 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1497 (RE_UDPPKT(rxstat) && 1498 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1499 m->m_pkthdr.csum_flags |= 1500 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1501 m->m_pkthdr.csum_data = 0xffff; 1502 } 1503 } 1504 1505 if (rxvlan & RE_RDESC_VLANCTL_TAG) 1506 VLAN_INPUT_TAG(m, 1507 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1508 else 1509 (*ifp->if_input)(ifp, m); 1510 } 1511 1512 /* Flush the RX DMA ring */ 1513 1514 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1515 sc->re_ldata.re_rx_list_map, 1516 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1517 1518 sc->re_ldata.re_rx_prodidx = i; 1519 } 1520 1521 static void 1522 re_txeof(struct re_softc *sc) 1523 { 1524 struct ifnet *ifp = &sc->arpcom.ac_if; 1525 uint32_t txstat; 1526 int idx; 1527 1528 /* Invalidate the TX descriptor list */ 1529 1530 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1531 sc->re_ldata.re_tx_list_map, 1532 BUS_DMASYNC_POSTREAD); 1533 1534 for (idx = sc->re_ldata.re_tx_considx; 1535 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) { 1536 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1537 if (txstat & RE_TDESC_CMD_OWN) 1538 break; 1539 1540 /* 1541 * We only stash mbufs in the last descriptor 1542 * in a fragment chain, which also happens to 1543 * be the only place where the TX status bits 1544 * are valid. 1545 */ 1546 if (txstat & RE_TDESC_CMD_EOF) { 1547 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1548 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1549 bus_dmamap_unload(sc->re_ldata.re_mtag, 1550 sc->re_ldata.re_tx_dmamap[idx]); 1551 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1552 RE_TDESC_STAT_COLCNT)) 1553 ifp->if_collisions++; 1554 if (txstat & RE_TDESC_STAT_TXERRSUM) 1555 ifp->if_oerrors++; 1556 else 1557 ifp->if_opackets++; 1558 } 1559 sc->re_ldata.re_tx_free++; 1560 } 1561 1562 /* No changes made to the TX ring, so no flush needed */ 1563 if (idx != sc->re_ldata.re_tx_considx) { 1564 sc->re_ldata.re_tx_considx = idx; 1565 ifp->if_flags &= ~IFF_OACTIVE; 1566 ifp->if_timer = 0; 1567 } 1568 1569 /* 1570 * If not all descriptors have been released reaped yet, 1571 * reload the timer so that we will eventually get another 1572 * interrupt that will cause us to re-enter this routine. 1573 * This is done in case the transmitter has gone idle. 1574 */ 1575 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 1576 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1577 } 1578 1579 static void 1580 re_tick(void *xsc) 1581 { 1582 struct re_softc *sc = xsc; 1583 struct mii_data *mii; 1584 int s; 1585 1586 s = splimp(); 1587 1588 mii = device_get_softc(sc->re_miibus); 1589 mii_tick(mii); 1590 1591 callout_reset(&sc->re_timer, hz, re_tick, sc); 1592 splx(s); 1593 } 1594 1595 #ifdef DEVICE_POLLING 1596 1597 static void 1598 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1599 { 1600 struct re_softc *sc = ifp->if_softc; 1601 1602 switch(cmd) { 1603 case POLL_REGISTER: 1604 /* disable interrupts */ 1605 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1606 break; 1607 case POLL_DEREGISTER: 1608 /* enable interrupts */ 1609 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1610 break; 1611 default: 1612 sc->rxcycles = count; 1613 re_rxeof(sc); 1614 re_txeof(sc); 1615 1616 if (!ifq_is_empty(&ifp->if_snd)) 1617 (*ifp->if_start)(ifp); 1618 1619 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1620 uint16_t status; 1621 1622 status = CSR_READ_2(sc, RE_ISR); 1623 if (status == 0xffff) 1624 return; 1625 if (status) 1626 CSR_WRITE_2(sc, RE_ISR, status); 1627 1628 /* 1629 * XXX check behaviour on receiver stalls. 1630 */ 1631 1632 if (status & RE_ISR_SYSTEM_ERR) { 1633 re_reset(sc); 1634 re_init(sc); 1635 } 1636 } 1637 break; 1638 } 1639 } 1640 #endif /* DEVICE_POLLING */ 1641 1642 static void 1643 re_intr(void *arg) 1644 { 1645 struct re_softc *sc = arg; 1646 struct ifnet *ifp = &sc->arpcom.ac_if; 1647 uint16_t status; 1648 int s; 1649 1650 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1651 return; 1652 1653 s = splimp(); 1654 1655 for (;;) { 1656 status = CSR_READ_2(sc, RE_ISR); 1657 /* If the card has gone away the read returns 0xffff. */ 1658 if (status == 0xffff) 1659 break; 1660 if (status) 1661 CSR_WRITE_2(sc, RE_ISR, status); 1662 1663 if ((status & RE_INTRS_CPLUS) == 0) 1664 break; 1665 1666 if (status & RE_ISR_RX_OK) 1667 re_rxeof(sc); 1668 1669 if (status & RE_ISR_RX_ERR) 1670 re_rxeof(sc); 1671 1672 if ((status & RE_ISR_TIMEOUT_EXPIRED) || 1673 (status & RE_ISR_TX_ERR) || 1674 (status & RE_ISR_TX_DESC_UNAVAIL)) 1675 re_txeof(sc); 1676 1677 if (status & RE_ISR_SYSTEM_ERR) { 1678 re_reset(sc); 1679 re_init(sc); 1680 } 1681 1682 if (status & RE_ISR_LINKCHG) 1683 re_tick(sc); 1684 } 1685 1686 if (!ifq_is_empty(&ifp->if_snd)) 1687 (*ifp->if_start)(ifp); 1688 1689 splx(s); 1690 } 1691 1692 static int 1693 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1694 { 1695 struct ifnet *ifp = &sc->arpcom.ac_if; 1696 struct mbuf *m, *m_new = NULL; 1697 struct re_dmaload_arg arg; 1698 bus_dmamap_t map; 1699 int error; 1700 1701 *called_defrag = 0; 1702 if (sc->re_ldata.re_tx_free <= 4) 1703 return(EFBIG); 1704 1705 m = *m_head; 1706 1707 /* 1708 * Set up checksum offload. Note: checksum offload bits must 1709 * appear in all descriptors of a multi-descriptor transmit 1710 * attempt. (This is according to testing done with an 8169 1711 * chip. I'm not sure if this is a requirement or a bug.) 1712 */ 1713 1714 arg.re_flags = 0; 1715 1716 if (m->m_pkthdr.csum_flags & CSUM_IP) 1717 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1718 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1719 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1720 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1721 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1722 1723 arg.sc = sc; 1724 arg.re_idx = *idx; 1725 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1726 if (arg.re_maxsegs > 4) 1727 arg.re_maxsegs -= 4; 1728 arg.re_ring = sc->re_ldata.re_tx_list; 1729 1730 map = sc->re_ldata.re_tx_dmamap[*idx]; 1731 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1732 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1733 1734 if (error && error != EFBIG) { 1735 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1736 return(ENOBUFS); 1737 } 1738 1739 /* Too many segments to map, coalesce into a single mbuf */ 1740 1741 if (error || arg.re_maxsegs == 0) { 1742 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1743 if (m_new == NULL) 1744 return(1); 1745 else { 1746 m = m_new; 1747 *m_head = m; 1748 } 1749 1750 *called_defrag = 1; 1751 arg.sc = sc; 1752 arg.re_idx = *idx; 1753 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1754 arg.re_ring = sc->re_ldata.re_tx_list; 1755 1756 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1757 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1758 if (error) { 1759 m_freem(m); 1760 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1761 return(EFBIG); 1762 } 1763 } 1764 1765 /* 1766 * Insure that the map for this transmission 1767 * is placed at the array index of the last descriptor 1768 * in this chain. 1769 */ 1770 sc->re_ldata.re_tx_dmamap[*idx] = 1771 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1772 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1773 1774 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1775 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1776 1777 /* 1778 * Set up hardware VLAN tagging. Note: vlan tag info must 1779 * appear in the first descriptor of a multi-descriptor 1780 * transmission attempt. 1781 */ 1782 1783 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1784 m->m_pkthdr.rcvif != NULL && 1785 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1786 struct ifvlan *ifv; 1787 ifv = m->m_pkthdr.rcvif->if_softc; 1788 if (ifv != NULL) 1789 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1790 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1791 } 1792 1793 /* Transfer ownership of packet to the chip. */ 1794 1795 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1796 htole32(RE_TDESC_CMD_OWN); 1797 if (*idx != arg.re_idx) 1798 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1799 htole32(RE_TDESC_CMD_OWN); 1800 1801 RE_DESC_INC(arg.re_idx); 1802 *idx = arg.re_idx; 1803 1804 return(0); 1805 } 1806 1807 /* 1808 * Main transmit routine for C+ and gigE NICs. 1809 */ 1810 1811 static void 1812 re_start(struct ifnet *ifp) 1813 { 1814 struct re_softc *sc = ifp->if_softc; 1815 struct mbuf *m_head = NULL, *m_head2; 1816 int called_defrag, idx, s; 1817 1818 s = splimp(); 1819 1820 idx = sc->re_ldata.re_tx_prodidx; 1821 1822 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1823 m_head = ifq_poll(&ifp->if_snd); 1824 if (m_head == NULL) 1825 break; 1826 1827 if (re_encap(sc, &m_head, &idx, &called_defrag)) { 1828 if (called_defrag) { 1829 m_head2 = ifq_dequeue(&ifp->if_snd); 1830 m_freem(m_head2); 1831 } 1832 ifp->if_flags |= IFF_OACTIVE; 1833 break; 1834 } 1835 1836 m_head2 = ifq_dequeue(&ifp->if_snd); 1837 if (called_defrag) 1838 m_freem(m_head2); 1839 1840 /* 1841 * If there's a BPF listener, bounce a copy of this frame 1842 * to him. 1843 */ 1844 BPF_MTAP(ifp, m_head); 1845 } 1846 1847 /* Flush the TX descriptors */ 1848 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1849 sc->re_ldata.re_tx_list_map, 1850 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1851 1852 sc->re_ldata.re_tx_prodidx = idx; 1853 1854 /* 1855 * RealTek put the TX poll request register in a different 1856 * location on the 8169 gigE chip. I don't know why. 1857 */ 1858 if (sc->re_type == RE_8169) 1859 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START); 1860 else 1861 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START); 1862 1863 /* 1864 * Use the countdown timer for interrupt moderation. 1865 * 'TX done' interrupts are disabled. Instead, we reset the 1866 * countdown timer, which will begin counting until it hits 1867 * the value in the TIMERINT register, and then trigger an 1868 * interrupt. Each time we write to the TIMERCNT register, 1869 * the timer count is reset to 0. 1870 */ 1871 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1872 1873 splx(s); 1874 1875 /* 1876 * Set a timeout in case the chip goes out to lunch. 1877 */ 1878 ifp->if_timer = 5; 1879 } 1880 1881 static void 1882 re_init(void *xsc) 1883 { 1884 struct re_softc *sc = xsc; 1885 struct ifnet *ifp = &sc->arpcom.ac_if; 1886 struct mii_data *mii; 1887 uint32_t rxcfg = 0; 1888 int s; 1889 1890 s = splimp(); 1891 mii = device_get_softc(sc->re_miibus); 1892 1893 /* 1894 * Cancel pending I/O and free all RX/TX buffers. 1895 */ 1896 re_stop(sc); 1897 1898 /* 1899 * Enable C+ RX and TX mode, as well as VLAN stripping and 1900 * RX checksum offload. We must configure the C+ register 1901 * before all others. 1902 */ 1903 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 1904 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 1905 (ifp->if_capenable & IFCAP_RXCSUM ? 1906 RE_CPLUSCMD_RXCSUM_ENB : 0)); 1907 1908 /* 1909 * Init our MAC address. Even though the chipset 1910 * documentation doesn't mention it, we need to enter "Config 1911 * register write enable" mode to modify the ID registers. 1912 */ 1913 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 1914 CSR_WRITE_STREAM_4(sc, RE_IDR0, 1915 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1916 CSR_WRITE_STREAM_4(sc, RE_IDR4, 1917 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1918 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 1919 1920 /* 1921 * For C+ mode, initialize the RX descriptors and mbufs. 1922 */ 1923 re_rx_list_init(sc); 1924 re_tx_list_init(sc); 1925 1926 /* 1927 * Enable transmit and receive. 1928 */ 1929 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1930 1931 /* 1932 * Set the initial TX and RX configuration. 1933 */ 1934 if (sc->re_testmode) { 1935 if (sc->re_type == RE_8169) 1936 CSR_WRITE_4(sc, RE_TXCFG, 1937 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 1938 else 1939 CSR_WRITE_4(sc, RE_TXCFG, 1940 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 1941 } else 1942 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 1943 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 1944 1945 /* Set the individual bit to receive frames for this host only. */ 1946 rxcfg = CSR_READ_4(sc, RE_RXCFG); 1947 rxcfg |= RE_RXCFG_RX_INDIV; 1948 1949 /* If we want promiscuous mode, set the allframes bit. */ 1950 if (ifp->if_flags & IFF_PROMISC) { 1951 rxcfg |= RE_RXCFG_RX_ALLPHYS; 1952 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1953 } else { 1954 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 1955 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1956 } 1957 1958 /* 1959 * Set capture broadcast bit to capture broadcast frames. 1960 */ 1961 if (ifp->if_flags & IFF_BROADCAST) { 1962 rxcfg |= RE_RXCFG_RX_BROAD; 1963 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1964 } else { 1965 rxcfg &= ~RE_RXCFG_RX_BROAD; 1966 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1967 } 1968 1969 /* 1970 * Program the multicast filter, if necessary. 1971 */ 1972 re_setmulti(sc); 1973 1974 #ifdef DEVICE_POLLING 1975 /* 1976 * Disable interrupts if we are polling. 1977 */ 1978 if (ifp->if_flags & IFF_POLLING) 1979 CSR_WRITE_2(sc, RE_IMR, 0); 1980 else /* otherwise ... */ 1981 #endif /* DEVICE_POLLING */ 1982 /* 1983 * Enable interrupts. 1984 */ 1985 if (sc->re_testmode) 1986 CSR_WRITE_2(sc, RE_IMR, 0); 1987 else 1988 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1989 1990 /* Set initial TX threshold */ 1991 sc->re_txthresh = RE_TX_THRESH_INIT; 1992 1993 /* Start RX/TX process. */ 1994 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 1995 #ifdef notdef 1996 /* Enable receiver and transmitter. */ 1997 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1998 #endif 1999 /* 2000 * Load the addresses of the RX and TX lists into the chip. 2001 */ 2002 2003 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2004 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2005 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2006 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2007 2008 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2009 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2010 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2011 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2012 2013 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2014 2015 /* 2016 * Initialize the timer interrupt register so that 2017 * a timer interrupt will be generated once the timer 2018 * reaches a certain number of ticks. The timer is 2019 * reloaded on each transmit. This gives us TX interrupt 2020 * moderation, which dramatically improves TX frame rate. 2021 */ 2022 2023 if (sc->re_type == RE_8169) 2024 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2025 else 2026 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2027 2028 /* 2029 * For 8169 gigE NICs, set the max allowed RX packet 2030 * size so we can receive jumbo frames. 2031 */ 2032 if (sc->re_type == RE_8169) 2033 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2034 2035 if (sc->re_testmode) { 2036 splx(s); 2037 return; 2038 } 2039 2040 mii_mediachg(mii); 2041 2042 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2043 2044 ifp->if_flags |= IFF_RUNNING; 2045 ifp->if_flags &= ~IFF_OACTIVE; 2046 2047 callout_reset(&sc->re_timer, hz, re_tick, sc); 2048 splx(s); 2049 } 2050 2051 /* 2052 * Set media options. 2053 */ 2054 static int 2055 re_ifmedia_upd(struct ifnet *ifp) 2056 { 2057 struct re_softc *sc = ifp->if_softc; 2058 struct mii_data *mii; 2059 2060 mii = device_get_softc(sc->re_miibus); 2061 mii_mediachg(mii); 2062 2063 return(0); 2064 } 2065 2066 /* 2067 * Report current media status. 2068 */ 2069 static void 2070 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2071 { 2072 struct re_softc *sc = ifp->if_softc; 2073 struct mii_data *mii; 2074 2075 mii = device_get_softc(sc->re_miibus); 2076 2077 mii_pollstat(mii); 2078 ifmr->ifm_active = mii->mii_media_active; 2079 ifmr->ifm_status = mii->mii_media_status; 2080 } 2081 2082 static int 2083 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2084 { 2085 struct re_softc *sc = ifp->if_softc; 2086 struct ifreq *ifr = (struct ifreq *) data; 2087 struct mii_data *mii; 2088 int error = 0, s; 2089 2090 s = splimp(); 2091 2092 switch(command) { 2093 case SIOCSIFMTU: 2094 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2095 error = EINVAL; 2096 ifp->if_mtu = ifr->ifr_mtu; 2097 break; 2098 case SIOCSIFFLAGS: 2099 if (ifp->if_flags & IFF_UP) 2100 re_init(sc); 2101 else if (ifp->if_flags & IFF_RUNNING) 2102 re_stop(sc); 2103 error = 0; 2104 break; 2105 case SIOCADDMULTI: 2106 case SIOCDELMULTI: 2107 re_setmulti(sc); 2108 error = 0; 2109 break; 2110 case SIOCGIFMEDIA: 2111 case SIOCSIFMEDIA: 2112 mii = device_get_softc(sc->re_miibus); 2113 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2114 break; 2115 case SIOCSIFCAP: 2116 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2117 ifp->if_capenable |= 2118 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2119 if (ifp->if_capenable & IFCAP_TXCSUM) 2120 ifp->if_hwassist = RE_CSUM_FEATURES; 2121 else 2122 ifp->if_hwassist = 0; 2123 if (ifp->if_flags & IFF_RUNNING) 2124 re_init(sc); 2125 break; 2126 default: 2127 error = ether_ioctl(ifp, command, data); 2128 break; 2129 } 2130 2131 splx(s); 2132 2133 return(error); 2134 } 2135 2136 static void 2137 re_watchdog(struct ifnet *ifp) 2138 { 2139 struct re_softc *sc = ifp->if_softc; 2140 int s; 2141 2142 s = splimp(); 2143 if_printf(ifp, "watchdog timeout\n"); 2144 ifp->if_oerrors++; 2145 2146 re_txeof(sc); 2147 re_rxeof(sc); 2148 2149 re_init(sc); 2150 2151 splx(s); 2152 } 2153 2154 /* 2155 * Stop the adapter and free any mbufs allocated to the 2156 * RX and TX lists. 2157 */ 2158 static void 2159 re_stop(struct re_softc *sc) 2160 { 2161 struct ifnet *ifp = &sc->arpcom.ac_if; 2162 int i, s; 2163 2164 s = splimp(); 2165 ifp->if_timer = 0; 2166 callout_stop(&sc->re_timer); 2167 2168 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2169 2170 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2171 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2172 2173 if (sc->re_head != NULL) { 2174 m_freem(sc->re_head); 2175 sc->re_head = sc->re_tail = NULL; 2176 } 2177 2178 /* Free the TX list buffers. */ 2179 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2180 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2181 bus_dmamap_unload(sc->re_ldata.re_mtag, 2182 sc->re_ldata.re_tx_dmamap[i]); 2183 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2184 sc->re_ldata.re_tx_mbuf[i] = NULL; 2185 } 2186 } 2187 2188 /* Free the RX list buffers. */ 2189 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2190 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2191 bus_dmamap_unload(sc->re_ldata.re_mtag, 2192 sc->re_ldata.re_rx_dmamap[i]); 2193 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2194 sc->re_ldata.re_rx_mbuf[i] = NULL; 2195 } 2196 } 2197 2198 splx(s); 2199 } 2200 2201 /* 2202 * Device suspend routine. Stop the interface and save some PCI 2203 * settings in case the BIOS doesn't restore them properly on 2204 * resume. 2205 */ 2206 static int 2207 re_suspend(device_t dev) 2208 { 2209 #ifndef BURN_BRIDGES 2210 int i; 2211 #endif 2212 struct re_softc *sc = device_get_softc(dev); 2213 2214 re_stop(sc); 2215 2216 #ifndef BURN_BRIDGES 2217 for (i = 0; i < 5; i++) 2218 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2219 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2220 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2221 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2222 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2223 #endif 2224 2225 sc->suspended = 1; 2226 2227 return (0); 2228 } 2229 2230 /* 2231 * Device resume routine. Restore some PCI settings in case the BIOS 2232 * doesn't, re-enable busmastering, and restart the interface if 2233 * appropriate. 2234 */ 2235 static int 2236 re_resume(device_t dev) 2237 { 2238 struct re_softc *sc = device_get_softc(dev); 2239 struct ifnet *ifp = &sc->arpcom.ac_if; 2240 #ifndef BURN_BRIDGES 2241 int i; 2242 #endif 2243 2244 #ifndef BURN_BRIDGES 2245 /* better way to do this? */ 2246 for (i = 0; i < 5; i++) 2247 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2248 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2249 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2250 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2251 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2252 2253 /* reenable busmastering */ 2254 pci_enable_busmaster(dev); 2255 pci_enable_io(dev, SYS_RES_IOPORT); 2256 #endif 2257 2258 /* reinitialize interface if necessary */ 2259 if (ifp->if_flags & IFF_UP) 2260 re_init(sc); 2261 2262 sc->suspended = 0; 2263 2264 return (0); 2265 } 2266 2267 /* 2268 * Stop all chip I/O so that the kernel's probe routines don't 2269 * get confused by errant DMAs when rebooting. 2270 */ 2271 static void 2272 re_shutdown(device_t dev) 2273 { 2274 struct re_softc *sc = device_get_softc(dev); 2275 2276 re_stop(sc); 2277 } 2278