1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.48 2008/08/17 04:32:34 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #include "opt_polling.h" 115 #include "opt_ethernet.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/interrupt.h> 122 #include <sys/malloc.h> 123 #include <sys/mbuf.h> 124 #include <sys/rman.h> 125 #include <sys/serialize.h> 126 #include <sys/socket.h> 127 #include <sys/sockio.h> 128 #include <sys/sysctl.h> 129 130 #include <net/bpf.h> 131 #include <net/ethernet.h> 132 #include <net/if.h> 133 #include <net/ifq_var.h> 134 #include <net/if_arp.h> 135 #include <net/if_dl.h> 136 #include <net/if_media.h> 137 #include <net/if_types.h> 138 #include <net/vlan/if_vlan_var.h> 139 #include <net/vlan/if_vlan_ether.h> 140 141 #include <dev/netif/mii_layer/mii.h> 142 #include <dev/netif/mii_layer/miivar.h> 143 144 #include <bus/pci/pcidevs.h> 145 #include <bus/pci/pcireg.h> 146 #include <bus/pci/pcivar.h> 147 148 /* "device miibus" required. See GENERIC if you get errors here. */ 149 #include "miibus_if.h" 150 151 #include <dev/netif/re/if_rereg.h> 152 #include <dev/netif/re/if_revar.h> 153 154 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 155 #if 0 156 #define RE_DISABLE_HWCSUM 157 #endif 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static const struct re_type re_devs[] = { 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 164 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 166 "RealTek 8139C+ 10/100BaseTX" }, 167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E, 168 "RealTek 8101E PCIe 10/100baseTX" }, 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1, 170 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2, 172 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3, 174 "RealTek 8168B/8111B PCIe Gigabit Ethernet" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168C, 176 "RealTek 8168C/8111C PCIe Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 178 "RealTek 8169 Gigabit Ethernet" }, 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 180 "RealTek 8169S Single-chip Gigabit Ethernet" }, 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB, 182 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S, 190 "Corega CG-LAPCIGT Gigabit Ethernet" }, 191 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S, 192 "Linksys EG1032 Gigabit Ethernet" }, 193 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S, 194 "US Robotics 997902 Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196 }; 197 198 static const struct re_hwrev re_hwrevs[] = { 199 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" }, 200 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" }, 201 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" }, 202 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" }, 203 { RE_HWREV_8168C, RE_8169, RE_F_PCIE, "8168C" }, 204 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" }, 205 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" }, 206 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" }, 207 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" }, 208 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" }, 209 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" }, 210 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" }, 211 { 0, 0, 0, NULL } 212 }; 213 214 static int re_probe(device_t); 215 static int re_attach(device_t); 216 static int re_detach(device_t); 217 static int re_suspend(device_t); 218 static int re_resume(device_t); 219 static void re_shutdown(device_t); 220 221 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 222 223 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 224 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 225 bus_size_t, int); 226 static int re_allocmem(device_t, struct re_softc *); 227 static int re_newbuf(struct re_softc *, int, struct mbuf *); 228 static int re_rx_list_init(struct re_softc *); 229 static int re_tx_list_init(struct re_softc *); 230 static void re_rxeof(struct re_softc *); 231 static void re_txeof(struct re_softc *); 232 static void re_intr(void *); 233 static void re_tick(void *); 234 static void re_tick_serialized(void *); 235 236 static void re_start(struct ifnet *); 237 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 238 static void re_init(void *); 239 static void re_stop(struct re_softc *); 240 static void re_watchdog(struct ifnet *); 241 static int re_ifmedia_upd(struct ifnet *); 242 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 243 244 static void re_eeprom_putbyte(struct re_softc *, int); 245 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 246 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 247 static int re_gmii_readreg(device_t, int, int); 248 static int re_gmii_writereg(device_t, int, int, int); 249 250 static int re_miibus_readreg(device_t, int, int); 251 static int re_miibus_writereg(device_t, int, int, int); 252 static void re_miibus_statchg(device_t); 253 254 static void re_setmulti(struct re_softc *); 255 static void re_reset(struct re_softc *); 256 257 #ifdef RE_DIAG 258 static int re_diag(struct re_softc *); 259 #endif 260 261 #ifdef DEVICE_POLLING 262 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 263 #endif 264 265 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS); 266 267 static device_method_t re_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, re_probe), 270 DEVMETHOD(device_attach, re_attach), 271 DEVMETHOD(device_detach, re_detach), 272 DEVMETHOD(device_suspend, re_suspend), 273 DEVMETHOD(device_resume, re_resume), 274 DEVMETHOD(device_shutdown, re_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, re_miibus_readreg), 282 DEVMETHOD(miibus_writereg, re_miibus_writereg), 283 DEVMETHOD(miibus_statchg, re_miibus_statchg), 284 285 { 0, 0 } 286 }; 287 288 static driver_t re_driver = { 289 "re", 290 re_methods, 291 sizeof(struct re_softc) 292 }; 293 294 static devclass_t re_devclass; 295 296 DECLARE_DUMMY_MODULE(if_re); 297 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 298 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 299 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 300 301 #define EE_SET(x) \ 302 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 303 304 #define EE_CLR(x) \ 305 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 306 307 /* 308 * Send a read command and address to the EEPROM, check for ACK. 309 */ 310 static void 311 re_eeprom_putbyte(struct re_softc *sc, int addr) 312 { 313 int d, i; 314 315 d = addr | (RE_9346_READ << sc->re_eewidth); 316 317 /* 318 * Feed in each bit and strobe the clock. 319 */ 320 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 321 if (d & i) 322 EE_SET(RE_EE_DATAIN); 323 else 324 EE_CLR(RE_EE_DATAIN); 325 DELAY(100); 326 EE_SET(RE_EE_CLK); 327 DELAY(150); 328 EE_CLR(RE_EE_CLK); 329 DELAY(100); 330 } 331 } 332 333 /* 334 * Read a word of data stored in the EEPROM at address 'addr.' 335 */ 336 static void 337 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 338 { 339 int i; 340 uint16_t word = 0; 341 342 /* 343 * Send address of word we want to read. 344 */ 345 re_eeprom_putbyte(sc, addr); 346 347 /* 348 * Start reading bits from EEPROM. 349 */ 350 for (i = 0x8000; i != 0; i >>= 1) { 351 EE_SET(RE_EE_CLK); 352 DELAY(100); 353 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 354 word |= i; 355 EE_CLR(RE_EE_CLK); 356 DELAY(100); 357 } 358 359 *dest = word; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void 366 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 367 { 368 int i; 369 uint16_t word = 0, *ptr; 370 371 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 372 DELAY(100); 373 374 for (i = 0; i < cnt; i++) { 375 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 376 re_eeprom_getword(sc, off + i, &word); 377 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 378 ptr = (uint16_t *)(dest + (i * 2)); 379 *ptr = word; 380 } 381 382 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 383 } 384 385 static int 386 re_gmii_readreg(device_t dev, int phy, int reg) 387 { 388 struct re_softc *sc = device_get_softc(dev); 389 u_int32_t rval; 390 int i; 391 392 if (phy != 1) 393 return(0); 394 395 /* Let the rgephy driver read the GMEDIASTAT register */ 396 397 if (reg == RE_GMEDIASTAT) 398 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 399 400 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 401 DELAY(1000); 402 403 for (i = 0; i < RE_TIMEOUT; i++) { 404 rval = CSR_READ_4(sc, RE_PHYAR); 405 if (rval & RE_PHYAR_BUSY) 406 break; 407 DELAY(100); 408 } 409 410 if (i == RE_TIMEOUT) { 411 device_printf(dev, "PHY read failed\n"); 412 return(0); 413 } 414 415 return(rval & RE_PHYAR_PHYDATA); 416 } 417 418 static int 419 re_gmii_writereg(device_t dev, int phy, int reg, int data) 420 { 421 struct re_softc *sc = device_get_softc(dev); 422 uint32_t rval; 423 int i; 424 425 CSR_WRITE_4(sc, RE_PHYAR, 426 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 427 DELAY(1000); 428 429 for (i = 0; i < RE_TIMEOUT; i++) { 430 rval = CSR_READ_4(sc, RE_PHYAR); 431 if ((rval & RE_PHYAR_BUSY) == 0) 432 break; 433 DELAY(100); 434 } 435 436 if (i == RE_TIMEOUT) 437 device_printf(dev, "PHY write failed\n"); 438 439 return(0); 440 } 441 442 static int 443 re_miibus_readreg(device_t dev, int phy, int reg) 444 { 445 struct re_softc *sc = device_get_softc(dev); 446 uint16_t rval = 0; 447 uint16_t re8139_reg = 0; 448 449 if (sc->re_type == RE_8169) { 450 rval = re_gmii_readreg(dev, phy, reg); 451 return(rval); 452 } 453 454 /* Pretend the internal PHY is only at address 0 */ 455 if (phy) 456 return(0); 457 458 switch(reg) { 459 case MII_BMCR: 460 re8139_reg = RE_BMCR; 461 break; 462 case MII_BMSR: 463 re8139_reg = RE_BMSR; 464 break; 465 case MII_ANAR: 466 re8139_reg = RE_ANAR; 467 break; 468 case MII_ANER: 469 re8139_reg = RE_ANER; 470 break; 471 case MII_ANLPAR: 472 re8139_reg = RE_LPAR; 473 break; 474 case MII_PHYIDR1: 475 case MII_PHYIDR2: 476 return(0); 477 /* 478 * Allow the rlphy driver to read the media status 479 * register. If we have a link partner which does not 480 * support NWAY, this is the register which will tell 481 * us the results of parallel detection. 482 */ 483 case RE_MEDIASTAT: 484 return(CSR_READ_1(sc, RE_MEDIASTAT)); 485 default: 486 device_printf(dev, "bad phy register\n"); 487 return(0); 488 } 489 rval = CSR_READ_2(sc, re8139_reg); 490 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) { 491 /* 8139C+ has different bit layout. */ 492 rval &= ~(BMCR_LOOP | BMCR_ISO); 493 } 494 return(rval); 495 } 496 497 static int 498 re_miibus_writereg(device_t dev, int phy, int reg, int data) 499 { 500 struct re_softc *sc= device_get_softc(dev); 501 u_int16_t re8139_reg = 0; 502 503 if (sc->re_type == RE_8169) 504 return(re_gmii_writereg(dev, phy, reg, data)); 505 506 /* Pretend the internal PHY is only at address 0 */ 507 if (phy) 508 return(0); 509 510 switch(reg) { 511 case MII_BMCR: 512 re8139_reg = RE_BMCR; 513 if (sc->re_type == RE_8139CPLUS) { 514 /* 8139C+ has different bit layout. */ 515 data &= ~(BMCR_LOOP | BMCR_ISO); 516 } 517 break; 518 case MII_BMSR: 519 re8139_reg = RE_BMSR; 520 break; 521 case MII_ANAR: 522 re8139_reg = RE_ANAR; 523 break; 524 case MII_ANER: 525 re8139_reg = RE_ANER; 526 break; 527 case MII_ANLPAR: 528 re8139_reg = RE_LPAR; 529 break; 530 case MII_PHYIDR1: 531 case MII_PHYIDR2: 532 return(0); 533 default: 534 device_printf(dev, "bad phy register\n"); 535 return(0); 536 } 537 CSR_WRITE_2(sc, re8139_reg, data); 538 return(0); 539 } 540 541 static void 542 re_miibus_statchg(device_t dev) 543 { 544 } 545 546 /* 547 * Program the 64-bit multicast hash filter. 548 */ 549 static void 550 re_setmulti(struct re_softc *sc) 551 { 552 struct ifnet *ifp = &sc->arpcom.ac_if; 553 int h = 0; 554 uint32_t hashes[2] = { 0, 0 }; 555 struct ifmultiaddr *ifma; 556 uint32_t rxfilt; 557 int mcnt = 0; 558 559 rxfilt = CSR_READ_4(sc, RE_RXCFG); 560 561 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 562 rxfilt |= RE_RXCFG_RX_MULTI; 563 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 564 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 565 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 566 return; 567 } 568 569 /* first, zot all the existing hash bits */ 570 CSR_WRITE_4(sc, RE_MAR0, 0); 571 CSR_WRITE_4(sc, RE_MAR4, 0); 572 573 /* now program new ones */ 574 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 575 if (ifma->ifma_addr->sa_family != AF_LINK) 576 continue; 577 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 578 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 579 if (h < 32) 580 hashes[0] |= (1 << h); 581 else 582 hashes[1] |= (1 << (h - 32)); 583 mcnt++; 584 } 585 586 if (mcnt) 587 rxfilt |= RE_RXCFG_RX_MULTI; 588 else 589 rxfilt &= ~RE_RXCFG_RX_MULTI; 590 591 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 592 593 /* 594 * For some unfathomable reason, RealTek decided to reverse 595 * the order of the multicast hash registers in the PCI Express 596 * parts. This means we have to write the hash pattern in reverse 597 * order for those devices. 598 */ 599 if (sc->re_flags & RE_F_PCIE) { 600 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); 601 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); 602 } else { 603 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 605 } 606 } 607 608 static void 609 re_reset(struct re_softc *sc) 610 { 611 int i; 612 613 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 614 615 for (i = 0; i < RE_TIMEOUT; i++) { 616 DELAY(10); 617 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 618 break; 619 } 620 if (i == RE_TIMEOUT) 621 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 622 623 CSR_WRITE_1(sc, 0x82, 1); 624 } 625 626 #ifdef RE_DIAG 627 /* 628 * The following routine is designed to test for a defect on some 629 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 630 * lines connected to the bus, however for a 32-bit only card, they 631 * should be pulled high. The result of this defect is that the 632 * NIC will not work right if you plug it into a 64-bit slot: DMA 633 * operations will be done with 64-bit transfers, which will fail 634 * because the 64-bit data lines aren't connected. 635 * 636 * There's no way to work around this (short of talking a soldering 637 * iron to the board), however we can detect it. The method we use 638 * here is to put the NIC into digital loopback mode, set the receiver 639 * to promiscuous mode, and then try to send a frame. We then compare 640 * the frame data we sent to what was received. If the data matches, 641 * then the NIC is working correctly, otherwise we know the user has 642 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 643 * slot. In the latter case, there's no way the NIC can work correctly, 644 * so we print out a message on the console and abort the device attach. 645 */ 646 647 static int 648 re_diag(struct re_softc *sc) 649 { 650 struct ifnet *ifp = &sc->arpcom.ac_if; 651 struct mbuf *m0; 652 struct ether_header *eh; 653 struct re_desc *cur_rx; 654 uint16_t status; 655 uint32_t rxstat; 656 int total_len, i, error = 0, phyaddr; 657 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 658 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 659 660 /* Allocate a single mbuf */ 661 662 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 663 if (m0 == NULL) 664 return(ENOBUFS); 665 666 /* 667 * Initialize the NIC in test mode. This sets the chip up 668 * so that it can send and receive frames, but performs the 669 * following special functions: 670 * - Puts receiver in promiscuous mode 671 * - Enables digital loopback mode 672 * - Leaves interrupts turned off 673 */ 674 675 ifp->if_flags |= IFF_PROMISC; 676 sc->re_testmode = 1; 677 re_reset(sc); 678 re_init(sc); 679 sc->re_link = 1; 680 if (sc->re_type == RE_8169) 681 phyaddr = 1; 682 else 683 phyaddr = 0; 684 685 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 686 for (i = 0; i < RE_TIMEOUT; i++) { 687 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 688 if (!(status & BMCR_RESET)) 689 break; 690 } 691 692 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 693 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 694 695 DELAY(100000); 696 697 /* Put some data in the mbuf */ 698 699 eh = mtod(m0, struct ether_header *); 700 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 701 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 702 eh->ether_type = htons(ETHERTYPE_IP); 703 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 704 705 /* 706 * Queue the packet, start transmission. 707 * Note: ifq_handoff() ultimately calls re_start() for us. 708 */ 709 710 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 711 error = ifq_handoff(ifp, m0, NULL); 712 if (error) { 713 m0 = NULL; 714 goto done; 715 } 716 m0 = NULL; 717 718 /* Wait for it to propagate through the chip */ 719 720 DELAY(100000); 721 for (i = 0; i < RE_TIMEOUT; i++) { 722 status = CSR_READ_2(sc, RE_ISR); 723 CSR_WRITE_2(sc, RE_ISR, status); 724 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 725 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 726 break; 727 DELAY(10); 728 } 729 730 if (i == RE_TIMEOUT) { 731 if_printf(ifp, "diagnostic failed to receive packet " 732 "in loopback mode\n"); 733 error = EIO; 734 goto done; 735 } 736 737 /* 738 * The packet should have been dumped into the first 739 * entry in the RX DMA ring. Grab it from there. 740 */ 741 742 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 743 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 744 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 745 BUS_DMASYNC_POSTWRITE); 746 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 747 748 m0 = sc->re_ldata.re_rx_mbuf[0]; 749 sc->re_ldata.re_rx_mbuf[0] = NULL; 750 eh = mtod(m0, struct ether_header *); 751 752 cur_rx = &sc->re_ldata.re_rx_list[0]; 753 total_len = RE_RXBYTES(cur_rx); 754 rxstat = le32toh(cur_rx->re_cmdstat); 755 756 if (total_len != ETHER_MIN_LEN) { 757 if_printf(ifp, "diagnostic failed, received short packet\n"); 758 error = EIO; 759 goto done; 760 } 761 762 /* Test that the received packet data matches what we sent. */ 763 764 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 765 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 766 be16toh(eh->ether_type) != ETHERTYPE_IP) { 767 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 768 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 769 dst, ":", src, ":", ETHERTYPE_IP); 770 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 771 eh->ether_dhost, ":", eh->ether_shost, ":", 772 ntohs(eh->ether_type)); 773 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 774 "into a 64-bit PCI slot.\n"); 775 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 776 "for proper operation.\n"); 777 if_printf(ifp, "Read the re(4) man page for more details.\n"); 778 error = EIO; 779 } 780 781 done: 782 /* Turn interface off, release resources */ 783 784 sc->re_testmode = 0; 785 sc->re_link = 0; 786 ifp->if_flags &= ~IFF_PROMISC; 787 re_stop(sc); 788 if (m0 != NULL) 789 m_freem(m0); 790 791 return (error); 792 } 793 #endif /* RE_DIAG */ 794 795 /* 796 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 797 * IDs against our list and return a device name if we find a match. 798 */ 799 static int 800 re_probe(device_t dev) 801 { 802 const struct re_type *t; 803 struct re_softc *sc; 804 int rid; 805 uint32_t hwrev; 806 uint16_t vendor, product; 807 808 vendor = pci_get_vendor(dev); 809 product = pci_get_device(dev); 810 811 /* 812 * Only attach to rev.3 of the Linksys EG1032 adapter. 813 * Rev.2 is supported by sk(4). 814 */ 815 if (vendor == PCI_VENDOR_LINKSYS && 816 product == PCI_PRODUCT_LINKSYS_EG1032 && 817 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 818 return ENXIO; 819 820 for (t = re_devs; t->re_name != NULL; t++) { 821 if (product == t->re_did && vendor == t->re_vid) 822 break; 823 } 824 825 /* 826 * Check if we found a RealTek device. 827 */ 828 if (t->re_name == NULL) 829 return(ENXIO); 830 831 /* 832 * Temporarily map the I/O space so we can read the chip ID register. 833 */ 834 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 835 rid = RE_PCI_LOIO; 836 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 837 RF_ACTIVE); 838 if (sc->re_res == NULL) { 839 device_printf(dev, "couldn't map ports/memory\n"); 840 kfree(sc, M_TEMP); 841 return(ENXIO); 842 } 843 844 sc->re_btag = rman_get_bustag(sc->re_res); 845 sc->re_bhandle = rman_get_bushandle(sc->re_res); 846 847 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 848 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 849 kfree(sc, M_TEMP); 850 851 /* 852 * and continue matching for the specific chip... 853 */ 854 for (; t->re_name != NULL; t++) { 855 if (product == t->re_did && vendor == t->re_vid && 856 t->re_basetype == hwrev) { 857 device_set_desc(dev, t->re_name); 858 return(0); 859 } 860 } 861 862 if (bootverbose) 863 kprintf("re: unknown hwrev %#x\n", hwrev); 864 return(ENXIO); 865 } 866 867 /* 868 * This routine takes the segment list provided as the result of 869 * a bus_dma_map_load() operation and assigns the addresses/lengths 870 * to RealTek DMA descriptors. This can be called either by the RX 871 * code or the TX code. In the RX case, we'll probably wind up mapping 872 * at most one segment. For the TX case, there could be any number of 873 * segments since TX packets may span multiple mbufs. In either case, 874 * if the number of segments is larger than the re_maxsegs limit 875 * specified by the caller, we abort the mapping operation. Sadly, 876 * whoever designed the buffer mapping API did not provide a way to 877 * return an error from here, so we have to fake it a bit. 878 */ 879 880 static void 881 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 882 bus_size_t mapsize, int error) 883 { 884 struct re_dmaload_arg *ctx; 885 struct re_desc *d = NULL; 886 int i = 0, idx; 887 uint32_t cmdstat; 888 889 if (error) 890 return; 891 892 ctx = arg; 893 894 /* Signal error to caller if there's too many segments */ 895 if (nseg > ctx->re_maxsegs) { 896 ctx->re_maxsegs = 0; 897 return; 898 } 899 900 /* 901 * Map the segment array into descriptors. Note that we set the 902 * start-of-frame and end-of-frame markers for either TX or RX, but 903 * they really only have meaning in the TX case. (In the RX case, 904 * it's the chip that tells us where packets begin and end.) 905 * We also keep track of the end of the ring and set the 906 * end-of-ring bits as needed, and we set the ownership bits 907 * in all except the very first descriptor. (The caller will 908 * set this descriptor later when it start transmission or 909 * reception.) 910 */ 911 idx = ctx->re_idx; 912 for (;;) { 913 d = &ctx->re_ring[idx]; 914 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 915 ctx->re_maxsegs = 0; 916 return; 917 } 918 cmdstat = segs[i].ds_len; 919 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 920 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 921 if (i == 0) 922 cmdstat |= RE_TDESC_CMD_SOF; 923 else 924 cmdstat |= RE_TDESC_CMD_OWN; 925 if (idx == (RE_RX_DESC_CNT - 1)) 926 cmdstat |= RE_TDESC_CMD_EOR; 927 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 928 i++; 929 if (i == nseg) 930 break; 931 RE_DESC_INC(idx); 932 } 933 934 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 935 ctx->re_maxsegs = nseg; 936 ctx->re_idx = idx; 937 } 938 939 /* 940 * Map a single buffer address. 941 */ 942 943 static void 944 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 945 { 946 uint32_t *addr; 947 948 if (error) 949 return; 950 951 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 952 addr = arg; 953 *addr = segs->ds_addr; 954 } 955 956 static int 957 re_allocmem(device_t dev, struct re_softc *sc) 958 { 959 int error, i, nseg; 960 961 /* 962 * Allocate map for RX mbufs. 963 */ 964 nseg = 32; 965 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 966 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 967 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 968 &sc->re_ldata.re_mtag); 969 if (error) { 970 device_printf(dev, "could not allocate dma tag\n"); 971 return(error); 972 } 973 974 /* 975 * Allocate map for TX descriptor list. 976 */ 977 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 978 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 979 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 980 &sc->re_ldata.re_tx_list_tag); 981 if (error) { 982 device_printf(dev, "could not allocate dma tag\n"); 983 return(error); 984 } 985 986 /* Allocate DMA'able memory for the TX ring */ 987 988 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 989 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 990 &sc->re_ldata.re_tx_list_map); 991 if (error) { 992 device_printf(dev, "could not allocate TX ring\n"); 993 return(error); 994 } 995 996 /* Load the map for the TX ring. */ 997 998 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 999 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 1000 RE_TX_LIST_SZ, re_dma_map_addr, 1001 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 1002 if (error) { 1003 device_printf(dev, "could not get address of TX ring\n"); 1004 return(error); 1005 } 1006 1007 /* Create DMA maps for TX buffers */ 1008 1009 for (i = 0; i < RE_TX_DESC_CNT; i++) { 1010 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1011 &sc->re_ldata.re_tx_dmamap[i]); 1012 if (error) { 1013 device_printf(dev, "can't create DMA map for TX\n"); 1014 return(error); 1015 } 1016 } 1017 1018 /* 1019 * Allocate map for RX descriptor list. 1020 */ 1021 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 1022 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1023 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1024 &sc->re_ldata.re_rx_list_tag); 1025 if (error) { 1026 device_printf(dev, "could not allocate dma tag\n"); 1027 return(error); 1028 } 1029 1030 /* Allocate DMA'able memory for the RX ring */ 1031 1032 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1033 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1034 &sc->re_ldata.re_rx_list_map); 1035 if (error) { 1036 device_printf(dev, "could not allocate RX ring\n"); 1037 return(error); 1038 } 1039 1040 /* Load the map for the RX ring. */ 1041 1042 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1043 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 1044 RE_RX_LIST_SZ, re_dma_map_addr, 1045 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 1046 if (error) { 1047 device_printf(dev, "could not get address of RX ring\n"); 1048 return(error); 1049 } 1050 1051 /* Create DMA maps for RX buffers */ 1052 1053 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1054 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1055 &sc->re_ldata.re_rx_dmamap[i]); 1056 if (error) { 1057 device_printf(dev, "can't create DMA map for RX\n"); 1058 return(ENOMEM); 1059 } 1060 } 1061 1062 return(0); 1063 } 1064 1065 /* 1066 * Attach the interface. Allocate softc structures, do ifmedia 1067 * setup and ethernet/BPF attach. 1068 */ 1069 static int 1070 re_attach(device_t dev) 1071 { 1072 struct re_softc *sc = device_get_softc(dev); 1073 struct ifnet *ifp; 1074 const struct re_hwrev *hw_rev; 1075 uint8_t eaddr[ETHER_ADDR_LEN]; 1076 uint16_t as[ETHER_ADDR_LEN / 2]; 1077 uint16_t re_did = 0; 1078 uint32_t hwrev; 1079 int error = 0, rid, i; 1080 1081 callout_init(&sc->re_timer); 1082 #ifdef RE_DIAG 1083 sc->re_dev = dev; 1084 #endif 1085 1086 RE_ENABLE_TX_MODERATION(sc); 1087 1088 sysctl_ctx_init(&sc->re_sysctl_ctx); 1089 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1090 SYSCTL_STATIC_CHILDREN(_hw), 1091 OID_AUTO, 1092 device_get_nameunit(dev), 1093 CTLFLAG_RD, 0, ""); 1094 if (sc->re_sysctl_tree == NULL) { 1095 device_printf(dev, "can't add sysctl node\n"); 1096 error = ENXIO; 1097 goto fail; 1098 } 1099 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1100 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1101 OID_AUTO, "tx_moderation", 1102 CTLTYPE_INT | CTLFLAG_RW, 1103 sc, 0, re_sysctl_tx_moderation, "I", 1104 "Enable/Disable TX moderation"); 1105 1106 #ifndef BURN_BRIDGES 1107 /* 1108 * Handle power management nonsense. 1109 */ 1110 1111 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1112 uint32_t membase, irq; 1113 1114 /* Save important PCI config data. */ 1115 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1116 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1117 1118 /* Reset the power state. */ 1119 device_printf(dev, "chip is in D%d power mode " 1120 "-- setting to D0\n", pci_get_powerstate(dev)); 1121 1122 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1123 1124 /* Restore PCI config data. */ 1125 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1126 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1127 } 1128 #endif 1129 /* 1130 * Map control/status registers. 1131 */ 1132 pci_enable_busmaster(dev); 1133 1134 rid = RE_PCI_LOIO; 1135 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1136 RF_ACTIVE); 1137 1138 if (sc->re_res == NULL) { 1139 device_printf(dev, "couldn't map ports\n"); 1140 error = ENXIO; 1141 goto fail; 1142 } 1143 1144 sc->re_btag = rman_get_bustag(sc->re_res); 1145 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1146 1147 /* Allocate interrupt */ 1148 rid = 0; 1149 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1150 RF_SHAREABLE | RF_ACTIVE); 1151 1152 if (sc->re_irq == NULL) { 1153 device_printf(dev, "couldn't map interrupt\n"); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 1158 /* Reset the adapter. */ 1159 re_reset(sc); 1160 1161 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1162 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1163 if (hw_rev->re_rev == hwrev) { 1164 sc->re_type = hw_rev->re_type; 1165 sc->re_flags = hw_rev->re_flags; 1166 break; 1167 } 1168 } 1169 1170 sc->re_eewidth = 6; 1171 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1172 if (re_did != 0x8129) 1173 sc->re_eewidth = 8; 1174 1175 /* 1176 * Get station address from the EEPROM. 1177 */ 1178 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 1179 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1180 as[i] = le16toh(as[i]); 1181 bcopy(as, eaddr, sizeof(eaddr)); 1182 1183 if (sc->re_type == RE_8169) { 1184 /* Set RX length mask */ 1185 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1186 sc->re_txstart = RE_GTXSTART; 1187 } else { 1188 /* Set RX length mask */ 1189 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1190 sc->re_txstart = RE_TXSTART; 1191 } 1192 1193 /* 1194 * Allocate the parent bus DMA tag appropriate for PCI. 1195 */ 1196 #define RE_NSEG_NEW 32 1197 error = bus_dma_tag_create(NULL, /* parent */ 1198 1, 0, /* alignment, boundary */ 1199 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, NULL, /* filter, filterarg */ 1202 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1203 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1204 BUS_DMA_ALLOCNOW, /* flags */ 1205 &sc->re_parent_tag); 1206 if (error) 1207 goto fail; 1208 1209 error = re_allocmem(dev, sc); 1210 1211 if (error) 1212 goto fail; 1213 1214 /* Do MII setup */ 1215 if (mii_phy_probe(dev, &sc->re_miibus, 1216 re_ifmedia_upd, re_ifmedia_sts)) { 1217 device_printf(dev, "MII without any phy!\n"); 1218 error = ENXIO; 1219 goto fail; 1220 } 1221 1222 ifp = &sc->arpcom.ac_if; 1223 ifp->if_softc = sc; 1224 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1225 ifp->if_mtu = ETHERMTU; 1226 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1227 ifp->if_ioctl = re_ioctl; 1228 ifp->if_start = re_start; 1229 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1230 if (hwrev != RE_HWREV_8168C) /* XXX does not work yet */ 1231 ifp->if_capabilities |= IFCAP_HWCSUM; 1232 #ifdef DEVICE_POLLING 1233 ifp->if_poll = re_poll; 1234 #endif 1235 ifp->if_watchdog = re_watchdog; 1236 ifp->if_init = re_init; 1237 if (sc->re_type == RE_8169) 1238 ifp->if_baudrate = 1000000000; 1239 else 1240 ifp->if_baudrate = 100000000; 1241 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1242 ifq_set_ready(&ifp->if_snd); 1243 1244 #ifdef RE_DISABLE_HWCSUM 1245 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1246 ifp->if_hwassist = 0; 1247 #else 1248 ifp->if_capenable = ifp->if_capabilities; 1249 if (ifp->if_capabilities & IFCAP_HWCSUM) 1250 ifp->if_hwassist = RE_CSUM_FEATURES; 1251 else 1252 ifp->if_hwassist = 0; 1253 #endif /* RE_DISABLE_HWCSUM */ 1254 1255 /* 1256 * Call MI attach routine. 1257 */ 1258 ether_ifattach(ifp, eaddr, NULL); 1259 1260 #ifdef RE_DIAG 1261 /* 1262 * Perform hardware diagnostic on the original RTL8169. 1263 * Some 32-bit cards were incorrectly wired and would 1264 * malfunction if plugged into a 64-bit slot. 1265 */ 1266 if (hwrev == RE_HWREV_8169) { 1267 lwkt_serialize_enter(ifp->if_serializer); 1268 error = re_diag(sc); 1269 lwkt_serialize_exit(ifp->if_serializer); 1270 1271 if (error) { 1272 device_printf(dev, "hardware diagnostic failure\n"); 1273 ether_ifdetach(ifp); 1274 goto fail; 1275 } 1276 } 1277 #endif /* RE_DIAG */ 1278 1279 /* Hook interrupt last to avoid having to lock softc */ 1280 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1281 &sc->re_intrhand, ifp->if_serializer); 1282 1283 if (error) { 1284 device_printf(dev, "couldn't set up irq\n"); 1285 ether_ifdetach(ifp); 1286 goto fail; 1287 } 1288 1289 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); 1290 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1291 1292 fail: 1293 if (error) 1294 re_detach(dev); 1295 1296 return (error); 1297 } 1298 1299 /* 1300 * Shutdown hardware and free up resources. This can be called any 1301 * time after the mutex has been initialized. It is called in both 1302 * the error case in attach and the normal detach case so it needs 1303 * to be careful about only freeing resources that have actually been 1304 * allocated. 1305 */ 1306 static int 1307 re_detach(device_t dev) 1308 { 1309 struct re_softc *sc = device_get_softc(dev); 1310 struct ifnet *ifp = &sc->arpcom.ac_if; 1311 int i; 1312 1313 /* These should only be active if attach succeeded */ 1314 if (device_is_attached(dev)) { 1315 lwkt_serialize_enter(ifp->if_serializer); 1316 re_stop(sc); 1317 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1318 lwkt_serialize_exit(ifp->if_serializer); 1319 1320 ether_ifdetach(ifp); 1321 } 1322 if (sc->re_miibus) 1323 device_delete_child(dev, sc->re_miibus); 1324 bus_generic_detach(dev); 1325 1326 if (sc->re_irq) 1327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1328 if (sc->re_res) { 1329 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1330 sc->re_res); 1331 } 1332 1333 /* Unload and free the RX DMA ring memory and map */ 1334 1335 if (sc->re_ldata.re_rx_list_tag) { 1336 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1337 sc->re_ldata.re_rx_list_map); 1338 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1339 sc->re_ldata.re_rx_list, 1340 sc->re_ldata.re_rx_list_map); 1341 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1342 } 1343 1344 /* Unload and free the TX DMA ring memory and map */ 1345 1346 if (sc->re_ldata.re_tx_list_tag) { 1347 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1348 sc->re_ldata.re_tx_list_map); 1349 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1350 sc->re_ldata.re_tx_list, 1351 sc->re_ldata.re_tx_list_map); 1352 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1353 } 1354 1355 /* Destroy all the RX and TX buffer maps */ 1356 1357 if (sc->re_ldata.re_mtag) { 1358 for (i = 0; i < RE_TX_DESC_CNT; i++) 1359 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1360 sc->re_ldata.re_tx_dmamap[i]); 1361 for (i = 0; i < RE_RX_DESC_CNT; i++) 1362 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1363 sc->re_ldata.re_rx_dmamap[i]); 1364 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1365 } 1366 1367 /* Unload and free the stats buffer and map */ 1368 1369 if (sc->re_ldata.re_stag) { 1370 bus_dmamap_unload(sc->re_ldata.re_stag, 1371 sc->re_ldata.re_rx_list_map); 1372 bus_dmamem_free(sc->re_ldata.re_stag, 1373 sc->re_ldata.re_stats, 1374 sc->re_ldata.re_smap); 1375 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1376 } 1377 1378 if (sc->re_parent_tag) 1379 bus_dma_tag_destroy(sc->re_parent_tag); 1380 1381 return(0); 1382 } 1383 1384 static int 1385 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1386 { 1387 struct re_dmaload_arg arg; 1388 struct mbuf *n = NULL; 1389 int error; 1390 1391 if (m == NULL) { 1392 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1393 if (n == NULL) 1394 return(ENOBUFS); 1395 m = n; 1396 } else 1397 m->m_data = m->m_ext.ext_buf; 1398 1399 m->m_len = m->m_pkthdr.len = MCLBYTES; 1400 1401 /* 1402 * NOTE: 1403 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1404 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1405 */ 1406 1407 arg.sc = sc; 1408 arg.re_idx = idx; 1409 arg.re_maxsegs = 1; 1410 arg.re_flags = 0; 1411 arg.re_ring = sc->re_ldata.re_rx_list; 1412 1413 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1414 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1415 &arg, BUS_DMA_NOWAIT); 1416 if (error || arg.re_maxsegs != 1) { 1417 if (n != NULL) 1418 m_freem(n); 1419 return (ENOMEM); 1420 } 1421 1422 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1423 sc->re_ldata.re_rx_mbuf[idx] = m; 1424 1425 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1426 BUS_DMASYNC_PREREAD); 1427 1428 return(0); 1429 } 1430 1431 static int 1432 re_tx_list_init(struct re_softc *sc) 1433 { 1434 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1435 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1436 1437 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1438 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1439 sc->re_ldata.re_tx_prodidx = 0; 1440 sc->re_ldata.re_tx_considx = 0; 1441 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1442 1443 return(0); 1444 } 1445 1446 static int 1447 re_rx_list_init(struct re_softc *sc) 1448 { 1449 int i, error; 1450 1451 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1452 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1453 1454 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1455 error = re_newbuf(sc, i, NULL); 1456 if (error) 1457 return(error); 1458 } 1459 1460 /* Flush the RX descriptors */ 1461 1462 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1463 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1464 1465 sc->re_ldata.re_rx_prodidx = 0; 1466 sc->re_head = sc->re_tail = NULL; 1467 1468 return(0); 1469 } 1470 1471 /* 1472 * RX handler for C+ and 8169. For the gigE chips, we support 1473 * the reception of jumbo frames that have been fragmented 1474 * across multiple 2K mbuf cluster buffers. 1475 */ 1476 static void 1477 re_rxeof(struct re_softc *sc) 1478 { 1479 struct ifnet *ifp = &sc->arpcom.ac_if; 1480 struct mbuf *m; 1481 struct re_desc *cur_rx; 1482 uint32_t rxstat, rxvlan; 1483 int i, total_len; 1484 #ifdef ETHER_INPUT_CHAIN 1485 struct mbuf_chain chain[MAXCPU]; 1486 #endif 1487 1488 /* Invalidate the descriptor memory */ 1489 1490 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1491 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1492 1493 #ifdef ETHER_INPUT_CHAIN 1494 ether_input_chain_init(chain); 1495 #endif 1496 1497 for (i = sc->re_ldata.re_rx_prodidx; 1498 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1499 cur_rx = &sc->re_ldata.re_rx_list[i]; 1500 m = sc->re_ldata.re_rx_mbuf[i]; 1501 total_len = RE_RXBYTES(cur_rx); 1502 rxstat = le32toh(cur_rx->re_cmdstat); 1503 rxvlan = le32toh(cur_rx->re_vlanctl); 1504 1505 /* Invalidate the RX mbuf and unload its map */ 1506 1507 bus_dmamap_sync(sc->re_ldata.re_mtag, 1508 sc->re_ldata.re_rx_dmamap[i], 1509 BUS_DMASYNC_POSTWRITE); 1510 bus_dmamap_unload(sc->re_ldata.re_mtag, 1511 sc->re_ldata.re_rx_dmamap[i]); 1512 1513 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1514 m->m_len = MCLBYTES - ETHER_ALIGN; 1515 if (sc->re_head == NULL) { 1516 sc->re_head = sc->re_tail = m; 1517 } else { 1518 sc->re_tail->m_next = m; 1519 sc->re_tail = m; 1520 } 1521 re_newbuf(sc, i, NULL); 1522 continue; 1523 } 1524 1525 /* 1526 * NOTE: for the 8139C+, the frame length field 1527 * is always 12 bits in size, but for the gigE chips, 1528 * it is 13 bits (since the max RX frame length is 16K). 1529 * Unfortunately, all 32 bits in the status word 1530 * were already used, so to make room for the extra 1531 * length bit, RealTek took out the 'frame alignment 1532 * error' bit and shifted the other status bits 1533 * over one slot. The OWN, EOR, FS and LS bits are 1534 * still in the same places. We have already extracted 1535 * the frame length and checked the OWN bit, so rather 1536 * than using an alternate bit mapping, we shift the 1537 * status bits one space to the right so we can evaluate 1538 * them using the 8169 status as though it was in the 1539 * same format as that of the 8139C+. 1540 */ 1541 if (sc->re_type == RE_8169) 1542 rxstat >>= 1; 1543 1544 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1545 ifp->if_ierrors++; 1546 /* 1547 * If this is part of a multi-fragment packet, 1548 * discard all the pieces. 1549 */ 1550 if (sc->re_head != NULL) { 1551 m_freem(sc->re_head); 1552 sc->re_head = sc->re_tail = NULL; 1553 } 1554 re_newbuf(sc, i, m); 1555 continue; 1556 } 1557 1558 /* 1559 * If allocating a replacement mbuf fails, 1560 * reload the current one. 1561 */ 1562 1563 if (re_newbuf(sc, i, NULL)) { 1564 ifp->if_ierrors++; 1565 if (sc->re_head != NULL) { 1566 m_freem(sc->re_head); 1567 sc->re_head = sc->re_tail = NULL; 1568 } 1569 re_newbuf(sc, i, m); 1570 continue; 1571 } 1572 1573 if (sc->re_head != NULL) { 1574 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1575 /* 1576 * Special case: if there's 4 bytes or less 1577 * in this buffer, the mbuf can be discarded: 1578 * the last 4 bytes is the CRC, which we don't 1579 * care about anyway. 1580 */ 1581 if (m->m_len <= ETHER_CRC_LEN) { 1582 sc->re_tail->m_len -= 1583 (ETHER_CRC_LEN - m->m_len); 1584 m_freem(m); 1585 } else { 1586 m->m_len -= ETHER_CRC_LEN; 1587 sc->re_tail->m_next = m; 1588 } 1589 m = sc->re_head; 1590 sc->re_head = sc->re_tail = NULL; 1591 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1592 } else 1593 m->m_pkthdr.len = m->m_len = 1594 (total_len - ETHER_CRC_LEN); 1595 1596 ifp->if_ipackets++; 1597 m->m_pkthdr.rcvif = ifp; 1598 1599 /* Do RX checksumming if enabled */ 1600 1601 if (ifp->if_capenable & IFCAP_RXCSUM) { 1602 1603 /* Check IP header checksum */ 1604 if (rxstat & RE_RDESC_STAT_PROTOID) 1605 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1606 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1607 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1608 1609 /* Check TCP/UDP checksum */ 1610 if ((RE_TCPPKT(rxstat) && 1611 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1612 (RE_UDPPKT(rxstat) && 1613 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1614 m->m_pkthdr.csum_flags |= 1615 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1616 CSUM_FRAG_NOT_CHECKED; 1617 m->m_pkthdr.csum_data = 0xffff; 1618 } 1619 } 1620 1621 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1622 m->m_flags |= M_VLANTAG; 1623 m->m_pkthdr.ether_vlantag = 1624 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)); 1625 } 1626 #ifdef ETHER_INPUT_CHAIN 1627 ether_input_chain2(ifp, m, chain); 1628 #else 1629 ifp->if_input(ifp, m); 1630 #endif 1631 } 1632 1633 #ifdef ETHER_INPUT_CHAIN 1634 ether_input_dispatch(chain); 1635 #endif 1636 1637 /* Flush the RX DMA ring */ 1638 1639 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1640 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1641 1642 sc->re_ldata.re_rx_prodidx = i; 1643 } 1644 1645 static void 1646 re_txeof(struct re_softc *sc) 1647 { 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 uint32_t txstat; 1650 int idx; 1651 1652 /* Invalidate the TX descriptor list */ 1653 1654 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1655 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 1656 1657 for (idx = sc->re_ldata.re_tx_considx; 1658 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) { 1659 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1660 if (txstat & RE_TDESC_CMD_OWN) 1661 break; 1662 1663 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 1664 1665 /* 1666 * We only stash mbufs in the last descriptor 1667 * in a fragment chain, which also happens to 1668 * be the only place where the TX status bits 1669 * are valid. 1670 */ 1671 if (txstat & RE_TDESC_CMD_EOF) { 1672 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1673 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1674 bus_dmamap_unload(sc->re_ldata.re_mtag, 1675 sc->re_ldata.re_tx_dmamap[idx]); 1676 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1677 RE_TDESC_STAT_COLCNT)) 1678 ifp->if_collisions++; 1679 if (txstat & RE_TDESC_STAT_TXERRSUM) 1680 ifp->if_oerrors++; 1681 else 1682 ifp->if_opackets++; 1683 } 1684 sc->re_ldata.re_tx_free++; 1685 } 1686 1687 /* No changes made to the TX ring, so no flush needed */ 1688 if (sc->re_ldata.re_tx_free) { 1689 sc->re_ldata.re_tx_considx = idx; 1690 ifp->if_flags &= ~IFF_OACTIVE; 1691 ifp->if_timer = 0; 1692 } 1693 1694 /* 1695 * Some chips will ignore a second TX request issued while an 1696 * existing transmission is in progress. If the transmitter goes 1697 * idle but there are still packets waiting to be sent, we need 1698 * to restart the channel here to flush them out. This only seems 1699 * to be required with the PCIe devices. 1700 */ 1701 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1702 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 1703 1704 /* 1705 * If not all descriptors have been released reaped yet, 1706 * reload the timer so that we will eventually get another 1707 * interrupt that will cause us to re-enter this routine. 1708 * This is done in case the transmitter has gone idle. 1709 */ 1710 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1711 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1712 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1713 } 1714 1715 static void 1716 re_tick(void *xsc) 1717 { 1718 struct re_softc *sc = xsc; 1719 1720 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1721 re_tick_serialized(xsc); 1722 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1723 } 1724 1725 static void 1726 re_tick_serialized(void *xsc) 1727 { 1728 struct re_softc *sc = xsc; 1729 struct ifnet *ifp = &sc->arpcom.ac_if; 1730 struct mii_data *mii; 1731 1732 ASSERT_SERIALIZED(ifp->if_serializer); 1733 1734 mii = device_get_softc(sc->re_miibus); 1735 mii_tick(mii); 1736 if (sc->re_link) { 1737 if (!(mii->mii_media_status & IFM_ACTIVE)) 1738 sc->re_link = 0; 1739 } else { 1740 if (mii->mii_media_status & IFM_ACTIVE && 1741 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1742 sc->re_link = 1; 1743 if (!ifq_is_empty(&ifp->if_snd)) 1744 if_devstart(ifp); 1745 } 1746 } 1747 1748 callout_reset(&sc->re_timer, hz, re_tick, sc); 1749 } 1750 1751 #ifdef DEVICE_POLLING 1752 1753 static void 1754 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1755 { 1756 struct re_softc *sc = ifp->if_softc; 1757 1758 ASSERT_SERIALIZED(ifp->if_serializer); 1759 1760 switch(cmd) { 1761 case POLL_REGISTER: 1762 /* disable interrupts */ 1763 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1764 break; 1765 case POLL_DEREGISTER: 1766 /* enable interrupts */ 1767 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 1768 break; 1769 default: 1770 sc->rxcycles = count; 1771 re_rxeof(sc); 1772 re_txeof(sc); 1773 1774 if (!ifq_is_empty(&ifp->if_snd)) 1775 if_devstart(ifp); 1776 1777 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1778 uint16_t status; 1779 1780 status = CSR_READ_2(sc, RE_ISR); 1781 if (status == 0xffff) 1782 return; 1783 if (status) 1784 CSR_WRITE_2(sc, RE_ISR, status); 1785 1786 /* 1787 * XXX check behaviour on receiver stalls. 1788 */ 1789 1790 if (status & RE_ISR_SYSTEM_ERR) { 1791 re_reset(sc); 1792 re_init(sc); 1793 } 1794 } 1795 break; 1796 } 1797 } 1798 #endif /* DEVICE_POLLING */ 1799 1800 static void 1801 re_intr(void *arg) 1802 { 1803 struct re_softc *sc = arg; 1804 struct ifnet *ifp = &sc->arpcom.ac_if; 1805 uint16_t status; 1806 1807 ASSERT_SERIALIZED(ifp->if_serializer); 1808 1809 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1810 return; 1811 1812 for (;;) { 1813 status = CSR_READ_2(sc, RE_ISR); 1814 /* If the card has gone away the read returns 0xffff. */ 1815 if (status == 0xffff) 1816 break; 1817 if (status) 1818 CSR_WRITE_2(sc, RE_ISR, status); 1819 1820 if ((status & sc->re_intrs) == 0) 1821 break; 1822 1823 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW)) 1824 re_rxeof(sc); 1825 1826 if ((status & sc->re_tx_ack) || 1827 (status & RE_ISR_TX_ERR) || 1828 (status & RE_ISR_TX_DESC_UNAVAIL)) 1829 re_txeof(sc); 1830 1831 if (status & RE_ISR_SYSTEM_ERR) { 1832 re_reset(sc); 1833 re_init(sc); 1834 } 1835 1836 if (status & RE_ISR_LINKCHG) { 1837 callout_stop(&sc->re_timer); 1838 re_tick_serialized(sc); 1839 } 1840 } 1841 1842 if (!ifq_is_empty(&ifp->if_snd)) 1843 if_devstart(ifp); 1844 } 1845 1846 static int 1847 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1848 { 1849 struct ifnet *ifp = &sc->arpcom.ac_if; 1850 struct mbuf *m, *m_new = NULL; 1851 struct re_dmaload_arg arg; 1852 bus_dmamap_t map; 1853 int error; 1854 1855 KASSERT(sc->re_ldata.re_tx_free > 4, ("not enough free TX desc\n")); 1856 1857 *called_defrag = 0; 1858 m = *m_head; 1859 1860 /* 1861 * Set up checksum offload. Note: checksum offload bits must 1862 * appear in all descriptors of a multi-descriptor transmit 1863 * attempt. (This is according to testing done with an 8169 1864 * chip. I'm not sure if this is a requirement or a bug.) 1865 */ 1866 1867 arg.re_flags = 0; 1868 1869 if (m->m_pkthdr.csum_flags & CSUM_IP) 1870 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1871 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1872 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1873 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1874 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1875 1876 arg.sc = sc; 1877 arg.re_idx = *idx; 1878 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1879 if (arg.re_maxsegs > 4) 1880 arg.re_maxsegs -= 4; 1881 arg.re_ring = sc->re_ldata.re_tx_list; 1882 1883 map = sc->re_ldata.re_tx_dmamap[*idx]; 1884 1885 /* 1886 * With some of the RealTek chips, using the checksum offload 1887 * support in conjunction with the autopadding feature results 1888 * in the transmission of corrupt frames. For example, if we 1889 * need to send a really small IP fragment that's less than 60 1890 * bytes in size, and IP header checksumming is enabled, the 1891 * resulting ethernet frame that appears on the wire will 1892 * have garbled payload. To work around this, if TX checksum 1893 * offload is enabled, we always manually pad short frames out 1894 * to the minimum ethernet frame size. We do this by pretending 1895 * the mbuf chain has too many fragments so the coalescing code 1896 * below can assemble the packet into a single buffer that's 1897 * padded out to the mininum frame size. 1898 * 1899 * Note: this appears unnecessary for TCP, and doing it for TCP 1900 * with PCIe adapters seems to result in bad checksums. 1901 */ 1902 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) && 1903 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 1904 error = EFBIG; 1905 } else { 1906 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1907 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1908 } 1909 1910 if (error && error != EFBIG) { 1911 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1912 return(ENOBUFS); 1913 } 1914 1915 /* Too many segments to map, coalesce into a single mbuf */ 1916 1917 if (error || arg.re_maxsegs == 0) { 1918 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1919 if (m_new == NULL) { 1920 return(1); 1921 } else { 1922 m = m_new; 1923 *m_head = m; 1924 } 1925 1926 /* 1927 * Manually pad short frames, and zero the pad space 1928 * to avoid leaking data. 1929 */ 1930 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) { 1931 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 1932 RE_MIN_FRAMELEN - m_new->m_pkthdr.len); 1933 m_new->m_pkthdr.len += RE_MIN_FRAMELEN - 1934 m_new->m_pkthdr.len; 1935 m_new->m_len = m_new->m_pkthdr.len; 1936 } 1937 1938 *called_defrag = 1; 1939 arg.sc = sc; 1940 arg.re_idx = *idx; 1941 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1942 arg.re_ring = sc->re_ldata.re_tx_list; 1943 1944 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1945 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1946 if (error) { 1947 m_freem(m); 1948 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1949 return(EFBIG); 1950 } 1951 } 1952 1953 /* 1954 * Insure that the map for this transmission 1955 * is placed at the array index of the last descriptor 1956 * in this chain. 1957 */ 1958 sc->re_ldata.re_tx_dmamap[*idx] = 1959 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1960 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1961 1962 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1963 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1964 1965 /* 1966 * Set up hardware VLAN tagging. Note: vlan tag info must 1967 * appear in the first descriptor of a multi-descriptor 1968 * transmission attempt. 1969 */ 1970 1971 if (m->m_flags & M_VLANTAG) { 1972 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1973 htole32(htobe16(m->m_pkthdr.ether_vlantag) | 1974 RE_TDESC_VLANCTL_TAG); 1975 } 1976 1977 /* Transfer ownership of packet to the chip. */ 1978 1979 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1980 htole32(RE_TDESC_CMD_OWN); 1981 if (*idx != arg.re_idx) 1982 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1983 htole32(RE_TDESC_CMD_OWN); 1984 1985 RE_DESC_INC(arg.re_idx); 1986 *idx = arg.re_idx; 1987 1988 return(0); 1989 } 1990 1991 /* 1992 * Main transmit routine for C+ and gigE NICs. 1993 */ 1994 1995 static void 1996 re_start(struct ifnet *ifp) 1997 { 1998 struct re_softc *sc = ifp->if_softc; 1999 struct mbuf *m_head; 2000 struct mbuf *m_head2; 2001 int called_defrag, idx, need_trans; 2002 2003 ASSERT_SERIALIZED(ifp->if_serializer); 2004 2005 if (!sc->re_link) { 2006 ifq_purge(&ifp->if_snd); 2007 return; 2008 } 2009 2010 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2011 return; 2012 2013 idx = sc->re_ldata.re_tx_prodidx; 2014 2015 need_trans = 0; 2016 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2017 if (sc->re_ldata.re_tx_free <= 4) { 2018 ifp->if_flags |= IFF_OACTIVE; 2019 break; 2020 } 2021 2022 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2023 if (m_head == NULL) 2024 break; 2025 2026 m_head2 = m_head; 2027 if (re_encap(sc, &m_head2, &idx, &called_defrag)) { 2028 /* 2029 * If we could not encapsulate the defragged packet, 2030 * the returned m_head2 is garbage and we must dequeue 2031 * and throw away the original packet. 2032 */ 2033 if (called_defrag) 2034 m_freem(m_head); 2035 ifp->if_flags |= IFF_OACTIVE; 2036 break; 2037 } 2038 2039 /* 2040 * Clean out the packet we encapsulated. If we defragged 2041 * the packet the m_head2 is the one that got encapsulated 2042 * and the original must be thrown away. Otherwise m_head2 2043 * *IS* the original. 2044 */ 2045 if (called_defrag) 2046 m_freem(m_head); 2047 need_trans = 1; 2048 2049 /* 2050 * If there's a BPF listener, bounce a copy of this frame 2051 * to him. 2052 */ 2053 ETHER_BPF_MTAP(ifp, m_head2); 2054 } 2055 2056 if (!need_trans) { 2057 if (RE_TX_MODERATION_IS_ENABLED(sc) && 2058 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 2059 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2060 return; 2061 } 2062 2063 /* Flush the TX descriptors */ 2064 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2065 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2066 2067 sc->re_ldata.re_tx_prodidx = idx; 2068 2069 /* 2070 * RealTek put the TX poll request register in a different 2071 * location on the 8169 gigE chip. I don't know why. 2072 */ 2073 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2074 2075 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2076 /* 2077 * Use the countdown timer for interrupt moderation. 2078 * 'TX done' interrupts are disabled. Instead, we reset the 2079 * countdown timer, which will begin counting until it hits 2080 * the value in the TIMERINT register, and then trigger an 2081 * interrupt. Each time we write to the TIMERCNT register, 2082 * the timer count is reset to 0. 2083 */ 2084 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2085 } 2086 2087 /* 2088 * Set a timeout in case the chip goes out to lunch. 2089 */ 2090 ifp->if_timer = 5; 2091 } 2092 2093 static void 2094 re_init(void *xsc) 2095 { 2096 struct re_softc *sc = xsc; 2097 struct ifnet *ifp = &sc->arpcom.ac_if; 2098 struct mii_data *mii; 2099 uint32_t rxcfg = 0; 2100 2101 ASSERT_SERIALIZED(ifp->if_serializer); 2102 2103 mii = device_get_softc(sc->re_miibus); 2104 2105 /* 2106 * Cancel pending I/O and free all RX/TX buffers. 2107 */ 2108 re_stop(sc); 2109 2110 /* 2111 * Enable C+ RX and TX mode, as well as VLAN stripping and 2112 * RX checksum offload. We must configure the C+ register 2113 * before all others. 2114 */ 2115 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2116 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 2117 (ifp->if_capenable & IFCAP_RXCSUM ? 2118 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2119 2120 /* 2121 * Init our MAC address. Even though the chipset 2122 * documentation doesn't mention it, we need to enter "Config 2123 * register write enable" mode to modify the ID registers. 2124 */ 2125 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2126 CSR_WRITE_4(sc, RE_IDR0, 2127 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2128 CSR_WRITE_2(sc, RE_IDR4, 2129 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2130 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2131 2132 /* 2133 * For C+ mode, initialize the RX descriptors and mbufs. 2134 */ 2135 re_rx_list_init(sc); 2136 re_tx_list_init(sc); 2137 2138 /* 2139 * Load the addresses of the RX and TX lists into the chip. 2140 */ 2141 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2142 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2143 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2144 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2145 2146 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2147 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2148 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2149 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2150 2151 /* 2152 * Enable transmit and receive. 2153 */ 2154 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2155 2156 /* 2157 * Set the initial TX and RX configuration. 2158 */ 2159 if (sc->re_testmode) { 2160 if (sc->re_type == RE_8169) 2161 CSR_WRITE_4(sc, RE_TXCFG, 2162 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2163 else 2164 CSR_WRITE_4(sc, RE_TXCFG, 2165 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2166 } else 2167 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2168 2169 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2170 2171 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2172 2173 /* Set the individual bit to receive frames for this host only. */ 2174 rxcfg = CSR_READ_4(sc, RE_RXCFG); 2175 rxcfg |= RE_RXCFG_RX_INDIV; 2176 2177 /* If we want promiscuous mode, set the allframes bit. */ 2178 if (ifp->if_flags & IFF_PROMISC) { 2179 rxcfg |= RE_RXCFG_RX_ALLPHYS; 2180 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2181 } else { 2182 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 2183 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2184 } 2185 2186 /* 2187 * Set capture broadcast bit to capture broadcast frames. 2188 */ 2189 if (ifp->if_flags & IFF_BROADCAST) { 2190 rxcfg |= RE_RXCFG_RX_BROAD; 2191 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2192 } else { 2193 rxcfg &= ~RE_RXCFG_RX_BROAD; 2194 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2195 } 2196 2197 /* 2198 * Program the multicast filter, if necessary. 2199 */ 2200 re_setmulti(sc); 2201 2202 #ifdef DEVICE_POLLING 2203 /* 2204 * Disable interrupts if we are polling. 2205 */ 2206 if (ifp->if_flags & IFF_POLLING) 2207 CSR_WRITE_2(sc, RE_IMR, 0); 2208 else /* otherwise ... */ 2209 #endif /* DEVICE_POLLING */ 2210 /* 2211 * Enable interrupts. 2212 */ 2213 if (sc->re_testmode) 2214 CSR_WRITE_2(sc, RE_IMR, 0); 2215 else 2216 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2217 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2218 2219 /* Set initial TX threshold */ 2220 sc->re_txthresh = RE_TX_THRESH_INIT; 2221 2222 /* Start RX/TX process. */ 2223 if (sc->re_flags & RE_F_HASMPC) 2224 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2225 #ifdef notdef 2226 /* Enable receiver and transmitter. */ 2227 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2228 #endif 2229 2230 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2231 /* 2232 * Initialize the timer interrupt register so that 2233 * a timer interrupt will be generated once the timer 2234 * reaches a certain number of ticks. The timer is 2235 * reloaded on each transmit. This gives us TX interrupt 2236 * moderation, which dramatically improves TX frame rate. 2237 */ 2238 if (sc->re_type == RE_8169) 2239 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2240 else 2241 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2242 } 2243 2244 /* 2245 * For 8169 gigE NICs, set the max allowed RX packet 2246 * size so we can receive jumbo frames. 2247 */ 2248 if (sc->re_type == RE_8169) 2249 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2250 2251 if (sc->re_testmode) { 2252 return; 2253 } 2254 2255 mii_mediachg(mii); 2256 2257 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2258 2259 ifp->if_flags |= IFF_RUNNING; 2260 ifp->if_flags &= ~IFF_OACTIVE; 2261 2262 sc->re_link = 0; 2263 callout_reset(&sc->re_timer, hz, re_tick, sc); 2264 } 2265 2266 /* 2267 * Set media options. 2268 */ 2269 static int 2270 re_ifmedia_upd(struct ifnet *ifp) 2271 { 2272 struct re_softc *sc = ifp->if_softc; 2273 struct mii_data *mii; 2274 2275 ASSERT_SERIALIZED(ifp->if_serializer); 2276 2277 mii = device_get_softc(sc->re_miibus); 2278 mii_mediachg(mii); 2279 2280 return(0); 2281 } 2282 2283 /* 2284 * Report current media status. 2285 */ 2286 static void 2287 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2288 { 2289 struct re_softc *sc = ifp->if_softc; 2290 struct mii_data *mii; 2291 2292 ASSERT_SERIALIZED(ifp->if_serializer); 2293 2294 mii = device_get_softc(sc->re_miibus); 2295 2296 mii_pollstat(mii); 2297 ifmr->ifm_active = mii->mii_media_active; 2298 ifmr->ifm_status = mii->mii_media_status; 2299 } 2300 2301 static int 2302 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2303 { 2304 struct re_softc *sc = ifp->if_softc; 2305 struct ifreq *ifr = (struct ifreq *) data; 2306 struct mii_data *mii; 2307 int error = 0; 2308 2309 ASSERT_SERIALIZED(ifp->if_serializer); 2310 2311 switch(command) { 2312 case SIOCSIFMTU: 2313 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2314 error = EINVAL; 2315 ifp->if_mtu = ifr->ifr_mtu; 2316 break; 2317 case SIOCSIFFLAGS: 2318 if (ifp->if_flags & IFF_UP) 2319 re_init(sc); 2320 else if (ifp->if_flags & IFF_RUNNING) 2321 re_stop(sc); 2322 break; 2323 case SIOCADDMULTI: 2324 case SIOCDELMULTI: 2325 re_setmulti(sc); 2326 error = 0; 2327 break; 2328 case SIOCGIFMEDIA: 2329 case SIOCSIFMEDIA: 2330 mii = device_get_softc(sc->re_miibus); 2331 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2332 break; 2333 case SIOCSIFCAP: 2334 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2335 ifp->if_capenable |= 2336 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2337 if (ifp->if_capenable & IFCAP_TXCSUM) 2338 ifp->if_hwassist = RE_CSUM_FEATURES; 2339 else 2340 ifp->if_hwassist = 0; 2341 if (ifp->if_flags & IFF_RUNNING) 2342 re_init(sc); 2343 break; 2344 default: 2345 error = ether_ioctl(ifp, command, data); 2346 break; 2347 } 2348 return(error); 2349 } 2350 2351 static void 2352 re_watchdog(struct ifnet *ifp) 2353 { 2354 struct re_softc *sc = ifp->if_softc; 2355 2356 ASSERT_SERIALIZED(ifp->if_serializer); 2357 2358 if_printf(ifp, "watchdog timeout\n"); 2359 2360 ifp->if_oerrors++; 2361 2362 re_txeof(sc); 2363 re_rxeof(sc); 2364 2365 re_init(sc); 2366 2367 if (!ifq_is_empty(&ifp->if_snd)) 2368 if_devstart(ifp); 2369 } 2370 2371 /* 2372 * Stop the adapter and free any mbufs allocated to the 2373 * RX and TX lists. 2374 */ 2375 static void 2376 re_stop(struct re_softc *sc) 2377 { 2378 struct ifnet *ifp = &sc->arpcom.ac_if; 2379 int i; 2380 2381 ASSERT_SERIALIZED(ifp->if_serializer); 2382 2383 ifp->if_timer = 0; 2384 callout_stop(&sc->re_timer); 2385 2386 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2387 2388 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2389 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2390 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2391 2392 if (sc->re_head != NULL) { 2393 m_freem(sc->re_head); 2394 sc->re_head = sc->re_tail = NULL; 2395 } 2396 2397 /* Free the TX list buffers. */ 2398 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2399 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2400 bus_dmamap_unload(sc->re_ldata.re_mtag, 2401 sc->re_ldata.re_tx_dmamap[i]); 2402 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2403 sc->re_ldata.re_tx_mbuf[i] = NULL; 2404 } 2405 } 2406 2407 /* Free the RX list buffers. */ 2408 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2409 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2410 bus_dmamap_unload(sc->re_ldata.re_mtag, 2411 sc->re_ldata.re_rx_dmamap[i]); 2412 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2413 sc->re_ldata.re_rx_mbuf[i] = NULL; 2414 } 2415 } 2416 } 2417 2418 /* 2419 * Device suspend routine. Stop the interface and save some PCI 2420 * settings in case the BIOS doesn't restore them properly on 2421 * resume. 2422 */ 2423 static int 2424 re_suspend(device_t dev) 2425 { 2426 #ifndef BURN_BRIDGES 2427 int i; 2428 #endif 2429 struct re_softc *sc = device_get_softc(dev); 2430 struct ifnet *ifp = &sc->arpcom.ac_if; 2431 2432 lwkt_serialize_enter(ifp->if_serializer); 2433 2434 re_stop(sc); 2435 2436 #ifndef BURN_BRIDGES 2437 for (i = 0; i < 5; i++) 2438 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2439 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2440 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2441 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2442 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2443 #endif 2444 2445 sc->suspended = 1; 2446 2447 lwkt_serialize_exit(ifp->if_serializer); 2448 2449 return (0); 2450 } 2451 2452 /* 2453 * Device resume routine. Restore some PCI settings in case the BIOS 2454 * doesn't, re-enable busmastering, and restart the interface if 2455 * appropriate. 2456 */ 2457 static int 2458 re_resume(device_t dev) 2459 { 2460 struct re_softc *sc = device_get_softc(dev); 2461 struct ifnet *ifp = &sc->arpcom.ac_if; 2462 #ifndef BURN_BRIDGES 2463 int i; 2464 #endif 2465 2466 lwkt_serialize_enter(ifp->if_serializer); 2467 2468 #ifndef BURN_BRIDGES 2469 /* better way to do this? */ 2470 for (i = 0; i < 5; i++) 2471 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2472 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2473 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2474 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2475 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2476 2477 /* reenable busmastering */ 2478 pci_enable_busmaster(dev); 2479 pci_enable_io(dev, SYS_RES_IOPORT); 2480 #endif 2481 2482 /* reinitialize interface if necessary */ 2483 if (ifp->if_flags & IFF_UP) 2484 re_init(sc); 2485 2486 sc->suspended = 0; 2487 2488 lwkt_serialize_exit(ifp->if_serializer); 2489 2490 return (0); 2491 } 2492 2493 /* 2494 * Stop all chip I/O so that the kernel's probe routines don't 2495 * get confused by errant DMAs when rebooting. 2496 */ 2497 static void 2498 re_shutdown(device_t dev) 2499 { 2500 struct re_softc *sc = device_get_softc(dev); 2501 struct ifnet *ifp = &sc->arpcom.ac_if; 2502 2503 lwkt_serialize_enter(ifp->if_serializer); 2504 re_stop(sc); 2505 lwkt_serialize_exit(ifp->if_serializer); 2506 } 2507 2508 static int 2509 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS) 2510 { 2511 struct re_softc *sc = arg1; 2512 struct ifnet *ifp = &sc->arpcom.ac_if; 2513 int error = 0, mod, mod_old; 2514 2515 lwkt_serialize_enter(ifp->if_serializer); 2516 2517 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc); 2518 2519 error = sysctl_handle_int(oidp, &mod, 0, req); 2520 if (error || req->newptr == NULL || mod == mod_old) 2521 goto back; 2522 if (mod != 0 && mod != 1) { 2523 error = EINVAL; 2524 goto back; 2525 } 2526 2527 if (mod) 2528 RE_ENABLE_TX_MODERATION(sc); 2529 else 2530 RE_DISABLE_TX_MODERATION(sc); 2531 2532 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP)) 2533 re_init(sc); 2534 back: 2535 lwkt_serialize_exit(ifp->if_serializer); 2536 return error; 2537 } 2538