1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.28 2006/11/14 13:35:49 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #include "opt_polling.h" 115 116 #include <sys/param.h> 117 #include <sys/bus.h> 118 #include <sys/endian.h> 119 #include <sys/kernel.h> 120 #include <sys/malloc.h> 121 #include <sys/mbuf.h> 122 /* #include <sys/module.h> */ 123 #include <sys/rman.h> 124 #include <sys/serialize.h> 125 #include <sys/socket.h> 126 #include <sys/sockio.h> 127 #include <sys/sysctl.h> 128 129 #include <net/bpf.h> 130 #include <net/ethernet.h> 131 #include <net/if.h> 132 #include <net/ifq_var.h> 133 #include <net/if_arp.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 #include <net/vlan/if_vlan_var.h> 138 139 #include <dev/netif/mii_layer/mii.h> 140 #include <dev/netif/mii_layer/miivar.h> 141 142 #include <bus/pci/pcidevs.h> 143 #include <bus/pci/pcireg.h> 144 #include <bus/pci/pcivar.h> 145 146 /* "device miibus" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 #include <dev/netif/re/if_rereg.h> 150 #include <dev/netif/re/if_revar.h> 151 152 /* 153 * The hardware supports checksumming but, as usual, some chipsets screw it 154 * all up and produce bogus packets, so we disable it by default. 155 */ 156 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 #if 0 158 #define RE_DISABLE_HWCSUM 159 #endif 160 161 /* 162 * Various supported device vendors/types and their names. 163 */ 164 static struct re_type re_devs[] = { 165 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 166 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 168 "RealTek 8139C+ 10/100BaseTX" }, 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E, 170 "RealTek 8101E PCIe 10/100baseTX" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1, 172 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2, 174 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 176 "RealTek 8169 Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 178 "RealTek 8169S Single-chip Gigabit Ethernet" }, 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB, 180 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 184 "RealTek 8110S Single-chip Gigabit Ethernet" }, 185 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S, 186 "Corega CG-LAPCIGT Gigabit Ethernet" }, 187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S, 188 "Linksys EG1032 Gigabit Ethernet" }, 189 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S, 190 "US Robotics 997902 Gigabit Ethernet" }, 191 { 0, 0, 0, NULL } 192 }; 193 194 static struct re_hwrev re_hwrevs[] = { 195 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"}, 196 { RE_HWREV_8168_SPIN1, RE_8169, "8168"}, 197 { RE_HWREV_8169, RE_8169, "8169"}, 198 { RE_HWREV_8169S, RE_8169, "8169S"}, 199 { RE_HWREV_8110S, RE_8169, "8110S"}, 200 { RE_HWREV_8169_8110SB, RE_8169, "8169SB"}, 201 { RE_HWREV_8169_8110SC, RE_8169, "8169SC"}, 202 { RE_HWREV_8100E, RE_8169, "8100E"}, 203 { RE_HWREV_8101E, RE_8169, "8101E"}, 204 { RE_HWREV_8168_SPIN2, RE_8169, "8168"}, 205 { 0, 0, NULL } 206 }; 207 208 static int re_probe(device_t); 209 static int re_attach(device_t); 210 static int re_detach(device_t); 211 212 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 213 214 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 215 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 216 bus_size_t, int); 217 static int re_allocmem(device_t, struct re_softc *); 218 static int re_newbuf(struct re_softc *, int, struct mbuf *); 219 static int re_rx_list_init(struct re_softc *); 220 static int re_tx_list_init(struct re_softc *); 221 static void re_rxeof(struct re_softc *); 222 static void re_txeof(struct re_softc *); 223 static void re_intr(void *); 224 static void re_tick(void *); 225 static void re_tick_serialized(void *); 226 static void re_start(struct ifnet *); 227 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 228 static void re_init(void *); 229 static void re_stop(struct re_softc *); 230 static void re_watchdog(struct ifnet *); 231 static int re_suspend(device_t); 232 static int re_resume(device_t); 233 static void re_shutdown(device_t); 234 static int re_ifmedia_upd(struct ifnet *); 235 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 236 237 static void re_eeprom_putbyte(struct re_softc *, int); 238 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 239 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 240 static int re_gmii_readreg(device_t, int, int); 241 static int re_gmii_writereg(device_t, int, int, int); 242 243 static int re_miibus_readreg(device_t, int, int); 244 static int re_miibus_writereg(device_t, int, int, int); 245 static void re_miibus_statchg(device_t); 246 247 static void re_setmulti(struct re_softc *); 248 static void re_reset(struct re_softc *); 249 250 #ifdef RE_DIAG 251 static int re_diag(struct re_softc *); 252 #endif 253 254 #ifdef DEVICE_POLLING 255 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 256 #endif 257 258 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS); 259 260 static device_method_t re_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, re_probe), 263 DEVMETHOD(device_attach, re_attach), 264 DEVMETHOD(device_detach, re_detach), 265 DEVMETHOD(device_suspend, re_suspend), 266 DEVMETHOD(device_resume, re_resume), 267 DEVMETHOD(device_shutdown, re_shutdown), 268 269 /* bus interface */ 270 DEVMETHOD(bus_print_child, bus_generic_print_child), 271 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 272 273 /* MII interface */ 274 DEVMETHOD(miibus_readreg, re_miibus_readreg), 275 DEVMETHOD(miibus_writereg, re_miibus_writereg), 276 DEVMETHOD(miibus_statchg, re_miibus_statchg), 277 278 { 0, 0 } 279 }; 280 281 static driver_t re_driver = { 282 "re", 283 re_methods, 284 sizeof(struct re_softc) 285 }; 286 287 static devclass_t re_devclass; 288 289 DECLARE_DUMMY_MODULE(if_re); 290 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 291 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 292 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 293 294 #define EE_SET(x) \ 295 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 296 297 #define EE_CLR(x) \ 298 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 299 300 /* 301 * Send a read command and address to the EEPROM, check for ACK. 302 */ 303 static void 304 re_eeprom_putbyte(struct re_softc *sc, int addr) 305 { 306 int d, i; 307 308 d = addr | (RE_9346_READ << sc->re_eewidth); 309 310 /* 311 * Feed in each bit and strobe the clock. 312 */ 313 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 314 if (d & i) 315 EE_SET(RE_EE_DATAIN); 316 else 317 EE_CLR(RE_EE_DATAIN); 318 DELAY(100); 319 EE_SET(RE_EE_CLK); 320 DELAY(150); 321 EE_CLR(RE_EE_CLK); 322 DELAY(100); 323 } 324 } 325 326 /* 327 * Read a word of data stored in the EEPROM at address 'addr.' 328 */ 329 static void 330 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 331 { 332 int i; 333 uint16_t word = 0; 334 335 /* 336 * Send address of word we want to read. 337 */ 338 re_eeprom_putbyte(sc, addr); 339 340 /* 341 * Start reading bits from EEPROM. 342 */ 343 for (i = 0x8000; i != 0; i >>= 1) { 344 EE_SET(RE_EE_CLK); 345 DELAY(100); 346 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 347 word |= i; 348 EE_CLR(RE_EE_CLK); 349 DELAY(100); 350 } 351 352 *dest = word; 353 } 354 355 /* 356 * Read a sequence of words from the EEPROM. 357 */ 358 static void 359 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 360 { 361 int i; 362 uint16_t word = 0, *ptr; 363 364 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 365 DELAY(100); 366 367 for (i = 0; i < cnt; i++) { 368 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 369 re_eeprom_getword(sc, off + i, &word); 370 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 371 ptr = (uint16_t *)(dest + (i * 2)); 372 *ptr = word; 373 } 374 375 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 376 } 377 378 static int 379 re_gmii_readreg(device_t dev, int phy, int reg) 380 { 381 struct re_softc *sc = device_get_softc(dev); 382 u_int32_t rval; 383 int i; 384 385 if (phy != 1) 386 return(0); 387 388 /* Let the rgephy driver read the GMEDIASTAT register */ 389 390 if (reg == RE_GMEDIASTAT) 391 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 392 393 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 394 DELAY(1000); 395 396 for (i = 0; i < RE_TIMEOUT; i++) { 397 rval = CSR_READ_4(sc, RE_PHYAR); 398 if (rval & RE_PHYAR_BUSY) 399 break; 400 DELAY(100); 401 } 402 403 if (i == RE_TIMEOUT) { 404 device_printf(dev, "PHY read failed\n"); 405 return(0); 406 } 407 408 return(rval & RE_PHYAR_PHYDATA); 409 } 410 411 static int 412 re_gmii_writereg(device_t dev, int phy, int reg, int data) 413 { 414 struct re_softc *sc = device_get_softc(dev); 415 uint32_t rval; 416 int i; 417 418 CSR_WRITE_4(sc, RE_PHYAR, 419 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 420 DELAY(1000); 421 422 for (i = 0; i < RE_TIMEOUT; i++) { 423 rval = CSR_READ_4(sc, RE_PHYAR); 424 if ((rval & RE_PHYAR_BUSY) == 0) 425 break; 426 DELAY(100); 427 } 428 429 if (i == RE_TIMEOUT) 430 device_printf(dev, "PHY write failed\n"); 431 432 return(0); 433 } 434 435 static int 436 re_miibus_readreg(device_t dev, int phy, int reg) 437 { 438 struct re_softc *sc = device_get_softc(dev); 439 uint16_t rval = 0; 440 uint16_t re8139_reg = 0; 441 442 if (sc->re_type == RE_8169) { 443 rval = re_gmii_readreg(dev, phy, reg); 444 return(rval); 445 } 446 447 /* Pretend the internal PHY is only at address 0 */ 448 if (phy) 449 return(0); 450 451 switch(reg) { 452 case MII_BMCR: 453 re8139_reg = RE_BMCR; 454 break; 455 case MII_BMSR: 456 re8139_reg = RE_BMSR; 457 break; 458 case MII_ANAR: 459 re8139_reg = RE_ANAR; 460 break; 461 case MII_ANER: 462 re8139_reg = RE_ANER; 463 break; 464 case MII_ANLPAR: 465 re8139_reg = RE_LPAR; 466 break; 467 case MII_PHYIDR1: 468 case MII_PHYIDR2: 469 return(0); 470 /* 471 * Allow the rlphy driver to read the media status 472 * register. If we have a link partner which does not 473 * support NWAY, this is the register which will tell 474 * us the results of parallel detection. 475 */ 476 case RE_MEDIASTAT: 477 return(CSR_READ_1(sc, RE_MEDIASTAT)); 478 default: 479 device_printf(dev, "bad phy register\n"); 480 return(0); 481 } 482 rval = CSR_READ_2(sc, re8139_reg); 483 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) { 484 /* 8139C+ has different bit layout. */ 485 rval &= ~(BMCR_LOOP | BMCR_ISO); 486 } 487 return(rval); 488 } 489 490 static int 491 re_miibus_writereg(device_t dev, int phy, int reg, int data) 492 { 493 struct re_softc *sc= device_get_softc(dev); 494 u_int16_t re8139_reg = 0; 495 496 if (sc->re_type == RE_8169) 497 return(re_gmii_writereg(dev, phy, reg, data)); 498 499 /* Pretend the internal PHY is only at address 0 */ 500 if (phy) 501 return(0); 502 503 switch(reg) { 504 case MII_BMCR: 505 re8139_reg = RE_BMCR; 506 if (sc->re_type == RE_8139CPLUS) { 507 /* 8139C+ has different bit layout. */ 508 data &= ~(BMCR_LOOP | BMCR_ISO); 509 } 510 break; 511 case MII_BMSR: 512 re8139_reg = RE_BMSR; 513 break; 514 case MII_ANAR: 515 re8139_reg = RE_ANAR; 516 break; 517 case MII_ANER: 518 re8139_reg = RE_ANER; 519 break; 520 case MII_ANLPAR: 521 re8139_reg = RE_LPAR; 522 break; 523 case MII_PHYIDR1: 524 case MII_PHYIDR2: 525 return(0); 526 default: 527 device_printf(dev, "bad phy register\n"); 528 return(0); 529 } 530 CSR_WRITE_2(sc, re8139_reg, data); 531 return(0); 532 } 533 534 static void 535 re_miibus_statchg(device_t dev) 536 { 537 } 538 539 /* 540 * Program the 64-bit multicast hash filter. 541 */ 542 static void 543 re_setmulti(struct re_softc *sc) 544 { 545 struct ifnet *ifp = &sc->arpcom.ac_if; 546 int h = 0; 547 uint32_t hashes[2] = { 0, 0 }; 548 struct ifmultiaddr *ifma; 549 uint32_t rxfilt; 550 int mcnt = 0; 551 552 rxfilt = CSR_READ_4(sc, RE_RXCFG); 553 554 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 555 rxfilt |= RE_RXCFG_RX_MULTI; 556 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 557 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 558 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 559 return; 560 } 561 562 /* first, zot all the existing hash bits */ 563 CSR_WRITE_4(sc, RE_MAR0, 0); 564 CSR_WRITE_4(sc, RE_MAR4, 0); 565 566 /* now program new ones */ 567 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 568 if (ifma->ifma_addr->sa_family != AF_LINK) 569 continue; 570 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 571 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 572 if (h < 32) 573 hashes[0] |= (1 << h); 574 else 575 hashes[1] |= (1 << (h - 32)); 576 mcnt++; 577 } 578 579 if (mcnt) 580 rxfilt |= RE_RXCFG_RX_MULTI; 581 else 582 rxfilt &= ~RE_RXCFG_RX_MULTI; 583 584 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 585 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 586 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 587 } 588 589 static void 590 re_reset(struct re_softc *sc) 591 { 592 int i; 593 594 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 595 596 for (i = 0; i < RE_TIMEOUT; i++) { 597 DELAY(10); 598 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 599 break; 600 } 601 if (i == RE_TIMEOUT) 602 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 603 604 CSR_WRITE_1(sc, 0x82, 1); 605 } 606 607 #ifdef RE_DIAG 608 /* 609 * The following routine is designed to test for a defect on some 610 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 611 * lines connected to the bus, however for a 32-bit only card, they 612 * should be pulled high. The result of this defect is that the 613 * NIC will not work right if you plug it into a 64-bit slot: DMA 614 * operations will be done with 64-bit transfers, which will fail 615 * because the 64-bit data lines aren't connected. 616 * 617 * There's no way to work around this (short of talking a soldering 618 * iron to the board), however we can detect it. The method we use 619 * here is to put the NIC into digital loopback mode, set the receiver 620 * to promiscuous mode, and then try to send a frame. We then compare 621 * the frame data we sent to what was received. If the data matches, 622 * then the NIC is working correctly, otherwise we know the user has 623 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 624 * slot. In the latter case, there's no way the NIC can work correctly, 625 * so we print out a message on the console and abort the device attach. 626 */ 627 628 static int 629 re_diag(struct re_softc *sc) 630 { 631 struct ifnet *ifp = &sc->arpcom.ac_if; 632 struct mbuf *m0; 633 struct ether_header *eh; 634 struct re_desc *cur_rx; 635 uint16_t status; 636 uint32_t rxstat; 637 int total_len, i, error = 0, phyaddr; 638 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 639 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 640 641 /* Allocate a single mbuf */ 642 643 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 644 if (m0 == NULL) 645 return(ENOBUFS); 646 647 /* 648 * Initialize the NIC in test mode. This sets the chip up 649 * so that it can send and receive frames, but performs the 650 * following special functions: 651 * - Puts receiver in promiscuous mode 652 * - Enables digital loopback mode 653 * - Leaves interrupts turned off 654 */ 655 656 ifp->if_flags |= IFF_PROMISC; 657 sc->re_testmode = 1; 658 re_reset(sc); 659 re_init(sc); 660 sc->re_link = 1; 661 if (sc->re_type == RE_8169) 662 phyaddr = 1; 663 else 664 phyaddr = 0; 665 666 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 667 for (i = 0; i < RE_TIMEOUT; i++) { 668 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 669 if (!(status & BMCR_RESET)) 670 break; 671 } 672 673 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 674 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 675 676 DELAY(100000); 677 678 /* Put some data in the mbuf */ 679 680 eh = mtod(m0, struct ether_header *); 681 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 682 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 683 eh->ether_type = htons(ETHERTYPE_IP); 684 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 685 686 /* 687 * Queue the packet, start transmission. 688 * Note: ifq_handoff() ultimately calls re_start() for us. 689 */ 690 691 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 692 error = ifq_handoff(ifp, m0, NULL); 693 if (error) { 694 m0 = NULL; 695 goto done; 696 } 697 m0 = NULL; 698 699 /* Wait for it to propagate through the chip */ 700 701 DELAY(100000); 702 for (i = 0; i < RE_TIMEOUT; i++) { 703 status = CSR_READ_2(sc, RE_ISR); 704 CSR_WRITE_2(sc, RE_ISR, status); 705 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 706 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 707 break; 708 DELAY(10); 709 } 710 711 if (i == RE_TIMEOUT) { 712 if_printf(ifp, "diagnostic failed to receive packet " 713 "in loopback mode\n"); 714 error = EIO; 715 goto done; 716 } 717 718 /* 719 * The packet should have been dumped into the first 720 * entry in the RX DMA ring. Grab it from there. 721 */ 722 723 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 724 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 725 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 726 BUS_DMASYNC_POSTWRITE); 727 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 728 729 m0 = sc->re_ldata.re_rx_mbuf[0]; 730 sc->re_ldata.re_rx_mbuf[0] = NULL; 731 eh = mtod(m0, struct ether_header *); 732 733 cur_rx = &sc->re_ldata.re_rx_list[0]; 734 total_len = RE_RXBYTES(cur_rx); 735 rxstat = le32toh(cur_rx->re_cmdstat); 736 737 if (total_len != ETHER_MIN_LEN) { 738 if_printf(ifp, "diagnostic failed, received short packet\n"); 739 error = EIO; 740 goto done; 741 } 742 743 /* Test that the received packet data matches what we sent. */ 744 745 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 746 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 747 be16toh(eh->ether_type) != ETHERTYPE_IP) { 748 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 749 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 750 dst, ":", src, ":", ETHERTYPE_IP); 751 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 752 eh->ether_dhost, ":", eh->ether_shost, ":", 753 ntohs(eh->ether_type)); 754 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 755 "into a 64-bit PCI slot.\n"); 756 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 757 "for proper operation.\n"); 758 if_printf(ifp, "Read the re(4) man page for more details.\n"); 759 error = EIO; 760 } 761 762 done: 763 /* Turn interface off, release resources */ 764 765 sc->re_testmode = 0; 766 sc->re_link = 0; 767 ifp->if_flags &= ~IFF_PROMISC; 768 re_stop(sc); 769 if (m0 != NULL) 770 m_freem(m0); 771 772 return (error); 773 } 774 #endif /* RE_DIAG */ 775 776 /* 777 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 778 * IDs against our list and return a device name if we find a match. 779 */ 780 static int 781 re_probe(device_t dev) 782 { 783 struct re_type *t; 784 struct re_softc *sc; 785 int rid; 786 uint32_t hwrev; 787 uint16_t vendor, product; 788 789 t = re_devs; 790 791 vendor = pci_get_vendor(dev); 792 product = pci_get_device(dev); 793 794 /* 795 * Only attach to rev.3 of the Linksys EG1032 adapter. 796 * Rev.2 is supported by sk(4). 797 */ 798 if (vendor == PCI_VENDOR_LINKSYS && 799 product == PCI_PRODUCT_LINKSYS_EG1032 && 800 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 801 return ENXIO; 802 803 for (t = re_devs; t->re_name != NULL; t++) { 804 if (product == t->re_did && vendor == t->re_vid) 805 break; 806 } 807 808 /* 809 * Check if we found a RealTek device. 810 */ 811 if (t->re_name == NULL) 812 return(ENXIO); 813 814 /* 815 * Temporarily map the I/O space so we can read the chip ID register. 816 */ 817 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 818 rid = RE_PCI_LOIO; 819 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 820 RF_ACTIVE); 821 if (sc->re_res == NULL) { 822 device_printf(dev, "couldn't map ports/memory\n"); 823 kfree(sc, M_TEMP); 824 return(ENXIO); 825 } 826 827 sc->re_btag = rman_get_bustag(sc->re_res); 828 sc->re_bhandle = rman_get_bushandle(sc->re_res); 829 830 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 831 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 832 kfree(sc, M_TEMP); 833 834 /* 835 * and continue matching for the specific chip... 836 */ 837 for (; t->re_name != NULL; t++) { 838 if (product == t->re_did && vendor == t->re_vid && 839 t->re_basetype == hwrev) { 840 device_set_desc(dev, t->re_name); 841 return(0); 842 } 843 } 844 return(ENXIO); 845 } 846 847 /* 848 * This routine takes the segment list provided as the result of 849 * a bus_dma_map_load() operation and assigns the addresses/lengths 850 * to RealTek DMA descriptors. This can be called either by the RX 851 * code or the TX code. In the RX case, we'll probably wind up mapping 852 * at most one segment. For the TX case, there could be any number of 853 * segments since TX packets may span multiple mbufs. In either case, 854 * if the number of segments is larger than the re_maxsegs limit 855 * specified by the caller, we abort the mapping operation. Sadly, 856 * whoever designed the buffer mapping API did not provide a way to 857 * return an error from here, so we have to fake it a bit. 858 */ 859 860 static void 861 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 862 bus_size_t mapsize, int error) 863 { 864 struct re_dmaload_arg *ctx; 865 struct re_desc *d = NULL; 866 int i = 0, idx; 867 uint32_t cmdstat; 868 869 if (error) 870 return; 871 872 ctx = arg; 873 874 /* Signal error to caller if there's too many segments */ 875 if (nseg > ctx->re_maxsegs) { 876 ctx->re_maxsegs = 0; 877 return; 878 } 879 880 /* 881 * Map the segment array into descriptors. Note that we set the 882 * start-of-frame and end-of-frame markers for either TX or RX, but 883 * they really only have meaning in the TX case. (In the RX case, 884 * it's the chip that tells us where packets begin and end.) 885 * We also keep track of the end of the ring and set the 886 * end-of-ring bits as needed, and we set the ownership bits 887 * in all except the very first descriptor. (The caller will 888 * set this descriptor later when it start transmission or 889 * reception.) 890 */ 891 idx = ctx->re_idx; 892 for (;;) { 893 d = &ctx->re_ring[idx]; 894 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 895 ctx->re_maxsegs = 0; 896 return; 897 } 898 cmdstat = segs[i].ds_len; 899 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 900 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 901 if (i == 0) 902 cmdstat |= RE_TDESC_CMD_SOF; 903 else 904 cmdstat |= RE_TDESC_CMD_OWN; 905 if (idx == (RE_RX_DESC_CNT - 1)) 906 cmdstat |= RE_TDESC_CMD_EOR; 907 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 908 i++; 909 if (i == nseg) 910 break; 911 RE_DESC_INC(idx); 912 } 913 914 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 915 ctx->re_maxsegs = nseg; 916 ctx->re_idx = idx; 917 } 918 919 /* 920 * Map a single buffer address. 921 */ 922 923 static void 924 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 925 { 926 uint32_t *addr; 927 928 if (error) 929 return; 930 931 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 932 addr = arg; 933 *addr = segs->ds_addr; 934 } 935 936 static int 937 re_allocmem(device_t dev, struct re_softc *sc) 938 { 939 int error, i, nseg; 940 941 /* 942 * Allocate map for RX mbufs. 943 */ 944 nseg = 32; 945 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 946 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 947 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 948 &sc->re_ldata.re_mtag); 949 if (error) { 950 device_printf(dev, "could not allocate dma tag\n"); 951 return(error); 952 } 953 954 /* 955 * Allocate map for TX descriptor list. 956 */ 957 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 958 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 959 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 960 &sc->re_ldata.re_tx_list_tag); 961 if (error) { 962 device_printf(dev, "could not allocate dma tag\n"); 963 return(error); 964 } 965 966 /* Allocate DMA'able memory for the TX ring */ 967 968 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 969 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 970 &sc->re_ldata.re_tx_list_map); 971 if (error) { 972 device_printf(dev, "could not allocate TX ring\n"); 973 return(error); 974 } 975 976 /* Load the map for the TX ring. */ 977 978 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 979 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 980 RE_TX_LIST_SZ, re_dma_map_addr, 981 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 982 if (error) { 983 device_printf(dev, "could not get addres of TX ring\n"); 984 return(error); 985 } 986 987 /* Create DMA maps for TX buffers */ 988 989 for (i = 0; i < RE_TX_DESC_CNT; i++) { 990 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 991 &sc->re_ldata.re_tx_dmamap[i]); 992 if (error) { 993 device_printf(dev, "can't create DMA map for TX\n"); 994 return(error); 995 } 996 } 997 998 /* 999 * Allocate map for RX descriptor list. 1000 */ 1001 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 1002 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1003 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1004 &sc->re_ldata.re_rx_list_tag); 1005 if (error) { 1006 device_printf(dev, "could not allocate dma tag\n"); 1007 return(error); 1008 } 1009 1010 /* Allocate DMA'able memory for the RX ring */ 1011 1012 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1013 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1014 &sc->re_ldata.re_rx_list_map); 1015 if (error) { 1016 device_printf(dev, "could not allocate RX ring\n"); 1017 return(error); 1018 } 1019 1020 /* Load the map for the RX ring. */ 1021 1022 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1023 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 1024 RE_RX_LIST_SZ, re_dma_map_addr, 1025 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 1026 if (error) { 1027 device_printf(dev, "could not get address of RX ring\n"); 1028 return(error); 1029 } 1030 1031 /* Create DMA maps for RX buffers */ 1032 1033 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1034 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1035 &sc->re_ldata.re_rx_dmamap[i]); 1036 if (error) { 1037 device_printf(dev, "can't create DMA map for RX\n"); 1038 return(ENOMEM); 1039 } 1040 } 1041 1042 return(0); 1043 } 1044 1045 /* 1046 * Attach the interface. Allocate softc structures, do ifmedia 1047 * setup and ethernet/BPF attach. 1048 */ 1049 static int 1050 re_attach(device_t dev) 1051 { 1052 struct re_softc *sc = device_get_softc(dev); 1053 struct ifnet *ifp; 1054 struct re_hwrev *hw_rev; 1055 uint8_t eaddr[ETHER_ADDR_LEN]; 1056 uint16_t as[ETHER_ADDR_LEN / 2]; 1057 int hwrev; 1058 uint16_t re_did = 0; 1059 int error = 0, rid, i; 1060 1061 callout_init(&sc->re_timer); 1062 #ifdef RE_DIAG 1063 sc->re_dev = dev; 1064 #endif 1065 1066 RE_ENABLE_TX_MODERATION(sc); 1067 1068 sysctl_ctx_init(&sc->re_sysctl_ctx); 1069 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1070 SYSCTL_STATIC_CHILDREN(_hw), 1071 OID_AUTO, 1072 device_get_nameunit(dev), 1073 CTLFLAG_RD, 0, ""); 1074 if (sc->re_sysctl_tree == NULL) { 1075 device_printf(dev, "can't add sysctl node\n"); 1076 error = ENXIO; 1077 goto fail; 1078 } 1079 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1080 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1081 OID_AUTO, "tx_moderation", 1082 CTLTYPE_INT | CTLFLAG_RW, 1083 sc, 0, re_sysctl_tx_moderation, "I", 1084 "Enable/Disable TX moderation"); 1085 1086 #ifndef BURN_BRIDGES 1087 /* 1088 * Handle power management nonsense. 1089 */ 1090 1091 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1092 uint32_t membase, irq; 1093 1094 /* Save important PCI config data. */ 1095 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1096 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1097 1098 /* Reset the power state. */ 1099 device_printf(dev, "chip is is in D%d power mode " 1100 "-- setting to D0\n", pci_get_powerstate(dev)); 1101 1102 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1103 1104 /* Restore PCI config data. */ 1105 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1106 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1107 } 1108 #endif 1109 /* 1110 * Map control/status registers. 1111 */ 1112 pci_enable_busmaster(dev); 1113 1114 rid = RE_PCI_LOIO; 1115 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1116 RF_ACTIVE); 1117 1118 if (sc->re_res == NULL) { 1119 device_printf(dev, "couldn't map ports\n"); 1120 error = ENXIO; 1121 goto fail; 1122 } 1123 1124 sc->re_btag = rman_get_bustag(sc->re_res); 1125 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1126 1127 /* Allocate interrupt */ 1128 rid = 0; 1129 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1130 RF_SHAREABLE | RF_ACTIVE); 1131 1132 if (sc->re_irq == NULL) { 1133 device_printf(dev, "couldn't map interrupt\n"); 1134 error = ENXIO; 1135 goto fail; 1136 } 1137 1138 /* Reset the adapter. */ 1139 re_reset(sc); 1140 1141 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1142 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1143 if (hw_rev->re_rev == hwrev) { 1144 sc->re_type = hw_rev->re_type; 1145 break; 1146 } 1147 } 1148 1149 sc->re_eewidth = 6; 1150 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1151 if (re_did != 0x8129) 1152 sc->re_eewidth = 8; 1153 1154 /* 1155 * Get station address from the EEPROM. 1156 */ 1157 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 1158 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1159 as[i] = le16toh(as[i]); 1160 bcopy(as, eaddr, sizeof(eaddr)); 1161 1162 if (sc->re_type == RE_8169) { 1163 /* Set RX length mask */ 1164 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1165 sc->re_txstart = RE_GTXSTART; 1166 } else { 1167 /* Set RX length mask */ 1168 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1169 sc->re_txstart = RE_TXSTART; 1170 } 1171 1172 /* 1173 * Allocate the parent bus DMA tag appropriate for PCI. 1174 */ 1175 #define RE_NSEG_NEW 32 1176 error = bus_dma_tag_create(NULL, /* parent */ 1177 1, 0, /* alignment, boundary */ 1178 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1179 BUS_SPACE_MAXADDR, /* highaddr */ 1180 NULL, NULL, /* filter, filterarg */ 1181 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1182 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1183 BUS_DMA_ALLOCNOW, /* flags */ 1184 &sc->re_parent_tag); 1185 if (error) 1186 goto fail; 1187 1188 error = re_allocmem(dev, sc); 1189 1190 if (error) 1191 goto fail; 1192 1193 /* Do MII setup */ 1194 if (mii_phy_probe(dev, &sc->re_miibus, 1195 re_ifmedia_upd, re_ifmedia_sts)) { 1196 device_printf(dev, "MII without any phy!\n"); 1197 error = ENXIO; 1198 goto fail; 1199 } 1200 1201 ifp = &sc->arpcom.ac_if; 1202 ifp->if_softc = sc; 1203 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1204 ifp->if_mtu = ETHERMTU; 1205 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1206 ifp->if_ioctl = re_ioctl; 1207 ifp->if_capabilities = IFCAP_VLAN_MTU; 1208 ifp->if_start = re_start; 1209 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1210 #ifdef DEVICE_POLLING 1211 ifp->if_poll = re_poll; 1212 #endif 1213 ifp->if_watchdog = re_watchdog; 1214 ifp->if_init = re_init; 1215 if (sc->re_type == RE_8169) 1216 ifp->if_baudrate = 1000000000; 1217 else 1218 ifp->if_baudrate = 100000000; 1219 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1220 ifq_set_ready(&ifp->if_snd); 1221 #ifdef RE_DISABLE_HWCSUM 1222 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1223 ifp->if_hwassist = 0; 1224 #else 1225 ifp->if_capenable = ifp->if_capabilities; 1226 ifp->if_hwassist = RE_CSUM_FEATURES; 1227 #endif 1228 1229 /* 1230 * Call MI attach routine. 1231 */ 1232 ether_ifattach(ifp, eaddr, NULL); 1233 1234 #ifdef RE_DIAG 1235 /* 1236 * Perform hardware diagnostic on the original RTL8169. 1237 * Some 32-bit cards were incorrectly wired and would 1238 * malfunction if plugged into a 64-bit slot. 1239 */ 1240 if (hwrev == RE_HWREV_8169) { 1241 lwkt_serialize_enter(ifp->if_serializer); 1242 error = re_diag(sc); 1243 lwkt_serialize_exit(ifp->if_serializer); 1244 1245 if (error) { 1246 device_printf(dev, "hardware diagnostic failure\n"); 1247 ether_ifdetach(ifp); 1248 goto fail; 1249 } 1250 } 1251 #endif /* RE_DIAG */ 1252 1253 /* Hook interrupt last to avoid having to lock softc */ 1254 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc, 1255 &sc->re_intrhand, ifp->if_serializer); 1256 1257 if (error) { 1258 device_printf(dev, "couldn't set up irq\n"); 1259 ether_ifdetach(ifp); 1260 goto fail; 1261 } 1262 1263 fail: 1264 if (error) 1265 re_detach(dev); 1266 1267 return (error); 1268 } 1269 1270 /* 1271 * Shutdown hardware and free up resources. This can be called any 1272 * time after the mutex has been initialized. It is called in both 1273 * the error case in attach and the normal detach case so it needs 1274 * to be careful about only freeing resources that have actually been 1275 * allocated. 1276 */ 1277 static int 1278 re_detach(device_t dev) 1279 { 1280 struct re_softc *sc = device_get_softc(dev); 1281 struct ifnet *ifp = &sc->arpcom.ac_if; 1282 int i; 1283 1284 /* These should only be active if attach succeeded */ 1285 if (device_is_attached(dev)) { 1286 lwkt_serialize_enter(ifp->if_serializer); 1287 re_stop(sc); 1288 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1289 lwkt_serialize_exit(ifp->if_serializer); 1290 1291 ether_ifdetach(ifp); 1292 } 1293 if (sc->re_miibus) 1294 device_delete_child(dev, sc->re_miibus); 1295 bus_generic_detach(dev); 1296 1297 if (sc->re_irq) 1298 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1299 if (sc->re_res) { 1300 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1301 sc->re_res); 1302 } 1303 1304 /* Unload and free the RX DMA ring memory and map */ 1305 1306 if (sc->re_ldata.re_rx_list_tag) { 1307 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1308 sc->re_ldata.re_rx_list_map); 1309 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1310 sc->re_ldata.re_rx_list, 1311 sc->re_ldata.re_rx_list_map); 1312 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1313 } 1314 1315 /* Unload and free the TX DMA ring memory and map */ 1316 1317 if (sc->re_ldata.re_tx_list_tag) { 1318 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1319 sc->re_ldata.re_tx_list_map); 1320 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1321 sc->re_ldata.re_tx_list, 1322 sc->re_ldata.re_tx_list_map); 1323 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1324 } 1325 1326 /* Destroy all the RX and TX buffer maps */ 1327 1328 if (sc->re_ldata.re_mtag) { 1329 for (i = 0; i < RE_TX_DESC_CNT; i++) 1330 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1331 sc->re_ldata.re_tx_dmamap[i]); 1332 for (i = 0; i < RE_RX_DESC_CNT; i++) 1333 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1334 sc->re_ldata.re_rx_dmamap[i]); 1335 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1336 } 1337 1338 /* Unload and free the stats buffer and map */ 1339 1340 if (sc->re_ldata.re_stag) { 1341 bus_dmamap_unload(sc->re_ldata.re_stag, 1342 sc->re_ldata.re_rx_list_map); 1343 bus_dmamem_free(sc->re_ldata.re_stag, 1344 sc->re_ldata.re_stats, 1345 sc->re_ldata.re_smap); 1346 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1347 } 1348 1349 if (sc->re_parent_tag) 1350 bus_dma_tag_destroy(sc->re_parent_tag); 1351 1352 return(0); 1353 } 1354 1355 static int 1356 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1357 { 1358 struct re_dmaload_arg arg; 1359 struct mbuf *n = NULL; 1360 int error; 1361 1362 if (m == NULL) { 1363 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1364 if (n == NULL) 1365 return(ENOBUFS); 1366 m = n; 1367 } else 1368 m->m_data = m->m_ext.ext_buf; 1369 1370 /* 1371 * Initialize mbuf length fields and fixup 1372 * alignment so that the frame payload is 1373 * longword aligned. 1374 */ 1375 m->m_len = m->m_pkthdr.len = MCLBYTES; 1376 m_adj(m, ETHER_ALIGN); 1377 1378 arg.sc = sc; 1379 arg.re_idx = idx; 1380 arg.re_maxsegs = 1; 1381 arg.re_flags = 0; 1382 arg.re_ring = sc->re_ldata.re_rx_list; 1383 1384 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1385 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1386 &arg, BUS_DMA_NOWAIT); 1387 if (error || arg.re_maxsegs != 1) { 1388 if (n != NULL) 1389 m_freem(n); 1390 return (ENOMEM); 1391 } 1392 1393 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1394 sc->re_ldata.re_rx_mbuf[idx] = m; 1395 1396 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1397 BUS_DMASYNC_PREREAD); 1398 1399 return(0); 1400 } 1401 1402 static int 1403 re_tx_list_init(struct re_softc *sc) 1404 { 1405 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1406 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1407 1408 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1409 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1410 sc->re_ldata.re_tx_prodidx = 0; 1411 sc->re_ldata.re_tx_considx = 0; 1412 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1413 1414 return(0); 1415 } 1416 1417 static int 1418 re_rx_list_init(struct re_softc *sc) 1419 { 1420 int i, error; 1421 1422 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1423 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1424 1425 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1426 error = re_newbuf(sc, i, NULL); 1427 if (error) 1428 return(error); 1429 } 1430 1431 /* Flush the RX descriptors */ 1432 1433 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1434 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1435 1436 sc->re_ldata.re_rx_prodidx = 0; 1437 sc->re_head = sc->re_tail = NULL; 1438 1439 return(0); 1440 } 1441 1442 /* 1443 * RX handler for C+ and 8169. For the gigE chips, we support 1444 * the reception of jumbo frames that have been fragmented 1445 * across multiple 2K mbuf cluster buffers. 1446 */ 1447 static void 1448 re_rxeof(struct re_softc *sc) 1449 { 1450 struct ifnet *ifp = &sc->arpcom.ac_if; 1451 struct mbuf *m; 1452 struct re_desc *cur_rx; 1453 uint32_t rxstat, rxvlan; 1454 int i, total_len; 1455 1456 /* Invalidate the descriptor memory */ 1457 1458 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1459 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1460 1461 for (i = sc->re_ldata.re_rx_prodidx; 1462 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1463 cur_rx = &sc->re_ldata.re_rx_list[i]; 1464 m = sc->re_ldata.re_rx_mbuf[i]; 1465 total_len = RE_RXBYTES(cur_rx); 1466 rxstat = le32toh(cur_rx->re_cmdstat); 1467 rxvlan = le32toh(cur_rx->re_vlanctl); 1468 1469 /* Invalidate the RX mbuf and unload its map */ 1470 1471 bus_dmamap_sync(sc->re_ldata.re_mtag, 1472 sc->re_ldata.re_rx_dmamap[i], 1473 BUS_DMASYNC_POSTWRITE); 1474 bus_dmamap_unload(sc->re_ldata.re_mtag, 1475 sc->re_ldata.re_rx_dmamap[i]); 1476 1477 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1478 m->m_len = MCLBYTES - ETHER_ALIGN; 1479 if (sc->re_head == NULL) { 1480 sc->re_head = sc->re_tail = m; 1481 } else { 1482 sc->re_tail->m_next = m; 1483 sc->re_tail = m; 1484 } 1485 re_newbuf(sc, i, NULL); 1486 continue; 1487 } 1488 1489 /* 1490 * NOTE: for the 8139C+, the frame length field 1491 * is always 12 bits in size, but for the gigE chips, 1492 * it is 13 bits (since the max RX frame length is 16K). 1493 * Unfortunately, all 32 bits in the status word 1494 * were already used, so to make room for the extra 1495 * length bit, RealTek took out the 'frame alignment 1496 * error' bit and shifted the other status bits 1497 * over one slot. The OWN, EOR, FS and LS bits are 1498 * still in the same places. We have already extracted 1499 * the frame length and checked the OWN bit, so rather 1500 * than using an alternate bit mapping, we shift the 1501 * status bits one space to the right so we can evaluate 1502 * them using the 8169 status as though it was in the 1503 * same format as that of the 8139C+. 1504 */ 1505 if (sc->re_type == RE_8169) 1506 rxstat >>= 1; 1507 1508 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1509 ifp->if_ierrors++; 1510 /* 1511 * If this is part of a multi-fragment packet, 1512 * discard all the pieces. 1513 */ 1514 if (sc->re_head != NULL) { 1515 m_freem(sc->re_head); 1516 sc->re_head = sc->re_tail = NULL; 1517 } 1518 re_newbuf(sc, i, m); 1519 continue; 1520 } 1521 1522 /* 1523 * If allocating a replacement mbuf fails, 1524 * reload the current one. 1525 */ 1526 1527 if (re_newbuf(sc, i, NULL)) { 1528 ifp->if_ierrors++; 1529 if (sc->re_head != NULL) { 1530 m_freem(sc->re_head); 1531 sc->re_head = sc->re_tail = NULL; 1532 } 1533 re_newbuf(sc, i, m); 1534 continue; 1535 } 1536 1537 if (sc->re_head != NULL) { 1538 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1539 /* 1540 * Special case: if there's 4 bytes or less 1541 * in this buffer, the mbuf can be discarded: 1542 * the last 4 bytes is the CRC, which we don't 1543 * care about anyway. 1544 */ 1545 if (m->m_len <= ETHER_CRC_LEN) { 1546 sc->re_tail->m_len -= 1547 (ETHER_CRC_LEN - m->m_len); 1548 m_freem(m); 1549 } else { 1550 m->m_len -= ETHER_CRC_LEN; 1551 sc->re_tail->m_next = m; 1552 } 1553 m = sc->re_head; 1554 sc->re_head = sc->re_tail = NULL; 1555 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1556 } else 1557 m->m_pkthdr.len = m->m_len = 1558 (total_len - ETHER_CRC_LEN); 1559 1560 ifp->if_ipackets++; 1561 m->m_pkthdr.rcvif = ifp; 1562 1563 /* Do RX checksumming if enabled */ 1564 1565 if (ifp->if_capenable & IFCAP_RXCSUM) { 1566 1567 /* Check IP header checksum */ 1568 if (rxstat & RE_RDESC_STAT_PROTOID) 1569 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1570 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1571 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1572 1573 /* Check TCP/UDP checksum */ 1574 if ((RE_TCPPKT(rxstat) && 1575 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1576 (RE_UDPPKT(rxstat) && 1577 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1578 m->m_pkthdr.csum_flags |= 1579 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1580 m->m_pkthdr.csum_data = 0xffff; 1581 } 1582 } 1583 1584 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1585 VLAN_INPUT_TAG(m, 1586 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1587 } else { 1588 ifp->if_input(ifp, m); 1589 } 1590 } 1591 1592 /* Flush the RX DMA ring */ 1593 1594 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1595 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1596 1597 sc->re_ldata.re_rx_prodidx = i; 1598 } 1599 1600 static void 1601 re_txeof(struct re_softc *sc) 1602 { 1603 struct ifnet *ifp = &sc->arpcom.ac_if; 1604 uint32_t txstat; 1605 int idx; 1606 1607 /* Invalidate the TX descriptor list */ 1608 1609 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1610 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 1611 1612 for (idx = sc->re_ldata.re_tx_considx; 1613 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) { 1614 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1615 if (txstat & RE_TDESC_CMD_OWN) 1616 break; 1617 1618 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 1619 1620 /* 1621 * We only stash mbufs in the last descriptor 1622 * in a fragment chain, which also happens to 1623 * be the only place where the TX status bits 1624 * are valid. 1625 */ 1626 if (txstat & RE_TDESC_CMD_EOF) { 1627 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1628 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1629 bus_dmamap_unload(sc->re_ldata.re_mtag, 1630 sc->re_ldata.re_tx_dmamap[idx]); 1631 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1632 RE_TDESC_STAT_COLCNT)) 1633 ifp->if_collisions++; 1634 if (txstat & RE_TDESC_STAT_TXERRSUM) 1635 ifp->if_oerrors++; 1636 else 1637 ifp->if_opackets++; 1638 } 1639 sc->re_ldata.re_tx_free++; 1640 } 1641 1642 /* No changes made to the TX ring, so no flush needed */ 1643 if (sc->re_ldata.re_tx_free) { 1644 sc->re_ldata.re_tx_considx = idx; 1645 ifp->if_flags &= ~IFF_OACTIVE; 1646 ifp->if_timer = 0; 1647 } 1648 1649 /* 1650 * Some chips will ignore a second TX request issued while an 1651 * existing transmission is in progress. If the transmitter goes 1652 * idle but there are still packets waiting to be sent, we need 1653 * to restart the channel here to flush them out. This only seems 1654 * to be required with the PCIe devices. 1655 */ 1656 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1657 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 1658 1659 /* 1660 * If not all descriptors have been released reaped yet, 1661 * reload the timer so that we will eventually get another 1662 * interrupt that will cause us to re-enter this routine. 1663 * This is done in case the transmitter has gone idle. 1664 */ 1665 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1666 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1667 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1668 } 1669 1670 static void 1671 re_tick(void *xsc) 1672 { 1673 struct re_softc *sc = xsc; 1674 1675 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1676 re_tick_serialized(xsc); 1677 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1678 } 1679 1680 static void 1681 re_tick_serialized(void *xsc) 1682 { 1683 struct re_softc *sc = xsc; 1684 struct ifnet *ifp = &sc->arpcom.ac_if; 1685 struct mii_data *mii; 1686 1687 mii = device_get_softc(sc->re_miibus); 1688 mii_tick(mii); 1689 if (sc->re_link) { 1690 if (!(mii->mii_media_status & IFM_ACTIVE)) 1691 sc->re_link = 0; 1692 } else { 1693 if (mii->mii_media_status & IFM_ACTIVE && 1694 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1695 sc->re_link = 1; 1696 if (!ifq_is_empty(&ifp->if_snd)) 1697 ifp->if_start(ifp); 1698 } 1699 } 1700 1701 callout_reset(&sc->re_timer, hz, re_tick, sc); 1702 } 1703 1704 #ifdef DEVICE_POLLING 1705 1706 static void 1707 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1708 { 1709 struct re_softc *sc = ifp->if_softc; 1710 1711 switch(cmd) { 1712 case POLL_REGISTER: 1713 /* disable interrupts */ 1714 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1715 break; 1716 case POLL_DEREGISTER: 1717 /* enable interrupts */ 1718 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 1719 break; 1720 default: 1721 sc->rxcycles = count; 1722 re_rxeof(sc); 1723 re_txeof(sc); 1724 1725 if (!ifq_is_empty(&ifp->if_snd)) 1726 (*ifp->if_start)(ifp); 1727 1728 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1729 uint16_t status; 1730 1731 status = CSR_READ_2(sc, RE_ISR); 1732 if (status == 0xffff) 1733 return; 1734 if (status) 1735 CSR_WRITE_2(sc, RE_ISR, status); 1736 1737 /* 1738 * XXX check behaviour on receiver stalls. 1739 */ 1740 1741 if (status & RE_ISR_SYSTEM_ERR) { 1742 re_reset(sc); 1743 re_init(sc); 1744 } 1745 } 1746 break; 1747 } 1748 } 1749 #endif /* DEVICE_POLLING */ 1750 1751 static void 1752 re_intr(void *arg) 1753 { 1754 struct re_softc *sc = arg; 1755 struct ifnet *ifp = &sc->arpcom.ac_if; 1756 uint16_t status; 1757 1758 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1759 return; 1760 1761 for (;;) { 1762 status = CSR_READ_2(sc, RE_ISR); 1763 /* If the card has gone away the read returns 0xffff. */ 1764 if (status == 0xffff) 1765 break; 1766 if (status) 1767 CSR_WRITE_2(sc, RE_ISR, status); 1768 1769 if ((status & sc->re_intrs) == 0) 1770 break; 1771 1772 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW)) 1773 re_rxeof(sc); 1774 1775 if ((status & sc->re_tx_ack) || 1776 (status & RE_ISR_TX_ERR) || 1777 (status & RE_ISR_TX_DESC_UNAVAIL)) 1778 re_txeof(sc); 1779 1780 if (status & RE_ISR_SYSTEM_ERR) { 1781 re_reset(sc); 1782 re_init(sc); 1783 } 1784 1785 if (status & RE_ISR_LINKCHG) { 1786 callout_stop(&sc->re_timer); 1787 re_tick_serialized(sc); 1788 } 1789 } 1790 1791 if (!ifq_is_empty(&ifp->if_snd)) 1792 (*ifp->if_start)(ifp); 1793 } 1794 1795 static int 1796 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1797 { 1798 struct ifnet *ifp = &sc->arpcom.ac_if; 1799 struct mbuf *m, *m_new = NULL; 1800 struct re_dmaload_arg arg; 1801 bus_dmamap_t map; 1802 int error; 1803 1804 *called_defrag = 0; 1805 if (sc->re_ldata.re_tx_free <= 4) 1806 return(EFBIG); 1807 1808 m = *m_head; 1809 1810 /* 1811 * Set up checksum offload. Note: checksum offload bits must 1812 * appear in all descriptors of a multi-descriptor transmit 1813 * attempt. (This is according to testing done with an 8169 1814 * chip. I'm not sure if this is a requirement or a bug.) 1815 */ 1816 1817 arg.re_flags = 0; 1818 1819 if (m->m_pkthdr.csum_flags & CSUM_IP) 1820 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1821 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1822 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1823 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1824 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1825 1826 arg.sc = sc; 1827 arg.re_idx = *idx; 1828 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1829 if (arg.re_maxsegs > 4) 1830 arg.re_maxsegs -= 4; 1831 arg.re_ring = sc->re_ldata.re_tx_list; 1832 1833 map = sc->re_ldata.re_tx_dmamap[*idx]; 1834 1835 /* 1836 * With some of the RealTek chips, using the checksum offload 1837 * support in conjunction with the autopadding feature results 1838 * in the transmission of corrupt frames. For example, if we 1839 * need to send a really small IP fragment that's less than 60 1840 * bytes in size, and IP header checksumming is enabled, the 1841 * resulting ethernet frame that appears on the wire will 1842 * have garbled payload. To work around this, if TX checksum 1843 * offload is enabled, we always manually pad short frames out 1844 * to the minimum ethernet frame size. We do this by pretending 1845 * the mbuf chain has too many fragments so the coalescing code 1846 * below can assemble the packet into a single buffer that's 1847 * padded out to the mininum frame size. 1848 */ 1849 if (arg.re_flags && m->m_pkthdr.len < RE_MIN_FRAMELEN) { 1850 error = EFBIG; 1851 } else { 1852 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1853 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1854 } 1855 1856 if (error && error != EFBIG) { 1857 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1858 return(ENOBUFS); 1859 } 1860 1861 /* Too many segments to map, coalesce into a single mbuf */ 1862 1863 if (error || arg.re_maxsegs == 0) { 1864 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1865 if (m_new == NULL) 1866 return(1); 1867 else { 1868 m = m_new; 1869 *m_head = m; 1870 } 1871 1872 /* 1873 * Manually pad short frames, and zero the pad space 1874 * to avoid leaking data. 1875 */ 1876 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) { 1877 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 1878 RE_MIN_FRAMELEN - m_new->m_pkthdr.len); 1879 m_new->m_pkthdr.len += RE_MIN_FRAMELEN - 1880 m_new->m_pkthdr.len; 1881 m_new->m_len = m_new->m_pkthdr.len; 1882 } 1883 1884 *called_defrag = 1; 1885 arg.sc = sc; 1886 arg.re_idx = *idx; 1887 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1888 arg.re_ring = sc->re_ldata.re_tx_list; 1889 1890 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1891 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1892 if (error) { 1893 m_freem(m); 1894 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1895 return(EFBIG); 1896 } 1897 } 1898 1899 /* 1900 * Insure that the map for this transmission 1901 * is placed at the array index of the last descriptor 1902 * in this chain. 1903 */ 1904 sc->re_ldata.re_tx_dmamap[*idx] = 1905 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1906 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1907 1908 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1909 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1910 1911 /* 1912 * Set up hardware VLAN tagging. Note: vlan tag info must 1913 * appear in the first descriptor of a multi-descriptor 1914 * transmission attempt. 1915 */ 1916 1917 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1918 m->m_pkthdr.rcvif != NULL && 1919 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1920 struct ifvlan *ifv; 1921 ifv = m->m_pkthdr.rcvif->if_softc; 1922 if (ifv != NULL) 1923 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1924 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1925 } 1926 1927 /* Transfer ownership of packet to the chip. */ 1928 1929 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1930 htole32(RE_TDESC_CMD_OWN); 1931 if (*idx != arg.re_idx) 1932 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1933 htole32(RE_TDESC_CMD_OWN); 1934 1935 RE_DESC_INC(arg.re_idx); 1936 *idx = arg.re_idx; 1937 1938 return(0); 1939 } 1940 1941 /* 1942 * Main transmit routine for C+ and gigE NICs. 1943 */ 1944 1945 static void 1946 re_start(struct ifnet *ifp) 1947 { 1948 struct re_softc *sc = ifp->if_softc; 1949 struct mbuf *m_head; 1950 struct mbuf *m_head2; 1951 int called_defrag, idx, need_trans; 1952 1953 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE)) 1954 return; 1955 1956 idx = sc->re_ldata.re_tx_prodidx; 1957 1958 need_trans = 0; 1959 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1960 m_head = ifq_poll(&ifp->if_snd); 1961 if (m_head == NULL) 1962 break; 1963 m_head2 = m_head; 1964 if (re_encap(sc, &m_head2, &idx, &called_defrag)) { 1965 /* 1966 * If we could not encapsulate the defragged packet, 1967 * the returned m_head2 is garbage and we must dequeue 1968 * and throw away the original packet. 1969 */ 1970 if (called_defrag) { 1971 ifq_dequeue(&ifp->if_snd, m_head); 1972 m_freem(m_head); 1973 } 1974 ifp->if_flags |= IFF_OACTIVE; 1975 break; 1976 } 1977 1978 /* 1979 * Clean out the packet we encapsulated. If we defragged 1980 * the packet the m_head2 is the one that got encapsulated 1981 * and the original must be thrown away. Otherwise m_head2 1982 * *IS* the original. 1983 */ 1984 ifq_dequeue(&ifp->if_snd, m_head); 1985 if (called_defrag) 1986 m_freem(m_head); 1987 need_trans = 1; 1988 1989 /* 1990 * If there's a BPF listener, bounce a copy of this frame 1991 * to him. 1992 */ 1993 BPF_MTAP(ifp, m_head2); 1994 } 1995 1996 if (!need_trans) { 1997 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1998 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 1999 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2000 return; 2001 } 2002 2003 /* Flush the TX descriptors */ 2004 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2005 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2006 2007 sc->re_ldata.re_tx_prodidx = idx; 2008 2009 /* 2010 * RealTek put the TX poll request register in a different 2011 * location on the 8169 gigE chip. I don't know why. 2012 */ 2013 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2014 2015 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2016 /* 2017 * Use the countdown timer for interrupt moderation. 2018 * 'TX done' interrupts are disabled. Instead, we reset the 2019 * countdown timer, which will begin counting until it hits 2020 * the value in the TIMERINT register, and then trigger an 2021 * interrupt. Each time we write to the TIMERCNT register, 2022 * the timer count is reset to 0. 2023 */ 2024 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2025 } 2026 2027 /* 2028 * Set a timeout in case the chip goes out to lunch. 2029 */ 2030 ifp->if_timer = 5; 2031 } 2032 2033 static void 2034 re_init(void *xsc) 2035 { 2036 struct re_softc *sc = xsc; 2037 struct ifnet *ifp = &sc->arpcom.ac_if; 2038 struct mii_data *mii; 2039 uint32_t rxcfg = 0; 2040 2041 mii = device_get_softc(sc->re_miibus); 2042 2043 /* 2044 * Cancel pending I/O and free all RX/TX buffers. 2045 */ 2046 re_stop(sc); 2047 2048 /* 2049 * Enable C+ RX and TX mode, as well as VLAN stripping and 2050 * RX checksum offload. We must configure the C+ register 2051 * before all others. 2052 */ 2053 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2054 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 2055 (ifp->if_capenable & IFCAP_RXCSUM ? 2056 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2057 2058 /* 2059 * Init our MAC address. Even though the chipset 2060 * documentation doesn't mention it, we need to enter "Config 2061 * register write enable" mode to modify the ID registers. 2062 */ 2063 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2064 CSR_WRITE_4(sc, RE_IDR0, 2065 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2066 CSR_WRITE_4(sc, RE_IDR4, 2067 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[4]))); 2068 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2069 2070 /* 2071 * For C+ mode, initialize the RX descriptors and mbufs. 2072 */ 2073 re_rx_list_init(sc); 2074 re_tx_list_init(sc); 2075 2076 /* 2077 * Enable transmit and receive. 2078 */ 2079 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2080 2081 /* 2082 * Set the initial TX and RX configuration. 2083 */ 2084 if (sc->re_testmode) { 2085 if (sc->re_type == RE_8169) 2086 CSR_WRITE_4(sc, RE_TXCFG, 2087 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2088 else 2089 CSR_WRITE_4(sc, RE_TXCFG, 2090 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2091 } else 2092 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2093 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2094 2095 /* Set the individual bit to receive frames for this host only. */ 2096 rxcfg = CSR_READ_4(sc, RE_RXCFG); 2097 rxcfg |= RE_RXCFG_RX_INDIV; 2098 2099 /* If we want promiscuous mode, set the allframes bit. */ 2100 if (ifp->if_flags & IFF_PROMISC) { 2101 rxcfg |= RE_RXCFG_RX_ALLPHYS; 2102 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2103 } else { 2104 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 2105 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2106 } 2107 2108 /* 2109 * Set capture broadcast bit to capture broadcast frames. 2110 */ 2111 if (ifp->if_flags & IFF_BROADCAST) { 2112 rxcfg |= RE_RXCFG_RX_BROAD; 2113 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2114 } else { 2115 rxcfg &= ~RE_RXCFG_RX_BROAD; 2116 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2117 } 2118 2119 /* 2120 * Program the multicast filter, if necessary. 2121 */ 2122 re_setmulti(sc); 2123 2124 #ifdef DEVICE_POLLING 2125 /* 2126 * Disable interrupts if we are polling. 2127 */ 2128 if (ifp->if_flags & IFF_POLLING) 2129 CSR_WRITE_2(sc, RE_IMR, 0); 2130 else /* otherwise ... */ 2131 #endif /* DEVICE_POLLING */ 2132 /* 2133 * Enable interrupts. 2134 */ 2135 if (sc->re_testmode) 2136 CSR_WRITE_2(sc, RE_IMR, 0); 2137 else 2138 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2139 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2140 2141 /* Set initial TX threshold */ 2142 sc->re_txthresh = RE_TX_THRESH_INIT; 2143 2144 /* Start RX/TX process. */ 2145 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2146 #ifdef notdef 2147 /* Enable receiver and transmitter. */ 2148 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2149 #endif 2150 /* 2151 * Load the addresses of the RX and TX lists into the chip. 2152 */ 2153 2154 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2155 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2156 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2157 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2158 2159 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2160 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2161 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2162 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2163 2164 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2165 2166 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2167 /* 2168 * Initialize the timer interrupt register so that 2169 * a timer interrupt will be generated once the timer 2170 * reaches a certain number of ticks. The timer is 2171 * reloaded on each transmit. This gives us TX interrupt 2172 * moderation, which dramatically improves TX frame rate. 2173 */ 2174 if (sc->re_type == RE_8169) 2175 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2176 else 2177 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2178 } 2179 2180 /* 2181 * For 8169 gigE NICs, set the max allowed RX packet 2182 * size so we can receive jumbo frames. 2183 */ 2184 if (sc->re_type == RE_8169) 2185 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2186 2187 if (sc->re_testmode) { 2188 return; 2189 } 2190 2191 mii_mediachg(mii); 2192 2193 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2194 2195 ifp->if_flags |= IFF_RUNNING; 2196 ifp->if_flags &= ~IFF_OACTIVE; 2197 2198 sc->re_link = 0; 2199 callout_reset(&sc->re_timer, hz, re_tick, sc); 2200 } 2201 2202 /* 2203 * Set media options. 2204 */ 2205 static int 2206 re_ifmedia_upd(struct ifnet *ifp) 2207 { 2208 struct re_softc *sc = ifp->if_softc; 2209 struct mii_data *mii; 2210 2211 mii = device_get_softc(sc->re_miibus); 2212 mii_mediachg(mii); 2213 2214 return(0); 2215 } 2216 2217 /* 2218 * Report current media status. 2219 */ 2220 static void 2221 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2222 { 2223 struct re_softc *sc = ifp->if_softc; 2224 struct mii_data *mii; 2225 2226 mii = device_get_softc(sc->re_miibus); 2227 2228 mii_pollstat(mii); 2229 ifmr->ifm_active = mii->mii_media_active; 2230 ifmr->ifm_status = mii->mii_media_status; 2231 } 2232 2233 static int 2234 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2235 { 2236 struct re_softc *sc = ifp->if_softc; 2237 struct ifreq *ifr = (struct ifreq *) data; 2238 struct mii_data *mii; 2239 int error = 0; 2240 2241 switch(command) { 2242 case SIOCSIFMTU: 2243 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2244 error = EINVAL; 2245 ifp->if_mtu = ifr->ifr_mtu; 2246 break; 2247 case SIOCSIFFLAGS: 2248 if (ifp->if_flags & IFF_UP) 2249 re_init(sc); 2250 else if (ifp->if_flags & IFF_RUNNING) 2251 re_stop(sc); 2252 break; 2253 case SIOCADDMULTI: 2254 case SIOCDELMULTI: 2255 re_setmulti(sc); 2256 error = 0; 2257 break; 2258 case SIOCGIFMEDIA: 2259 case SIOCSIFMEDIA: 2260 mii = device_get_softc(sc->re_miibus); 2261 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2262 break; 2263 case SIOCSIFCAP: 2264 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2265 ifp->if_capenable |= 2266 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2267 if (ifp->if_capenable & IFCAP_TXCSUM) 2268 ifp->if_hwassist = RE_CSUM_FEATURES; 2269 else 2270 ifp->if_hwassist = 0; 2271 if (ifp->if_flags & IFF_RUNNING) 2272 re_init(sc); 2273 break; 2274 default: 2275 error = ether_ioctl(ifp, command, data); 2276 break; 2277 } 2278 return(error); 2279 } 2280 2281 static void 2282 re_watchdog(struct ifnet *ifp) 2283 { 2284 struct re_softc *sc = ifp->if_softc; 2285 2286 if_printf(ifp, "watchdog timeout\n"); 2287 2288 ifp->if_oerrors++; 2289 2290 re_txeof(sc); 2291 re_rxeof(sc); 2292 2293 re_init(sc); 2294 2295 if (!ifq_is_empty(&ifp->if_snd)) 2296 ifp->if_start(ifp); 2297 } 2298 2299 /* 2300 * Stop the adapter and free any mbufs allocated to the 2301 * RX and TX lists. 2302 */ 2303 static void 2304 re_stop(struct re_softc *sc) 2305 { 2306 struct ifnet *ifp = &sc->arpcom.ac_if; 2307 int i; 2308 2309 ifp->if_timer = 0; 2310 callout_stop(&sc->re_timer); 2311 2312 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2313 2314 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2315 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2316 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2317 2318 if (sc->re_head != NULL) { 2319 m_freem(sc->re_head); 2320 sc->re_head = sc->re_tail = NULL; 2321 } 2322 2323 /* Free the TX list buffers. */ 2324 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2325 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2326 bus_dmamap_unload(sc->re_ldata.re_mtag, 2327 sc->re_ldata.re_tx_dmamap[i]); 2328 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2329 sc->re_ldata.re_tx_mbuf[i] = NULL; 2330 } 2331 } 2332 2333 /* Free the RX list buffers. */ 2334 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2335 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2336 bus_dmamap_unload(sc->re_ldata.re_mtag, 2337 sc->re_ldata.re_rx_dmamap[i]); 2338 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2339 sc->re_ldata.re_rx_mbuf[i] = NULL; 2340 } 2341 } 2342 } 2343 2344 /* 2345 * Device suspend routine. Stop the interface and save some PCI 2346 * settings in case the BIOS doesn't restore them properly on 2347 * resume. 2348 */ 2349 static int 2350 re_suspend(device_t dev) 2351 { 2352 #ifndef BURN_BRIDGES 2353 int i; 2354 #endif 2355 struct re_softc *sc = device_get_softc(dev); 2356 2357 re_stop(sc); 2358 2359 #ifndef BURN_BRIDGES 2360 for (i = 0; i < 5; i++) 2361 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2362 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2363 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2364 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2365 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2366 #endif 2367 2368 sc->suspended = 1; 2369 2370 return (0); 2371 } 2372 2373 /* 2374 * Device resume routine. Restore some PCI settings in case the BIOS 2375 * doesn't, re-enable busmastering, and restart the interface if 2376 * appropriate. 2377 */ 2378 static int 2379 re_resume(device_t dev) 2380 { 2381 struct re_softc *sc = device_get_softc(dev); 2382 struct ifnet *ifp = &sc->arpcom.ac_if; 2383 #ifndef BURN_BRIDGES 2384 int i; 2385 #endif 2386 2387 #ifndef BURN_BRIDGES 2388 /* better way to do this? */ 2389 for (i = 0; i < 5; i++) 2390 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2391 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2392 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2393 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2394 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2395 2396 /* reenable busmastering */ 2397 pci_enable_busmaster(dev); 2398 pci_enable_io(dev, SYS_RES_IOPORT); 2399 #endif 2400 2401 /* reinitialize interface if necessary */ 2402 if (ifp->if_flags & IFF_UP) 2403 re_init(sc); 2404 2405 sc->suspended = 0; 2406 2407 return (0); 2408 } 2409 2410 /* 2411 * Stop all chip I/O so that the kernel's probe routines don't 2412 * get confused by errant DMAs when rebooting. 2413 */ 2414 static void 2415 re_shutdown(device_t dev) 2416 { 2417 struct re_softc *sc = device_get_softc(dev); 2418 struct ifnet *ifp = &sc->arpcom.ac_if; 2419 2420 lwkt_serialize_enter(ifp->if_serializer); 2421 re_stop(sc); 2422 lwkt_serialize_exit(ifp->if_serializer); 2423 } 2424 2425 static int 2426 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS) 2427 { 2428 struct re_softc *sc = arg1; 2429 struct ifnet *ifp = &sc->arpcom.ac_if; 2430 int error = 0, mod, mod_old; 2431 2432 lwkt_serialize_enter(ifp->if_serializer); 2433 2434 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc); 2435 2436 error = sysctl_handle_int(oidp, &mod, 0, req); 2437 if (error || req->newptr == NULL || mod == mod_old) 2438 goto back; 2439 if (mod != 0 && mod != 1) { 2440 error = EINVAL; 2441 goto back; 2442 } 2443 2444 if (mod) 2445 RE_ENABLE_TX_MODERATION(sc); 2446 else 2447 RE_DISABLE_TX_MODERATION(sc); 2448 2449 re_init(sc); 2450 back: 2451 lwkt_serialize_exit(ifp->if_serializer); 2452 return error; 2453 } 2454