1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.17 2005/10/24 08:06:15 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "opt_polling.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/module.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/thread2.h> 126 127 #include <net/if.h> 128 #include <net/ifq_var.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/vlan/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus_pio.h> 139 #include <machine/bus_memio.h> 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcireg.h> 149 #include <bus/pci/pcivar.h> 150 151 /* "controller miibus0" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 #include <dev/netif/re/if_rereg.h> 155 156 /* 157 * The hardware supports checksumming but, as usual, some chipsets screw it 158 * all up and produce bogus packets, so we disable it by default. 159 */ 160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 #define RE_DISABLE_HWCSUM 162 163 /* 164 * Various supported device vendors/types and their names. 165 */ 166 static struct re_type re_devs[] = { 167 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS, 168 "RealTek 8139C+ 10/100BaseTX" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169, 170 "RealTek 8169 Gigabit Ethernet" }, 171 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S, 172 "RealTek 8169S Single-chip Gigabit Ethernet" }, 173 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S, 174 "RealTek 8110S Single-chip Gigabit Ethernet" }, 175 { 0, 0, 0, NULL } 176 }; 177 178 static struct re_hwrev re_hwrevs[] = { 179 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"}, 180 { RE_HWREV_8169, RE_8169, "8169"}, 181 { RE_HWREV_8169S, RE_8169, "8169S"}, 182 { RE_HWREV_8110S, RE_8169, "8110S"}, 183 { 0, 0, NULL } 184 }; 185 186 static int re_probe(device_t); 187 static int re_attach(device_t); 188 static int re_detach(device_t); 189 190 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 191 192 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 193 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 194 bus_size_t, int); 195 static int re_allocmem(device_t, struct re_softc *); 196 static int re_newbuf(struct re_softc *, int, struct mbuf *); 197 static int re_rx_list_init(struct re_softc *); 198 static int re_tx_list_init(struct re_softc *); 199 static void re_rxeof(struct re_softc *); 200 static void re_txeof(struct re_softc *); 201 static void re_intr(void *); 202 static void re_tick(void *); 203 static void re_start(struct ifnet *); 204 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 205 static void re_init(void *); 206 static void re_stop(struct re_softc *); 207 static void re_watchdog(struct ifnet *); 208 static int re_suspend(device_t); 209 static int re_resume(device_t); 210 static void re_shutdown(device_t); 211 static int re_ifmedia_upd(struct ifnet *); 212 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 213 214 static void re_eeprom_putbyte(struct re_softc *, int); 215 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 216 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int); 217 static int re_gmii_readreg(device_t, int, int); 218 static int re_gmii_writereg(device_t, int, int, int); 219 220 static int re_miibus_readreg(device_t, int, int); 221 static int re_miibus_writereg(device_t, int, int, int); 222 static void re_miibus_statchg(device_t); 223 224 static void re_setmulti(struct re_softc *); 225 static void re_reset(struct re_softc *); 226 227 static int re_diag(struct re_softc *); 228 #ifdef DEVICE_POLLING 229 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 230 #endif 231 232 static device_method_t re_methods[] = { 233 /* Device interface */ 234 DEVMETHOD(device_probe, re_probe), 235 DEVMETHOD(device_attach, re_attach), 236 DEVMETHOD(device_detach, re_detach), 237 DEVMETHOD(device_suspend, re_suspend), 238 DEVMETHOD(device_resume, re_resume), 239 DEVMETHOD(device_shutdown, re_shutdown), 240 241 /* bus interface */ 242 DEVMETHOD(bus_print_child, bus_generic_print_child), 243 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 244 245 /* MII interface */ 246 DEVMETHOD(miibus_readreg, re_miibus_readreg), 247 DEVMETHOD(miibus_writereg, re_miibus_writereg), 248 DEVMETHOD(miibus_statchg, re_miibus_statchg), 249 250 { 0, 0 } 251 }; 252 253 static driver_t re_driver = { 254 "re", 255 re_methods, 256 sizeof(struct re_softc) 257 }; 258 259 static devclass_t re_devclass; 260 261 DECLARE_DUMMY_MODULE(if_re); 262 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 263 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 264 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 265 266 #define EE_SET(x) \ 267 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 268 269 #define EE_CLR(x) \ 270 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 271 272 /* 273 * Send a read command and address to the EEPROM, check for ACK. 274 */ 275 static void 276 re_eeprom_putbyte(struct re_softc *sc, int addr) 277 { 278 int d, i; 279 280 d = addr | sc->re_eecmd_read; 281 282 /* 283 * Feed in each bit and strobe the clock. 284 */ 285 for (i = 0x400; i != 0; i >>= 1) { 286 if (d & i) 287 EE_SET(RE_EE_DATAIN); 288 else 289 EE_CLR(RE_EE_DATAIN); 290 DELAY(100); 291 EE_SET(RE_EE_CLK); 292 DELAY(150); 293 EE_CLR(RE_EE_CLK); 294 DELAY(100); 295 } 296 } 297 298 /* 299 * Read a word of data stored in the EEPROM at address 'addr.' 300 */ 301 static void 302 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 303 { 304 int i; 305 uint16_t word = 0; 306 307 /* Enter EEPROM access mode. */ 308 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 309 310 /* 311 * Send address of word we want to read. 312 */ 313 re_eeprom_putbyte(sc, addr); 314 315 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 for (i = 0x8000; i != 0; i >>= 1) { 321 EE_SET(RE_EE_CLK); 322 DELAY(100); 323 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 324 word |= i; 325 EE_CLR(RE_EE_CLK); 326 DELAY(100); 327 } 328 329 /* Turn off EEPROM access mode. */ 330 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 331 332 *dest = word; 333 } 334 335 /* 336 * Read a sequence of words from the EEPROM. 337 */ 338 static void 339 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap) 340 { 341 int i; 342 uint16_t word = 0, *ptr; 343 344 for (i = 0; i < cnt; i++) { 345 re_eeprom_getword(sc, off + i, &word); 346 ptr = (u_int16_t *)(dest + (i * 2)); 347 if (swap) 348 *ptr = be16toh(word); 349 else 350 *ptr = word; 351 } 352 } 353 354 static int 355 re_gmii_readreg(device_t dev, int phy, int reg) 356 { 357 struct re_softc *sc = device_get_softc(dev); 358 u_int32_t rval; 359 int i; 360 361 if (phy != 1) 362 return(0); 363 364 /* Let the rgephy driver read the GMEDIASTAT register */ 365 366 if (reg == RE_GMEDIASTAT) 367 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 368 369 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 370 DELAY(1000); 371 372 for (i = 0; i < RE_TIMEOUT; i++) { 373 rval = CSR_READ_4(sc, RE_PHYAR); 374 if (rval & RE_PHYAR_BUSY) 375 break; 376 DELAY(100); 377 } 378 379 if (i == RE_TIMEOUT) { 380 device_printf(dev, "PHY read failed\n"); 381 return(0); 382 } 383 384 return(rval & RE_PHYAR_PHYDATA); 385 } 386 387 static int 388 re_gmii_writereg(device_t dev, int phy, int reg, int data) 389 { 390 struct re_softc *sc = device_get_softc(dev); 391 uint32_t rval; 392 int i; 393 394 CSR_WRITE_4(sc, RE_PHYAR, 395 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 396 DELAY(1000); 397 398 for (i = 0; i < RE_TIMEOUT; i++) { 399 rval = CSR_READ_4(sc, RE_PHYAR); 400 if ((rval & RE_PHYAR_BUSY) == 0) 401 break; 402 DELAY(100); 403 } 404 405 if (i == RE_TIMEOUT) 406 device_printf(dev, "PHY write failed\n"); 407 408 return(0); 409 } 410 411 static int 412 re_miibus_readreg(device_t dev, int phy, int reg) 413 { 414 struct re_softc *sc = device_get_softc(dev); 415 uint16_t rval = 0; 416 uint16_t re8139_reg = 0; 417 418 if (sc->re_type == RE_8169) { 419 rval = re_gmii_readreg(dev, phy, reg); 420 return(rval); 421 } 422 423 /* Pretend the internal PHY is only at address 0 */ 424 if (phy) 425 return(0); 426 427 switch(reg) { 428 case MII_BMCR: 429 re8139_reg = RE_BMCR; 430 break; 431 case MII_BMSR: 432 re8139_reg = RE_BMSR; 433 break; 434 case MII_ANAR: 435 re8139_reg = RE_ANAR; 436 break; 437 case MII_ANER: 438 re8139_reg = RE_ANER; 439 break; 440 case MII_ANLPAR: 441 re8139_reg = RE_LPAR; 442 break; 443 case MII_PHYIDR1: 444 case MII_PHYIDR2: 445 return(0); 446 /* 447 * Allow the rlphy driver to read the media status 448 * register. If we have a link partner which does not 449 * support NWAY, this is the register which will tell 450 * us the results of parallel detection. 451 */ 452 case RE_MEDIASTAT: 453 return(CSR_READ_1(sc, RE_MEDIASTAT)); 454 default: 455 device_printf(dev, "bad phy register\n"); 456 return(0); 457 } 458 rval = CSR_READ_2(sc, re8139_reg); 459 return(rval); 460 } 461 462 static int 463 re_miibus_writereg(device_t dev, int phy, int reg, int data) 464 { 465 struct re_softc *sc= device_get_softc(dev); 466 u_int16_t re8139_reg = 0; 467 468 if (sc->re_type == RE_8169) 469 return(re_gmii_writereg(dev, phy, reg, data)); 470 471 /* Pretend the internal PHY is only at address 0 */ 472 if (phy) 473 return(0); 474 475 switch(reg) { 476 case MII_BMCR: 477 re8139_reg = RE_BMCR; 478 break; 479 case MII_BMSR: 480 re8139_reg = RE_BMSR; 481 break; 482 case MII_ANAR: 483 re8139_reg = RE_ANAR; 484 break; 485 case MII_ANER: 486 re8139_reg = RE_ANER; 487 break; 488 case MII_ANLPAR: 489 re8139_reg = RE_LPAR; 490 break; 491 case MII_PHYIDR1: 492 case MII_PHYIDR2: 493 return(0); 494 default: 495 device_printf(dev, "bad phy register\n"); 496 return(0); 497 } 498 CSR_WRITE_2(sc, re8139_reg, data); 499 return(0); 500 } 501 502 static void 503 re_miibus_statchg(device_t dev) 504 { 505 } 506 507 /* 508 * Program the 64-bit multicast hash filter. 509 */ 510 static void 511 re_setmulti(struct re_softc *sc) 512 { 513 struct ifnet *ifp = &sc->arpcom.ac_if; 514 int h = 0; 515 uint32_t hashes[2] = { 0, 0 }; 516 struct ifmultiaddr *ifma; 517 uint32_t rxfilt; 518 int mcnt = 0; 519 520 rxfilt = CSR_READ_4(sc, RE_RXCFG); 521 522 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 523 rxfilt |= RE_RXCFG_RX_MULTI; 524 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 525 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 526 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 527 return; 528 } 529 530 /* first, zot all the existing hash bits */ 531 CSR_WRITE_4(sc, RE_MAR0, 0); 532 CSR_WRITE_4(sc, RE_MAR4, 0); 533 534 /* now program new ones */ 535 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 536 if (ifma->ifma_addr->sa_family != AF_LINK) 537 continue; 538 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 539 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 540 if (h < 32) 541 hashes[0] |= (1 << h); 542 else 543 hashes[1] |= (1 << (h - 32)); 544 mcnt++; 545 } 546 547 if (mcnt) 548 rxfilt |= RE_RXCFG_RX_MULTI; 549 else 550 rxfilt &= ~RE_RXCFG_RX_MULTI; 551 552 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 553 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 554 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 555 } 556 557 static void 558 re_reset(struct re_softc *sc) 559 { 560 int i; 561 562 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 563 564 for (i = 0; i < RE_TIMEOUT; i++) { 565 DELAY(10); 566 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 567 break; 568 } 569 if (i == RE_TIMEOUT) 570 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 571 572 CSR_WRITE_1(sc, 0x82, 1); 573 } 574 575 /* 576 * The following routine is designed to test for a defect on some 577 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 578 * lines connected to the bus, however for a 32-bit only card, they 579 * should be pulled high. The result of this defect is that the 580 * NIC will not work right if you plug it into a 64-bit slot: DMA 581 * operations will be done with 64-bit transfers, which will fail 582 * because the 64-bit data lines aren't connected. 583 * 584 * There's no way to work around this (short of talking a soldering 585 * iron to the board), however we can detect it. The method we use 586 * here is to put the NIC into digital loopback mode, set the receiver 587 * to promiscuous mode, and then try to send a frame. We then compare 588 * the frame data we sent to what was received. If the data matches, 589 * then the NIC is working correctly, otherwise we know the user has 590 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 591 * slot. In the latter case, there's no way the NIC can work correctly, 592 * so we print out a message on the console and abort the device attach. 593 */ 594 595 static int 596 re_diag(struct re_softc *sc) 597 { 598 struct ifnet *ifp = &sc->arpcom.ac_if; 599 struct mbuf *m0; 600 struct ether_header *eh; 601 struct re_desc *cur_rx; 602 uint16_t status; 603 uint32_t rxstat; 604 int total_len, i, error = 0; 605 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 606 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 607 608 /* Allocate a single mbuf */ 609 610 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 611 if (m0 == NULL) 612 return(ENOBUFS); 613 614 /* 615 * Initialize the NIC in test mode. This sets the chip up 616 * so that it can send and receive frames, but performs the 617 * following special functions: 618 * - Puts receiver in promiscuous mode 619 * - Enables digital loopback mode 620 * - Leaves interrupts turned off 621 */ 622 623 ifp->if_flags |= IFF_PROMISC; 624 sc->re_testmode = 1; 625 re_init(sc); 626 re_stop(sc); 627 DELAY(100000); 628 re_init(sc); 629 630 /* Put some data in the mbuf */ 631 632 eh = mtod(m0, struct ether_header *); 633 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 634 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 635 eh->ether_type = htons(ETHERTYPE_IP); 636 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 637 638 /* 639 * Queue the packet, start transmission. 640 * Note: ifq_handoff() ultimately calls re_start() for us. 641 */ 642 643 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 644 error = ifq_handoff(ifp, m0, NULL); 645 if (error) { 646 m0 = NULL; 647 goto done; 648 } 649 m0 = NULL; 650 651 /* Wait for it to propagate through the chip */ 652 653 DELAY(100000); 654 for (i = 0; i < RE_TIMEOUT; i++) { 655 status = CSR_READ_2(sc, RE_ISR); 656 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 657 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 658 break; 659 DELAY(10); 660 } 661 662 if (i == RE_TIMEOUT) { 663 if_printf(ifp, "diagnostic failed to receive packet " 664 "in loopback mode\n"); 665 error = EIO; 666 goto done; 667 } 668 669 /* 670 * The packet should have been dumped into the first 671 * entry in the RX DMA ring. Grab it from there. 672 */ 673 674 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 675 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 676 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 677 BUS_DMASYNC_POSTWRITE); 678 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 679 680 m0 = sc->re_ldata.re_rx_mbuf[0]; 681 sc->re_ldata.re_rx_mbuf[0] = NULL; 682 eh = mtod(m0, struct ether_header *); 683 684 cur_rx = &sc->re_ldata.re_rx_list[0]; 685 total_len = RE_RXBYTES(cur_rx); 686 rxstat = le32toh(cur_rx->re_cmdstat); 687 688 if (total_len != ETHER_MIN_LEN) { 689 if_printf(ifp, "diagnostic failed, received short packet\n"); 690 error = EIO; 691 goto done; 692 } 693 694 /* Test that the received packet data matches what we sent. */ 695 696 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 697 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 698 be16toh(eh->ether_type) != ETHERTYPE_IP) { 699 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 700 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 701 dst, ":", src, ":", ETHERTYPE_IP); 702 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 703 eh->ether_dhost, ":", eh->ether_shost, ":", 704 ntohs(eh->ether_type)); 705 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 706 "into a 64-bit PCI slot.\n"); 707 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 708 "for proper operation.\n"); 709 if_printf(ifp, "Read the re(4) man page for more details.\n"); 710 error = EIO; 711 } 712 713 done: 714 /* Turn interface off, release resources */ 715 716 sc->re_testmode = 0; 717 ifp->if_flags &= ~IFF_PROMISC; 718 re_stop(sc); 719 if (m0 != NULL) 720 m_freem(m0); 721 722 return (error); 723 } 724 725 /* 726 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 727 * IDs against our list and return a device name if we find a match. 728 */ 729 static int 730 re_probe(device_t dev) 731 { 732 struct re_type *t; 733 struct re_softc *sc; 734 int rid; 735 uint32_t hwrev; 736 uint16_t vendor, product; 737 738 t = re_devs; 739 740 vendor = pci_get_vendor(dev); 741 product = pci_get_device(dev); 742 743 for (t = re_devs; t->re_name != NULL; t++) { 744 if (product == t->re_did && vendor == t->re_vid) 745 break; 746 } 747 748 /* 749 * Check if we found a RealTek device. 750 */ 751 if (t->re_name == NULL) 752 return(ENXIO); 753 754 /* 755 * Temporarily map the I/O space so we can read the chip ID register. 756 */ 757 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 758 rid = RE_PCI_LOIO; 759 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 760 RF_ACTIVE); 761 if (sc->re_res == NULL) { 762 device_printf(dev, "couldn't map ports/memory\n"); 763 free(sc, M_TEMP); 764 return(ENXIO); 765 } 766 767 sc->re_btag = rman_get_bustag(sc->re_res); 768 sc->re_bhandle = rman_get_bushandle(sc->re_res); 769 770 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 771 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 772 free(sc, M_TEMP); 773 774 /* 775 * and continue matching for the specific chip... 776 */ 777 for (; t->re_name != NULL; t++) { 778 if (product == t->re_did && vendor == t->re_vid && 779 t->re_basetype == hwrev) { 780 device_set_desc(dev, t->re_name); 781 return(0); 782 } 783 } 784 return(ENXIO); 785 } 786 787 /* 788 * This routine takes the segment list provided as the result of 789 * a bus_dma_map_load() operation and assigns the addresses/lengths 790 * to RealTek DMA descriptors. This can be called either by the RX 791 * code or the TX code. In the RX case, we'll probably wind up mapping 792 * at most one segment. For the TX case, there could be any number of 793 * segments since TX packets may span multiple mbufs. In either case, 794 * if the number of segments is larger than the re_maxsegs limit 795 * specified by the caller, we abort the mapping operation. Sadly, 796 * whoever designed the buffer mapping API did not provide a way to 797 * return an error from here, so we have to fake it a bit. 798 */ 799 800 static void 801 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 802 bus_size_t mapsize, int error) 803 { 804 struct re_dmaload_arg *ctx; 805 struct re_desc *d = NULL; 806 int i = 0, idx; 807 uint32_t cmdstat; 808 809 if (error) 810 return; 811 812 ctx = arg; 813 814 /* Signal error to caller if there's too many segments */ 815 if (nseg > ctx->re_maxsegs) { 816 ctx->re_maxsegs = 0; 817 return; 818 } 819 820 /* 821 * Map the segment array into descriptors. Note that we set the 822 * start-of-frame and end-of-frame markers for either TX or RX, but 823 * they really only have meaning in the TX case. (In the RX case, 824 * it's the chip that tells us where packets begin and end.) 825 * We also keep track of the end of the ring and set the 826 * end-of-ring bits as needed, and we set the ownership bits 827 * in all except the very first descriptor. (The caller will 828 * set this descriptor later when it start transmission or 829 * reception.) 830 */ 831 idx = ctx->re_idx; 832 for (;;) { 833 d = &ctx->re_ring[idx]; 834 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 835 ctx->re_maxsegs = 0; 836 return; 837 } 838 cmdstat = segs[i].ds_len; 839 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 840 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 841 if (i == 0) 842 cmdstat |= RE_TDESC_CMD_SOF; 843 else 844 cmdstat |= RE_TDESC_CMD_OWN; 845 if (idx == (RE_RX_DESC_CNT - 1)) 846 cmdstat |= RE_TDESC_CMD_EOR; 847 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 848 i++; 849 if (i == nseg) 850 break; 851 RE_DESC_INC(idx); 852 } 853 854 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 855 ctx->re_maxsegs = nseg; 856 ctx->re_idx = idx; 857 } 858 859 /* 860 * Map a single buffer address. 861 */ 862 863 static void 864 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 865 { 866 uint32_t *addr; 867 868 if (error) 869 return; 870 871 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 872 addr = arg; 873 *addr = segs->ds_addr; 874 } 875 876 static int 877 re_allocmem(device_t dev, struct re_softc *sc) 878 { 879 int error, i, nseg; 880 881 /* 882 * Allocate map for RX mbufs. 883 */ 884 nseg = 32; 885 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 886 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 887 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 888 &sc->re_ldata.re_mtag); 889 if (error) { 890 device_printf(dev, "could not allocate dma tag\n"); 891 return(error); 892 } 893 894 /* 895 * Allocate map for TX descriptor list. 896 */ 897 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 898 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 899 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 900 &sc->re_ldata.re_tx_list_tag); 901 if (error) { 902 device_printf(dev, "could not allocate dma tag\n"); 903 return(error); 904 } 905 906 /* Allocate DMA'able memory for the TX ring */ 907 908 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 909 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 910 &sc->re_ldata.re_tx_list_map); 911 if (error) { 912 device_printf(dev, "could not allocate TX ring\n"); 913 return(error); 914 } 915 916 /* Load the map for the TX ring. */ 917 918 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 919 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 920 RE_TX_LIST_SZ, re_dma_map_addr, 921 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 922 if (error) { 923 device_printf(dev, "could not get addres of TX ring\n"); 924 return(error); 925 } 926 927 /* Create DMA maps for TX buffers */ 928 929 for (i = 0; i < RE_TX_DESC_CNT; i++) { 930 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 931 &sc->re_ldata.re_tx_dmamap[i]); 932 if (error) { 933 device_printf(dev, "can't create DMA map for TX\n"); 934 return(error); 935 } 936 } 937 938 /* 939 * Allocate map for RX descriptor list. 940 */ 941 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 942 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 943 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 944 &sc->re_ldata.re_rx_list_tag); 945 if (error) { 946 device_printf(dev, "could not allocate dma tag\n"); 947 return(error); 948 } 949 950 /* Allocate DMA'able memory for the RX ring */ 951 952 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 953 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 954 &sc->re_ldata.re_rx_list_map); 955 if (error) { 956 device_printf(dev, "could not allocate RX ring\n"); 957 return(error); 958 } 959 960 /* Load the map for the RX ring. */ 961 962 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 963 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 964 RE_TX_LIST_SZ, re_dma_map_addr, 965 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 966 if (error) { 967 device_printf(dev, "could not get address of RX ring\n"); 968 return(error); 969 } 970 971 /* Create DMA maps for RX buffers */ 972 973 for (i = 0; i < RE_RX_DESC_CNT; i++) { 974 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 975 &sc->re_ldata.re_rx_dmamap[i]); 976 if (error) { 977 device_printf(dev, "can't create DMA map for RX\n"); 978 return(ENOMEM); 979 } 980 } 981 982 return(0); 983 } 984 985 /* 986 * Attach the interface. Allocate softc structures, do ifmedia 987 * setup and ethernet/BPF attach. 988 */ 989 static int 990 re_attach(device_t dev) 991 { 992 struct re_softc *sc = device_get_softc(dev); 993 struct ifnet *ifp; 994 struct re_hwrev *hw_rev; 995 uint8_t eaddr[ETHER_ADDR_LEN]; 996 int hwrev; 997 u_int16_t re_did = 0; 998 int error = 0, rid, i; 999 1000 callout_init(&sc->re_timer); 1001 1002 #ifndef BURN_BRIDGES 1003 /* 1004 * Handle power management nonsense. 1005 */ 1006 1007 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1008 uint32_t membase, irq; 1009 1010 /* Save important PCI config data. */ 1011 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1012 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1013 1014 /* Reset the power state. */ 1015 device_printf(dev, "chip is is in D%d power mode " 1016 "-- setting to D0\n", pci_get_powerstate(dev)); 1017 1018 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1019 1020 /* Restore PCI config data. */ 1021 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1022 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1023 } 1024 #endif 1025 /* 1026 * Map control/status registers. 1027 */ 1028 pci_enable_busmaster(dev); 1029 1030 rid = RE_PCI_LOIO; 1031 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1032 RF_ACTIVE); 1033 1034 if (sc->re_res == NULL) { 1035 device_printf(dev, "couldn't map ports/memory\n"); 1036 error = ENXIO; 1037 goto fail; 1038 } 1039 1040 sc->re_btag = rman_get_bustag(sc->re_res); 1041 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1042 1043 /* Allocate interrupt */ 1044 rid = 0; 1045 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1046 RF_SHAREABLE | RF_ACTIVE); 1047 1048 if (sc->re_irq == NULL) { 1049 device_printf(dev, "couldn't map interrupt\n"); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 1054 /* Reset the adapter. */ 1055 re_reset(sc); 1056 1057 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1058 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1059 if (hw_rev->re_rev == hwrev) { 1060 sc->re_type = hw_rev->re_type; 1061 break; 1062 } 1063 } 1064 1065 if (sc->re_type == RE_8169) { 1066 /* Set RX length mask */ 1067 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1068 1069 /* Force station address autoload from the EEPROM */ 1070 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD); 1071 for (i = 0; i < RE_TIMEOUT; i++) { 1072 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0) 1073 break; 1074 DELAY(100); 1075 } 1076 if (i == RE_TIMEOUT) 1077 device_printf(dev, "eeprom autoload timed out\n"); 1078 1079 for (i = 0; i < ETHER_ADDR_LEN; i++) 1080 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 1081 } else { 1082 uint16_t as[3]; 1083 1084 /* Set RX length mask */ 1085 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1086 1087 sc->re_eecmd_read = RE_EECMD_READ_6BIT; 1088 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1089 if (re_did != 0x8129) 1090 sc->re_eecmd_read = RE_EECMD_READ_8BIT; 1091 1092 /* 1093 * Get station address from the EEPROM. 1094 */ 1095 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0); 1096 for (i = 0; i < 3; i++) { 1097 eaddr[(i * 2) + 0] = as[i] & 0xff; 1098 eaddr[(i * 2) + 1] = as[i] >> 8; 1099 } 1100 } 1101 1102 /* 1103 * Allocate the parent bus DMA tag appropriate for PCI. 1104 */ 1105 #define RE_NSEG_NEW 32 1106 error = bus_dma_tag_create(NULL, /* parent */ 1107 1, 0, /* alignment, boundary */ 1108 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, NULL, /* filter, filterarg */ 1111 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1112 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1113 BUS_DMA_ALLOCNOW, /* flags */ 1114 &sc->re_parent_tag); 1115 if (error) 1116 goto fail; 1117 1118 error = re_allocmem(dev, sc); 1119 1120 if (error) 1121 goto fail; 1122 1123 /* Do MII setup */ 1124 if (mii_phy_probe(dev, &sc->re_miibus, 1125 re_ifmedia_upd, re_ifmedia_sts)) { 1126 device_printf(dev, "MII without any phy!\n"); 1127 error = ENXIO; 1128 goto fail; 1129 } 1130 1131 ifp = &sc->arpcom.ac_if; 1132 ifp->if_softc = sc; 1133 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1134 ifp->if_mtu = ETHERMTU; 1135 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1136 ifp->if_ioctl = re_ioctl; 1137 ifp->if_capabilities = IFCAP_VLAN_MTU; 1138 ifp->if_start = re_start; 1139 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1140 #ifdef DEVICE_POLLING 1141 ifp->if_poll = re_poll; 1142 #endif 1143 ifp->if_watchdog = re_watchdog; 1144 ifp->if_init = re_init; 1145 if (sc->re_type == RE_8169) 1146 ifp->if_baudrate = 1000000000; 1147 else 1148 ifp->if_baudrate = 100000000; 1149 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1150 ifq_set_ready(&ifp->if_snd); 1151 #ifdef RE_DISABLE_HWCSUM 1152 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1153 ifp->if_hwassist = 0; 1154 #else 1155 ifp->if_capenable = ifp->if_capabilities; 1156 ifp->if_hwassist = RE_CSUM_FEATURES; 1157 #endif 1158 1159 /* 1160 * Call MI attach routine. 1161 */ 1162 ether_ifattach(ifp, eaddr); 1163 1164 /* Perform hardware diagnostic. */ 1165 error = re_diag(sc); 1166 1167 if (error) { 1168 device_printf(dev, "hardware diagnostic failure\n"); 1169 ether_ifdetach(ifp); 1170 goto fail; 1171 } 1172 1173 /* Hook interrupt last to avoid having to lock softc */ 1174 error = bus_setup_intr(dev, sc->re_irq, 0, re_intr, sc, 1175 &sc->re_intrhand, NULL); 1176 1177 if (error) { 1178 device_printf(dev, "couldn't set up irq\n"); 1179 ether_ifdetach(ifp); 1180 goto fail; 1181 } 1182 1183 fail: 1184 if (error) 1185 re_detach(dev); 1186 1187 return (error); 1188 } 1189 1190 /* 1191 * Shutdown hardware and free up resources. This can be called any 1192 * time after the mutex has been initialized. It is called in both 1193 * the error case in attach and the normal detach case so it needs 1194 * to be careful about only freeing resources that have actually been 1195 * allocated. 1196 */ 1197 static int 1198 re_detach(device_t dev) 1199 { 1200 struct re_softc *sc = device_get_softc(dev); 1201 struct ifnet *ifp = &sc->arpcom.ac_if; 1202 int i; 1203 1204 crit_enter(); 1205 1206 /* These should only be active if attach succeeded */ 1207 if (device_is_attached(dev)) { 1208 re_stop(sc); 1209 ether_ifdetach(ifp); 1210 } 1211 if (sc->re_miibus) 1212 device_delete_child(dev, sc->re_miibus); 1213 bus_generic_detach(dev); 1214 1215 if (sc->re_intrhand) 1216 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1217 1218 crit_exit(); 1219 1220 if (sc->re_irq) 1221 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1222 if (sc->re_res) 1223 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1224 sc->re_res); 1225 1226 /* Unload and free the RX DMA ring memory and map */ 1227 1228 if (sc->re_ldata.re_rx_list_tag) { 1229 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1230 sc->re_ldata.re_rx_list_map); 1231 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1232 sc->re_ldata.re_rx_list, 1233 sc->re_ldata.re_rx_list_map); 1234 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1235 } 1236 1237 /* Unload and free the TX DMA ring memory and map */ 1238 1239 if (sc->re_ldata.re_tx_list_tag) { 1240 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1241 sc->re_ldata.re_tx_list_map); 1242 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1243 sc->re_ldata.re_tx_list, 1244 sc->re_ldata.re_tx_list_map); 1245 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1246 } 1247 1248 /* Destroy all the RX and TX buffer maps */ 1249 1250 if (sc->re_ldata.re_mtag) { 1251 for (i = 0; i < RE_TX_DESC_CNT; i++) 1252 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1253 sc->re_ldata.re_tx_dmamap[i]); 1254 for (i = 0; i < RE_RX_DESC_CNT; i++) 1255 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1256 sc->re_ldata.re_rx_dmamap[i]); 1257 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1258 } 1259 1260 /* Unload and free the stats buffer and map */ 1261 1262 if (sc->re_ldata.re_stag) { 1263 bus_dmamap_unload(sc->re_ldata.re_stag, 1264 sc->re_ldata.re_rx_list_map); 1265 bus_dmamem_free(sc->re_ldata.re_stag, 1266 sc->re_ldata.re_stats, 1267 sc->re_ldata.re_smap); 1268 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1269 } 1270 1271 if (sc->re_parent_tag) 1272 bus_dma_tag_destroy(sc->re_parent_tag); 1273 1274 return(0); 1275 } 1276 1277 static int 1278 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1279 { 1280 struct re_dmaload_arg arg; 1281 struct mbuf *n = NULL; 1282 int error; 1283 1284 if (m == NULL) { 1285 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1286 if (n == NULL) 1287 return(ENOBUFS); 1288 m = n; 1289 } else 1290 m->m_data = m->m_ext.ext_buf; 1291 1292 /* 1293 * Initialize mbuf length fields and fixup 1294 * alignment so that the frame payload is 1295 * longword aligned. 1296 */ 1297 m->m_len = m->m_pkthdr.len = MCLBYTES; 1298 m_adj(m, ETHER_ALIGN); 1299 1300 arg.sc = sc; 1301 arg.re_idx = idx; 1302 arg.re_maxsegs = 1; 1303 arg.re_flags = 0; 1304 arg.re_ring = sc->re_ldata.re_rx_list; 1305 1306 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1307 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1308 &arg, BUS_DMA_NOWAIT); 1309 if (error || arg.re_maxsegs != 1) { 1310 if (n != NULL) 1311 m_freem(n); 1312 return (ENOMEM); 1313 } 1314 1315 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1316 sc->re_ldata.re_rx_mbuf[idx] = m; 1317 1318 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1319 BUS_DMASYNC_PREREAD); 1320 1321 return(0); 1322 } 1323 1324 static int 1325 re_tx_list_init(struct re_softc *sc) 1326 { 1327 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1328 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1329 1330 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1331 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1332 sc->re_ldata.re_tx_prodidx = 0; 1333 sc->re_ldata.re_tx_considx = 0; 1334 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1335 1336 return(0); 1337 } 1338 1339 static int 1340 re_rx_list_init(struct re_softc *sc) 1341 { 1342 int i, error; 1343 1344 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1345 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1346 1347 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1348 error = re_newbuf(sc, i, NULL); 1349 if (error) 1350 return(error); 1351 } 1352 1353 /* Flush the RX descriptors */ 1354 1355 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1356 sc->re_ldata.re_rx_list_map, 1357 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1358 1359 sc->re_ldata.re_rx_prodidx = 0; 1360 sc->re_head = sc->re_tail = NULL; 1361 1362 return(0); 1363 } 1364 1365 /* 1366 * RX handler for C+ and 8169. For the gigE chips, we support 1367 * the reception of jumbo frames that have been fragmented 1368 * across multiple 2K mbuf cluster buffers. 1369 */ 1370 static void 1371 re_rxeof(struct re_softc *sc) 1372 { 1373 struct ifnet *ifp = &sc->arpcom.ac_if; 1374 struct mbuf *m; 1375 struct re_desc *cur_rx; 1376 uint32_t rxstat, rxvlan; 1377 int i, total_len; 1378 1379 /* Invalidate the descriptor memory */ 1380 1381 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1382 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1383 1384 for (i = sc->re_ldata.re_rx_prodidx; 1385 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1386 cur_rx = &sc->re_ldata.re_rx_list[i]; 1387 m = sc->re_ldata.re_rx_mbuf[i]; 1388 total_len = RE_RXBYTES(cur_rx); 1389 rxstat = le32toh(cur_rx->re_cmdstat); 1390 rxvlan = le32toh(cur_rx->re_vlanctl); 1391 1392 /* Invalidate the RX mbuf and unload its map */ 1393 1394 bus_dmamap_sync(sc->re_ldata.re_mtag, 1395 sc->re_ldata.re_rx_dmamap[i], 1396 BUS_DMASYNC_POSTWRITE); 1397 bus_dmamap_unload(sc->re_ldata.re_mtag, 1398 sc->re_ldata.re_rx_dmamap[i]); 1399 1400 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1401 m->m_len = MCLBYTES - ETHER_ALIGN; 1402 if (sc->re_head == NULL) { 1403 sc->re_head = sc->re_tail = m; 1404 } else { 1405 sc->re_tail->m_next = m; 1406 sc->re_tail = m; 1407 } 1408 re_newbuf(sc, i, NULL); 1409 continue; 1410 } 1411 1412 /* 1413 * NOTE: for the 8139C+, the frame length field 1414 * is always 12 bits in size, but for the gigE chips, 1415 * it is 13 bits (since the max RX frame length is 16K). 1416 * Unfortunately, all 32 bits in the status word 1417 * were already used, so to make room for the extra 1418 * length bit, RealTek took out the 'frame alignment 1419 * error' bit and shifted the other status bits 1420 * over one slot. The OWN, EOR, FS and LS bits are 1421 * still in the same places. We have already extracted 1422 * the frame length and checked the OWN bit, so rather 1423 * than using an alternate bit mapping, we shift the 1424 * status bits one space to the right so we can evaluate 1425 * them using the 8169 status as though it was in the 1426 * same format as that of the 8139C+. 1427 */ 1428 if (sc->re_type == RE_8169) 1429 rxstat >>= 1; 1430 1431 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1432 ifp->if_ierrors++; 1433 /* 1434 * If this is part of a multi-fragment packet, 1435 * discard all the pieces. 1436 */ 1437 if (sc->re_head != NULL) { 1438 m_freem(sc->re_head); 1439 sc->re_head = sc->re_tail = NULL; 1440 } 1441 re_newbuf(sc, i, m); 1442 continue; 1443 } 1444 1445 /* 1446 * If allocating a replacement mbuf fails, 1447 * reload the current one. 1448 */ 1449 1450 if (re_newbuf(sc, i, NULL)) { 1451 ifp->if_ierrors++; 1452 if (sc->re_head != NULL) { 1453 m_freem(sc->re_head); 1454 sc->re_head = sc->re_tail = NULL; 1455 } 1456 re_newbuf(sc, i, m); 1457 continue; 1458 } 1459 1460 if (sc->re_head != NULL) { 1461 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1462 /* 1463 * Special case: if there's 4 bytes or less 1464 * in this buffer, the mbuf can be discarded: 1465 * the last 4 bytes is the CRC, which we don't 1466 * care about anyway. 1467 */ 1468 if (m->m_len <= ETHER_CRC_LEN) { 1469 sc->re_tail->m_len -= 1470 (ETHER_CRC_LEN - m->m_len); 1471 m_freem(m); 1472 } else { 1473 m->m_len -= ETHER_CRC_LEN; 1474 sc->re_tail->m_next = m; 1475 } 1476 m = sc->re_head; 1477 sc->re_head = sc->re_tail = NULL; 1478 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1479 } else 1480 m->m_pkthdr.len = m->m_len = 1481 (total_len - ETHER_CRC_LEN); 1482 1483 ifp->if_ipackets++; 1484 m->m_pkthdr.rcvif = ifp; 1485 1486 /* Do RX checksumming if enabled */ 1487 1488 if (ifp->if_capenable & IFCAP_RXCSUM) { 1489 1490 /* Check IP header checksum */ 1491 if (rxstat & RE_RDESC_STAT_PROTOID) 1492 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1493 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1494 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1495 1496 /* Check TCP/UDP checksum */ 1497 if ((RE_TCPPKT(rxstat) && 1498 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1499 (RE_UDPPKT(rxstat) && 1500 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1501 m->m_pkthdr.csum_flags |= 1502 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1503 m->m_pkthdr.csum_data = 0xffff; 1504 } 1505 } 1506 1507 if (rxvlan & RE_RDESC_VLANCTL_TAG) 1508 VLAN_INPUT_TAG(m, 1509 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1510 else 1511 (*ifp->if_input)(ifp, m); 1512 } 1513 1514 /* Flush the RX DMA ring */ 1515 1516 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1517 sc->re_ldata.re_rx_list_map, 1518 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1519 1520 sc->re_ldata.re_rx_prodidx = i; 1521 } 1522 1523 static void 1524 re_txeof(struct re_softc *sc) 1525 { 1526 struct ifnet *ifp = &sc->arpcom.ac_if; 1527 uint32_t txstat; 1528 int idx; 1529 1530 /* Invalidate the TX descriptor list */ 1531 1532 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1533 sc->re_ldata.re_tx_list_map, 1534 BUS_DMASYNC_POSTREAD); 1535 1536 for (idx = sc->re_ldata.re_tx_considx; 1537 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) { 1538 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1539 if (txstat & RE_TDESC_CMD_OWN) 1540 break; 1541 1542 /* 1543 * We only stash mbufs in the last descriptor 1544 * in a fragment chain, which also happens to 1545 * be the only place where the TX status bits 1546 * are valid. 1547 */ 1548 if (txstat & RE_TDESC_CMD_EOF) { 1549 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1550 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1551 bus_dmamap_unload(sc->re_ldata.re_mtag, 1552 sc->re_ldata.re_tx_dmamap[idx]); 1553 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1554 RE_TDESC_STAT_COLCNT)) 1555 ifp->if_collisions++; 1556 if (txstat & RE_TDESC_STAT_TXERRSUM) 1557 ifp->if_oerrors++; 1558 else 1559 ifp->if_opackets++; 1560 } 1561 sc->re_ldata.re_tx_free++; 1562 } 1563 1564 /* No changes made to the TX ring, so no flush needed */ 1565 if (idx != sc->re_ldata.re_tx_considx) { 1566 sc->re_ldata.re_tx_considx = idx; 1567 ifp->if_flags &= ~IFF_OACTIVE; 1568 ifp->if_timer = 0; 1569 } 1570 1571 /* 1572 * If not all descriptors have been released reaped yet, 1573 * reload the timer so that we will eventually get another 1574 * interrupt that will cause us to re-enter this routine. 1575 * This is done in case the transmitter has gone idle. 1576 */ 1577 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 1578 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1579 } 1580 1581 static void 1582 re_tick(void *xsc) 1583 { 1584 struct re_softc *sc = xsc; 1585 struct mii_data *mii; 1586 1587 crit_enter(); 1588 1589 mii = device_get_softc(sc->re_miibus); 1590 mii_tick(mii); 1591 1592 callout_reset(&sc->re_timer, hz, re_tick, sc); 1593 1594 crit_exit(); 1595 } 1596 1597 #ifdef DEVICE_POLLING 1598 1599 static void 1600 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1601 { 1602 struct re_softc *sc = ifp->if_softc; 1603 1604 switch(cmd) { 1605 case POLL_REGISTER: 1606 /* disable interrupts */ 1607 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1608 break; 1609 case POLL_DEREGISTER: 1610 /* enable interrupts */ 1611 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1612 break; 1613 default: 1614 sc->rxcycles = count; 1615 re_rxeof(sc); 1616 re_txeof(sc); 1617 1618 if (!ifq_is_empty(&ifp->if_snd)) 1619 (*ifp->if_start)(ifp); 1620 1621 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1622 uint16_t status; 1623 1624 status = CSR_READ_2(sc, RE_ISR); 1625 if (status == 0xffff) 1626 return; 1627 if (status) 1628 CSR_WRITE_2(sc, RE_ISR, status); 1629 1630 /* 1631 * XXX check behaviour on receiver stalls. 1632 */ 1633 1634 if (status & RE_ISR_SYSTEM_ERR) { 1635 re_reset(sc); 1636 re_init(sc); 1637 } 1638 } 1639 break; 1640 } 1641 } 1642 #endif /* DEVICE_POLLING */ 1643 1644 static void 1645 re_intr(void *arg) 1646 { 1647 struct re_softc *sc = arg; 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 uint16_t status; 1650 1651 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1652 return; 1653 1654 for (;;) { 1655 status = CSR_READ_2(sc, RE_ISR); 1656 /* If the card has gone away the read returns 0xffff. */ 1657 if (status == 0xffff) 1658 break; 1659 if (status) 1660 CSR_WRITE_2(sc, RE_ISR, status); 1661 1662 if ((status & RE_INTRS_CPLUS) == 0) 1663 break; 1664 1665 if (status & RE_ISR_RX_OK) 1666 re_rxeof(sc); 1667 1668 if (status & RE_ISR_RX_ERR) 1669 re_rxeof(sc); 1670 1671 if ((status & RE_ISR_TIMEOUT_EXPIRED) || 1672 (status & RE_ISR_TX_ERR) || 1673 (status & RE_ISR_TX_DESC_UNAVAIL)) 1674 re_txeof(sc); 1675 1676 if (status & RE_ISR_SYSTEM_ERR) { 1677 re_reset(sc); 1678 re_init(sc); 1679 } 1680 1681 if (status & RE_ISR_LINKCHG) 1682 re_tick(sc); 1683 } 1684 1685 if (!ifq_is_empty(&ifp->if_snd)) 1686 (*ifp->if_start)(ifp); 1687 } 1688 1689 static int 1690 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1691 { 1692 struct ifnet *ifp = &sc->arpcom.ac_if; 1693 struct mbuf *m, *m_new = NULL; 1694 struct re_dmaload_arg arg; 1695 bus_dmamap_t map; 1696 int error; 1697 1698 *called_defrag = 0; 1699 if (sc->re_ldata.re_tx_free <= 4) 1700 return(EFBIG); 1701 1702 m = *m_head; 1703 1704 /* 1705 * Set up checksum offload. Note: checksum offload bits must 1706 * appear in all descriptors of a multi-descriptor transmit 1707 * attempt. (This is according to testing done with an 8169 1708 * chip. I'm not sure if this is a requirement or a bug.) 1709 */ 1710 1711 arg.re_flags = 0; 1712 1713 if (m->m_pkthdr.csum_flags & CSUM_IP) 1714 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1715 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1716 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1717 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1718 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1719 1720 arg.sc = sc; 1721 arg.re_idx = *idx; 1722 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1723 if (arg.re_maxsegs > 4) 1724 arg.re_maxsegs -= 4; 1725 arg.re_ring = sc->re_ldata.re_tx_list; 1726 1727 map = sc->re_ldata.re_tx_dmamap[*idx]; 1728 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1729 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1730 1731 if (error && error != EFBIG) { 1732 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1733 return(ENOBUFS); 1734 } 1735 1736 /* Too many segments to map, coalesce into a single mbuf */ 1737 1738 if (error || arg.re_maxsegs == 0) { 1739 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1740 if (m_new == NULL) 1741 return(1); 1742 else { 1743 m = m_new; 1744 *m_head = m; 1745 } 1746 1747 *called_defrag = 1; 1748 arg.sc = sc; 1749 arg.re_idx = *idx; 1750 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1751 arg.re_ring = sc->re_ldata.re_tx_list; 1752 1753 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1754 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1755 if (error) { 1756 m_freem(m); 1757 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1758 return(EFBIG); 1759 } 1760 } 1761 1762 /* 1763 * Insure that the map for this transmission 1764 * is placed at the array index of the last descriptor 1765 * in this chain. 1766 */ 1767 sc->re_ldata.re_tx_dmamap[*idx] = 1768 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1769 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1770 1771 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1772 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1773 1774 /* 1775 * Set up hardware VLAN tagging. Note: vlan tag info must 1776 * appear in the first descriptor of a multi-descriptor 1777 * transmission attempt. 1778 */ 1779 1780 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1781 m->m_pkthdr.rcvif != NULL && 1782 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1783 struct ifvlan *ifv; 1784 ifv = m->m_pkthdr.rcvif->if_softc; 1785 if (ifv != NULL) 1786 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1787 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1788 } 1789 1790 /* Transfer ownership of packet to the chip. */ 1791 1792 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1793 htole32(RE_TDESC_CMD_OWN); 1794 if (*idx != arg.re_idx) 1795 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1796 htole32(RE_TDESC_CMD_OWN); 1797 1798 RE_DESC_INC(arg.re_idx); 1799 *idx = arg.re_idx; 1800 1801 return(0); 1802 } 1803 1804 /* 1805 * Main transmit routine for C+ and gigE NICs. 1806 */ 1807 1808 static void 1809 re_start(struct ifnet *ifp) 1810 { 1811 struct re_softc *sc = ifp->if_softc; 1812 struct mbuf *m_head = NULL, *m_head2; 1813 int called_defrag, idx, need_trans; 1814 1815 crit_enter(); 1816 1817 idx = sc->re_ldata.re_tx_prodidx; 1818 1819 need_trans = 0; 1820 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1821 m_head = ifq_poll(&ifp->if_snd); 1822 if (m_head == NULL) 1823 break; 1824 1825 if (re_encap(sc, &m_head, &idx, &called_defrag)) { 1826 if (called_defrag) { 1827 m_head2 = ifq_dequeue(&ifp->if_snd); 1828 m_freem(m_head2); 1829 } 1830 ifp->if_flags |= IFF_OACTIVE; 1831 break; 1832 } 1833 1834 m_head2 = ifq_dequeue(&ifp->if_snd); 1835 if (called_defrag) 1836 m_freem(m_head2); 1837 need_trans = 1; 1838 1839 /* 1840 * If there's a BPF listener, bounce a copy of this frame 1841 * to him. 1842 */ 1843 BPF_MTAP(ifp, m_head); 1844 } 1845 1846 if (!need_trans) { 1847 crit_exit(); 1848 return; 1849 } 1850 1851 /* Flush the TX descriptors */ 1852 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1853 sc->re_ldata.re_tx_list_map, 1854 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1855 1856 sc->re_ldata.re_tx_prodidx = idx; 1857 1858 /* 1859 * RealTek put the TX poll request register in a different 1860 * location on the 8169 gigE chip. I don't know why. 1861 */ 1862 if (sc->re_type == RE_8169) 1863 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START); 1864 else 1865 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START); 1866 1867 /* 1868 * Use the countdown timer for interrupt moderation. 1869 * 'TX done' interrupts are disabled. Instead, we reset the 1870 * countdown timer, which will begin counting until it hits 1871 * the value in the TIMERINT register, and then trigger an 1872 * interrupt. Each time we write to the TIMERCNT register, 1873 * the timer count is reset to 0. 1874 */ 1875 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1876 1877 /* 1878 * Set a timeout in case the chip goes out to lunch. 1879 */ 1880 ifp->if_timer = 5; 1881 1882 crit_exit(); 1883 } 1884 1885 static void 1886 re_init(void *xsc) 1887 { 1888 struct re_softc *sc = xsc; 1889 struct ifnet *ifp = &sc->arpcom.ac_if; 1890 struct mii_data *mii; 1891 uint32_t rxcfg = 0; 1892 1893 crit_enter(); 1894 1895 mii = device_get_softc(sc->re_miibus); 1896 1897 /* 1898 * Cancel pending I/O and free all RX/TX buffers. 1899 */ 1900 re_stop(sc); 1901 1902 /* 1903 * Enable C+ RX and TX mode, as well as VLAN stripping and 1904 * RX checksum offload. We must configure the C+ register 1905 * before all others. 1906 */ 1907 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 1908 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 1909 (ifp->if_capenable & IFCAP_RXCSUM ? 1910 RE_CPLUSCMD_RXCSUM_ENB : 0)); 1911 1912 /* 1913 * Init our MAC address. Even though the chipset 1914 * documentation doesn't mention it, we need to enter "Config 1915 * register write enable" mode to modify the ID registers. 1916 */ 1917 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 1918 CSR_WRITE_STREAM_4(sc, RE_IDR0, 1919 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1920 CSR_WRITE_STREAM_4(sc, RE_IDR4, 1921 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1922 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 1923 1924 /* 1925 * For C+ mode, initialize the RX descriptors and mbufs. 1926 */ 1927 re_rx_list_init(sc); 1928 re_tx_list_init(sc); 1929 1930 /* 1931 * Enable transmit and receive. 1932 */ 1933 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1934 1935 /* 1936 * Set the initial TX and RX configuration. 1937 */ 1938 if (sc->re_testmode) { 1939 if (sc->re_type == RE_8169) 1940 CSR_WRITE_4(sc, RE_TXCFG, 1941 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 1942 else 1943 CSR_WRITE_4(sc, RE_TXCFG, 1944 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 1945 } else 1946 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 1947 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 1948 1949 /* Set the individual bit to receive frames for this host only. */ 1950 rxcfg = CSR_READ_4(sc, RE_RXCFG); 1951 rxcfg |= RE_RXCFG_RX_INDIV; 1952 1953 /* If we want promiscuous mode, set the allframes bit. */ 1954 if (ifp->if_flags & IFF_PROMISC) { 1955 rxcfg |= RE_RXCFG_RX_ALLPHYS; 1956 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1957 } else { 1958 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 1959 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1960 } 1961 1962 /* 1963 * Set capture broadcast bit to capture broadcast frames. 1964 */ 1965 if (ifp->if_flags & IFF_BROADCAST) { 1966 rxcfg |= RE_RXCFG_RX_BROAD; 1967 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1968 } else { 1969 rxcfg &= ~RE_RXCFG_RX_BROAD; 1970 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1971 } 1972 1973 /* 1974 * Program the multicast filter, if necessary. 1975 */ 1976 re_setmulti(sc); 1977 1978 #ifdef DEVICE_POLLING 1979 /* 1980 * Disable interrupts if we are polling. 1981 */ 1982 if (ifp->if_flags & IFF_POLLING) 1983 CSR_WRITE_2(sc, RE_IMR, 0); 1984 else /* otherwise ... */ 1985 #endif /* DEVICE_POLLING */ 1986 /* 1987 * Enable interrupts. 1988 */ 1989 if (sc->re_testmode) 1990 CSR_WRITE_2(sc, RE_IMR, 0); 1991 else 1992 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1993 1994 /* Set initial TX threshold */ 1995 sc->re_txthresh = RE_TX_THRESH_INIT; 1996 1997 /* Start RX/TX process. */ 1998 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 1999 #ifdef notdef 2000 /* Enable receiver and transmitter. */ 2001 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2002 #endif 2003 /* 2004 * Load the addresses of the RX and TX lists into the chip. 2005 */ 2006 2007 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2008 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2009 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2010 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2011 2012 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2013 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2014 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2015 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2016 2017 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2018 2019 /* 2020 * Initialize the timer interrupt register so that 2021 * a timer interrupt will be generated once the timer 2022 * reaches a certain number of ticks. The timer is 2023 * reloaded on each transmit. This gives us TX interrupt 2024 * moderation, which dramatically improves TX frame rate. 2025 */ 2026 2027 if (sc->re_type == RE_8169) 2028 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2029 else 2030 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2031 2032 /* 2033 * For 8169 gigE NICs, set the max allowed RX packet 2034 * size so we can receive jumbo frames. 2035 */ 2036 if (sc->re_type == RE_8169) 2037 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2038 2039 if (sc->re_testmode) { 2040 crit_exit(); 2041 return; 2042 } 2043 2044 mii_mediachg(mii); 2045 2046 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2047 2048 ifp->if_flags |= IFF_RUNNING; 2049 ifp->if_flags &= ~IFF_OACTIVE; 2050 2051 callout_reset(&sc->re_timer, hz, re_tick, sc); 2052 2053 crit_exit(); 2054 } 2055 2056 /* 2057 * Set media options. 2058 */ 2059 static int 2060 re_ifmedia_upd(struct ifnet *ifp) 2061 { 2062 struct re_softc *sc = ifp->if_softc; 2063 struct mii_data *mii; 2064 2065 mii = device_get_softc(sc->re_miibus); 2066 mii_mediachg(mii); 2067 2068 return(0); 2069 } 2070 2071 /* 2072 * Report current media status. 2073 */ 2074 static void 2075 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2076 { 2077 struct re_softc *sc = ifp->if_softc; 2078 struct mii_data *mii; 2079 2080 mii = device_get_softc(sc->re_miibus); 2081 2082 mii_pollstat(mii); 2083 ifmr->ifm_active = mii->mii_media_active; 2084 ifmr->ifm_status = mii->mii_media_status; 2085 } 2086 2087 static int 2088 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2089 { 2090 struct re_softc *sc = ifp->if_softc; 2091 struct ifreq *ifr = (struct ifreq *) data; 2092 struct mii_data *mii; 2093 int error = 0; 2094 2095 crit_enter(); 2096 2097 switch(command) { 2098 case SIOCSIFMTU: 2099 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2100 error = EINVAL; 2101 ifp->if_mtu = ifr->ifr_mtu; 2102 break; 2103 case SIOCSIFFLAGS: 2104 if (ifp->if_flags & IFF_UP) 2105 re_init(sc); 2106 else if (ifp->if_flags & IFF_RUNNING) 2107 re_stop(sc); 2108 error = 0; 2109 break; 2110 case SIOCADDMULTI: 2111 case SIOCDELMULTI: 2112 re_setmulti(sc); 2113 error = 0; 2114 break; 2115 case SIOCGIFMEDIA: 2116 case SIOCSIFMEDIA: 2117 mii = device_get_softc(sc->re_miibus); 2118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2119 break; 2120 case SIOCSIFCAP: 2121 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2122 ifp->if_capenable |= 2123 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2124 if (ifp->if_capenable & IFCAP_TXCSUM) 2125 ifp->if_hwassist = RE_CSUM_FEATURES; 2126 else 2127 ifp->if_hwassist = 0; 2128 if (ifp->if_flags & IFF_RUNNING) 2129 re_init(sc); 2130 break; 2131 default: 2132 error = ether_ioctl(ifp, command, data); 2133 break; 2134 } 2135 2136 crit_exit(); 2137 2138 return(error); 2139 } 2140 2141 static void 2142 re_watchdog(struct ifnet *ifp) 2143 { 2144 struct re_softc *sc = ifp->if_softc; 2145 2146 if_printf(ifp, "watchdog timeout\n"); 2147 2148 crit_enter(); 2149 2150 ifp->if_oerrors++; 2151 2152 re_txeof(sc); 2153 re_rxeof(sc); 2154 2155 re_init(sc); 2156 2157 if (!ifq_is_empty(&ifp->if_snd)) 2158 ifp->if_start(ifp); 2159 2160 crit_exit(); 2161 } 2162 2163 /* 2164 * Stop the adapter and free any mbufs allocated to the 2165 * RX and TX lists. 2166 */ 2167 static void 2168 re_stop(struct re_softc *sc) 2169 { 2170 struct ifnet *ifp = &sc->arpcom.ac_if; 2171 int i; 2172 2173 crit_enter(); 2174 2175 ifp->if_timer = 0; 2176 callout_stop(&sc->re_timer); 2177 2178 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2179 2180 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2181 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2182 2183 if (sc->re_head != NULL) { 2184 m_freem(sc->re_head); 2185 sc->re_head = sc->re_tail = NULL; 2186 } 2187 2188 /* Free the TX list buffers. */ 2189 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2190 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2191 bus_dmamap_unload(sc->re_ldata.re_mtag, 2192 sc->re_ldata.re_tx_dmamap[i]); 2193 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2194 sc->re_ldata.re_tx_mbuf[i] = NULL; 2195 } 2196 } 2197 2198 /* Free the RX list buffers. */ 2199 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2200 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2201 bus_dmamap_unload(sc->re_ldata.re_mtag, 2202 sc->re_ldata.re_rx_dmamap[i]); 2203 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2204 sc->re_ldata.re_rx_mbuf[i] = NULL; 2205 } 2206 } 2207 2208 crit_exit(); 2209 } 2210 2211 /* 2212 * Device suspend routine. Stop the interface and save some PCI 2213 * settings in case the BIOS doesn't restore them properly on 2214 * resume. 2215 */ 2216 static int 2217 re_suspend(device_t dev) 2218 { 2219 #ifndef BURN_BRIDGES 2220 int i; 2221 #endif 2222 struct re_softc *sc = device_get_softc(dev); 2223 2224 re_stop(sc); 2225 2226 #ifndef BURN_BRIDGES 2227 for (i = 0; i < 5; i++) 2228 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2229 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2230 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2231 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2232 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2233 #endif 2234 2235 sc->suspended = 1; 2236 2237 return (0); 2238 } 2239 2240 /* 2241 * Device resume routine. Restore some PCI settings in case the BIOS 2242 * doesn't, re-enable busmastering, and restart the interface if 2243 * appropriate. 2244 */ 2245 static int 2246 re_resume(device_t dev) 2247 { 2248 struct re_softc *sc = device_get_softc(dev); 2249 struct ifnet *ifp = &sc->arpcom.ac_if; 2250 #ifndef BURN_BRIDGES 2251 int i; 2252 #endif 2253 2254 #ifndef BURN_BRIDGES 2255 /* better way to do this? */ 2256 for (i = 0; i < 5; i++) 2257 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2258 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2259 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2260 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2261 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2262 2263 /* reenable busmastering */ 2264 pci_enable_busmaster(dev); 2265 pci_enable_io(dev, SYS_RES_IOPORT); 2266 #endif 2267 2268 /* reinitialize interface if necessary */ 2269 if (ifp->if_flags & IFF_UP) 2270 re_init(sc); 2271 2272 sc->suspended = 0; 2273 2274 return (0); 2275 } 2276 2277 /* 2278 * Stop all chip I/O so that the kernel's probe routines don't 2279 * get confused by errant DMAs when rebooting. 2280 */ 2281 static void 2282 re_shutdown(device_t dev) 2283 { 2284 struct re_softc *sc = device_get_softc(dev); 2285 2286 re_stop(sc); 2287 } 2288