1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_ifpoll.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_poll.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct re_type { 164 uint16_t re_vid; 165 uint16_t re_did; 166 const char *re_name; 167 } re_devs[] = { 168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 175 "RealTek 810x PCIe 10/100baseTX" }, 176 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 178 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 179 180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 181 "RealTek 8110/8169 Gigabit Ethernet" }, 182 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 187 "Corega CG-LAPCIGT Gigabit Ethernet" }, 188 189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" }, 191 192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 193 "US Robotics 997902 Gigabit Ethernet" }, 194 195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 196 "TTTech MC322 Gigabit Ethernet" }, 197 198 { 0, 0, NULL } 199 }; 200 201 static const struct re_hwrev re_hwrevs[] = { 202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 204 205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 206 RE_C_HWCSUM | RE_C_8169 }, 207 208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 209 RE_C_HWCSUM | RE_C_8169 }, 210 211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 212 RE_C_HWCSUM | RE_C_8169 }, 213 214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 216 217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 219 220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 222 223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 225 226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 228 229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 231 232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K, 245 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 246 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 247 248 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K, 249 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 250 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 251 252 { RE_HWREV_8168F, RE_MACVER_UNKN, RE_MTU_9K, 253 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 254 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 255 256 { RE_HWREV_8111F, RE_MACVER_UNKN, RE_MTU_9K, 257 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 258 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 259 260 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 261 RE_C_HWCSUM | RE_C_FASTE }, 262 263 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 264 RE_C_HWCSUM | RE_C_FASTE }, 265 266 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 267 RE_C_HWCSUM | RE_C_FASTE }, 268 269 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 270 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 271 RE_C_FASTE }, 272 273 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 274 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 275 RE_C_FASTE }, 276 277 { RE_HWREV_8105E, RE_MACVER_UNKN, ETHERMTU, 278 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 279 RE_C_STOP_RXTX | RE_C_FASTE }, 280 281 { RE_HWREV_NULL, 0, 0, 0 } 282 }; 283 284 static int re_probe(device_t); 285 static int re_attach(device_t); 286 static int re_detach(device_t); 287 static int re_suspend(device_t); 288 static int re_resume(device_t); 289 static void re_shutdown(device_t); 290 291 static int re_allocmem(device_t); 292 static void re_freemem(device_t); 293 static void re_freebufmem(struct re_softc *, int, int); 294 static int re_encap(struct re_softc *, struct mbuf **, int *); 295 static int re_newbuf_std(struct re_softc *, int, int); 296 static int re_newbuf_jumbo(struct re_softc *, int, int); 297 static void re_setup_rxdesc(struct re_softc *, int); 298 static int re_rx_list_init(struct re_softc *); 299 static int re_tx_list_init(struct re_softc *); 300 static int re_rxeof(struct re_softc *); 301 static int re_txeof(struct re_softc *); 302 static int re_tx_collect(struct re_softc *); 303 static void re_intr(void *); 304 static void re_tick(void *); 305 static void re_tick_serialized(void *); 306 307 static void re_start(struct ifnet *); 308 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 309 static void re_init(void *); 310 static void re_stop(struct re_softc *); 311 static void re_watchdog(struct ifnet *); 312 static int re_ifmedia_upd(struct ifnet *); 313 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 314 315 static void re_eeprom_putbyte(struct re_softc *, int); 316 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 317 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 318 static void re_get_eewidth(struct re_softc *); 319 320 static int re_gmii_readreg(device_t, int, int); 321 static int re_gmii_writereg(device_t, int, int, int); 322 323 static int re_miibus_readreg(device_t, int, int); 324 static int re_miibus_writereg(device_t, int, int, int); 325 static void re_miibus_statchg(device_t); 326 327 static void re_setmulti(struct re_softc *); 328 static void re_reset(struct re_softc *, int); 329 static void re_get_eaddr(struct re_softc *, uint8_t *); 330 331 static void re_setup_hw_im(struct re_softc *); 332 static void re_setup_sim_im(struct re_softc *); 333 static void re_disable_hw_im(struct re_softc *); 334 static void re_disable_sim_im(struct re_softc *); 335 static void re_config_imtype(struct re_softc *, int); 336 static void re_setup_intr(struct re_softc *, int, int); 337 338 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 339 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 340 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 341 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 342 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 343 344 static int re_jpool_alloc(struct re_softc *); 345 static void re_jpool_free(struct re_softc *); 346 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 347 static void re_jbuf_free(void *); 348 static void re_jbuf_ref(void *); 349 350 #ifdef RE_DIAG 351 static int re_diag(struct re_softc *); 352 #endif 353 354 #ifdef IFPOLL_ENABLE 355 static void re_npoll(struct ifnet *, struct ifpoll_info *); 356 static void re_npoll_compat(struct ifnet *, void *, int); 357 #endif 358 359 static device_method_t re_methods[] = { 360 /* Device interface */ 361 DEVMETHOD(device_probe, re_probe), 362 DEVMETHOD(device_attach, re_attach), 363 DEVMETHOD(device_detach, re_detach), 364 DEVMETHOD(device_suspend, re_suspend), 365 DEVMETHOD(device_resume, re_resume), 366 DEVMETHOD(device_shutdown, re_shutdown), 367 368 /* bus interface */ 369 DEVMETHOD(bus_print_child, bus_generic_print_child), 370 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 371 372 /* MII interface */ 373 DEVMETHOD(miibus_readreg, re_miibus_readreg), 374 DEVMETHOD(miibus_writereg, re_miibus_writereg), 375 DEVMETHOD(miibus_statchg, re_miibus_statchg), 376 377 { 0, 0 } 378 }; 379 380 static driver_t re_driver = { 381 "re", 382 re_methods, 383 sizeof(struct re_softc) 384 }; 385 386 static devclass_t re_devclass; 387 388 DECLARE_DUMMY_MODULE(if_re); 389 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 390 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 391 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 392 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 393 394 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 395 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 396 static int re_msi_enable = 0; 397 398 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 399 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 400 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 401 402 #define EE_SET(x) \ 403 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 404 405 #define EE_CLR(x) \ 406 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 407 408 static __inline void 409 re_free_rxchain(struct re_softc *sc) 410 { 411 if (sc->re_head != NULL) { 412 m_freem(sc->re_head); 413 sc->re_head = sc->re_tail = NULL; 414 } 415 } 416 417 /* 418 * Send a read command and address to the EEPROM, check for ACK. 419 */ 420 static void 421 re_eeprom_putbyte(struct re_softc *sc, int addr) 422 { 423 int d, i; 424 425 d = addr | (RE_9346_READ << sc->re_eewidth); 426 427 /* 428 * Feed in each bit and strobe the clock. 429 */ 430 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 431 if (d & i) 432 EE_SET(RE_EE_DATAIN); 433 else 434 EE_CLR(RE_EE_DATAIN); 435 DELAY(100); 436 EE_SET(RE_EE_CLK); 437 DELAY(150); 438 EE_CLR(RE_EE_CLK); 439 DELAY(100); 440 } 441 } 442 443 /* 444 * Read a word of data stored in the EEPROM at address 'addr.' 445 */ 446 static void 447 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 448 { 449 int i; 450 uint16_t word = 0; 451 452 /* 453 * Send address of word we want to read. 454 */ 455 re_eeprom_putbyte(sc, addr); 456 457 /* 458 * Start reading bits from EEPROM. 459 */ 460 for (i = 0x8000; i != 0; i >>= 1) { 461 EE_SET(RE_EE_CLK); 462 DELAY(100); 463 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 464 word |= i; 465 EE_CLR(RE_EE_CLK); 466 DELAY(100); 467 } 468 469 *dest = word; 470 } 471 472 /* 473 * Read a sequence of words from the EEPROM. 474 */ 475 static void 476 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 477 { 478 int i; 479 uint16_t word = 0, *ptr; 480 481 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 482 DELAY(100); 483 484 for (i = 0; i < cnt; i++) { 485 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 486 re_eeprom_getword(sc, off + i, &word); 487 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 488 ptr = (uint16_t *)(dest + (i * 2)); 489 *ptr = word; 490 } 491 492 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 493 } 494 495 static void 496 re_get_eewidth(struct re_softc *sc) 497 { 498 uint16_t re_did = 0; 499 500 sc->re_eewidth = 6; 501 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 502 if (re_did != 0x8129) 503 sc->re_eewidth = 8; 504 } 505 506 static int 507 re_gmii_readreg(device_t dev, int phy, int reg) 508 { 509 struct re_softc *sc = device_get_softc(dev); 510 u_int32_t rval; 511 int i; 512 513 if (phy != 1) 514 return(0); 515 516 /* Let the rgephy driver read the GMEDIASTAT register */ 517 518 if (reg == RE_GMEDIASTAT) 519 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 520 521 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 522 DELAY(1000); 523 524 for (i = 0; i < RE_TIMEOUT; i++) { 525 rval = CSR_READ_4(sc, RE_PHYAR); 526 if (rval & RE_PHYAR_BUSY) 527 break; 528 DELAY(100); 529 } 530 531 if (i == RE_TIMEOUT) { 532 device_printf(dev, "PHY read failed\n"); 533 return(0); 534 } 535 536 return(rval & RE_PHYAR_PHYDATA); 537 } 538 539 static int 540 re_gmii_writereg(device_t dev, int phy, int reg, int data) 541 { 542 struct re_softc *sc = device_get_softc(dev); 543 uint32_t rval; 544 int i; 545 546 CSR_WRITE_4(sc, RE_PHYAR, 547 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 548 DELAY(1000); 549 550 for (i = 0; i < RE_TIMEOUT; i++) { 551 rval = CSR_READ_4(sc, RE_PHYAR); 552 if ((rval & RE_PHYAR_BUSY) == 0) 553 break; 554 DELAY(100); 555 } 556 557 if (i == RE_TIMEOUT) 558 device_printf(dev, "PHY write failed\n"); 559 560 return(0); 561 } 562 563 static int 564 re_miibus_readreg(device_t dev, int phy, int reg) 565 { 566 struct re_softc *sc = device_get_softc(dev); 567 uint16_t rval = 0; 568 uint16_t re8139_reg = 0; 569 570 if (!RE_IS_8139CP(sc)) { 571 rval = re_gmii_readreg(dev, phy, reg); 572 return(rval); 573 } 574 575 /* Pretend the internal PHY is only at address 0 */ 576 if (phy) 577 return(0); 578 579 switch(reg) { 580 case MII_BMCR: 581 re8139_reg = RE_BMCR; 582 break; 583 case MII_BMSR: 584 re8139_reg = RE_BMSR; 585 break; 586 case MII_ANAR: 587 re8139_reg = RE_ANAR; 588 break; 589 case MII_ANER: 590 re8139_reg = RE_ANER; 591 break; 592 case MII_ANLPAR: 593 re8139_reg = RE_LPAR; 594 break; 595 case MII_PHYIDR1: 596 case MII_PHYIDR2: 597 return(0); 598 /* 599 * Allow the rlphy driver to read the media status 600 * register. If we have a link partner which does not 601 * support NWAY, this is the register which will tell 602 * us the results of parallel detection. 603 */ 604 case RE_MEDIASTAT: 605 return(CSR_READ_1(sc, RE_MEDIASTAT)); 606 default: 607 device_printf(dev, "bad phy register\n"); 608 return(0); 609 } 610 rval = CSR_READ_2(sc, re8139_reg); 611 if (re8139_reg == RE_BMCR) { 612 /* 8139C+ has different bit layout. */ 613 rval &= ~(BMCR_LOOP | BMCR_ISO); 614 } 615 return(rval); 616 } 617 618 static int 619 re_miibus_writereg(device_t dev, int phy, int reg, int data) 620 { 621 struct re_softc *sc= device_get_softc(dev); 622 u_int16_t re8139_reg = 0; 623 624 if (!RE_IS_8139CP(sc)) 625 return(re_gmii_writereg(dev, phy, reg, data)); 626 627 /* Pretend the internal PHY is only at address 0 */ 628 if (phy) 629 return(0); 630 631 switch(reg) { 632 case MII_BMCR: 633 re8139_reg = RE_BMCR; 634 /* 8139C+ has different bit layout. */ 635 data &= ~(BMCR_LOOP | BMCR_ISO); 636 break; 637 case MII_BMSR: 638 re8139_reg = RE_BMSR; 639 break; 640 case MII_ANAR: 641 re8139_reg = RE_ANAR; 642 break; 643 case MII_ANER: 644 re8139_reg = RE_ANER; 645 break; 646 case MII_ANLPAR: 647 re8139_reg = RE_LPAR; 648 break; 649 case MII_PHYIDR1: 650 case MII_PHYIDR2: 651 return(0); 652 default: 653 device_printf(dev, "bad phy register\n"); 654 return(0); 655 } 656 CSR_WRITE_2(sc, re8139_reg, data); 657 return(0); 658 } 659 660 static void 661 re_miibus_statchg(device_t dev) 662 { 663 } 664 665 /* 666 * Program the 64-bit multicast hash filter. 667 */ 668 static void 669 re_setmulti(struct re_softc *sc) 670 { 671 struct ifnet *ifp = &sc->arpcom.ac_if; 672 int h = 0; 673 uint32_t hashes[2] = { 0, 0 }; 674 struct ifmultiaddr *ifma; 675 uint32_t rxfilt; 676 int mcnt = 0; 677 678 rxfilt = CSR_READ_4(sc, RE_RXCFG); 679 680 /* Set the individual bit to receive frames for this host only. */ 681 rxfilt |= RE_RXCFG_RX_INDIV; 682 /* Set capture broadcast bit to capture broadcast frames. */ 683 rxfilt |= RE_RXCFG_RX_BROAD; 684 685 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 686 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 687 rxfilt |= RE_RXCFG_RX_MULTI; 688 689 /* If we want promiscuous mode, set the allframes bit. */ 690 if (ifp->if_flags & IFF_PROMISC) 691 rxfilt |= RE_RXCFG_RX_ALLPHYS; 692 693 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 694 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 695 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 696 return; 697 } 698 699 /* first, zot all the existing hash bits */ 700 CSR_WRITE_4(sc, RE_MAR0, 0); 701 CSR_WRITE_4(sc, RE_MAR4, 0); 702 703 /* now program new ones */ 704 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 705 if (ifma->ifma_addr->sa_family != AF_LINK) 706 continue; 707 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 708 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 709 if (h < 32) 710 hashes[0] |= (1 << h); 711 else 712 hashes[1] |= (1 << (h - 32)); 713 mcnt++; 714 } 715 716 if (mcnt) 717 rxfilt |= RE_RXCFG_RX_MULTI; 718 else 719 rxfilt &= ~RE_RXCFG_RX_MULTI; 720 721 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 722 723 /* 724 * For some unfathomable reason, RealTek decided to reverse 725 * the order of the multicast hash registers in the PCI Express 726 * parts. This means we have to write the hash pattern in reverse 727 * order for those devices. 728 */ 729 if (sc->re_caps & RE_C_PCIE) { 730 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 731 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 732 } else { 733 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 734 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 735 } 736 } 737 738 static void 739 re_reset(struct re_softc *sc, int running) 740 { 741 int i; 742 743 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 744 CSR_WRITE_1(sc, RE_COMMAND, 745 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 746 DELAY(100); 747 } 748 749 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 750 751 for (i = 0; i < RE_TIMEOUT; i++) { 752 DELAY(10); 753 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 754 break; 755 } 756 if (i == RE_TIMEOUT) 757 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 758 } 759 760 #ifdef RE_DIAG 761 /* 762 * The following routine is designed to test for a defect on some 763 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 764 * lines connected to the bus, however for a 32-bit only card, they 765 * should be pulled high. The result of this defect is that the 766 * NIC will not work right if you plug it into a 64-bit slot: DMA 767 * operations will be done with 64-bit transfers, which will fail 768 * because the 64-bit data lines aren't connected. 769 * 770 * There's no way to work around this (short of talking a soldering 771 * iron to the board), however we can detect it. The method we use 772 * here is to put the NIC into digital loopback mode, set the receiver 773 * to promiscuous mode, and then try to send a frame. We then compare 774 * the frame data we sent to what was received. If the data matches, 775 * then the NIC is working correctly, otherwise we know the user has 776 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 777 * slot. In the latter case, there's no way the NIC can work correctly, 778 * so we print out a message on the console and abort the device attach. 779 */ 780 781 static int 782 re_diag(struct re_softc *sc) 783 { 784 struct ifnet *ifp = &sc->arpcom.ac_if; 785 struct mbuf *m0; 786 struct ether_header *eh; 787 struct re_desc *cur_rx; 788 uint16_t status; 789 int total_len, i, error = 0, phyaddr; 790 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 791 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 792 793 /* Allocate a single mbuf */ 794 795 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 796 if (m0 == NULL) 797 return(ENOBUFS); 798 799 /* 800 * Initialize the NIC in test mode. This sets the chip up 801 * so that it can send and receive frames, but performs the 802 * following special functions: 803 * - Puts receiver in promiscuous mode 804 * - Enables digital loopback mode 805 * - Leaves interrupts turned off 806 */ 807 808 ifp->if_flags |= IFF_PROMISC; 809 sc->re_flags |= RE_F_TESTMODE; 810 re_init(sc); 811 sc->re_flags |= RE_F_LINKED; 812 if (!RE_IS_8139CP(sc)) 813 phyaddr = 1; 814 else 815 phyaddr = 0; 816 817 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 818 for (i = 0; i < RE_TIMEOUT; i++) { 819 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 820 if (!(status & BMCR_RESET)) 821 break; 822 } 823 824 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 825 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 826 827 DELAY(100000); 828 829 /* Put some data in the mbuf */ 830 831 eh = mtod(m0, struct ether_header *); 832 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 833 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 834 eh->ether_type = htons(ETHERTYPE_IP); 835 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 836 837 /* 838 * Queue the packet, start transmission. 839 * Note: ifq_handoff() ultimately calls re_start() for us. 840 */ 841 842 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 843 error = ifq_handoff(ifp, m0, NULL); 844 if (error) { 845 m0 = NULL; 846 goto done; 847 } 848 m0 = NULL; 849 850 /* Wait for it to propagate through the chip */ 851 852 DELAY(100000); 853 for (i = 0; i < RE_TIMEOUT; i++) { 854 status = CSR_READ_2(sc, RE_ISR); 855 CSR_WRITE_2(sc, RE_ISR, status); 856 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 857 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 858 break; 859 DELAY(10); 860 } 861 862 if (i == RE_TIMEOUT) { 863 if_printf(ifp, "diagnostic failed to receive packet " 864 "in loopback mode\n"); 865 error = EIO; 866 goto done; 867 } 868 869 /* 870 * The packet should have been dumped into the first 871 * entry in the RX DMA ring. Grab it from there. 872 */ 873 874 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 875 BUS_DMASYNC_POSTREAD); 876 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 877 sc->re_ldata.re_rx_dmamap[0]); 878 879 m0 = sc->re_ldata.re_rx_mbuf[0]; 880 sc->re_ldata.re_rx_mbuf[0] = NULL; 881 eh = mtod(m0, struct ether_header *); 882 883 cur_rx = &sc->re_ldata.re_rx_list[0]; 884 total_len = RE_RXBYTES(cur_rx); 885 886 if (total_len != ETHER_MIN_LEN) { 887 if_printf(ifp, "diagnostic failed, received short packet\n"); 888 error = EIO; 889 goto done; 890 } 891 892 /* Test that the received packet data matches what we sent. */ 893 894 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 895 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 896 be16toh(eh->ether_type) != ETHERTYPE_IP) { 897 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 898 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 899 dst, ":", src, ":", ETHERTYPE_IP); 900 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 901 eh->ether_dhost, ":", eh->ether_shost, ":", 902 ntohs(eh->ether_type)); 903 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 904 "into a 64-bit PCI slot.\n"); 905 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 906 "for proper operation.\n"); 907 if_printf(ifp, "Read the re(4) man page for more details.\n"); 908 error = EIO; 909 } 910 911 done: 912 /* Turn interface off, release resources */ 913 914 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 915 ifp->if_flags &= ~IFF_PROMISC; 916 re_stop(sc); 917 if (m0 != NULL) 918 m_freem(m0); 919 920 return (error); 921 } 922 #endif /* RE_DIAG */ 923 924 /* 925 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 926 * IDs against our list and return a device name if we find a match. 927 */ 928 static int 929 re_probe(device_t dev) 930 { 931 const struct re_type *t; 932 const struct re_hwrev *hw_rev; 933 struct re_softc *sc; 934 int rid; 935 uint32_t hwrev, macmode, txcfg; 936 uint16_t vendor, product; 937 938 vendor = pci_get_vendor(dev); 939 product = pci_get_device(dev); 940 941 /* 942 * Only attach to rev.3 of the Linksys EG1032 adapter. 943 * Rev.2 is supported by sk(4). 944 */ 945 if (vendor == PCI_VENDOR_LINKSYS && 946 product == PCI_PRODUCT_LINKSYS_EG1032 && 947 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 948 return ENXIO; 949 950 if (vendor == PCI_VENDOR_REALTEK && 951 product == PCI_PRODUCT_REALTEK_RT8139 && 952 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 953 /* Poor 8139 */ 954 return ENXIO; 955 } 956 957 for (t = re_devs; t->re_name != NULL; t++) { 958 if (product == t->re_did && vendor == t->re_vid) 959 break; 960 } 961 962 /* 963 * Check if we found a RealTek device. 964 */ 965 if (t->re_name == NULL) 966 return ENXIO; 967 968 /* 969 * Temporarily map the I/O space so we can read the chip ID register. 970 */ 971 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 972 rid = RE_PCI_LOIO; 973 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 974 RF_ACTIVE); 975 if (sc->re_res == NULL) { 976 device_printf(dev, "couldn't map ports/memory\n"); 977 kfree(sc, M_TEMP); 978 return ENXIO; 979 } 980 981 sc->re_btag = rman_get_bustag(sc->re_res); 982 sc->re_bhandle = rman_get_bushandle(sc->re_res); 983 984 txcfg = CSR_READ_4(sc, RE_TXCFG); 985 hwrev = txcfg & RE_TXCFG_HWREV; 986 macmode = txcfg & RE_TXCFG_MACMODE; 987 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 988 kfree(sc, M_TEMP); 989 990 /* 991 * and continue matching for the specific chip... 992 */ 993 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 994 if (hw_rev->re_hwrev == hwrev) { 995 sc = device_get_softc(dev); 996 997 sc->re_hwrev = hw_rev->re_hwrev; 998 sc->re_macver = hw_rev->re_macver; 999 sc->re_caps = hw_rev->re_caps; 1000 sc->re_maxmtu = hw_rev->re_maxmtu; 1001 1002 /* 1003 * Apply chip property fixup 1004 */ 1005 switch (sc->re_hwrev) { 1006 case RE_HWREV_8101E1: 1007 case RE_HWREV_8101E2: 1008 if (macmode == 0) 1009 sc->re_macver = RE_MACVER_11; 1010 else if (macmode == 0x200000) 1011 sc->re_macver = RE_MACVER_12; 1012 break; 1013 case RE_HWREV_8102E: 1014 case RE_HWREV_8102EL: 1015 if (macmode == 0) 1016 sc->re_macver = RE_MACVER_13; 1017 else if (macmode == 0x100000) 1018 sc->re_macver = RE_MACVER_14; 1019 break; 1020 case RE_HWREV_8168B2: 1021 case RE_HWREV_8168B3: 1022 if (macmode == 0) 1023 sc->re_macver = RE_MACVER_22; 1024 break; 1025 case RE_HWREV_8168C: 1026 if (macmode == 0) 1027 sc->re_macver = RE_MACVER_24; 1028 else if (macmode == 0x200000) 1029 sc->re_macver = RE_MACVER_25; 1030 else if (macmode == 0x300000) 1031 sc->re_macver = RE_MACVER_27; 1032 break; 1033 case RE_HWREV_8168CP: 1034 if (macmode == 0) 1035 sc->re_macver = RE_MACVER_26; 1036 else if (macmode == 0x100000) 1037 sc->re_macver = RE_MACVER_28; 1038 break; 1039 case RE_HWREV_8168DP: 1040 if (macmode == 0) 1041 sc->re_macver = RE_MACVER_2B; 1042 else if (macmode == 0x200000) 1043 sc->re_macver = RE_MACVER_2C; 1044 break; 1045 case RE_HWREV_8168E: 1046 if (macmode == 0x100000) 1047 sc->re_macver = RE_MACVER_2E; 1048 else if (macmode == 0x200000) 1049 sc->re_macver = RE_MACVER_2F; 1050 break; 1051 case RE_HWREV_8168F: 1052 case RE_HWREV_8111F: 1053 if (macmode == 0x000000) 1054 sc->re_macver = RE_MACVER_30; 1055 else if (macmode == 0x100000) 1056 sc->re_macver = RE_MACVER_31; 1057 break; 1058 } 1059 if (pci_is_pcie(dev)) 1060 sc->re_caps |= RE_C_PCIE; 1061 1062 device_set_desc(dev, t->re_name); 1063 return 0; 1064 } 1065 } 1066 1067 if (bootverbose) { 1068 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1069 hwrev, macmode); 1070 } 1071 return ENXIO; 1072 } 1073 1074 static int 1075 re_allocmem(device_t dev) 1076 { 1077 struct re_softc *sc = device_get_softc(dev); 1078 bus_dmamem_t dmem; 1079 int error, i; 1080 1081 /* 1082 * Allocate list data 1083 */ 1084 sc->re_ldata.re_tx_mbuf = 1085 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1086 M_DEVBUF, M_ZERO | M_WAITOK); 1087 1088 sc->re_ldata.re_rx_mbuf = 1089 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1090 M_DEVBUF, M_ZERO | M_WAITOK); 1091 1092 sc->re_ldata.re_rx_paddr = 1093 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1094 M_DEVBUF, M_ZERO | M_WAITOK); 1095 1096 sc->re_ldata.re_tx_dmamap = 1097 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1098 M_DEVBUF, M_ZERO | M_WAITOK); 1099 1100 sc->re_ldata.re_rx_dmamap = 1101 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1102 M_DEVBUF, M_ZERO | M_WAITOK); 1103 1104 /* 1105 * Allocate the parent bus DMA tag appropriate for PCI. 1106 */ 1107 error = bus_dma_tag_create(NULL, /* parent */ 1108 1, 0, /* alignment, boundary */ 1109 BUS_SPACE_MAXADDR, /* lowaddr */ 1110 BUS_SPACE_MAXADDR, /* highaddr */ 1111 NULL, NULL, /* filter, filterarg */ 1112 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1113 0, /* nsegments */ 1114 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1115 0, /* flags */ 1116 &sc->re_parent_tag); 1117 if (error) { 1118 device_printf(dev, "could not allocate parent dma tag\n"); 1119 return error; 1120 } 1121 1122 /* Allocate TX descriptor list. */ 1123 error = bus_dmamem_coherent(sc->re_parent_tag, 1124 RE_RING_ALIGN, 0, 1125 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1126 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1127 &dmem); 1128 if (error) { 1129 device_printf(dev, "could not allocate TX ring\n"); 1130 return error; 1131 } 1132 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1133 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1134 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1135 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1136 1137 /* Allocate RX descriptor list. */ 1138 error = bus_dmamem_coherent(sc->re_parent_tag, 1139 RE_RING_ALIGN, 0, 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1141 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1142 &dmem); 1143 if (error) { 1144 device_printf(dev, "could not allocate RX ring\n"); 1145 return error; 1146 } 1147 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1148 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1149 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1150 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1151 1152 /* Allocate maps for TX mbufs. */ 1153 error = bus_dma_tag_create(sc->re_parent_tag, 1154 1, 0, 1155 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1156 NULL, NULL, 1157 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1158 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1159 &sc->re_ldata.re_tx_mtag); 1160 if (error) { 1161 device_printf(dev, "could not allocate TX buf dma tag\n"); 1162 return(error); 1163 } 1164 1165 /* Create DMA maps for TX buffers */ 1166 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1167 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1168 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1169 &sc->re_ldata.re_tx_dmamap[i]); 1170 if (error) { 1171 device_printf(dev, "can't create DMA map for TX buf\n"); 1172 re_freebufmem(sc, i, 0); 1173 return(error); 1174 } 1175 } 1176 1177 /* Allocate maps for RX mbufs. */ 1178 error = bus_dma_tag_create(sc->re_parent_tag, 1179 RE_RXBUF_ALIGN, 0, 1180 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1181 NULL, NULL, 1182 MCLBYTES, 1, MCLBYTES, 1183 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1184 &sc->re_ldata.re_rx_mtag); 1185 if (error) { 1186 device_printf(dev, "could not allocate RX buf dma tag\n"); 1187 return(error); 1188 } 1189 1190 /* Create spare DMA map for RX */ 1191 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1192 &sc->re_ldata.re_rx_spare); 1193 if (error) { 1194 device_printf(dev, "can't create spare DMA map for RX\n"); 1195 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1196 sc->re_ldata.re_rx_mtag = NULL; 1197 return error; 1198 } 1199 1200 /* Create DMA maps for RX buffers */ 1201 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1202 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1203 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1204 if (error) { 1205 device_printf(dev, "can't create DMA map for RX buf\n"); 1206 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1207 return(error); 1208 } 1209 } 1210 1211 /* Create jumbo buffer pool for RX if required */ 1212 if (sc->re_caps & RE_C_CONTIGRX) { 1213 error = re_jpool_alloc(sc); 1214 if (error) { 1215 re_jpool_free(sc); 1216 /* Disable jumbo frame support */ 1217 sc->re_maxmtu = ETHERMTU; 1218 } 1219 } 1220 return(0); 1221 } 1222 1223 static void 1224 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1225 { 1226 int i; 1227 1228 /* Destroy all the RX and TX buffer maps */ 1229 if (sc->re_ldata.re_tx_mtag) { 1230 for (i = 0; i < tx_cnt; i++) { 1231 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1232 sc->re_ldata.re_tx_dmamap[i]); 1233 } 1234 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1235 sc->re_ldata.re_tx_mtag = NULL; 1236 } 1237 1238 if (sc->re_ldata.re_rx_mtag) { 1239 for (i = 0; i < rx_cnt; i++) { 1240 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1241 sc->re_ldata.re_rx_dmamap[i]); 1242 } 1243 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1244 sc->re_ldata.re_rx_spare); 1245 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1246 sc->re_ldata.re_rx_mtag = NULL; 1247 } 1248 } 1249 1250 static void 1251 re_freemem(device_t dev) 1252 { 1253 struct re_softc *sc = device_get_softc(dev); 1254 1255 /* Unload and free the RX DMA ring memory and map */ 1256 if (sc->re_ldata.re_rx_list_tag) { 1257 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1258 sc->re_ldata.re_rx_list_map); 1259 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1260 sc->re_ldata.re_rx_list, 1261 sc->re_ldata.re_rx_list_map); 1262 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1263 } 1264 1265 /* Unload and free the TX DMA ring memory and map */ 1266 if (sc->re_ldata.re_tx_list_tag) { 1267 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1268 sc->re_ldata.re_tx_list_map); 1269 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1270 sc->re_ldata.re_tx_list, 1271 sc->re_ldata.re_tx_list_map); 1272 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1273 } 1274 1275 /* Free RX/TX buf DMA stuffs */ 1276 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1277 1278 /* Unload and free the stats buffer and map */ 1279 if (sc->re_ldata.re_stag) { 1280 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1281 bus_dmamem_free(sc->re_ldata.re_stag, 1282 sc->re_ldata.re_stats, 1283 sc->re_ldata.re_smap); 1284 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1285 } 1286 1287 if (sc->re_caps & RE_C_CONTIGRX) 1288 re_jpool_free(sc); 1289 1290 if (sc->re_parent_tag) 1291 bus_dma_tag_destroy(sc->re_parent_tag); 1292 1293 if (sc->re_ldata.re_tx_mbuf != NULL) 1294 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1295 if (sc->re_ldata.re_rx_mbuf != NULL) 1296 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1297 if (sc->re_ldata.re_rx_paddr != NULL) 1298 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1299 if (sc->re_ldata.re_tx_dmamap != NULL) 1300 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1301 if (sc->re_ldata.re_rx_dmamap != NULL) 1302 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1303 } 1304 1305 /* 1306 * Attach the interface. Allocate softc structures, do ifmedia 1307 * setup and ethernet/BPF attach. 1308 */ 1309 static int 1310 re_attach(device_t dev) 1311 { 1312 struct re_softc *sc = device_get_softc(dev); 1313 struct ifnet *ifp; 1314 uint8_t eaddr[ETHER_ADDR_LEN]; 1315 int error = 0, rid, qlen; 1316 u_int irq_flags; 1317 1318 callout_init(&sc->re_timer); 1319 sc->re_dev = dev; 1320 1321 if (RE_IS_8139CP(sc)) { 1322 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1323 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1324 } else { 1325 sc->re_rx_desc_cnt = re_rx_desc_count; 1326 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1327 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1328 1329 sc->re_tx_desc_cnt = re_tx_desc_count; 1330 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1331 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1332 } 1333 1334 qlen = RE_IFQ_MAXLEN; 1335 if (sc->re_tx_desc_cnt > qlen) 1336 qlen = sc->re_tx_desc_cnt; 1337 1338 sc->re_rxbuf_size = MCLBYTES; 1339 sc->re_newbuf = re_newbuf_std; 1340 1341 sc->re_tx_time = 5; /* 125us */ 1342 sc->re_rx_time = 2; /* 50us */ 1343 if (sc->re_caps & RE_C_PCIE) 1344 sc->re_sim_time = 75; /* 75us */ 1345 else 1346 sc->re_sim_time = 125; /* 125us */ 1347 if (!RE_IS_8139CP(sc)) { 1348 /* simulated interrupt moderation */ 1349 sc->re_imtype = RE_IMTYPE_SIM; 1350 } else { 1351 sc->re_imtype = RE_IMTYPE_NONE; 1352 } 1353 re_config_imtype(sc, sc->re_imtype); 1354 1355 sysctl_ctx_init(&sc->re_sysctl_ctx); 1356 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1357 SYSCTL_STATIC_CHILDREN(_hw), 1358 OID_AUTO, 1359 device_get_nameunit(dev), 1360 CTLFLAG_RD, 0, ""); 1361 if (sc->re_sysctl_tree == NULL) { 1362 device_printf(dev, "can't add sysctl node\n"); 1363 error = ENXIO; 1364 goto fail; 1365 } 1366 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1367 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1368 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1369 0, "RX desc count"); 1370 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1371 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1372 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1373 0, "TX desc count"); 1374 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1375 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1376 OID_AUTO, "sim_time", 1377 CTLTYPE_INT | CTLFLAG_RW, 1378 sc, 0, re_sysctl_simtime, "I", 1379 "Simulated interrupt moderation time (usec)."); 1380 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1381 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1382 OID_AUTO, "imtype", 1383 CTLTYPE_INT | CTLFLAG_RW, 1384 sc, 0, re_sysctl_imtype, "I", 1385 "Interrupt moderation type -- " 1386 "0:disable, 1:simulated, " 1387 "2:hardware(if supported)"); 1388 if (sc->re_caps & RE_C_HWIM) { 1389 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1390 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1391 OID_AUTO, "hw_rxtime", 1392 CTLTYPE_INT | CTLFLAG_RW, 1393 sc, 0, re_sysctl_rxtime, "I", 1394 "Hardware interrupt moderation time " 1395 "(unit: 25usec)."); 1396 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1397 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1398 OID_AUTO, "hw_txtime", 1399 CTLTYPE_INT | CTLFLAG_RW, 1400 sc, 0, re_sysctl_txtime, "I", 1401 "Hardware interrupt moderation time " 1402 "(unit: 25usec)."); 1403 } 1404 1405 #ifndef BURN_BRIDGES 1406 /* 1407 * Handle power management nonsense. 1408 */ 1409 1410 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1411 uint32_t membase, irq; 1412 1413 /* Save important PCI config data. */ 1414 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1415 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1416 1417 /* Reset the power state. */ 1418 device_printf(dev, "chip is in D%d power mode " 1419 "-- setting to D0\n", pci_get_powerstate(dev)); 1420 1421 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1422 1423 /* Restore PCI config data. */ 1424 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1425 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1426 } 1427 #endif 1428 /* 1429 * Map control/status registers. 1430 */ 1431 pci_enable_busmaster(dev); 1432 1433 rid = RE_PCI_LOIO; 1434 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1435 RF_ACTIVE); 1436 1437 if (sc->re_res == NULL) { 1438 device_printf(dev, "couldn't map ports\n"); 1439 error = ENXIO; 1440 goto fail; 1441 } 1442 1443 sc->re_btag = rman_get_bustag(sc->re_res); 1444 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1445 1446 /* Allocate interrupt */ 1447 sc->re_irq_type = pci_alloc_1intr(dev, re_msi_enable, 1448 &sc->re_irq_rid, &irq_flags); 1449 1450 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1451 irq_flags); 1452 if (sc->re_irq == NULL) { 1453 device_printf(dev, "couldn't map interrupt\n"); 1454 error = ENXIO; 1455 goto fail; 1456 } 1457 1458 /* Reset the adapter. */ 1459 re_reset(sc, 0); 1460 1461 if (RE_IS_8139CP(sc)) { 1462 sc->re_bus_speed = 33; /* XXX */ 1463 } else if (sc->re_caps & RE_C_PCIE) { 1464 sc->re_bus_speed = 125; 1465 } else { 1466 uint8_t cfg2; 1467 1468 cfg2 = CSR_READ_1(sc, RE_CFG2); 1469 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1470 case RE_CFG2_PCICLK_33MHZ: 1471 sc->re_bus_speed = 33; 1472 break; 1473 case RE_CFG2_PCICLK_66MHZ: 1474 sc->re_bus_speed = 66; 1475 break; 1476 default: 1477 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1478 sc->re_bus_speed = 33; 1479 break; 1480 } 1481 if (cfg2 & RE_CFG2_PCI64) 1482 sc->re_caps |= RE_C_PCI64; 1483 } 1484 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1485 "PCI%s %dMHz\n", 1486 sc->re_hwrev, sc->re_macver, 1487 (sc->re_caps & RE_C_PCIE) ? 1488 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1489 sc->re_bus_speed); 1490 1491 /* 1492 * NOTE: 1493 * DO NOT try to adjust config1 and config5 which was spotted in 1494 * Realtek's Linux drivers. It will _permanently_ damage certain 1495 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1496 */ 1497 1498 re_get_eaddr(sc, eaddr); 1499 1500 if (!RE_IS_8139CP(sc)) { 1501 /* Set RX length mask */ 1502 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1503 sc->re_txstart = RE_GTXSTART; 1504 } else { 1505 /* Set RX length mask */ 1506 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1507 sc->re_txstart = RE_TXSTART; 1508 } 1509 1510 /* Allocate DMA stuffs */ 1511 error = re_allocmem(dev); 1512 if (error) 1513 goto fail; 1514 1515 /* 1516 * Apply some magic PCI settings from Realtek ... 1517 */ 1518 if (RE_IS_8169(sc)) { 1519 CSR_WRITE_1(sc, 0x82, 1); 1520 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1521 } 1522 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1523 1524 if (sc->re_caps & RE_C_MAC2) { 1525 /* 1526 * Following part is extracted from Realtek BSD driver v176. 1527 * However, this does _not_ make much/any sense: 1528 * 8168C's PCI Express device control is located at 0x78, 1529 * so the reading from 0x79 (higher part of 0x78) and setting 1530 * the 4~6bits intend to enlarge the "max read request size" 1531 * (we will do it). The content of the rest part of this 1532 * register is not meaningful to other PCI registers, so 1533 * writing the value to 0x54 could be completely wrong. 1534 * 0x80 is the lower part of PCI Express device status, non- 1535 * reserved bits are RW1C, writing 0 to them will not have 1536 * any effect at all. 1537 */ 1538 #ifdef foo 1539 uint8_t val; 1540 1541 val = pci_read_config(dev, 0x79, 1); 1542 val = (val & ~0x70) | 0x50; 1543 pci_write_config(dev, 0x54, val, 1); 1544 pci_write_config(dev, 0x80, 0, 1); 1545 #endif 1546 } 1547 1548 /* 1549 * Apply some PHY fixup from Realtek ... 1550 */ 1551 if (sc->re_hwrev == RE_HWREV_8110S) { 1552 CSR_WRITE_1(sc, 0x82, 1); 1553 re_miibus_writereg(dev, 1, 0xb, 0); 1554 } 1555 if (sc->re_caps & RE_C_PHYPMGT) { 1556 /* Power up PHY */ 1557 re_miibus_writereg(dev, 1, 0x1f, 0); 1558 re_miibus_writereg(dev, 1, 0xe, 0); 1559 } 1560 1561 /* Do MII setup */ 1562 if (mii_phy_probe(dev, &sc->re_miibus, 1563 re_ifmedia_upd, re_ifmedia_sts)) { 1564 device_printf(dev, "MII without any phy!\n"); 1565 error = ENXIO; 1566 goto fail; 1567 } 1568 1569 ifp = &sc->arpcom.ac_if; 1570 ifp->if_softc = sc; 1571 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1572 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1573 ifp->if_ioctl = re_ioctl; 1574 ifp->if_start = re_start; 1575 #ifdef IFPOLL_ENABLE 1576 ifp->if_npoll = re_npoll; 1577 #endif 1578 ifp->if_watchdog = re_watchdog; 1579 ifp->if_init = re_init; 1580 if (!RE_IS_8139CP(sc)) /* XXX */ 1581 ifp->if_baudrate = 1000000000; 1582 else 1583 ifp->if_baudrate = 100000000; 1584 ifq_set_maxlen(&ifp->if_snd, qlen); 1585 ifq_set_ready(&ifp->if_snd); 1586 1587 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1588 if (sc->re_caps & RE_C_HWCSUM) 1589 ifp->if_capabilities |= IFCAP_HWCSUM; 1590 1591 ifp->if_capenable = ifp->if_capabilities; 1592 if (ifp->if_capabilities & IFCAP_HWCSUM) 1593 ifp->if_hwassist = RE_CSUM_FEATURES; 1594 else 1595 ifp->if_hwassist = 0; 1596 1597 /* 1598 * Call MI attach routine. 1599 */ 1600 ether_ifattach(ifp, eaddr, NULL); 1601 1602 #ifdef IFPOLL_ENABLE 1603 ifpoll_compat_setup(&sc->re_npoll, 1604 &sc->re_sysctl_ctx, sc->re_sysctl_tree, device_get_unit(dev), 1605 ifp->if_serializer); 1606 #endif 1607 1608 #ifdef RE_DIAG 1609 /* 1610 * Perform hardware diagnostic on the original RTL8169. 1611 * Some 32-bit cards were incorrectly wired and would 1612 * malfunction if plugged into a 64-bit slot. 1613 */ 1614 if (sc->re_hwrev == RE_HWREV_8169) { 1615 lwkt_serialize_enter(ifp->if_serializer); 1616 error = re_diag(sc); 1617 lwkt_serialize_exit(ifp->if_serializer); 1618 1619 if (error) { 1620 device_printf(dev, "hardware diagnostic failure\n"); 1621 ether_ifdetach(ifp); 1622 goto fail; 1623 } 1624 } 1625 #endif /* RE_DIAG */ 1626 1627 /* Hook interrupt last to avoid having to lock softc */ 1628 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1629 &sc->re_intrhand, ifp->if_serializer); 1630 1631 if (error) { 1632 device_printf(dev, "couldn't set up irq\n"); 1633 ether_ifdetach(ifp); 1634 goto fail; 1635 } 1636 1637 ifp->if_cpuid = rman_get_cpuid(sc->re_irq); 1638 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1639 1640 fail: 1641 if (error) 1642 re_detach(dev); 1643 1644 return (error); 1645 } 1646 1647 /* 1648 * Shutdown hardware and free up resources. This can be called any 1649 * time after the mutex has been initialized. It is called in both 1650 * the error case in attach and the normal detach case so it needs 1651 * to be careful about only freeing resources that have actually been 1652 * allocated. 1653 */ 1654 static int 1655 re_detach(device_t dev) 1656 { 1657 struct re_softc *sc = device_get_softc(dev); 1658 struct ifnet *ifp = &sc->arpcom.ac_if; 1659 1660 /* These should only be active if attach succeeded */ 1661 if (device_is_attached(dev)) { 1662 lwkt_serialize_enter(ifp->if_serializer); 1663 re_stop(sc); 1664 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1665 lwkt_serialize_exit(ifp->if_serializer); 1666 1667 ether_ifdetach(ifp); 1668 } 1669 if (sc->re_miibus) 1670 device_delete_child(dev, sc->re_miibus); 1671 bus_generic_detach(dev); 1672 1673 if (sc->re_sysctl_tree != NULL) 1674 sysctl_ctx_free(&sc->re_sysctl_ctx); 1675 1676 if (sc->re_irq) 1677 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1678 sc->re_irq); 1679 1680 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1681 pci_release_msi(dev); 1682 1683 if (sc->re_res) { 1684 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1685 sc->re_res); 1686 } 1687 1688 /* Free DMA stuffs */ 1689 re_freemem(dev); 1690 1691 return(0); 1692 } 1693 1694 static void 1695 re_setup_rxdesc(struct re_softc *sc, int idx) 1696 { 1697 bus_addr_t paddr; 1698 uint32_t cmdstat; 1699 struct re_desc *d; 1700 1701 paddr = sc->re_ldata.re_rx_paddr[idx]; 1702 d = &sc->re_ldata.re_rx_list[idx]; 1703 1704 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1705 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1706 1707 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1708 if (idx == (sc->re_rx_desc_cnt - 1)) 1709 cmdstat |= RE_RDESC_CMD_EOR; 1710 d->re_cmdstat = htole32(cmdstat); 1711 } 1712 1713 static int 1714 re_newbuf_std(struct re_softc *sc, int idx, int init) 1715 { 1716 bus_dma_segment_t seg; 1717 bus_dmamap_t map; 1718 struct mbuf *m; 1719 int error, nsegs; 1720 1721 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1722 if (m == NULL) { 1723 error = ENOBUFS; 1724 1725 if (init) { 1726 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1727 return error; 1728 } else { 1729 goto back; 1730 } 1731 } 1732 m->m_len = m->m_pkthdr.len = MCLBYTES; 1733 1734 /* 1735 * NOTE: 1736 * re(4) chips need address of the receive buffer to be 8-byte 1737 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1738 */ 1739 1740 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1741 sc->re_ldata.re_rx_spare, m, 1742 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1743 if (error) { 1744 m_freem(m); 1745 if (init) { 1746 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1747 return error; 1748 } else { 1749 goto back; 1750 } 1751 } 1752 1753 if (!init) { 1754 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1755 sc->re_ldata.re_rx_dmamap[idx], 1756 BUS_DMASYNC_POSTREAD); 1757 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1758 sc->re_ldata.re_rx_dmamap[idx]); 1759 } 1760 sc->re_ldata.re_rx_mbuf[idx] = m; 1761 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1762 1763 map = sc->re_ldata.re_rx_dmamap[idx]; 1764 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1765 sc->re_ldata.re_rx_spare = map; 1766 back: 1767 re_setup_rxdesc(sc, idx); 1768 return error; 1769 } 1770 1771 static int 1772 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1773 { 1774 struct mbuf *m; 1775 struct re_jbuf *jbuf; 1776 int error = 0; 1777 1778 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1779 if (m == NULL) { 1780 error = ENOBUFS; 1781 if (init) { 1782 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1783 return error; 1784 } else { 1785 goto back; 1786 } 1787 } 1788 1789 jbuf = re_jbuf_alloc(sc); 1790 if (jbuf == NULL) { 1791 m_freem(m); 1792 1793 error = ENOBUFS; 1794 if (init) { 1795 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1796 return error; 1797 } else { 1798 goto back; 1799 } 1800 } 1801 1802 m->m_ext.ext_arg = jbuf; 1803 m->m_ext.ext_buf = jbuf->re_buf; 1804 m->m_ext.ext_free = re_jbuf_free; 1805 m->m_ext.ext_ref = re_jbuf_ref; 1806 m->m_ext.ext_size = sc->re_rxbuf_size; 1807 1808 m->m_data = m->m_ext.ext_buf; 1809 m->m_flags |= M_EXT; 1810 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1811 1812 /* 1813 * NOTE: 1814 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1815 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1816 */ 1817 1818 sc->re_ldata.re_rx_mbuf[idx] = m; 1819 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1820 back: 1821 re_setup_rxdesc(sc, idx); 1822 return error; 1823 } 1824 1825 static int 1826 re_tx_list_init(struct re_softc *sc) 1827 { 1828 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1829 1830 sc->re_ldata.re_tx_prodidx = 0; 1831 sc->re_ldata.re_tx_considx = 0; 1832 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1833 1834 return(0); 1835 } 1836 1837 static int 1838 re_rx_list_init(struct re_softc *sc) 1839 { 1840 int i, error; 1841 1842 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1843 1844 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1845 error = sc->re_newbuf(sc, i, 1); 1846 if (error) 1847 return(error); 1848 } 1849 1850 sc->re_ldata.re_rx_prodidx = 0; 1851 sc->re_head = sc->re_tail = NULL; 1852 1853 return(0); 1854 } 1855 1856 #define RE_IP4_PACKET 0x1 1857 #define RE_TCP_PACKET 0x2 1858 #define RE_UDP_PACKET 0x4 1859 1860 static __inline uint8_t 1861 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1862 { 1863 uint8_t packet_type = 0; 1864 1865 if (sc->re_caps & RE_C_MAC2) { 1866 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1867 packet_type |= RE_IP4_PACKET; 1868 } else { 1869 if (rxstat & RE_RDESC_STAT_PROTOID) 1870 packet_type |= RE_IP4_PACKET; 1871 } 1872 if (RE_TCPPKT(rxstat)) 1873 packet_type |= RE_TCP_PACKET; 1874 else if (RE_UDPPKT(rxstat)) 1875 packet_type |= RE_UDP_PACKET; 1876 return packet_type; 1877 } 1878 1879 /* 1880 * RX handler for C+ and 8169. For the gigE chips, we support 1881 * the reception of jumbo frames that have been fragmented 1882 * across multiple 2K mbuf cluster buffers. 1883 */ 1884 static int 1885 re_rxeof(struct re_softc *sc) 1886 { 1887 struct ifnet *ifp = &sc->arpcom.ac_if; 1888 struct mbuf *m; 1889 struct re_desc *cur_rx; 1890 uint32_t rxstat, rxctrl; 1891 int i, total_len, rx = 0; 1892 1893 for (i = sc->re_ldata.re_rx_prodidx; 1894 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1895 cur_rx = &sc->re_ldata.re_rx_list[i]; 1896 m = sc->re_ldata.re_rx_mbuf[i]; 1897 total_len = RE_RXBYTES(cur_rx); 1898 rxstat = le32toh(cur_rx->re_cmdstat); 1899 rxctrl = le32toh(cur_rx->re_control); 1900 1901 rx = 1; 1902 1903 #ifdef INVARIANTS 1904 if (sc->re_flags & RE_F_USE_JPOOL) 1905 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1906 #endif 1907 1908 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1909 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1910 re_setup_rxdesc(sc, i); 1911 continue; 1912 } 1913 1914 if (sc->re_newbuf(sc, i, 0)) { 1915 /* Drop upcoming fragments */ 1916 sc->re_flags |= RE_F_DROP_RXFRAG; 1917 continue; 1918 } 1919 1920 m->m_len = MCLBYTES; 1921 if (sc->re_head == NULL) { 1922 sc->re_head = sc->re_tail = m; 1923 } else { 1924 sc->re_tail->m_next = m; 1925 sc->re_tail = m; 1926 } 1927 continue; 1928 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1929 /* 1930 * Last fragment of a multi-fragment packet. 1931 * 1932 * Since error already happened, this fragment 1933 * must be dropped as well as the fragment chain. 1934 */ 1935 re_setup_rxdesc(sc, i); 1936 re_free_rxchain(sc); 1937 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1938 continue; 1939 } 1940 1941 /* 1942 * NOTE: for the 8139C+, the frame length field 1943 * is always 12 bits in size, but for the gigE chips, 1944 * it is 13 bits (since the max RX frame length is 16K). 1945 * Unfortunately, all 32 bits in the status word 1946 * were already used, so to make room for the extra 1947 * length bit, RealTek took out the 'frame alignment 1948 * error' bit and shifted the other status bits 1949 * over one slot. The OWN, EOR, FS and LS bits are 1950 * still in the same places. We have already extracted 1951 * the frame length and checked the OWN bit, so rather 1952 * than using an alternate bit mapping, we shift the 1953 * status bits one space to the right so we can evaluate 1954 * them using the 8169 status as though it was in the 1955 * same format as that of the 8139C+. 1956 */ 1957 if (!RE_IS_8139CP(sc)) 1958 rxstat >>= 1; 1959 1960 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1961 ifp->if_ierrors++; 1962 /* 1963 * If this is part of a multi-fragment packet, 1964 * discard all the pieces. 1965 */ 1966 re_free_rxchain(sc); 1967 re_setup_rxdesc(sc, i); 1968 continue; 1969 } 1970 1971 /* 1972 * If allocating a replacement mbuf fails, 1973 * reload the current one. 1974 */ 1975 1976 if (sc->re_newbuf(sc, i, 0)) { 1977 ifp->if_ierrors++; 1978 continue; 1979 } 1980 1981 if (sc->re_head != NULL) { 1982 m->m_len = total_len % MCLBYTES; 1983 /* 1984 * Special case: if there's 4 bytes or less 1985 * in this buffer, the mbuf can be discarded: 1986 * the last 4 bytes is the CRC, which we don't 1987 * care about anyway. 1988 */ 1989 if (m->m_len <= ETHER_CRC_LEN) { 1990 sc->re_tail->m_len -= 1991 (ETHER_CRC_LEN - m->m_len); 1992 m_freem(m); 1993 } else { 1994 m->m_len -= ETHER_CRC_LEN; 1995 sc->re_tail->m_next = m; 1996 } 1997 m = sc->re_head; 1998 sc->re_head = sc->re_tail = NULL; 1999 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2000 } else { 2001 m->m_pkthdr.len = m->m_len = 2002 (total_len - ETHER_CRC_LEN); 2003 } 2004 2005 ifp->if_ipackets++; 2006 m->m_pkthdr.rcvif = ifp; 2007 2008 /* Do RX checksumming if enabled */ 2009 2010 if (ifp->if_capenable & IFCAP_RXCSUM) { 2011 uint8_t packet_type; 2012 2013 packet_type = re_packet_type(sc, rxstat, rxctrl); 2014 2015 /* Check IP header checksum */ 2016 if (packet_type & RE_IP4_PACKET) { 2017 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2018 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2019 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2020 } 2021 2022 /* Check TCP/UDP checksum */ 2023 if (((packet_type & RE_TCP_PACKET) && 2024 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2025 ((packet_type & RE_UDP_PACKET) && 2026 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2027 m->m_pkthdr.csum_flags |= 2028 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2029 CSUM_FRAG_NOT_CHECKED; 2030 m->m_pkthdr.csum_data = 0xffff; 2031 } 2032 } 2033 2034 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2035 m->m_flags |= M_VLANTAG; 2036 m->m_pkthdr.ether_vlantag = 2037 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2038 } 2039 ifp->if_input(ifp, m); 2040 } 2041 2042 sc->re_ldata.re_rx_prodidx = i; 2043 2044 return rx; 2045 } 2046 2047 #undef RE_IP4_PACKET 2048 #undef RE_TCP_PACKET 2049 #undef RE_UDP_PACKET 2050 2051 static int 2052 re_tx_collect(struct re_softc *sc) 2053 { 2054 struct ifnet *ifp = &sc->arpcom.ac_if; 2055 uint32_t txstat; 2056 int idx, tx = 0; 2057 2058 for (idx = sc->re_ldata.re_tx_considx; 2059 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2060 RE_TXDESC_INC(sc, idx)) { 2061 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2062 if (txstat & RE_TDESC_CMD_OWN) 2063 break; 2064 2065 tx = 1; 2066 2067 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2068 2069 /* 2070 * We only stash mbufs in the last descriptor 2071 * in a fragment chain, which also happens to 2072 * be the only place where the TX status bits 2073 * are valid. 2074 */ 2075 if (txstat & RE_TDESC_CMD_EOF) { 2076 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2077 sc->re_ldata.re_tx_dmamap[idx]); 2078 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2079 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2080 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2081 RE_TDESC_STAT_COLCNT)) 2082 ifp->if_collisions++; 2083 if (txstat & RE_TDESC_STAT_TXERRSUM) 2084 ifp->if_oerrors++; 2085 else 2086 ifp->if_opackets++; 2087 } 2088 sc->re_ldata.re_tx_free++; 2089 } 2090 sc->re_ldata.re_tx_considx = idx; 2091 2092 return tx; 2093 } 2094 2095 static int 2096 re_txeof(struct re_softc *sc) 2097 { 2098 struct ifnet *ifp = &sc->arpcom.ac_if; 2099 int tx; 2100 2101 tx = re_tx_collect(sc); 2102 2103 /* There is enough free TX descs */ 2104 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2105 ifq_clr_oactive(&ifp->if_snd); 2106 2107 /* 2108 * Some chips will ignore a second TX request issued while an 2109 * existing transmission is in progress. If the transmitter goes 2110 * idle but there are still packets waiting to be sent, we need 2111 * to restart the channel here to flush them out. This only seems 2112 * to be required with the PCIe devices. 2113 */ 2114 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2115 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2116 else 2117 ifp->if_timer = 0; 2118 2119 return tx; 2120 } 2121 2122 static void 2123 re_tick(void *xsc) 2124 { 2125 struct re_softc *sc = xsc; 2126 2127 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2128 re_tick_serialized(xsc); 2129 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2130 } 2131 2132 static void 2133 re_tick_serialized(void *xsc) 2134 { 2135 struct re_softc *sc = xsc; 2136 struct ifnet *ifp = &sc->arpcom.ac_if; 2137 struct mii_data *mii; 2138 2139 ASSERT_SERIALIZED(ifp->if_serializer); 2140 2141 mii = device_get_softc(sc->re_miibus); 2142 mii_tick(mii); 2143 if (sc->re_flags & RE_F_LINKED) { 2144 if (!(mii->mii_media_status & IFM_ACTIVE)) 2145 sc->re_flags &= ~RE_F_LINKED; 2146 } else { 2147 if (mii->mii_media_status & IFM_ACTIVE && 2148 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2149 sc->re_flags |= RE_F_LINKED; 2150 if (!ifq_is_empty(&ifp->if_snd)) 2151 if_devstart(ifp); 2152 } 2153 } 2154 2155 callout_reset(&sc->re_timer, hz, re_tick, sc); 2156 } 2157 2158 #ifdef IFPOLL_ENABLE 2159 2160 static void 2161 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2162 { 2163 struct re_softc *sc = ifp->if_softc; 2164 2165 ASSERT_SERIALIZED(ifp->if_serializer); 2166 2167 if (sc->re_npoll.ifpc_stcount-- == 0) { 2168 uint16_t status; 2169 2170 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac; 2171 2172 status = CSR_READ_2(sc, RE_ISR); 2173 if (status == 0xffff) 2174 return; 2175 if (status) 2176 CSR_WRITE_2(sc, RE_ISR, status); 2177 2178 /* 2179 * XXX check behaviour on receiver stalls. 2180 */ 2181 2182 if (status & RE_ISR_SYSTEM_ERR) 2183 re_init(sc); 2184 } 2185 2186 sc->rxcycles = count; 2187 re_rxeof(sc); 2188 re_txeof(sc); 2189 2190 if (!ifq_is_empty(&ifp->if_snd)) 2191 if_devstart(ifp); 2192 } 2193 2194 static void 2195 re_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2196 { 2197 struct re_softc *sc = ifp->if_softc; 2198 2199 ASSERT_SERIALIZED(ifp->if_serializer); 2200 2201 if (info != NULL) { 2202 int cpuid = sc->re_npoll.ifpc_cpuid; 2203 2204 info->ifpi_rx[cpuid].poll_func = re_npoll_compat; 2205 info->ifpi_rx[cpuid].arg = NULL; 2206 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2207 2208 if (ifp->if_flags & IFF_RUNNING) 2209 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2210 ifp->if_npoll_cpuid = cpuid; 2211 } else { 2212 if (ifp->if_flags & IFF_RUNNING) 2213 re_setup_intr(sc, 1, sc->re_imtype); 2214 ifp->if_npoll_cpuid = -1; 2215 } 2216 } 2217 #endif /* IFPOLL_ENABLE */ 2218 2219 static void 2220 re_intr(void *arg) 2221 { 2222 struct re_softc *sc = arg; 2223 struct ifnet *ifp = &sc->arpcom.ac_if; 2224 uint16_t status; 2225 int rx, tx; 2226 2227 ASSERT_SERIALIZED(ifp->if_serializer); 2228 2229 if ((sc->re_flags & RE_F_SUSPENDED) || 2230 (ifp->if_flags & IFF_RUNNING) == 0) 2231 return; 2232 2233 rx = tx = 0; 2234 for (;;) { 2235 status = CSR_READ_2(sc, RE_ISR); 2236 /* If the card has gone away the read returns 0xffff. */ 2237 if (status == 0xffff) 2238 break; 2239 if (status) 2240 CSR_WRITE_2(sc, RE_ISR, status); 2241 2242 if ((status & sc->re_intrs) == 0) 2243 break; 2244 2245 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2246 rx |= re_rxeof(sc); 2247 2248 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2249 tx |= re_txeof(sc); 2250 2251 if (status & RE_ISR_SYSTEM_ERR) 2252 re_init(sc); 2253 2254 if (status & RE_ISR_LINKCHG) { 2255 callout_stop(&sc->re_timer); 2256 re_tick_serialized(sc); 2257 } 2258 } 2259 2260 if (sc->re_imtype == RE_IMTYPE_SIM) { 2261 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2262 if ((tx | rx) == 0) { 2263 /* 2264 * Nothing needs to be processed, fallback 2265 * to use TX/RX interrupts. 2266 */ 2267 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2268 2269 /* 2270 * Recollect, mainly to avoid the possible 2271 * race introduced by changing interrupt 2272 * masks. 2273 */ 2274 re_rxeof(sc); 2275 tx = re_txeof(sc); 2276 } else { 2277 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2278 } 2279 } else if (tx | rx) { 2280 /* 2281 * Assume that using simulated interrupt moderation 2282 * (hardware timer based) could reduce the interript 2283 * rate. 2284 */ 2285 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2286 } 2287 } 2288 2289 if (tx && !ifq_is_empty(&ifp->if_snd)) 2290 if_devstart(ifp); 2291 } 2292 2293 static int 2294 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2295 { 2296 struct mbuf *m = *m_head; 2297 bus_dma_segment_t segs[RE_MAXSEGS]; 2298 bus_dmamap_t map; 2299 int error, maxsegs, idx, i, nsegs; 2300 struct re_desc *d, *tx_ring; 2301 uint32_t cmd_csum, ctl_csum, vlantag; 2302 2303 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2304 ("not enough free TX desc")); 2305 2306 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2307 2308 /* 2309 * Set up checksum offload. Note: checksum offload bits must 2310 * appear in all descriptors of a multi-descriptor transmit 2311 * attempt. (This is according to testing done with an 8169 2312 * chip. I'm not sure if this is a requirement or a bug.) 2313 */ 2314 cmd_csum = ctl_csum = 0; 2315 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2316 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2317 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2318 } 2319 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2320 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2321 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2322 } 2323 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2324 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2325 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2326 } 2327 2328 /* For MAC2 chips, csum flags are set on re_control */ 2329 if (sc->re_caps & RE_C_MAC2) 2330 cmd_csum = 0; 2331 else 2332 ctl_csum = 0; 2333 2334 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2335 /* 2336 * With some of the RealTek chips, using the checksum offload 2337 * support in conjunction with the autopadding feature results 2338 * in the transmission of corrupt frames. For example, if we 2339 * need to send a really small IP fragment that's less than 60 2340 * bytes in size, and IP header checksumming is enabled, the 2341 * resulting ethernet frame that appears on the wire will 2342 * have garbled payload. To work around this, if TX checksum 2343 * offload is enabled, we always manually pad short frames out 2344 * to the minimum ethernet frame size. 2345 * 2346 * Note: this appears unnecessary for TCP, and doing it for TCP 2347 * with PCIe adapters seems to result in bad checksums. 2348 */ 2349 if ((m->m_pkthdr.csum_flags & 2350 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2351 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2352 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2353 error = m_devpad(m, RE_MIN_FRAMELEN); 2354 if (error) 2355 goto back; 2356 } 2357 } 2358 2359 vlantag = 0; 2360 if (m->m_flags & M_VLANTAG) { 2361 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2362 RE_TDESC_CTL_INSTAG; 2363 } 2364 2365 maxsegs = sc->re_ldata.re_tx_free; 2366 if (maxsegs > RE_MAXSEGS) 2367 maxsegs = RE_MAXSEGS; 2368 2369 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2370 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2371 if (error) 2372 goto back; 2373 2374 m = *m_head; 2375 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2376 2377 /* 2378 * Map the segment array into descriptors. We also keep track 2379 * of the end of the ring and set the end-of-ring bits as needed, 2380 * and we set the ownership bits in all except the very first 2381 * descriptor, whose ownership bits will be turned on later. 2382 */ 2383 tx_ring = sc->re_ldata.re_tx_list; 2384 idx = *idx0; 2385 i = 0; 2386 for (;;) { 2387 uint32_t cmdstat; 2388 2389 d = &tx_ring[idx]; 2390 2391 cmdstat = segs[i].ds_len; 2392 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2393 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2394 if (i == 0) 2395 cmdstat |= RE_TDESC_CMD_SOF; 2396 else 2397 cmdstat |= RE_TDESC_CMD_OWN; 2398 if (idx == (sc->re_tx_desc_cnt - 1)) 2399 cmdstat |= RE_TDESC_CMD_EOR; 2400 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2401 d->re_control = htole32(ctl_csum | vlantag); 2402 2403 i++; 2404 if (i == nsegs) 2405 break; 2406 RE_TXDESC_INC(sc, idx); 2407 } 2408 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2409 2410 /* Transfer ownership of packet to the chip. */ 2411 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2412 if (*idx0 != idx) 2413 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2414 2415 /* 2416 * Insure that the map for this transmission 2417 * is placed at the array index of the last descriptor 2418 * in this chain. 2419 */ 2420 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2421 sc->re_ldata.re_tx_dmamap[idx] = map; 2422 2423 sc->re_ldata.re_tx_mbuf[idx] = m; 2424 sc->re_ldata.re_tx_free -= nsegs; 2425 2426 RE_TXDESC_INC(sc, idx); 2427 *idx0 = idx; 2428 back: 2429 if (error) { 2430 m_freem(*m_head); 2431 *m_head = NULL; 2432 } 2433 return error; 2434 } 2435 2436 /* 2437 * Main transmit routine for C+ and gigE NICs. 2438 */ 2439 2440 static void 2441 re_start(struct ifnet *ifp) 2442 { 2443 struct re_softc *sc = ifp->if_softc; 2444 struct mbuf *m_head; 2445 int idx, need_trans, oactive, error; 2446 2447 ASSERT_SERIALIZED(ifp->if_serializer); 2448 2449 if ((sc->re_flags & RE_F_LINKED) == 0) { 2450 ifq_purge(&ifp->if_snd); 2451 return; 2452 } 2453 2454 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2455 return; 2456 2457 idx = sc->re_ldata.re_tx_prodidx; 2458 2459 need_trans = 0; 2460 oactive = 0; 2461 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2462 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2463 if (!oactive) { 2464 if (re_tx_collect(sc)) { 2465 oactive = 1; 2466 continue; 2467 } 2468 } 2469 ifq_set_oactive(&ifp->if_snd); 2470 break; 2471 } 2472 2473 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2474 if (m_head == NULL) 2475 break; 2476 2477 error = re_encap(sc, &m_head, &idx); 2478 if (error) { 2479 /* m_head is freed by re_encap(), if we reach here */ 2480 ifp->if_oerrors++; 2481 2482 if (error == EFBIG && !oactive) { 2483 if (re_tx_collect(sc)) { 2484 oactive = 1; 2485 continue; 2486 } 2487 } 2488 ifq_set_oactive(&ifp->if_snd); 2489 break; 2490 } 2491 2492 oactive = 0; 2493 need_trans = 1; 2494 2495 /* 2496 * If there's a BPF listener, bounce a copy of this frame 2497 * to him. 2498 */ 2499 ETHER_BPF_MTAP(ifp, m_head); 2500 } 2501 2502 /* 2503 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2504 * for OACTIVE to not be properly set when we also do not 2505 * have sufficient free tx descriptors, leaving packet in 2506 * ifp->if_snd. This can cause if_start_dispatch() to loop 2507 * infinitely so make sure OACTIVE is set properly. 2508 */ 2509 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2510 if (!ifq_is_oactive(&ifp->if_snd)) { 2511 if_printf(ifp, "Debug: OACTIVE was not set when " 2512 "re_tx_free was below minimum!\n"); 2513 ifq_set_oactive(&ifp->if_snd); 2514 } 2515 } 2516 if (!need_trans) 2517 return; 2518 2519 sc->re_ldata.re_tx_prodidx = idx; 2520 2521 /* 2522 * RealTek put the TX poll request register in a different 2523 * location on the 8169 gigE chip. I don't know why. 2524 */ 2525 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2526 2527 /* 2528 * Set a timeout in case the chip goes out to lunch. 2529 */ 2530 ifp->if_timer = 5; 2531 } 2532 2533 static void 2534 re_init(void *xsc) 2535 { 2536 struct re_softc *sc = xsc; 2537 struct ifnet *ifp = &sc->arpcom.ac_if; 2538 struct mii_data *mii; 2539 int error, framelen; 2540 2541 ASSERT_SERIALIZED(ifp->if_serializer); 2542 2543 mii = device_get_softc(sc->re_miibus); 2544 2545 /* 2546 * Cancel pending I/O and free all RX/TX buffers. 2547 */ 2548 re_stop(sc); 2549 2550 if (sc->re_caps & RE_C_CONTIGRX) { 2551 if (ifp->if_mtu > ETHERMTU) { 2552 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2553 sc->re_flags |= RE_F_USE_JPOOL; 2554 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2555 sc->re_newbuf = re_newbuf_jumbo; 2556 } else { 2557 sc->re_flags &= ~RE_F_USE_JPOOL; 2558 sc->re_rxbuf_size = MCLBYTES; 2559 sc->re_newbuf = re_newbuf_std; 2560 } 2561 } 2562 2563 /* 2564 * Adjust max read request size according to MTU; mainly to 2565 * improve TX performance for common case (ETHERMTU) on GigE 2566 * NICs. However, this could _not_ be done on 10/100 only 2567 * NICs; their DMA engines will malfunction using non-default 2568 * max read request size. 2569 */ 2570 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2571 if (ifp->if_mtu > ETHERMTU) { 2572 /* 2573 * 512 seems to be the only value that works 2574 * reliably with jumbo frame 2575 */ 2576 pcie_set_max_readrq(sc->re_dev, 2577 PCIEM_DEVCTL_MAX_READRQ_512); 2578 } else { 2579 pcie_set_max_readrq(sc->re_dev, 2580 PCIEM_DEVCTL_MAX_READRQ_4096); 2581 } 2582 } 2583 2584 /* 2585 * Enable C+ RX and TX mode, as well as VLAN stripping and 2586 * RX checksum offload. We must configure the C+ register 2587 * before all others. 2588 */ 2589 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2590 RE_CPLUSCMD_PCI_MRW | 2591 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2592 RE_CPLUSCMD_VLANSTRIP : 0) | 2593 (ifp->if_capenable & IFCAP_RXCSUM ? 2594 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2595 2596 /* 2597 * Init our MAC address. Even though the chipset 2598 * documentation doesn't mention it, we need to enter "Config 2599 * register write enable" mode to modify the ID registers. 2600 */ 2601 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2602 CSR_WRITE_4(sc, RE_IDR0, 2603 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2604 CSR_WRITE_2(sc, RE_IDR4, 2605 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2606 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2607 2608 /* 2609 * For C+ mode, initialize the RX descriptors and mbufs. 2610 */ 2611 error = re_rx_list_init(sc); 2612 if (error) { 2613 re_stop(sc); 2614 return; 2615 } 2616 error = re_tx_list_init(sc); 2617 if (error) { 2618 re_stop(sc); 2619 return; 2620 } 2621 2622 /* 2623 * Load the addresses of the RX and TX lists into the chip. 2624 */ 2625 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2626 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2627 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2628 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2629 2630 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2631 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2632 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2633 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2634 2635 /* 2636 * Enable transmit and receive. 2637 */ 2638 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2639 2640 /* 2641 * Set the initial TX and RX configuration. 2642 */ 2643 if (sc->re_flags & RE_F_TESTMODE) { 2644 if (!RE_IS_8139CP(sc)) 2645 CSR_WRITE_4(sc, RE_TXCFG, 2646 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2647 else 2648 CSR_WRITE_4(sc, RE_TXCFG, 2649 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2650 } else 2651 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2652 2653 framelen = RE_FRAMELEN(ifp->if_mtu); 2654 if (framelen < MCLBYTES) 2655 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2656 else 2657 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2658 2659 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2660 2661 /* 2662 * Program the multicast filter, if necessary. 2663 */ 2664 re_setmulti(sc); 2665 2666 #ifdef IFPOLL_ENABLE 2667 /* 2668 * Disable interrupts if we are polling. 2669 */ 2670 if (ifp->if_flags & IFF_NPOLLING) 2671 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2672 else /* otherwise ... */ 2673 #endif /* IFPOLL_ENABLE */ 2674 /* 2675 * Enable interrupts. 2676 */ 2677 if (sc->re_flags & RE_F_TESTMODE) 2678 CSR_WRITE_2(sc, RE_IMR, 0); 2679 else 2680 re_setup_intr(sc, 1, sc->re_imtype); 2681 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2682 2683 /* Start RX/TX process. */ 2684 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2685 2686 #ifdef notdef 2687 /* Enable receiver and transmitter. */ 2688 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2689 #endif 2690 2691 /* 2692 * For 8169 gigE NICs, set the max allowed RX packet 2693 * size so we can receive jumbo frames. 2694 */ 2695 if (!RE_IS_8139CP(sc)) { 2696 if (sc->re_caps & RE_C_CONTIGRX) 2697 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2698 else 2699 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2700 } 2701 2702 if (sc->re_flags & RE_F_TESTMODE) 2703 return; 2704 2705 mii_mediachg(mii); 2706 2707 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2708 2709 ifp->if_flags |= IFF_RUNNING; 2710 ifq_clr_oactive(&ifp->if_snd); 2711 2712 callout_reset(&sc->re_timer, hz, re_tick, sc); 2713 } 2714 2715 /* 2716 * Set media options. 2717 */ 2718 static int 2719 re_ifmedia_upd(struct ifnet *ifp) 2720 { 2721 struct re_softc *sc = ifp->if_softc; 2722 struct mii_data *mii; 2723 2724 ASSERT_SERIALIZED(ifp->if_serializer); 2725 2726 mii = device_get_softc(sc->re_miibus); 2727 mii_mediachg(mii); 2728 2729 return(0); 2730 } 2731 2732 /* 2733 * Report current media status. 2734 */ 2735 static void 2736 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2737 { 2738 struct re_softc *sc = ifp->if_softc; 2739 struct mii_data *mii; 2740 2741 ASSERT_SERIALIZED(ifp->if_serializer); 2742 2743 mii = device_get_softc(sc->re_miibus); 2744 2745 mii_pollstat(mii); 2746 ifmr->ifm_active = mii->mii_media_active; 2747 ifmr->ifm_status = mii->mii_media_status; 2748 } 2749 2750 static int 2751 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2752 { 2753 struct re_softc *sc = ifp->if_softc; 2754 struct ifreq *ifr = (struct ifreq *) data; 2755 struct mii_data *mii; 2756 int error = 0, mask; 2757 2758 ASSERT_SERIALIZED(ifp->if_serializer); 2759 2760 switch(command) { 2761 case SIOCSIFMTU: 2762 if (ifr->ifr_mtu > sc->re_maxmtu) { 2763 error = EINVAL; 2764 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2765 ifp->if_mtu = ifr->ifr_mtu; 2766 if (ifp->if_flags & IFF_RUNNING) 2767 ifp->if_init(sc); 2768 } 2769 break; 2770 2771 case SIOCSIFFLAGS: 2772 if (ifp->if_flags & IFF_UP) { 2773 if (ifp->if_flags & IFF_RUNNING) { 2774 if ((ifp->if_flags ^ sc->re_if_flags) & 2775 (IFF_PROMISC | IFF_ALLMULTI)) 2776 re_setmulti(sc); 2777 } else { 2778 re_init(sc); 2779 } 2780 } else if (ifp->if_flags & IFF_RUNNING) { 2781 re_stop(sc); 2782 } 2783 sc->re_if_flags = ifp->if_flags; 2784 break; 2785 2786 case SIOCADDMULTI: 2787 case SIOCDELMULTI: 2788 re_setmulti(sc); 2789 break; 2790 2791 case SIOCGIFMEDIA: 2792 case SIOCSIFMEDIA: 2793 mii = device_get_softc(sc->re_miibus); 2794 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2795 break; 2796 2797 case SIOCSIFCAP: 2798 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2799 ifp->if_capabilities; 2800 ifp->if_capenable ^= mask; 2801 2802 if (mask & IFCAP_HWCSUM) { 2803 if (ifp->if_capenable & IFCAP_TXCSUM) 2804 ifp->if_hwassist = RE_CSUM_FEATURES; 2805 else 2806 ifp->if_hwassist = 0; 2807 } 2808 if (mask && (ifp->if_flags & IFF_RUNNING)) 2809 re_init(sc); 2810 break; 2811 2812 default: 2813 error = ether_ioctl(ifp, command, data); 2814 break; 2815 } 2816 return(error); 2817 } 2818 2819 static void 2820 re_watchdog(struct ifnet *ifp) 2821 { 2822 struct re_softc *sc = ifp->if_softc; 2823 2824 ASSERT_SERIALIZED(ifp->if_serializer); 2825 2826 if_printf(ifp, "watchdog timeout\n"); 2827 2828 ifp->if_oerrors++; 2829 2830 re_txeof(sc); 2831 re_rxeof(sc); 2832 2833 re_init(sc); 2834 2835 if (!ifq_is_empty(&ifp->if_snd)) 2836 if_devstart(ifp); 2837 } 2838 2839 /* 2840 * Stop the adapter and free any mbufs allocated to the 2841 * RX and TX lists. 2842 */ 2843 static void 2844 re_stop(struct re_softc *sc) 2845 { 2846 struct ifnet *ifp = &sc->arpcom.ac_if; 2847 int i; 2848 2849 ASSERT_SERIALIZED(ifp->if_serializer); 2850 2851 /* Reset the adapter. */ 2852 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2853 2854 ifp->if_timer = 0; 2855 callout_stop(&sc->re_timer); 2856 2857 ifp->if_flags &= ~IFF_RUNNING; 2858 ifq_clr_oactive(&ifp->if_snd); 2859 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2860 2861 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2862 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2863 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2864 2865 re_free_rxchain(sc); 2866 2867 /* Free the TX list buffers. */ 2868 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2869 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2870 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2871 sc->re_ldata.re_tx_dmamap[i]); 2872 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2873 sc->re_ldata.re_tx_mbuf[i] = NULL; 2874 } 2875 } 2876 2877 /* Free the RX list buffers. */ 2878 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2879 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2880 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2881 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2882 sc->re_ldata.re_rx_dmamap[i]); 2883 } 2884 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2885 sc->re_ldata.re_rx_mbuf[i] = NULL; 2886 } 2887 } 2888 } 2889 2890 /* 2891 * Device suspend routine. Stop the interface and save some PCI 2892 * settings in case the BIOS doesn't restore them properly on 2893 * resume. 2894 */ 2895 static int 2896 re_suspend(device_t dev) 2897 { 2898 #ifndef BURN_BRIDGES 2899 int i; 2900 #endif 2901 struct re_softc *sc = device_get_softc(dev); 2902 struct ifnet *ifp = &sc->arpcom.ac_if; 2903 2904 lwkt_serialize_enter(ifp->if_serializer); 2905 2906 re_stop(sc); 2907 2908 #ifndef BURN_BRIDGES 2909 for (i = 0; i < 5; i++) 2910 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2911 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2912 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2913 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2914 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2915 #endif 2916 2917 sc->re_flags |= RE_F_SUSPENDED; 2918 2919 lwkt_serialize_exit(ifp->if_serializer); 2920 2921 return (0); 2922 } 2923 2924 /* 2925 * Device resume routine. Restore some PCI settings in case the BIOS 2926 * doesn't, re-enable busmastering, and restart the interface if 2927 * appropriate. 2928 */ 2929 static int 2930 re_resume(device_t dev) 2931 { 2932 struct re_softc *sc = device_get_softc(dev); 2933 struct ifnet *ifp = &sc->arpcom.ac_if; 2934 #ifndef BURN_BRIDGES 2935 int i; 2936 #endif 2937 2938 lwkt_serialize_enter(ifp->if_serializer); 2939 2940 #ifndef BURN_BRIDGES 2941 /* better way to do this? */ 2942 for (i = 0; i < 5; i++) 2943 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2944 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2945 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2946 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2947 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2948 2949 /* reenable busmastering */ 2950 pci_enable_busmaster(dev); 2951 pci_enable_io(dev, SYS_RES_IOPORT); 2952 #endif 2953 2954 /* reinitialize interface if necessary */ 2955 if (ifp->if_flags & IFF_UP) 2956 re_init(sc); 2957 2958 sc->re_flags &= ~RE_F_SUSPENDED; 2959 2960 lwkt_serialize_exit(ifp->if_serializer); 2961 2962 return (0); 2963 } 2964 2965 /* 2966 * Stop all chip I/O so that the kernel's probe routines don't 2967 * get confused by errant DMAs when rebooting. 2968 */ 2969 static void 2970 re_shutdown(device_t dev) 2971 { 2972 struct re_softc *sc = device_get_softc(dev); 2973 struct ifnet *ifp = &sc->arpcom.ac_if; 2974 2975 lwkt_serialize_enter(ifp->if_serializer); 2976 re_stop(sc); 2977 lwkt_serialize_exit(ifp->if_serializer); 2978 } 2979 2980 static int 2981 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 2982 { 2983 struct re_softc *sc = arg1; 2984 2985 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 2986 } 2987 2988 static int 2989 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 2990 { 2991 struct re_softc *sc = arg1; 2992 2993 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 2994 } 2995 2996 static int 2997 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 2998 { 2999 struct re_softc *sc = arg1; 3000 struct ifnet *ifp = &sc->arpcom.ac_if; 3001 int error, v; 3002 3003 lwkt_serialize_enter(ifp->if_serializer); 3004 3005 v = *hwtime; 3006 error = sysctl_handle_int(oidp, &v, 0, req); 3007 if (error || req->newptr == NULL) 3008 goto back; 3009 3010 if (v <= 0) { 3011 error = EINVAL; 3012 goto back; 3013 } 3014 3015 if (v != *hwtime) { 3016 *hwtime = v; 3017 3018 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3019 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3020 re_setup_hw_im(sc); 3021 } 3022 back: 3023 lwkt_serialize_exit(ifp->if_serializer); 3024 return error; 3025 } 3026 3027 static int 3028 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3029 { 3030 struct re_softc *sc = arg1; 3031 struct ifnet *ifp = &sc->arpcom.ac_if; 3032 int error, v; 3033 3034 lwkt_serialize_enter(ifp->if_serializer); 3035 3036 v = sc->re_sim_time; 3037 error = sysctl_handle_int(oidp, &v, 0, req); 3038 if (error || req->newptr == NULL) 3039 goto back; 3040 3041 if (v <= 0) { 3042 error = EINVAL; 3043 goto back; 3044 } 3045 3046 if (v != sc->re_sim_time) { 3047 sc->re_sim_time = v; 3048 3049 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3050 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3051 #ifdef foo 3052 int reg; 3053 3054 /* 3055 * Following code causes various strange 3056 * performance problems. Hmm ... 3057 */ 3058 CSR_WRITE_2(sc, RE_IMR, 0); 3059 if (!RE_IS_8139CP(sc)) 3060 reg = RE_TIMERINT_8169; 3061 else 3062 reg = RE_TIMERINT; 3063 CSR_WRITE_4(sc, reg, 0); 3064 CSR_READ_4(sc, reg); /* flush */ 3065 3066 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3067 re_setup_sim_im(sc); 3068 #else 3069 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3070 DELAY(10); 3071 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3072 #endif 3073 } 3074 } 3075 back: 3076 lwkt_serialize_exit(ifp->if_serializer); 3077 return error; 3078 } 3079 3080 static int 3081 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3082 { 3083 struct re_softc *sc = arg1; 3084 struct ifnet *ifp = &sc->arpcom.ac_if; 3085 int error, v; 3086 3087 lwkt_serialize_enter(ifp->if_serializer); 3088 3089 v = sc->re_imtype; 3090 error = sysctl_handle_int(oidp, &v, 0, req); 3091 if (error || req->newptr == NULL) 3092 goto back; 3093 3094 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3095 error = EINVAL; 3096 goto back; 3097 } 3098 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3099 /* Can't do hardware interrupt moderation */ 3100 error = EOPNOTSUPP; 3101 goto back; 3102 } 3103 3104 if (v != sc->re_imtype) { 3105 sc->re_imtype = v; 3106 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3107 IFF_RUNNING) 3108 re_setup_intr(sc, 1, sc->re_imtype); 3109 } 3110 back: 3111 lwkt_serialize_exit(ifp->if_serializer); 3112 return error; 3113 } 3114 3115 static void 3116 re_setup_hw_im(struct re_softc *sc) 3117 { 3118 KKASSERT(sc->re_caps & RE_C_HWIM); 3119 3120 /* 3121 * Interrupt moderation 3122 * 3123 * 0xABCD 3124 * A - unknown (maybe TX related) 3125 * B - TX timer (unit: 25us) 3126 * C - unknown (maybe RX related) 3127 * D - RX timer (unit: 25us) 3128 * 3129 * 3130 * re(4)'s interrupt moderation is actually controlled by 3131 * two variables, like most other NICs (bge, bce etc.) 3132 * o timer 3133 * o number of packets [P] 3134 * 3135 * The logic relationship between these two variables is 3136 * similar to other NICs too: 3137 * if (timer expire || packets > [P]) 3138 * Interrupt is delivered 3139 * 3140 * Currently we only know how to set 'timer', but not 3141 * 'number of packets', which should be ~30, as far as I 3142 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3143 */ 3144 CSR_WRITE_2(sc, RE_IM, 3145 RE_IM_RXTIME(sc->re_rx_time) | 3146 RE_IM_TXTIME(sc->re_tx_time) | 3147 RE_IM_MAGIC); 3148 } 3149 3150 static void 3151 re_disable_hw_im(struct re_softc *sc) 3152 { 3153 if (sc->re_caps & RE_C_HWIM) 3154 CSR_WRITE_2(sc, RE_IM, 0); 3155 } 3156 3157 static void 3158 re_setup_sim_im(struct re_softc *sc) 3159 { 3160 if (!RE_IS_8139CP(sc)) { 3161 uint32_t ticks; 3162 3163 /* 3164 * Datasheet says tick decreases at bus speed, 3165 * but it seems the clock runs a little bit 3166 * faster, so we do some compensation here. 3167 */ 3168 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3169 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3170 } else { 3171 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3172 } 3173 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3174 sc->re_flags |= RE_F_TIMER_INTR; 3175 } 3176 3177 static void 3178 re_disable_sim_im(struct re_softc *sc) 3179 { 3180 if (!RE_IS_8139CP(sc)) 3181 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3182 else 3183 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3184 sc->re_flags &= ~RE_F_TIMER_INTR; 3185 } 3186 3187 static void 3188 re_config_imtype(struct re_softc *sc, int imtype) 3189 { 3190 switch (imtype) { 3191 case RE_IMTYPE_HW: 3192 KKASSERT(sc->re_caps & RE_C_HWIM); 3193 /* FALL THROUGH */ 3194 case RE_IMTYPE_NONE: 3195 sc->re_intrs = RE_INTRS; 3196 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3197 RE_ISR_RX_OVERRUN; 3198 sc->re_tx_ack = RE_ISR_TX_OK; 3199 break; 3200 3201 case RE_IMTYPE_SIM: 3202 sc->re_intrs = RE_INTRS_TIMER; 3203 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3204 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3205 break; 3206 3207 default: 3208 panic("%s: unknown imtype %d", 3209 sc->arpcom.ac_if.if_xname, imtype); 3210 } 3211 } 3212 3213 static void 3214 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3215 { 3216 re_config_imtype(sc, imtype); 3217 3218 if (enable_intrs) 3219 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3220 else 3221 CSR_WRITE_2(sc, RE_IMR, 0); 3222 3223 sc->re_npoll.ifpc_stcount = 0; 3224 3225 switch (imtype) { 3226 case RE_IMTYPE_NONE: 3227 re_disable_sim_im(sc); 3228 re_disable_hw_im(sc); 3229 break; 3230 3231 case RE_IMTYPE_HW: 3232 KKASSERT(sc->re_caps & RE_C_HWIM); 3233 re_disable_sim_im(sc); 3234 re_setup_hw_im(sc); 3235 break; 3236 3237 case RE_IMTYPE_SIM: 3238 re_disable_hw_im(sc); 3239 re_setup_sim_im(sc); 3240 break; 3241 3242 default: 3243 panic("%s: unknown imtype %d", 3244 sc->arpcom.ac_if.if_xname, imtype); 3245 } 3246 } 3247 3248 static void 3249 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3250 { 3251 int i; 3252 3253 if (sc->re_macver == RE_MACVER_11 || 3254 sc->re_macver == RE_MACVER_12 || 3255 sc->re_macver == RE_MACVER_30 || 3256 sc->re_macver == RE_MACVER_31) { 3257 uint16_t re_did; 3258 3259 re_get_eewidth(sc); 3260 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3261 if (re_did == 0x8128) { 3262 uint16_t as[ETHER_ADDR_LEN / 2]; 3263 int eaddr_off; 3264 3265 if (sc->re_macver == RE_MACVER_30 || 3266 sc->re_macver == RE_MACVER_31) 3267 eaddr_off = RE_EE_EADDR1; 3268 else 3269 eaddr_off = RE_EE_EADDR0; 3270 3271 /* 3272 * Get station address from the EEPROM. 3273 */ 3274 re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3); 3275 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3276 as[i] = le16toh(as[i]); 3277 bcopy(as, eaddr, ETHER_ADDR_LEN); 3278 return; 3279 } 3280 } 3281 3282 /* 3283 * Get station address from IDRx. 3284 */ 3285 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3286 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3287 } 3288 3289 static int 3290 re_jpool_alloc(struct re_softc *sc) 3291 { 3292 struct re_list_data *ldata = &sc->re_ldata; 3293 struct re_jbuf *jbuf; 3294 bus_addr_t paddr; 3295 bus_size_t jpool_size; 3296 bus_dmamem_t dmem; 3297 caddr_t buf; 3298 int i, error; 3299 3300 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3301 3302 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3303 M_DEVBUF, M_WAITOK | M_ZERO); 3304 3305 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3306 3307 error = bus_dmamem_coherent(sc->re_parent_tag, 3308 RE_RXBUF_ALIGN, 0, 3309 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3310 jpool_size, BUS_DMA_WAITOK, &dmem); 3311 if (error) { 3312 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3313 return error; 3314 } 3315 ldata->re_jpool_tag = dmem.dmem_tag; 3316 ldata->re_jpool_map = dmem.dmem_map; 3317 ldata->re_jpool = dmem.dmem_addr; 3318 paddr = dmem.dmem_busaddr; 3319 3320 /* ..and split it into 9KB chunks */ 3321 SLIST_INIT(&ldata->re_jbuf_free); 3322 3323 buf = ldata->re_jpool; 3324 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3325 jbuf = &ldata->re_jbuf[i]; 3326 3327 jbuf->re_sc = sc; 3328 jbuf->re_inuse = 0; 3329 jbuf->re_slot = i; 3330 jbuf->re_buf = buf; 3331 jbuf->re_paddr = paddr; 3332 3333 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3334 3335 buf += RE_JBUF_SIZE; 3336 paddr += RE_JBUF_SIZE; 3337 } 3338 return 0; 3339 } 3340 3341 static void 3342 re_jpool_free(struct re_softc *sc) 3343 { 3344 struct re_list_data *ldata = &sc->re_ldata; 3345 3346 if (ldata->re_jpool_tag != NULL) { 3347 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3348 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3349 ldata->re_jpool_map); 3350 bus_dma_tag_destroy(ldata->re_jpool_tag); 3351 ldata->re_jpool_tag = NULL; 3352 } 3353 3354 if (ldata->re_jbuf != NULL) { 3355 kfree(ldata->re_jbuf, M_DEVBUF); 3356 ldata->re_jbuf = NULL; 3357 } 3358 } 3359 3360 static struct re_jbuf * 3361 re_jbuf_alloc(struct re_softc *sc) 3362 { 3363 struct re_list_data *ldata = &sc->re_ldata; 3364 struct re_jbuf *jbuf; 3365 3366 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3367 3368 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3369 if (jbuf != NULL) { 3370 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3371 jbuf->re_inuse = 1; 3372 } 3373 3374 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3375 3376 return jbuf; 3377 } 3378 3379 static void 3380 re_jbuf_free(void *arg) 3381 { 3382 struct re_jbuf *jbuf = arg; 3383 struct re_softc *sc = jbuf->re_sc; 3384 struct re_list_data *ldata = &sc->re_ldata; 3385 3386 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3387 panic("%s: free wrong jumbo buffer", 3388 sc->arpcom.ac_if.if_xname); 3389 } else if (jbuf->re_inuse == 0) { 3390 panic("%s: jumbo buffer already freed", 3391 sc->arpcom.ac_if.if_xname); 3392 } 3393 3394 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3395 atomic_subtract_int(&jbuf->re_inuse, 1); 3396 if (jbuf->re_inuse == 0) 3397 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3398 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3399 } 3400 3401 static void 3402 re_jbuf_ref(void *arg) 3403 { 3404 struct re_jbuf *jbuf = arg; 3405 struct re_softc *sc = jbuf->re_sc; 3406 struct re_list_data *ldata = &sc->re_ldata; 3407 3408 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3409 panic("%s: ref wrong jumbo buffer", 3410 sc->arpcom.ac_if.if_xname); 3411 } else if (jbuf->re_inuse == 0) { 3412 panic("%s: jumbo buffer already freed", 3413 sc->arpcom.ac_if.if_xname); 3414 } 3415 atomic_add_int(&jbuf->re_inuse, 1); 3416 } 3417