1 /* $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ 20 * $DragonFly$ 21 */ 22 23 /*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 #include <sys/rman.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/ifq_var.h> 52 53 #include <netproto/802_11/ieee80211_var.h> 54 #include <netproto/802_11/ieee80211_radiotap.h> 55 #include <netproto/802_11/ieee80211_regdomain.h> 56 #include <netproto/802_11/ieee80211_ratectl.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 64 #include <dev/netif/ral/rt2661reg.h> 65 #include <dev/netif/ral/rt2661var.h> 66 67 #define RAL_DEBUG 68 #ifdef RAL_DEBUG 69 #define DPRINTF(sc, fmt, ...) do { \ 70 if (sc->sc_debug > 0) \ 71 kprintf(fmt, __VA_ARGS__); \ 72 } while (0) 73 #define DPRINTFN(sc, n, fmt, ...) do { \ 74 if (sc->sc_debug >= (n)) \ 75 kprintf(fmt, __VA_ARGS__); \ 76 } while (0) 77 #else 78 #define DPRINTF(sc, fmt, ...) 79 #define DPRINTFN(sc, n, fmt, ...) 80 #endif 81 82 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 83 const char name[IFNAMSIZ], int unit, int opmode, 84 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 85 const uint8_t mac[IEEE80211_ADDR_LEN]); 86 static void rt2661_vap_delete(struct ieee80211vap *); 87 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 88 int); 89 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *, int); 91 static void rt2661_reset_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *); 93 static void rt2661_free_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *, int); 97 static void rt2661_reset_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *); 99 static void rt2661_free_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101 static int rt2661_newstate(struct ieee80211vap *, 102 enum ieee80211_state, int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_rx_intr(struct rt2661_softc *); 105 static void rt2661_tx_intr(struct rt2661_softc *); 106 static void rt2661_tx_dma_intr(struct rt2661_softc *, 107 struct rt2661_tx_ring *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 static void rt2661_scan_start(struct ieee80211com *); 112 static void rt2661_scan_end(struct ieee80211com *); 113 static void rt2661_set_channel(struct ieee80211com *); 114 static void rt2661_setup_tx_desc(struct rt2661_softc *, 115 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 116 int, const bus_dma_segment_t *, int, int); 117 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 118 struct ieee80211_node *, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static void rt2661_start_locked(struct ifnet *); 122 static void rt2661_start(struct ifnet *); 123 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 124 const struct ieee80211_bpf_params *); 125 static void rt2661_watchdog(void *); 126 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 127 struct ucred *); 128 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 129 uint8_t); 130 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 131 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 132 uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 134 uint16_t); 135 static void rt2661_select_antenna(struct rt2661_softc *); 136 static void rt2661_enable_mrr(struct rt2661_softc *); 137 static void rt2661_set_txpreamble(struct rt2661_softc *); 138 static void rt2661_set_basicrates(struct rt2661_softc *, 139 const struct ieee80211_rateset *); 140 static void rt2661_select_band(struct rt2661_softc *, 141 struct ieee80211_channel *); 142 static void rt2661_set_chan(struct rt2661_softc *, 143 struct ieee80211_channel *); 144 static void rt2661_set_bssid(struct rt2661_softc *, 145 const uint8_t *); 146 static void rt2661_set_macaddr(struct rt2661_softc *, 147 const uint8_t *); 148 static void rt2661_update_promisc(struct ifnet *); 149 static int rt2661_wme_update(struct ieee80211com *) __unused; 150 static void rt2661_update_slot(struct ifnet *); 151 static const char *rt2661_get_rf(int); 152 static void rt2661_read_eeprom(struct rt2661_softc *, 153 uint8_t macaddr[IEEE80211_ADDR_LEN]); 154 static int rt2661_bbp_init(struct rt2661_softc *); 155 static void rt2661_init_locked(struct rt2661_softc *); 156 static void rt2661_init(void *); 157 static void rt2661_stop_locked(struct rt2661_softc *); 158 static void rt2661_stop(void *); 159 static int rt2661_load_microcode(struct rt2661_softc *); 160 #ifdef notyet 161 static void rt2661_rx_tune(struct rt2661_softc *); 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *, 166 struct ieee80211vap *); 167 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 168 static void rt2661_enable_tsf(struct rt2661_softc *); 169 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 170 171 static const struct { 172 uint32_t reg; 173 uint32_t val; 174 } rt2661_def_mac[] = { 175 RT2661_DEF_MAC 176 }; 177 178 static const struct { 179 uint8_t reg; 180 uint8_t val; 181 } rt2661_def_bbp[] = { 182 RT2661_DEF_BBP 183 }; 184 185 static const struct rfprog { 186 uint8_t chan; 187 uint32_t r1, r2, r3, r4; 188 } rt2661_rf5225_1[] = { 189 RT2661_RF5225_1 190 }, rt2661_rf5225_2[] = { 191 RT2661_RF5225_2 192 }; 193 194 int 195 rt2661_attach(device_t dev, int id) 196 { 197 struct rt2661_softc *sc = device_get_softc(dev); 198 struct ieee80211com *ic; 199 struct ifnet *ifp; 200 uint32_t val; 201 int error, ac, ntries; 202 uint8_t bands; 203 uint8_t macaddr[IEEE80211_ADDR_LEN]; 204 struct sysctl_ctx_list *ctx; 205 struct sysctl_oid *tree; 206 207 sc->sc_id = id; 208 sc->sc_dev = dev; 209 210 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 211 if (ifp == NULL) { 212 device_printf(sc->sc_dev, "can not if_alloc()\n"); 213 return ENOMEM; 214 } 215 ic = ifp->if_l2com; 216 217 lockinit(&sc->sc_lock, __DECONST(char *, device_get_nameunit(dev)), 218 0, LK_CANRECURSE); 219 220 callout_init(&sc->watchdog_ch); 221 222 /* wait for NIC to initialize */ 223 for (ntries = 0; ntries < 1000; ntries++) { 224 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 225 break; 226 DELAY(1000); 227 } 228 if (ntries == 1000) { 229 device_printf(sc->sc_dev, 230 "timeout waiting for NIC to initialize\n"); 231 error = EIO; 232 goto fail1; 233 } 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2661_read_eeprom(sc, macaddr); 237 238 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 239 rt2661_get_rf(sc->rf_rev)); 240 241 /* 242 * Allocate Tx and Rx rings. 243 */ 244 for (ac = 0; ac < 4; ac++) { 245 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 246 RT2661_TX_RING_COUNT); 247 if (error != 0) { 248 device_printf(sc->sc_dev, 249 "could not allocate Tx ring %d\n", ac); 250 goto fail2; 251 } 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 255 if (error != 0) { 256 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 257 goto fail2; 258 } 259 260 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 263 goto fail3; 264 } 265 266 ifp->if_softc = sc; 267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_init = rt2661_init; 270 ifp->if_ioctl = rt2661_ioctl; 271 ifp->if_start = rt2661_start; 272 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 273 ifq_set_ready(&ifp->if_snd); 274 275 ic->ic_ifp = ifp; 276 ic->ic_opmode = IEEE80211_M_STA; 277 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 278 279 /* set device capabilities */ 280 ic->ic_caps = 281 IEEE80211_C_STA /* station mode */ 282 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 283 | IEEE80211_C_HOSTAP /* hostap mode */ 284 | IEEE80211_C_MONITOR /* monitor mode */ 285 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 286 | IEEE80211_C_WDS /* 4-address traffic works */ 287 | IEEE80211_C_MBSS /* mesh point link mode */ 288 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 289 | IEEE80211_C_SHSLOT /* short slot time supported */ 290 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 291 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 292 #ifdef notyet 293 | IEEE80211_C_TXFRAG /* handle tx frags */ 294 | IEEE80211_C_WME /* 802.11e */ 295 #endif 296 ; 297 298 bands = 0; 299 setbit(&bands, IEEE80211_MODE_11B); 300 setbit(&bands, IEEE80211_MODE_11G); 301 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 302 setbit(&bands, IEEE80211_MODE_11A); 303 ieee80211_init_channels(ic, NULL, &bands); 304 305 ieee80211_ifattach(ic, macaddr); 306 #if 0 307 ic->ic_wme.wme_update = rt2661_wme_update; 308 #endif 309 ic->ic_scan_start = rt2661_scan_start; 310 ic->ic_scan_end = rt2661_scan_end; 311 ic->ic_set_channel = rt2661_set_channel; 312 ic->ic_updateslot = rt2661_update_slot; 313 ic->ic_update_promisc = rt2661_update_promisc; 314 ic->ic_raw_xmit = rt2661_raw_xmit; 315 316 ic->ic_vap_create = rt2661_vap_create; 317 ic->ic_vap_delete = rt2661_vap_delete; 318 319 ieee80211_radiotap_attach(ic, 320 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 321 RT2661_TX_RADIOTAP_PRESENT, 322 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 323 RT2661_RX_RADIOTAP_PRESENT); 324 325 ctx = &sc->sc_sysctl_ctx; 326 sysctl_ctx_init(ctx); 327 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 328 OID_AUTO, 329 device_get_nameunit(sc->sc_dev), 330 CTLFLAG_RD, 0, ""); 331 if (tree == NULL) { 332 device_printf(sc->sc_dev, "can't add sysctl node\n"); 333 return 0; 334 } 335 #ifdef RAL_DEBUG 336 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 337 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 338 #endif 339 if (bootverbose) 340 ieee80211_announce(ic); 341 342 return 0; 343 344 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 345 fail2: while (--ac >= 0) 346 rt2661_free_tx_ring(sc, &sc->txq[ac]); 347 fail1: lockuninit(&sc->sc_lock); 348 if_free(ifp); 349 return error; 350 } 351 352 int 353 rt2661_detach(void *xsc) 354 { 355 struct rt2661_softc *sc = xsc; 356 struct ifnet *ifp = sc->sc_ifp; 357 struct ieee80211com *ic = ifp->if_l2com; 358 359 RAL_LOCK(sc); 360 rt2661_stop_locked(sc); 361 RAL_UNLOCK(sc); 362 363 ieee80211_ifdetach(ic); 364 365 rt2661_free_tx_ring(sc, &sc->txq[0]); 366 rt2661_free_tx_ring(sc, &sc->txq[1]); 367 rt2661_free_tx_ring(sc, &sc->txq[2]); 368 rt2661_free_tx_ring(sc, &sc->txq[3]); 369 rt2661_free_tx_ring(sc, &sc->mgtq); 370 rt2661_free_rx_ring(sc, &sc->rxq); 371 372 if_free(ifp); 373 374 lockuninit(&sc->sc_lock); 375 376 return 0; 377 } 378 379 static struct ieee80211vap * 380 rt2661_vap_create(struct ieee80211com *ic, 381 const char name[IFNAMSIZ], int unit, int opmode, int flags, 382 const uint8_t bssid[IEEE80211_ADDR_LEN], 383 const uint8_t mac[IEEE80211_ADDR_LEN]) 384 { 385 struct ifnet *ifp = ic->ic_ifp; 386 struct rt2661_vap *rvp; 387 struct ieee80211vap *vap; 388 389 switch (opmode) { 390 case IEEE80211_M_STA: 391 case IEEE80211_M_IBSS: 392 case IEEE80211_M_AHDEMO: 393 case IEEE80211_M_MONITOR: 394 case IEEE80211_M_HOSTAP: 395 case IEEE80211_M_MBSS: 396 /* XXXRP: TBD */ 397 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 398 if_printf(ifp, "only 1 vap supported\n"); 399 return NULL; 400 } 401 if (opmode == IEEE80211_M_STA) 402 flags |= IEEE80211_CLONE_NOBEACONS; 403 break; 404 case IEEE80211_M_WDS: 405 if (TAILQ_EMPTY(&ic->ic_vaps) || 406 ic->ic_opmode != IEEE80211_M_HOSTAP) { 407 if_printf(ifp, "wds only supported in ap mode\n"); 408 return NULL; 409 } 410 /* 411 * Silently remove any request for a unique 412 * bssid; WDS vap's always share the local 413 * mac address. 414 */ 415 flags &= ~IEEE80211_CLONE_BSSID; 416 break; 417 default: 418 if_printf(ifp, "unknown opmode %d\n", opmode); 419 return NULL; 420 } 421 rvp = (struct rt2661_vap *) kmalloc(sizeof(struct rt2661_vap), 422 M_80211_VAP, M_INTWAIT | M_ZERO); 423 if (rvp == NULL) 424 return NULL; 425 vap = &rvp->ral_vap; 426 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 427 428 /* override state transition machine */ 429 rvp->ral_newstate = vap->iv_newstate; 430 vap->iv_newstate = rt2661_newstate; 431 #if 0 432 vap->iv_update_beacon = rt2661_beacon_update; 433 #endif 434 435 ieee80211_ratectl_init(vap); 436 /* complete setup */ 437 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 438 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 439 ic->ic_opmode = opmode; 440 return vap; 441 } 442 443 static void 444 rt2661_vap_delete(struct ieee80211vap *vap) 445 { 446 struct rt2661_vap *rvp = RT2661_VAP(vap); 447 448 ieee80211_ratectl_deinit(vap); 449 ieee80211_vap_detach(vap); 450 kfree(rvp, M_80211_VAP); 451 } 452 453 void 454 rt2661_shutdown(void *xsc) 455 { 456 struct rt2661_softc *sc = xsc; 457 458 rt2661_stop(sc); 459 } 460 461 void 462 rt2661_suspend(void *xsc) 463 { 464 struct rt2661_softc *sc = xsc; 465 466 rt2661_stop(sc); 467 } 468 469 void 470 rt2661_resume(void *xsc) 471 { 472 struct rt2661_softc *sc = xsc; 473 struct ifnet *ifp = sc->sc_ifp; 474 475 if (ifp->if_flags & IFF_UP) 476 rt2661_init(sc); 477 } 478 479 static void 480 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 481 { 482 if (error != 0) 483 return; 484 485 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 486 487 *(bus_addr_t *)arg = segs[0].ds_addr; 488 } 489 490 static int 491 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 492 int count) 493 { 494 int i, error; 495 496 ring->count = count; 497 ring->queued = 0; 498 ring->cur = ring->next = ring->stat = 0; 499 500 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 501 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 502 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 503 0, &ring->desc_dmat); 504 if (error != 0) { 505 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 506 goto fail; 507 } 508 509 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 510 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 511 if (error != 0) { 512 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 513 goto fail; 514 } 515 516 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 517 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 518 0); 519 if (error != 0) { 520 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 521 goto fail; 522 } 523 524 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 525 M_INTWAIT | M_ZERO); 526 if (ring->data == NULL) { 527 device_printf(sc->sc_dev, "could not allocate soft data\n"); 528 error = ENOMEM; 529 goto fail; 530 } 531 532 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 533 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 534 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 535 if (error != 0) { 536 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 537 goto fail; 538 } 539 540 for (i = 0; i < count; i++) { 541 error = bus_dmamap_create(ring->data_dmat, 0, 542 &ring->data[i].map); 543 if (error != 0) { 544 device_printf(sc->sc_dev, "could not create DMA map\n"); 545 goto fail; 546 } 547 } 548 549 return 0; 550 551 fail: rt2661_free_tx_ring(sc, ring); 552 return error; 553 } 554 555 static void 556 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 557 { 558 struct rt2661_tx_desc *desc; 559 struct rt2661_tx_data *data; 560 int i; 561 562 for (i = 0; i < ring->count; i++) { 563 desc = &ring->desc[i]; 564 data = &ring->data[i]; 565 566 if (data->m != NULL) { 567 bus_dmamap_sync(ring->data_dmat, data->map, 568 BUS_DMASYNC_POSTWRITE); 569 bus_dmamap_unload(ring->data_dmat, data->map); 570 m_freem(data->m); 571 data->m = NULL; 572 } 573 574 if (data->ni != NULL) { 575 ieee80211_free_node(data->ni); 576 data->ni = NULL; 577 } 578 579 desc->flags = 0; 580 } 581 582 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 583 584 ring->queued = 0; 585 ring->cur = ring->next = ring->stat = 0; 586 } 587 588 static void 589 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 590 { 591 struct rt2661_tx_data *data; 592 int i; 593 594 if (ring->desc != NULL) { 595 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 596 BUS_DMASYNC_POSTWRITE); 597 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 598 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 599 } 600 601 if (ring->desc_dmat != NULL) 602 bus_dma_tag_destroy(ring->desc_dmat); 603 604 if (ring->data != NULL) { 605 for (i = 0; i < ring->count; i++) { 606 data = &ring->data[i]; 607 608 if (data->m != NULL) { 609 bus_dmamap_sync(ring->data_dmat, data->map, 610 BUS_DMASYNC_POSTWRITE); 611 bus_dmamap_unload(ring->data_dmat, data->map); 612 m_freem(data->m); 613 } 614 615 if (data->ni != NULL) 616 ieee80211_free_node(data->ni); 617 618 if (data->map != NULL) 619 bus_dmamap_destroy(ring->data_dmat, data->map); 620 } 621 622 kfree(ring->data, M_DEVBUF); 623 } 624 625 if (ring->data_dmat != NULL) 626 bus_dma_tag_destroy(ring->data_dmat); 627 } 628 629 static int 630 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 631 int count) 632 { 633 struct rt2661_rx_desc *desc; 634 struct rt2661_rx_data *data; 635 bus_addr_t physaddr; 636 int i, error; 637 638 ring->count = count; 639 ring->cur = ring->next = 0; 640 641 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 642 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 643 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 644 0, &ring->desc_dmat); 645 if (error != 0) { 646 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 647 goto fail; 648 } 649 650 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 651 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 652 if (error != 0) { 653 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 654 goto fail; 655 } 656 657 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 658 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 659 0); 660 if (error != 0) { 661 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 662 goto fail; 663 } 664 665 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 666 M_INTWAIT | M_ZERO); 667 if (ring->data == NULL) { 668 device_printf(sc->sc_dev, "could not allocate soft data\n"); 669 error = ENOMEM; 670 goto fail; 671 } 672 673 /* 674 * Pre-allocate Rx buffers and populate Rx ring. 675 */ 676 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 677 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 678 1, MCLBYTES, 0, &ring->data_dmat); 679 if (error != 0) { 680 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 681 goto fail; 682 } 683 684 for (i = 0; i < count; i++) { 685 desc = &sc->rxq.desc[i]; 686 data = &sc->rxq.data[i]; 687 688 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 689 if (error != 0) { 690 device_printf(sc->sc_dev, "could not create DMA map\n"); 691 goto fail; 692 } 693 694 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 695 if (data->m == NULL) { 696 device_printf(sc->sc_dev, 697 "could not allocate rx mbuf\n"); 698 error = ENOMEM; 699 goto fail; 700 } 701 702 error = bus_dmamap_load(ring->data_dmat, data->map, 703 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 704 &physaddr, 0); 705 if (error != 0) { 706 device_printf(sc->sc_dev, 707 "could not load rx buf DMA map"); 708 goto fail; 709 } 710 711 desc->flags = htole32(RT2661_RX_BUSY); 712 desc->physaddr = htole32(physaddr); 713 } 714 715 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 716 717 return 0; 718 719 fail: rt2661_free_rx_ring(sc, ring); 720 return error; 721 } 722 723 static void 724 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 725 { 726 int i; 727 728 for (i = 0; i < ring->count; i++) 729 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 730 731 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 732 733 ring->cur = ring->next = 0; 734 } 735 736 static void 737 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 738 { 739 struct rt2661_rx_data *data; 740 int i; 741 742 if (ring->desc != NULL) { 743 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 744 BUS_DMASYNC_POSTWRITE); 745 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 746 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 747 } 748 749 if (ring->desc_dmat != NULL) 750 bus_dma_tag_destroy(ring->desc_dmat); 751 752 if (ring->data != NULL) { 753 for (i = 0; i < ring->count; i++) { 754 data = &ring->data[i]; 755 756 if (data->m != NULL) { 757 bus_dmamap_sync(ring->data_dmat, data->map, 758 BUS_DMASYNC_POSTREAD); 759 bus_dmamap_unload(ring->data_dmat, data->map); 760 m_freem(data->m); 761 } 762 763 if (data->map != NULL) 764 bus_dmamap_destroy(ring->data_dmat, data->map); 765 } 766 767 kfree(ring->data, M_DEVBUF); 768 } 769 770 if (ring->data_dmat != NULL) 771 bus_dma_tag_destroy(ring->data_dmat); 772 } 773 774 static int 775 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 776 { 777 struct rt2661_vap *rvp = RT2661_VAP(vap); 778 struct ieee80211com *ic = vap->iv_ic; 779 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 780 int error; 781 782 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 783 uint32_t tmp; 784 785 /* abort TSF synchronization */ 786 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 787 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 788 } 789 790 error = rvp->ral_newstate(vap, nstate, arg); 791 792 if (error == 0 && nstate == IEEE80211_S_RUN) { 793 struct ieee80211_node *ni = vap->iv_bss; 794 795 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 796 rt2661_enable_mrr(sc); 797 rt2661_set_txpreamble(sc); 798 rt2661_set_basicrates(sc, &ni->ni_rates); 799 rt2661_set_bssid(sc, ni->ni_bssid); 800 } 801 802 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 803 vap->iv_opmode == IEEE80211_M_IBSS || 804 vap->iv_opmode == IEEE80211_M_MBSS) { 805 error = rt2661_prepare_beacon(sc, vap); 806 if (error != 0) 807 return error; 808 } 809 if (vap->iv_opmode != IEEE80211_M_MONITOR) 810 rt2661_enable_tsf_sync(sc); 811 else 812 rt2661_enable_tsf(sc); 813 } 814 return error; 815 } 816 817 /* 818 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 819 * 93C66). 820 */ 821 static uint16_t 822 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 823 { 824 uint32_t tmp; 825 uint16_t val; 826 int n; 827 828 /* clock C once before the first command */ 829 RT2661_EEPROM_CTL(sc, 0); 830 831 RT2661_EEPROM_CTL(sc, RT2661_S); 832 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 833 RT2661_EEPROM_CTL(sc, RT2661_S); 834 835 /* write start bit (1) */ 836 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 837 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 838 839 /* write READ opcode (10) */ 840 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 841 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 842 RT2661_EEPROM_CTL(sc, RT2661_S); 843 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 844 845 /* write address (A5-A0 or A7-A0) */ 846 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 847 for (; n >= 0; n--) { 848 RT2661_EEPROM_CTL(sc, RT2661_S | 849 (((addr >> n) & 1) << RT2661_SHIFT_D)); 850 RT2661_EEPROM_CTL(sc, RT2661_S | 851 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 852 } 853 854 RT2661_EEPROM_CTL(sc, RT2661_S); 855 856 /* read data Q15-Q0 */ 857 val = 0; 858 for (n = 15; n >= 0; n--) { 859 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 860 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 861 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 862 RT2661_EEPROM_CTL(sc, RT2661_S); 863 } 864 865 RT2661_EEPROM_CTL(sc, 0); 866 867 /* clear Chip Select and clock C */ 868 RT2661_EEPROM_CTL(sc, RT2661_S); 869 RT2661_EEPROM_CTL(sc, 0); 870 RT2661_EEPROM_CTL(sc, RT2661_C); 871 872 return val; 873 } 874 875 static void 876 rt2661_tx_intr(struct rt2661_softc *sc) 877 { 878 struct ifnet *ifp = sc->sc_ifp; 879 struct rt2661_tx_ring *txq; 880 struct rt2661_tx_data *data; 881 uint32_t val; 882 int qid, retrycnt; 883 struct ieee80211vap *vap; 884 885 for (;;) { 886 struct ieee80211_node *ni; 887 struct mbuf *m; 888 889 val = RAL_READ(sc, RT2661_STA_CSR4); 890 if (!(val & RT2661_TX_STAT_VALID)) 891 break; 892 893 /* retrieve the queue in which this frame was sent */ 894 qid = RT2661_TX_QID(val); 895 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 896 897 /* retrieve rate control algorithm context */ 898 data = &txq->data[txq->stat]; 899 m = data->m; 900 data->m = NULL; 901 ni = data->ni; 902 data->ni = NULL; 903 vap = ni->ni_vap; 904 905 /* if no frame has been sent, ignore */ 906 if (ni == NULL) 907 continue; 908 909 switch (RT2661_TX_RESULT(val)) { 910 case RT2661_TX_SUCCESS: 911 retrycnt = RT2661_TX_RETRYCNT(val); 912 913 DPRINTFN(sc, 10, "data frame sent successfully after " 914 "%d retries\n", retrycnt); 915 if (data->rix != IEEE80211_FIXED_RATE_NONE) 916 ieee80211_ratectl_tx_complete(vap, ni, 917 IEEE80211_RATECTL_TX_SUCCESS, 918 &retrycnt, NULL); 919 ifp->if_opackets++; 920 break; 921 922 case RT2661_TX_RETRY_FAIL: 923 retrycnt = RT2661_TX_RETRYCNT(val); 924 925 DPRINTFN(sc, 9, "%s\n", 926 "sending data frame failed (too much retries)"); 927 if (data->rix != IEEE80211_FIXED_RATE_NONE) 928 ieee80211_ratectl_tx_complete(vap, ni, 929 IEEE80211_RATECTL_TX_FAILURE, 930 &retrycnt, NULL); 931 ifp->if_oerrors++; 932 break; 933 934 default: 935 /* other failure */ 936 device_printf(sc->sc_dev, 937 "sending data frame failed 0x%08x\n", val); 938 ifp->if_oerrors++; 939 } 940 941 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 942 943 txq->queued--; 944 if (++txq->stat >= txq->count) /* faster than % count */ 945 txq->stat = 0; 946 947 if (m->m_flags & M_TXCB) 948 ieee80211_process_callback(ni, m, 949 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 950 m_freem(m); 951 ieee80211_free_node(ni); 952 } 953 954 sc->sc_tx_timer = 0; 955 ifp->if_flags &= ~IFF_OACTIVE; 956 957 rt2661_start_locked(ifp); 958 } 959 960 static void 961 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 962 { 963 struct rt2661_tx_desc *desc; 964 struct rt2661_tx_data *data; 965 966 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 967 968 for (;;) { 969 desc = &txq->desc[txq->next]; 970 data = &txq->data[txq->next]; 971 972 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 973 !(le32toh(desc->flags) & RT2661_TX_VALID)) 974 break; 975 976 bus_dmamap_sync(txq->data_dmat, data->map, 977 BUS_DMASYNC_POSTWRITE); 978 bus_dmamap_unload(txq->data_dmat, data->map); 979 980 /* descriptor is no longer valid */ 981 desc->flags &= ~htole32(RT2661_TX_VALID); 982 983 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 984 985 if (++txq->next >= txq->count) /* faster than % count */ 986 txq->next = 0; 987 } 988 989 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 990 } 991 992 static void 993 rt2661_rx_intr(struct rt2661_softc *sc) 994 { 995 struct ifnet *ifp = sc->sc_ifp; 996 struct ieee80211com *ic = ifp->if_l2com; 997 struct rt2661_rx_desc *desc; 998 struct rt2661_rx_data *data; 999 bus_addr_t physaddr; 1000 struct ieee80211_frame *wh; 1001 struct ieee80211_node *ni; 1002 struct mbuf *mnew, *m; 1003 int error; 1004 1005 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1006 BUS_DMASYNC_POSTREAD); 1007 1008 for (;;) { 1009 int8_t rssi, nf; 1010 1011 desc = &sc->rxq.desc[sc->rxq.cur]; 1012 data = &sc->rxq.data[sc->rxq.cur]; 1013 1014 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1015 break; 1016 1017 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1018 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1019 /* 1020 * This should not happen since we did not request 1021 * to receive those frames when we filled TXRX_CSR0. 1022 */ 1023 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1024 le32toh(desc->flags)); 1025 ifp->if_ierrors++; 1026 goto skip; 1027 } 1028 1029 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1030 ifp->if_ierrors++; 1031 goto skip; 1032 } 1033 1034 /* 1035 * Try to allocate a new mbuf for this ring element and load it 1036 * before processing the current mbuf. If the ring element 1037 * cannot be loaded, drop the received packet and reuse the old 1038 * mbuf. In the unlikely case that the old mbuf can't be 1039 * reloaded either, explicitly panic. 1040 */ 1041 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1042 if (mnew == NULL) { 1043 ifp->if_ierrors++; 1044 goto skip; 1045 } 1046 1047 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1048 BUS_DMASYNC_POSTREAD); 1049 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1050 1051 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1052 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1053 &physaddr, 0); 1054 if (error != 0) { 1055 m_freem(mnew); 1056 1057 /* try to reload the old mbuf */ 1058 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1059 mtod(data->m, void *), MCLBYTES, 1060 rt2661_dma_map_addr, &physaddr, 0); 1061 if (error != 0) { 1062 /* very unlikely that it will fail... */ 1063 panic("%s: could not load old rx mbuf", 1064 device_get_name(sc->sc_dev)); 1065 } 1066 ifp->if_ierrors++; 1067 goto skip; 1068 } 1069 1070 /* 1071 * New mbuf successfully loaded, update Rx ring and continue 1072 * processing. 1073 */ 1074 m = data->m; 1075 data->m = mnew; 1076 desc->physaddr = htole32(physaddr); 1077 1078 /* finalize mbuf */ 1079 m->m_pkthdr.rcvif = ifp; 1080 m->m_pkthdr.len = m->m_len = 1081 (le32toh(desc->flags) >> 16) & 0xfff; 1082 1083 rssi = rt2661_get_rssi(sc, desc->rssi); 1084 /* Error happened during RSSI conversion. */ 1085 if (rssi < 0) 1086 rssi = -30; /* XXX ignored by net80211 */ 1087 nf = RT2661_NOISE_FLOOR; 1088 1089 if (ieee80211_radiotap_active(ic)) { 1090 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1091 uint32_t tsf_lo, tsf_hi; 1092 1093 /* get timestamp (low and high 32 bits) */ 1094 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1095 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1096 1097 tap->wr_tsf = 1098 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1099 tap->wr_flags = 0; 1100 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1101 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1102 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1103 tap->wr_antsignal = nf + rssi; 1104 tap->wr_antnoise = nf; 1105 } 1106 sc->sc_flags |= RAL_INPUT_RUNNING; 1107 RAL_UNLOCK(sc); 1108 wh = mtod(m, struct ieee80211_frame *); 1109 1110 /* send the frame to the 802.11 layer */ 1111 ni = ieee80211_find_rxnode(ic, 1112 (struct ieee80211_frame_min *)wh); 1113 if (ni != NULL) { 1114 (void) ieee80211_input(ni, m, rssi, nf); 1115 ieee80211_free_node(ni); 1116 } else 1117 (void) ieee80211_input_all(ic, m, rssi, nf); 1118 1119 RAL_LOCK(sc); 1120 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1121 1122 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1123 1124 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1125 1126 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1127 } 1128 1129 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1130 BUS_DMASYNC_PREWRITE); 1131 } 1132 1133 /* ARGSUSED */ 1134 static void 1135 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1136 { 1137 /* do nothing */ 1138 } 1139 1140 static void 1141 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1142 { 1143 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1144 1145 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1146 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1147 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1148 1149 /* send wakeup command to MCU */ 1150 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1151 } 1152 1153 static void 1154 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1155 { 1156 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1157 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1158 } 1159 1160 void 1161 rt2661_intr(void *arg) 1162 { 1163 struct rt2661_softc *sc = arg; 1164 struct ifnet *ifp = sc->sc_ifp; 1165 uint32_t r1, r2; 1166 1167 RAL_LOCK(sc); 1168 1169 /* disable MAC and MCU interrupts */ 1170 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1171 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1172 1173 /* don't re-enable interrupts if we're shutting down */ 1174 if (!(ifp->if_flags & IFF_RUNNING)) { 1175 RAL_UNLOCK(sc); 1176 return; 1177 } 1178 1179 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1180 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1181 1182 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1183 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1184 1185 if (r1 & RT2661_MGT_DONE) 1186 rt2661_tx_dma_intr(sc, &sc->mgtq); 1187 1188 if (r1 & RT2661_RX_DONE) 1189 rt2661_rx_intr(sc); 1190 1191 if (r1 & RT2661_TX0_DMA_DONE) 1192 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1193 1194 if (r1 & RT2661_TX1_DMA_DONE) 1195 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1196 1197 if (r1 & RT2661_TX2_DMA_DONE) 1198 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1199 1200 if (r1 & RT2661_TX3_DMA_DONE) 1201 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1202 1203 if (r1 & RT2661_TX_DONE) 1204 rt2661_tx_intr(sc); 1205 1206 if (r2 & RT2661_MCU_CMD_DONE) 1207 rt2661_mcu_cmd_intr(sc); 1208 1209 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1210 rt2661_mcu_beacon_expire(sc); 1211 1212 if (r2 & RT2661_MCU_WAKEUP) 1213 rt2661_mcu_wakeup(sc); 1214 1215 /* re-enable MAC and MCU interrupts */ 1216 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1217 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1218 1219 RAL_UNLOCK(sc); 1220 } 1221 1222 static uint8_t 1223 rt2661_plcp_signal(int rate) 1224 { 1225 switch (rate) { 1226 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1227 case 12: return 0xb; 1228 case 18: return 0xf; 1229 case 24: return 0xa; 1230 case 36: return 0xe; 1231 case 48: return 0x9; 1232 case 72: return 0xd; 1233 case 96: return 0x8; 1234 case 108: return 0xc; 1235 1236 /* CCK rates (NB: not IEEE std, device-specific) */ 1237 case 2: return 0x0; 1238 case 4: return 0x1; 1239 case 11: return 0x2; 1240 case 22: return 0x3; 1241 } 1242 return 0xff; /* XXX unsupported/unknown rate */ 1243 } 1244 1245 static void 1246 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1247 uint32_t flags, uint16_t xflags, int len, int rate, 1248 const bus_dma_segment_t *segs, int nsegs, int ac) 1249 { 1250 struct ifnet *ifp = sc->sc_ifp; 1251 struct ieee80211com *ic = ifp->if_l2com; 1252 uint16_t plcp_length; 1253 int i, remainder; 1254 1255 desc->flags = htole32(flags); 1256 desc->flags |= htole32(len << 16); 1257 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1258 1259 desc->xflags = htole16(xflags); 1260 desc->xflags |= htole16(nsegs << 13); 1261 1262 desc->wme = htole16( 1263 RT2661_QID(ac) | 1264 RT2661_AIFSN(2) | 1265 RT2661_LOGCWMIN(4) | 1266 RT2661_LOGCWMAX(10)); 1267 1268 /* 1269 * Remember in which queue this frame was sent. This field is driver 1270 * private data only. It will be made available by the NIC in STA_CSR4 1271 * on Tx interrupts. 1272 */ 1273 desc->qid = ac; 1274 1275 /* setup PLCP fields */ 1276 desc->plcp_signal = rt2661_plcp_signal(rate); 1277 desc->plcp_service = 4; 1278 1279 len += IEEE80211_CRC_LEN; 1280 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1281 desc->flags |= htole32(RT2661_TX_OFDM); 1282 1283 plcp_length = len & 0xfff; 1284 desc->plcp_length_hi = plcp_length >> 6; 1285 desc->plcp_length_lo = plcp_length & 0x3f; 1286 } else { 1287 plcp_length = (16 * len + rate - 1) / rate; 1288 if (rate == 22) { 1289 remainder = (16 * len) % 22; 1290 if (remainder != 0 && remainder < 7) 1291 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1292 } 1293 desc->plcp_length_hi = plcp_length >> 8; 1294 desc->plcp_length_lo = plcp_length & 0xff; 1295 1296 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1297 desc->plcp_signal |= 0x08; 1298 } 1299 1300 /* RT2x61 supports scatter with up to 5 segments */ 1301 for (i = 0; i < nsegs; i++) { 1302 desc->addr[i] = htole32(segs[i].ds_addr); 1303 desc->len [i] = htole16(segs[i].ds_len); 1304 } 1305 } 1306 1307 static int 1308 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1309 struct ieee80211_node *ni) 1310 { 1311 struct ieee80211vap *vap = ni->ni_vap; 1312 struct ieee80211com *ic = ni->ni_ic; 1313 struct rt2661_tx_desc *desc; 1314 struct rt2661_tx_data *data; 1315 struct ieee80211_frame *wh; 1316 struct ieee80211_key *k; 1317 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1318 uint16_t dur; 1319 uint32_t flags = 0; /* XXX HWSEQ */ 1320 int nsegs, rate, error; 1321 1322 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1323 data = &sc->mgtq.data[sc->mgtq.cur]; 1324 1325 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1326 1327 wh = mtod(m0, struct ieee80211_frame *); 1328 1329 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1330 k = ieee80211_crypto_encap(ni, m0); 1331 if (k == NULL) { 1332 m_freem(m0); 1333 return ENOBUFS; 1334 } 1335 } 1336 1337 error = bus_dmamap_load_mbuf_segment(sc->mgtq.data_dmat, data->map, m0, 1338 segs, 1, &nsegs, 0); 1339 if (error != 0) { 1340 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1341 error); 1342 m_freem(m0); 1343 return error; 1344 } 1345 1346 if (ieee80211_radiotap_active_vap(vap)) { 1347 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1348 1349 tap->wt_flags = 0; 1350 tap->wt_rate = rate; 1351 1352 ieee80211_radiotap_tx(vap, m0); 1353 } 1354 1355 data->m = m0; 1356 data->ni = ni; 1357 /* management frames are not taken into account for amrr */ 1358 data->rix = IEEE80211_FIXED_RATE_NONE; 1359 1360 wh = mtod(m0, struct ieee80211_frame *); 1361 1362 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1363 flags |= RT2661_TX_NEED_ACK; 1364 1365 dur = ieee80211_ack_duration(ic->ic_rt, 1366 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1367 *(uint16_t *)wh->i_dur = htole16(dur); 1368 1369 /* tell hardware to add timestamp in probe responses */ 1370 if ((wh->i_fc[0] & 1371 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1372 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1373 flags |= RT2661_TX_TIMESTAMP; 1374 } 1375 1376 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1377 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1378 1379 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1380 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1381 BUS_DMASYNC_PREWRITE); 1382 1383 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1384 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1385 1386 /* kick mgt */ 1387 sc->mgtq.queued++; 1388 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1389 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1390 1391 return 0; 1392 } 1393 1394 static int 1395 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1396 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1397 { 1398 struct ieee80211com *ic = ni->ni_ic; 1399 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1400 const struct ieee80211_frame *wh; 1401 struct rt2661_tx_desc *desc; 1402 struct rt2661_tx_data *data; 1403 struct mbuf *mprot; 1404 int protrate, ackrate, pktlen, flags, isshort, error; 1405 uint16_t dur; 1406 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1407 int nsegs; 1408 1409 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1410 ("protection %d", prot)); 1411 1412 wh = mtod(m, const struct ieee80211_frame *); 1413 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1414 1415 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1416 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1417 1418 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1419 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1420 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1421 flags = RT2661_TX_MORE_FRAG; 1422 if (prot == IEEE80211_PROT_RTSCTS) { 1423 /* NB: CTS is the same size as an ACK */ 1424 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1425 flags |= RT2661_TX_NEED_ACK; 1426 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1427 } else { 1428 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1429 } 1430 if (mprot == NULL) { 1431 /* XXX stat + msg */ 1432 return ENOBUFS; 1433 } 1434 1435 data = &txq->data[txq->cur]; 1436 desc = &txq->desc[txq->cur]; 1437 1438 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, mprot, segs, 1439 1, &nsegs, 0); 1440 if (error != 0) { 1441 device_printf(sc->sc_dev, 1442 "could not map mbuf (error %d)\n", error); 1443 m_freem(mprot); 1444 return error; 1445 } 1446 1447 data->m = mprot; 1448 data->ni = ieee80211_ref_node(ni); 1449 /* ctl frames are not taken into account for amrr */ 1450 data->rix = IEEE80211_FIXED_RATE_NONE; 1451 1452 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1453 protrate, segs, 1, ac); 1454 1455 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1456 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1457 1458 txq->queued++; 1459 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1460 1461 return 0; 1462 } 1463 1464 static int 1465 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1466 struct ieee80211_node *ni, int ac) 1467 { 1468 struct ieee80211vap *vap = ni->ni_vap; 1469 struct ifnet *ifp = sc->sc_ifp; 1470 struct ieee80211com *ic = ifp->if_l2com; 1471 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1472 struct rt2661_tx_desc *desc; 1473 struct rt2661_tx_data *data; 1474 struct ieee80211_frame *wh; 1475 const struct ieee80211_txparam *tp; 1476 struct ieee80211_key *k; 1477 const struct chanAccParams *cap; 1478 struct mbuf *mnew; 1479 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1480 uint16_t dur; 1481 uint32_t flags; 1482 int error, nsegs, rate, noack = 0; 1483 1484 wh = mtod(m0, struct ieee80211_frame *); 1485 1486 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1487 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1488 rate = tp->mcastrate; 1489 } else if (m0->m_flags & M_EAPOL) { 1490 rate = tp->mgmtrate; 1491 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1492 rate = tp->ucastrate; 1493 } else { 1494 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1495 rate = ni->ni_txrate; 1496 } 1497 rate &= IEEE80211_RATE_VAL; 1498 1499 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1500 cap = &ic->ic_wme.wme_chanParams; 1501 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1502 } 1503 1504 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1505 k = ieee80211_crypto_encap(ni, m0); 1506 if (k == NULL) { 1507 m_freem(m0); 1508 return ENOBUFS; 1509 } 1510 1511 /* packet header may have moved, reset our local pointer */ 1512 wh = mtod(m0, struct ieee80211_frame *); 1513 } 1514 1515 flags = 0; 1516 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1517 int prot = IEEE80211_PROT_NONE; 1518 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1519 prot = IEEE80211_PROT_RTSCTS; 1520 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1521 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1522 prot = ic->ic_protmode; 1523 if (prot != IEEE80211_PROT_NONE) { 1524 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1525 if (error) { 1526 m_freem(m0); 1527 return error; 1528 } 1529 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1530 } 1531 } 1532 1533 data = &txq->data[txq->cur]; 1534 desc = &txq->desc[txq->cur]; 1535 1536 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, segs, 1537 1, &nsegs, 0); 1538 if (error != 0 && error != EFBIG) { 1539 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1540 error); 1541 m_freem(m0); 1542 return error; 1543 } 1544 if (error != 0) { 1545 mnew = m_defrag(m0, MB_DONTWAIT); 1546 if (mnew == NULL) { 1547 device_printf(sc->sc_dev, 1548 "could not defragment mbuf\n"); 1549 m_freem(m0); 1550 return ENOBUFS; 1551 } 1552 m0 = mnew; 1553 1554 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, 1555 segs, 1, &nsegs, 0); 1556 if (error != 0) { 1557 device_printf(sc->sc_dev, 1558 "could not map mbuf (error %d)\n", error); 1559 m_freem(m0); 1560 return error; 1561 } 1562 1563 /* packet header have moved, reset our local pointer */ 1564 wh = mtod(m0, struct ieee80211_frame *); 1565 } 1566 1567 if (ieee80211_radiotap_active_vap(vap)) { 1568 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1569 1570 tap->wt_flags = 0; 1571 tap->wt_rate = rate; 1572 1573 ieee80211_radiotap_tx(vap, m0); 1574 } 1575 1576 data->m = m0; 1577 data->ni = ni; 1578 1579 /* remember link conditions for rate adaptation algorithm */ 1580 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1581 data->rix = ni->ni_txrate; 1582 /* XXX probably need last rssi value and not avg */ 1583 data->rssi = ic->ic_node_getrssi(ni); 1584 } else 1585 data->rix = IEEE80211_FIXED_RATE_NONE; 1586 1587 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1588 flags |= RT2661_TX_NEED_ACK; 1589 1590 dur = ieee80211_ack_duration(ic->ic_rt, 1591 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1592 *(uint16_t *)wh->i_dur = htole16(dur); 1593 } 1594 1595 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1596 nsegs, ac); 1597 1598 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1599 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1600 1601 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1602 m0->m_pkthdr.len, txq->cur, rate); 1603 1604 /* kick Tx */ 1605 txq->queued++; 1606 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1607 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1608 1609 return 0; 1610 } 1611 1612 static void 1613 rt2661_start_locked(struct ifnet *ifp) 1614 { 1615 struct rt2661_softc *sc = ifp->if_softc; 1616 struct mbuf *m; 1617 struct ieee80211_node *ni; 1618 int ac; 1619 1620 RAL_LOCK_ASSERT(sc); 1621 1622 /* prevent management frames from being sent if we're not ready */ 1623 if (!(ifp->if_flags & IFF_RUNNING) || sc->sc_invalid) 1624 return; 1625 1626 for (;;) { 1627 IF_DEQUEUE(&ifp->if_snd, m); 1628 if (m == NULL) 1629 break; 1630 1631 ac = M_WME_GETAC(m); 1632 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1633 /* there is no place left in this ring */ 1634 IF_PREPEND(&ifp->if_snd, m); 1635 ifp->if_flags |= IFF_OACTIVE; 1636 break; 1637 } 1638 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1639 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1640 ieee80211_free_node(ni); 1641 ifp->if_oerrors++; 1642 break; 1643 } 1644 1645 sc->sc_tx_timer = 5; 1646 } 1647 } 1648 1649 static void 1650 rt2661_start(struct ifnet *ifp) 1651 { 1652 struct rt2661_softc *sc = ifp->if_softc; 1653 1654 RAL_LOCK(sc); 1655 rt2661_start_locked(ifp); 1656 RAL_UNLOCK(sc); 1657 } 1658 1659 static int 1660 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1661 const struct ieee80211_bpf_params *params) 1662 { 1663 struct ieee80211com *ic = ni->ni_ic; 1664 struct ifnet *ifp = ic->ic_ifp; 1665 struct rt2661_softc *sc = ifp->if_softc; 1666 1667 RAL_LOCK(sc); 1668 1669 /* prevent management frames from being sent if we're not ready */ 1670 if (!(ifp->if_flags & IFF_RUNNING)) { 1671 RAL_UNLOCK(sc); 1672 m_freem(m); 1673 ieee80211_free_node(ni); 1674 return ENETDOWN; 1675 } 1676 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1677 ifp->if_flags |= IFF_OACTIVE; 1678 RAL_UNLOCK(sc); 1679 m_freem(m); 1680 ieee80211_free_node(ni); 1681 return ENOBUFS; /* XXX */ 1682 } 1683 1684 ifp->if_opackets++; 1685 1686 /* 1687 * Legacy path; interpret frame contents to decide 1688 * precisely how to send the frame. 1689 * XXX raw path 1690 */ 1691 if (rt2661_tx_mgt(sc, m, ni) != 0) 1692 goto bad; 1693 sc->sc_tx_timer = 5; 1694 1695 RAL_UNLOCK(sc); 1696 1697 return 0; 1698 bad: 1699 ifp->if_oerrors++; 1700 ieee80211_free_node(ni); 1701 RAL_UNLOCK(sc); 1702 return EIO; /* XXX */ 1703 } 1704 1705 static void 1706 rt2661_watchdog(void *arg) 1707 { 1708 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1709 struct ifnet *ifp = sc->sc_ifp; 1710 1711 RAL_LOCK(sc); 1712 1713 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running")); 1714 1715 if (sc->sc_invalid) /* card ejected */ 1716 return; 1717 1718 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1719 if_printf(ifp, "device timeout\n"); 1720 rt2661_init_locked(sc); 1721 ifp->if_oerrors++; 1722 /* NB: callout is reset in rt2661_init() */ 1723 return; 1724 } 1725 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1726 1727 RAL_UNLOCK(sc); 1728 } 1729 1730 static int 1731 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 1732 { 1733 struct rt2661_softc *sc = ifp->if_softc; 1734 struct ieee80211com *ic = ifp->if_l2com; 1735 struct ifreq *ifr = (struct ifreq *) data; 1736 int error = 0, startall = 0; 1737 1738 switch (cmd) { 1739 case SIOCSIFFLAGS: 1740 RAL_LOCK(sc); 1741 if (ifp->if_flags & IFF_UP) { 1742 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1743 rt2661_init_locked(sc); 1744 startall = 1; 1745 } else 1746 rt2661_update_promisc(ifp); 1747 } else { 1748 if (ifp->if_flags & IFF_RUNNING) 1749 rt2661_stop_locked(sc); 1750 } 1751 RAL_UNLOCK(sc); 1752 if (startall) 1753 ieee80211_start_all(ic); 1754 break; 1755 case SIOCGIFMEDIA: 1756 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1757 break; 1758 case SIOCGIFADDR: 1759 error = ether_ioctl(ifp, cmd, data); 1760 break; 1761 default: 1762 error = EINVAL; 1763 break; 1764 } 1765 return error; 1766 } 1767 1768 static void 1769 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1770 { 1771 uint32_t tmp; 1772 int ntries; 1773 1774 for (ntries = 0; ntries < 100; ntries++) { 1775 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1776 break; 1777 DELAY(1); 1778 } 1779 if (ntries == 100) { 1780 device_printf(sc->sc_dev, "could not write to BBP\n"); 1781 return; 1782 } 1783 1784 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1785 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1786 1787 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1788 } 1789 1790 static uint8_t 1791 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1792 { 1793 uint32_t val; 1794 int ntries; 1795 1796 for (ntries = 0; ntries < 100; ntries++) { 1797 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1798 break; 1799 DELAY(1); 1800 } 1801 if (ntries == 100) { 1802 device_printf(sc->sc_dev, "could not read from BBP\n"); 1803 return 0; 1804 } 1805 1806 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1807 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1808 1809 for (ntries = 0; ntries < 100; ntries++) { 1810 val = RAL_READ(sc, RT2661_PHY_CSR3); 1811 if (!(val & RT2661_BBP_BUSY)) 1812 return val & 0xff; 1813 DELAY(1); 1814 } 1815 1816 device_printf(sc->sc_dev, "could not read from BBP\n"); 1817 return 0; 1818 } 1819 1820 static void 1821 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1822 { 1823 uint32_t tmp; 1824 int ntries; 1825 1826 for (ntries = 0; ntries < 100; ntries++) { 1827 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1828 break; 1829 DELAY(1); 1830 } 1831 if (ntries == 100) { 1832 device_printf(sc->sc_dev, "could not write to RF\n"); 1833 return; 1834 } 1835 1836 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1837 (reg & 3); 1838 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1839 1840 /* remember last written value in sc */ 1841 sc->rf_regs[reg] = val; 1842 1843 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1844 } 1845 1846 static int 1847 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1848 { 1849 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1850 return EIO; /* there is already a command pending */ 1851 1852 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1853 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1854 1855 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1856 1857 return 0; 1858 } 1859 1860 static void 1861 rt2661_select_antenna(struct rt2661_softc *sc) 1862 { 1863 uint8_t bbp4, bbp77; 1864 uint32_t tmp; 1865 1866 bbp4 = rt2661_bbp_read(sc, 4); 1867 bbp77 = rt2661_bbp_read(sc, 77); 1868 1869 /* TBD */ 1870 1871 /* make sure Rx is disabled before switching antenna */ 1872 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1873 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1874 1875 rt2661_bbp_write(sc, 4, bbp4); 1876 rt2661_bbp_write(sc, 77, bbp77); 1877 1878 /* restore Rx filter */ 1879 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1880 } 1881 1882 /* 1883 * Enable multi-rate retries for frames sent at OFDM rates. 1884 * In 802.11b/g mode, allow fallback to CCK rates. 1885 */ 1886 static void 1887 rt2661_enable_mrr(struct rt2661_softc *sc) 1888 { 1889 struct ifnet *ifp = sc->sc_ifp; 1890 struct ieee80211com *ic = ifp->if_l2com; 1891 uint32_t tmp; 1892 1893 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1894 1895 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1896 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1897 tmp |= RT2661_MRR_CCK_FALLBACK; 1898 tmp |= RT2661_MRR_ENABLED; 1899 1900 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1901 } 1902 1903 static void 1904 rt2661_set_txpreamble(struct rt2661_softc *sc) 1905 { 1906 struct ifnet *ifp = sc->sc_ifp; 1907 struct ieee80211com *ic = ifp->if_l2com; 1908 uint32_t tmp; 1909 1910 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1911 1912 tmp &= ~RT2661_SHORT_PREAMBLE; 1913 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1914 tmp |= RT2661_SHORT_PREAMBLE; 1915 1916 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1917 } 1918 1919 static void 1920 rt2661_set_basicrates(struct rt2661_softc *sc, 1921 const struct ieee80211_rateset *rs) 1922 { 1923 #define RV(r) ((r) & IEEE80211_RATE_VAL) 1924 struct ifnet *ifp = sc->sc_ifp; 1925 struct ieee80211com *ic = ifp->if_l2com; 1926 uint32_t mask = 0; 1927 uint8_t rate; 1928 int i, j; 1929 1930 for (i = 0; i < rs->rs_nrates; i++) { 1931 rate = rs->rs_rates[i]; 1932 1933 if (!(rate & IEEE80211_RATE_BASIC)) 1934 continue; 1935 1936 /* 1937 * Find h/w rate index. We know it exists because the rate 1938 * set has already been negotiated. 1939 */ 1940 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1941 1942 mask |= 1 << j; 1943 } 1944 1945 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1946 1947 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1948 #undef RV 1949 } 1950 1951 /* 1952 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1953 * driver. 1954 */ 1955 static void 1956 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1957 { 1958 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1959 uint32_t tmp; 1960 1961 /* update all BBP registers that depend on the band */ 1962 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1963 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1964 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1965 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1966 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1967 } 1968 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1969 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1970 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1971 } 1972 1973 rt2661_bbp_write(sc, 17, bbp17); 1974 rt2661_bbp_write(sc, 96, bbp96); 1975 rt2661_bbp_write(sc, 104, bbp104); 1976 1977 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1978 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1979 rt2661_bbp_write(sc, 75, 0x80); 1980 rt2661_bbp_write(sc, 86, 0x80); 1981 rt2661_bbp_write(sc, 88, 0x80); 1982 } 1983 1984 rt2661_bbp_write(sc, 35, bbp35); 1985 rt2661_bbp_write(sc, 97, bbp97); 1986 rt2661_bbp_write(sc, 98, bbp98); 1987 1988 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1989 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1990 if (IEEE80211_IS_CHAN_2GHZ(c)) 1991 tmp |= RT2661_PA_PE_2GHZ; 1992 else 1993 tmp |= RT2661_PA_PE_5GHZ; 1994 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1995 } 1996 1997 static void 1998 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1999 { 2000 struct ifnet *ifp = sc->sc_ifp; 2001 struct ieee80211com *ic = ifp->if_l2com; 2002 const struct rfprog *rfprog; 2003 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2004 int8_t power; 2005 u_int i, chan; 2006 2007 chan = ieee80211_chan2ieee(ic, c); 2008 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2009 2010 /* select the appropriate RF settings based on what EEPROM says */ 2011 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2012 2013 /* find the settings for this channel (we know it exists) */ 2014 for (i = 0; rfprog[i].chan != chan; i++); 2015 2016 power = sc->txpow[i]; 2017 if (power < 0) { 2018 bbp94 += power; 2019 power = 0; 2020 } else if (power > 31) { 2021 bbp94 += power - 31; 2022 power = 31; 2023 } 2024 2025 /* 2026 * If we are switching from the 2GHz band to the 5GHz band or 2027 * vice-versa, BBP registers need to be reprogrammed. 2028 */ 2029 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2030 rt2661_select_band(sc, c); 2031 rt2661_select_antenna(sc); 2032 } 2033 sc->sc_curchan = c; 2034 2035 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2036 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2037 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2038 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2039 2040 DELAY(200); 2041 2042 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2043 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2044 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2045 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2046 2047 DELAY(200); 2048 2049 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2050 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2051 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2052 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2053 2054 /* enable smart mode for MIMO-capable RFs */ 2055 bbp3 = rt2661_bbp_read(sc, 3); 2056 2057 bbp3 &= ~RT2661_SMART_MODE; 2058 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2059 bbp3 |= RT2661_SMART_MODE; 2060 2061 rt2661_bbp_write(sc, 3, bbp3); 2062 2063 if (bbp94 != RT2661_BBPR94_DEFAULT) 2064 rt2661_bbp_write(sc, 94, bbp94); 2065 2066 /* 5GHz radio needs a 1ms delay here */ 2067 if (IEEE80211_IS_CHAN_5GHZ(c)) 2068 DELAY(1000); 2069 } 2070 2071 static void 2072 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2073 { 2074 uint32_t tmp; 2075 2076 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2077 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2078 2079 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2080 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2081 } 2082 2083 static void 2084 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2085 { 2086 uint32_t tmp; 2087 2088 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2089 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2090 2091 tmp = addr[4] | addr[5] << 8; 2092 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2093 } 2094 2095 static void 2096 rt2661_update_promisc(struct ifnet *ifp) 2097 { 2098 struct rt2661_softc *sc = ifp->if_softc; 2099 uint32_t tmp; 2100 2101 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2102 2103 tmp &= ~RT2661_DROP_NOT_TO_ME; 2104 if (!(ifp->if_flags & IFF_PROMISC)) 2105 tmp |= RT2661_DROP_NOT_TO_ME; 2106 2107 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2108 2109 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2110 "entering" : "leaving"); 2111 } 2112 2113 /* 2114 * Update QoS (802.11e) settings for each h/w Tx ring. 2115 */ 2116 static int 2117 rt2661_wme_update(struct ieee80211com *ic) 2118 { 2119 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2120 const struct wmeParams *wmep; 2121 2122 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2123 2124 /* XXX: not sure about shifts. */ 2125 /* XXX: the reference driver plays with AC_VI settings too. */ 2126 2127 /* update TxOp */ 2128 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2129 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2130 wmep[WME_AC_BK].wmep_txopLimit); 2131 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2132 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2133 wmep[WME_AC_VO].wmep_txopLimit); 2134 2135 /* update CWmin */ 2136 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2137 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2138 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2139 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2140 wmep[WME_AC_VO].wmep_logcwmin); 2141 2142 /* update CWmax */ 2143 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2144 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2145 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2146 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2147 wmep[WME_AC_VO].wmep_logcwmax); 2148 2149 /* update Aifsn */ 2150 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2151 wmep[WME_AC_BE].wmep_aifsn << 12 | 2152 wmep[WME_AC_BK].wmep_aifsn << 8 | 2153 wmep[WME_AC_VI].wmep_aifsn << 4 | 2154 wmep[WME_AC_VO].wmep_aifsn); 2155 2156 return 0; 2157 } 2158 2159 static void 2160 rt2661_update_slot(struct ifnet *ifp) 2161 { 2162 struct rt2661_softc *sc = ifp->if_softc; 2163 struct ieee80211com *ic = ifp->if_l2com; 2164 uint8_t slottime; 2165 uint32_t tmp; 2166 2167 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2168 2169 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2170 tmp = (tmp & ~0xff) | slottime; 2171 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2172 } 2173 2174 static const char * 2175 rt2661_get_rf(int rev) 2176 { 2177 switch (rev) { 2178 case RT2661_RF_5225: return "RT5225"; 2179 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2180 case RT2661_RF_2527: return "RT2527"; 2181 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2182 default: return "unknown"; 2183 } 2184 } 2185 2186 static void 2187 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2188 { 2189 uint16_t val; 2190 int i; 2191 2192 /* read MAC address */ 2193 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2194 macaddr[0] = val & 0xff; 2195 macaddr[1] = val >> 8; 2196 2197 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2198 macaddr[2] = val & 0xff; 2199 macaddr[3] = val >> 8; 2200 2201 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2202 macaddr[4] = val & 0xff; 2203 macaddr[5] = val >> 8; 2204 2205 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2206 /* XXX: test if different from 0xffff? */ 2207 sc->rf_rev = (val >> 11) & 0x1f; 2208 sc->hw_radio = (val >> 10) & 0x1; 2209 sc->rx_ant = (val >> 4) & 0x3; 2210 sc->tx_ant = (val >> 2) & 0x3; 2211 sc->nb_ant = val & 0x3; 2212 2213 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2214 2215 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2216 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2217 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2218 2219 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2220 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2221 2222 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2223 if ((val & 0xff) != 0xff) 2224 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2225 2226 /* Only [-10, 10] is valid */ 2227 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2228 sc->rssi_2ghz_corr = 0; 2229 2230 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2231 if ((val & 0xff) != 0xff) 2232 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2233 2234 /* Only [-10, 10] is valid */ 2235 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2236 sc->rssi_5ghz_corr = 0; 2237 2238 /* adjust RSSI correction for external low-noise amplifier */ 2239 if (sc->ext_2ghz_lna) 2240 sc->rssi_2ghz_corr -= 14; 2241 if (sc->ext_5ghz_lna) 2242 sc->rssi_5ghz_corr -= 14; 2243 2244 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2245 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2246 2247 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2248 if ((val >> 8) != 0xff) 2249 sc->rfprog = (val >> 8) & 0x3; 2250 if ((val & 0xff) != 0xff) 2251 sc->rffreq = val & 0xff; 2252 2253 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2254 2255 /* read Tx power for all a/b/g channels */ 2256 for (i = 0; i < 19; i++) { 2257 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2258 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2259 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2260 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2261 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2262 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2263 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2264 } 2265 2266 /* read vendor-specific BBP values */ 2267 for (i = 0; i < 16; i++) { 2268 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2269 if (val == 0 || val == 0xffff) 2270 continue; /* skip invalid entries */ 2271 sc->bbp_prom[i].reg = val >> 8; 2272 sc->bbp_prom[i].val = val & 0xff; 2273 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2274 sc->bbp_prom[i].val); 2275 } 2276 } 2277 2278 static int 2279 rt2661_bbp_init(struct rt2661_softc *sc) 2280 { 2281 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2282 int i, ntries; 2283 uint8_t val; 2284 2285 /* wait for BBP to be ready */ 2286 for (ntries = 0; ntries < 100; ntries++) { 2287 val = rt2661_bbp_read(sc, 0); 2288 if (val != 0 && val != 0xff) 2289 break; 2290 DELAY(100); 2291 } 2292 if (ntries == 100) { 2293 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2294 return EIO; 2295 } 2296 2297 /* initialize BBP registers to default values */ 2298 for (i = 0; i < N(rt2661_def_bbp); i++) { 2299 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2300 rt2661_def_bbp[i].val); 2301 } 2302 2303 /* write vendor-specific BBP values (from EEPROM) */ 2304 for (i = 0; i < 16; i++) { 2305 if (sc->bbp_prom[i].reg == 0) 2306 continue; 2307 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2308 } 2309 2310 return 0; 2311 #undef N 2312 } 2313 2314 static void 2315 rt2661_init_locked(struct rt2661_softc *sc) 2316 { 2317 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2318 struct ifnet *ifp = sc->sc_ifp; 2319 struct ieee80211com *ic = ifp->if_l2com; 2320 uint32_t tmp, sta[3]; 2321 int i, error, ntries; 2322 2323 RAL_LOCK_ASSERT(sc); 2324 2325 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2326 error = rt2661_load_microcode(sc); 2327 if (error != 0) { 2328 if_printf(ifp, 2329 "%s: could not load 8051 microcode, error %d\n", 2330 __func__, error); 2331 return; 2332 } 2333 sc->sc_flags |= RAL_FW_LOADED; 2334 } 2335 2336 rt2661_stop_locked(sc); 2337 2338 /* initialize Tx rings */ 2339 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2340 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2341 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2342 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2343 2344 /* initialize Mgt ring */ 2345 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2346 2347 /* initialize Rx ring */ 2348 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2349 2350 /* initialize Tx rings sizes */ 2351 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2352 RT2661_TX_RING_COUNT << 24 | 2353 RT2661_TX_RING_COUNT << 16 | 2354 RT2661_TX_RING_COUNT << 8 | 2355 RT2661_TX_RING_COUNT); 2356 2357 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2358 RT2661_TX_DESC_WSIZE << 16 | 2359 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2360 RT2661_MGT_RING_COUNT); 2361 2362 /* initialize Rx rings */ 2363 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2364 RT2661_RX_DESC_BACK << 16 | 2365 RT2661_RX_DESC_WSIZE << 8 | 2366 RT2661_RX_RING_COUNT); 2367 2368 /* XXX: some magic here */ 2369 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2370 2371 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2372 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2373 2374 /* load base address of Rx ring */ 2375 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2376 2377 /* initialize MAC registers to default values */ 2378 for (i = 0; i < N(rt2661_def_mac); i++) 2379 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2380 2381 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2382 2383 /* set host ready */ 2384 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2385 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2386 2387 /* wait for BBP/RF to wakeup */ 2388 for (ntries = 0; ntries < 1000; ntries++) { 2389 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2390 break; 2391 DELAY(1000); 2392 } 2393 if (ntries == 1000) { 2394 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2395 rt2661_stop_locked(sc); 2396 return; 2397 } 2398 2399 if (rt2661_bbp_init(sc) != 0) { 2400 rt2661_stop_locked(sc); 2401 return; 2402 } 2403 2404 /* select default channel */ 2405 sc->sc_curchan = ic->ic_curchan; 2406 rt2661_select_band(sc, sc->sc_curchan); 2407 rt2661_select_antenna(sc); 2408 rt2661_set_chan(sc, sc->sc_curchan); 2409 2410 /* update Rx filter */ 2411 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2412 2413 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2414 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2415 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2416 RT2661_DROP_ACKCTS; 2417 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2418 ic->ic_opmode != IEEE80211_M_MBSS) 2419 tmp |= RT2661_DROP_TODS; 2420 if (!(ifp->if_flags & IFF_PROMISC)) 2421 tmp |= RT2661_DROP_NOT_TO_ME; 2422 } 2423 2424 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2425 2426 /* clear STA registers */ 2427 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2428 2429 /* initialize ASIC */ 2430 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2431 2432 /* clear any pending interrupt */ 2433 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2434 2435 /* enable interrupts */ 2436 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2437 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2438 2439 /* kick Rx */ 2440 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2441 2442 ifp->if_flags &= ~IFF_OACTIVE; 2443 ifp->if_flags |= IFF_RUNNING; 2444 2445 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2446 #undef N 2447 } 2448 2449 static void 2450 rt2661_init(void *priv) 2451 { 2452 struct rt2661_softc *sc = priv; 2453 struct ifnet *ifp = sc->sc_ifp; 2454 struct ieee80211com *ic = ifp->if_l2com; 2455 2456 RAL_LOCK(sc); 2457 rt2661_init_locked(sc); 2458 RAL_UNLOCK(sc); 2459 2460 if (ifp->if_flags & IFF_RUNNING) 2461 ieee80211_start_all(ic); /* start all vap's */ 2462 } 2463 2464 void 2465 rt2661_stop_locked(struct rt2661_softc *sc) 2466 { 2467 struct ifnet *ifp = sc->sc_ifp; 2468 uint32_t tmp; 2469 volatile int *flags = &sc->sc_flags; 2470 2471 while (*flags & RAL_INPUT_RUNNING) 2472 lksleep(sc, &sc->sc_lock, 0, "ralrunning", hz/10); 2473 2474 callout_stop(&sc->watchdog_ch); 2475 sc->sc_tx_timer = 0; 2476 2477 if (ifp->if_flags & IFF_RUNNING) { 2478 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2479 2480 /* abort Tx (for all 5 Tx rings) */ 2481 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2482 2483 /* disable Rx (value remains after reset!) */ 2484 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2485 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2486 2487 /* reset ASIC */ 2488 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2489 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2490 2491 /* disable interrupts */ 2492 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2493 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2494 2495 /* clear any pending interrupt */ 2496 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2497 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2498 2499 /* reset Tx and Rx rings */ 2500 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2501 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2502 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2503 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2504 rt2661_reset_tx_ring(sc, &sc->mgtq); 2505 rt2661_reset_rx_ring(sc, &sc->rxq); 2506 } 2507 } 2508 2509 void 2510 rt2661_stop(void *priv) 2511 { 2512 struct rt2661_softc *sc = priv; 2513 2514 RAL_LOCK(sc); 2515 rt2661_stop_locked(sc); 2516 RAL_UNLOCK(sc); 2517 } 2518 2519 static int 2520 rt2661_load_microcode(struct rt2661_softc *sc) 2521 { 2522 struct ifnet *ifp = sc->sc_ifp; 2523 const struct firmware *fp; 2524 const char *imagename; 2525 int ntries, error; 2526 2527 RAL_LOCK_ASSERT(sc); 2528 2529 switch (sc->sc_id) { 2530 case 0x0301: imagename = "rt2561sfw"; break; 2531 case 0x0302: imagename = "rt2561fw"; break; 2532 case 0x0401: imagename = "rt2661fw"; break; 2533 default: 2534 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2535 "don't know how to retrieve firmware\n", 2536 __func__, sc->sc_id); 2537 return EINVAL; 2538 } 2539 RAL_UNLOCK(sc); 2540 fp = firmware_get(imagename); 2541 RAL_LOCK(sc); 2542 if (fp == NULL) { 2543 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2544 __func__, imagename); 2545 return EINVAL; 2546 } 2547 2548 /* 2549 * Load 8051 microcode into NIC. 2550 */ 2551 /* reset 8051 */ 2552 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2553 2554 /* cancel any pending Host to MCU command */ 2555 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2556 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2557 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2558 2559 /* write 8051's microcode */ 2560 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2561 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2562 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2563 2564 /* kick 8051's ass */ 2565 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2566 2567 /* wait for 8051 to initialize */ 2568 for (ntries = 0; ntries < 500; ntries++) { 2569 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2570 break; 2571 DELAY(100); 2572 } 2573 if (ntries == 500) { 2574 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2575 __func__); 2576 error = EIO; 2577 } else 2578 error = 0; 2579 2580 firmware_put(fp, FIRMWARE_UNLOAD); 2581 return error; 2582 } 2583 2584 #ifdef notyet 2585 /* 2586 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2587 * false CCA count. This function is called periodically (every seconds) when 2588 * in the RUN state. Values taken from the reference driver. 2589 */ 2590 static void 2591 rt2661_rx_tune(struct rt2661_softc *sc) 2592 { 2593 uint8_t bbp17; 2594 uint16_t cca; 2595 int lo, hi, dbm; 2596 2597 /* 2598 * Tuning range depends on operating band and on the presence of an 2599 * external low-noise amplifier. 2600 */ 2601 lo = 0x20; 2602 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2603 lo += 0x08; 2604 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2605 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2606 lo += 0x10; 2607 hi = lo + 0x20; 2608 2609 /* retrieve false CCA count since last call (clear on read) */ 2610 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2611 2612 if (dbm >= -35) { 2613 bbp17 = 0x60; 2614 } else if (dbm >= -58) { 2615 bbp17 = hi; 2616 } else if (dbm >= -66) { 2617 bbp17 = lo + 0x10; 2618 } else if (dbm >= -74) { 2619 bbp17 = lo + 0x08; 2620 } else { 2621 /* RSSI < -74dBm, tune using false CCA count */ 2622 2623 bbp17 = sc->bbp17; /* current value */ 2624 2625 hi -= 2 * (-74 - dbm); 2626 if (hi < lo) 2627 hi = lo; 2628 2629 if (bbp17 > hi) { 2630 bbp17 = hi; 2631 2632 } else if (cca > 512) { 2633 if (++bbp17 > hi) 2634 bbp17 = hi; 2635 } else if (cca < 100) { 2636 if (--bbp17 < lo) 2637 bbp17 = lo; 2638 } 2639 } 2640 2641 if (bbp17 != sc->bbp17) { 2642 rt2661_bbp_write(sc, 17, bbp17); 2643 sc->bbp17 = bbp17; 2644 } 2645 } 2646 2647 /* 2648 * Enter/Leave radar detection mode. 2649 * This is for 802.11h additional regulatory domains. 2650 */ 2651 static void 2652 rt2661_radar_start(struct rt2661_softc *sc) 2653 { 2654 uint32_t tmp; 2655 2656 /* disable Rx */ 2657 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2658 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2659 2660 rt2661_bbp_write(sc, 82, 0x20); 2661 rt2661_bbp_write(sc, 83, 0x00); 2662 rt2661_bbp_write(sc, 84, 0x40); 2663 2664 /* save current BBP registers values */ 2665 sc->bbp18 = rt2661_bbp_read(sc, 18); 2666 sc->bbp21 = rt2661_bbp_read(sc, 21); 2667 sc->bbp22 = rt2661_bbp_read(sc, 22); 2668 sc->bbp16 = rt2661_bbp_read(sc, 16); 2669 sc->bbp17 = rt2661_bbp_read(sc, 17); 2670 sc->bbp64 = rt2661_bbp_read(sc, 64); 2671 2672 rt2661_bbp_write(sc, 18, 0xff); 2673 rt2661_bbp_write(sc, 21, 0x3f); 2674 rt2661_bbp_write(sc, 22, 0x3f); 2675 rt2661_bbp_write(sc, 16, 0xbd); 2676 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2677 rt2661_bbp_write(sc, 64, 0x21); 2678 2679 /* restore Rx filter */ 2680 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2681 } 2682 2683 static int 2684 rt2661_radar_stop(struct rt2661_softc *sc) 2685 { 2686 uint8_t bbp66; 2687 2688 /* read radar detection result */ 2689 bbp66 = rt2661_bbp_read(sc, 66); 2690 2691 /* restore BBP registers values */ 2692 rt2661_bbp_write(sc, 16, sc->bbp16); 2693 rt2661_bbp_write(sc, 17, sc->bbp17); 2694 rt2661_bbp_write(sc, 18, sc->bbp18); 2695 rt2661_bbp_write(sc, 21, sc->bbp21); 2696 rt2661_bbp_write(sc, 22, sc->bbp22); 2697 rt2661_bbp_write(sc, 64, sc->bbp64); 2698 2699 return bbp66 == 1; 2700 } 2701 #endif 2702 2703 static int 2704 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2705 { 2706 struct ieee80211com *ic = vap->iv_ic; 2707 struct ieee80211_beacon_offsets bo; 2708 struct rt2661_tx_desc desc; 2709 struct mbuf *m0; 2710 int rate; 2711 2712 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2713 if (m0 == NULL) { 2714 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2715 return ENOBUFS; 2716 } 2717 2718 /* send beacons at the lowest available rate */ 2719 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2720 2721 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2722 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2723 2724 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2725 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2726 2727 /* copy beacon header and payload into NIC memory */ 2728 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2729 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2730 2731 m_freem(m0); 2732 2733 return 0; 2734 } 2735 2736 /* 2737 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2738 * and HostAP operating modes. 2739 */ 2740 static void 2741 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2742 { 2743 struct ifnet *ifp = sc->sc_ifp; 2744 struct ieee80211com *ic = ifp->if_l2com; 2745 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2746 uint32_t tmp; 2747 2748 if (vap->iv_opmode != IEEE80211_M_STA) { 2749 /* 2750 * Change default 16ms TBTT adjustment to 8ms. 2751 * Must be done before enabling beacon generation. 2752 */ 2753 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2754 } 2755 2756 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2757 2758 /* set beacon interval (in 1/16ms unit) */ 2759 tmp |= vap->iv_bss->ni_intval * 16; 2760 2761 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2762 if (vap->iv_opmode == IEEE80211_M_STA) 2763 tmp |= RT2661_TSF_MODE(1); 2764 else 2765 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2766 2767 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2768 } 2769 2770 static void 2771 rt2661_enable_tsf(struct rt2661_softc *sc) 2772 { 2773 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2774 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2775 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2776 } 2777 2778 /* 2779 * Retrieve the "Received Signal Strength Indicator" from the raw values 2780 * contained in Rx descriptors. The computation depends on which band the 2781 * frame was received. Correction values taken from the reference driver. 2782 */ 2783 static int 2784 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2785 { 2786 int lna, agc, rssi; 2787 2788 lna = (raw >> 5) & 0x3; 2789 agc = raw & 0x1f; 2790 2791 if (lna == 0) { 2792 /* 2793 * No mapping available. 2794 * 2795 * NB: Since RSSI is relative to noise floor, -1 is 2796 * adequate for caller to know error happened. 2797 */ 2798 return -1; 2799 } 2800 2801 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2802 2803 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2804 rssi += sc->rssi_2ghz_corr; 2805 2806 if (lna == 1) 2807 rssi -= 64; 2808 else if (lna == 2) 2809 rssi -= 74; 2810 else if (lna == 3) 2811 rssi -= 90; 2812 } else { 2813 rssi += sc->rssi_5ghz_corr; 2814 2815 if (lna == 1) 2816 rssi -= 64; 2817 else if (lna == 2) 2818 rssi -= 86; 2819 else if (lna == 3) 2820 rssi -= 100; 2821 } 2822 return rssi; 2823 } 2824 2825 static void 2826 rt2661_scan_start(struct ieee80211com *ic) 2827 { 2828 struct ifnet *ifp = ic->ic_ifp; 2829 struct rt2661_softc *sc = ifp->if_softc; 2830 uint32_t tmp; 2831 2832 /* abort TSF synchronization */ 2833 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2834 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2835 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2836 } 2837 2838 static void 2839 rt2661_scan_end(struct ieee80211com *ic) 2840 { 2841 struct ifnet *ifp = ic->ic_ifp; 2842 struct rt2661_softc *sc = ifp->if_softc; 2843 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2844 2845 rt2661_enable_tsf_sync(sc); 2846 /* XXX keep local copy */ 2847 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2848 } 2849 2850 static void 2851 rt2661_set_channel(struct ieee80211com *ic) 2852 { 2853 struct ifnet *ifp = ic->ic_ifp; 2854 struct rt2661_softc *sc = ifp->if_softc; 2855 2856 RAL_LOCK(sc); 2857 rt2661_set_chan(sc, ic->ic_curchan); 2858 RAL_UNLOCK(sc); 2859 2860 } 2861