1 /* 2 * Copyright (c) 2006 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: src/sys/dev/ral/rt2661.c,v 1.4 2006/03/21 21:15:43 damien Exp $ 18 * $DragonFly: src/sys/dev/netif/ral/rt2661.c,v 1.28 2008/01/17 13:33:11 sephe Exp $ 19 */ 20 21 /* 22 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/bus.h> 28 #include <sys/endian.h> 29 #include <sys/kernel.h> 30 #include <sys/malloc.h> 31 #include <sys/mbuf.h> 32 #include <sys/module.h> 33 #include <sys/queue.h> 34 #include <sys/rman.h> 35 #include <sys/socket.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/serialize.h> 39 40 #include <net/bpf.h> 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 #include <net/ifq_var.h> 47 48 #include <netproto/802_11/ieee80211_var.h> 49 #include <netproto/802_11/ieee80211_radiotap.h> 50 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h> 51 #include <netproto/802_11/wlan_ratectl/sample/ieee80211_sample_param.h> 52 53 #include <dev/netif/ral/rt2661reg.h> 54 #include <dev/netif/ral/rt2661var.h> 55 #include <dev/netif/ral/rt2661_ucode.h> 56 57 #ifdef RAL_DEBUG 58 #define DPRINTF(x) do { if (ral_debug > 0) kprintf x; } while (0) 59 #define DPRINTFN(n, x) do { if (ral_debug >= (n)) kprintf x; } while (0) 60 int ral_debug = 1; 61 SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n, x) 65 #endif 66 67 MALLOC_DEFINE(M_RT2661, "rt2661_ratectl", "rt2661 rate control data"); 68 69 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 70 int); 71 static void rt2661_dma_map_mbuf(void *, bus_dma_segment_t *, int, 72 bus_size_t, int); 73 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 74 struct rt2661_tx_ring *, int); 75 static void rt2661_reset_tx_ring(struct rt2661_softc *, 76 struct rt2661_tx_ring *); 77 static void rt2661_free_tx_ring(struct rt2661_softc *, 78 struct rt2661_tx_ring *); 79 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 80 struct rt2661_rx_ring *, int); 81 static void rt2661_reset_rx_ring(struct rt2661_softc *, 82 struct rt2661_rx_ring *); 83 static void rt2661_free_rx_ring(struct rt2661_softc *, 84 struct rt2661_rx_ring *); 85 static int rt2661_media_change(struct ifnet *); 86 static void rt2661_next_scan(void *); 87 static int rt2661_newstate(struct ieee80211com *, 88 enum ieee80211_state, int); 89 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 90 static void rt2661_rx_intr(struct rt2661_softc *); 91 static void rt2661_tx_intr(struct rt2661_softc *); 92 static void rt2661_tx_dma_intr(struct rt2661_softc *, 93 struct rt2661_tx_ring *); 94 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 95 static void rt2661_mcu_wakeup(struct rt2661_softc *); 96 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 97 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 98 static uint8_t rt2661_plcp_signal(int); 99 static void rt2661_setup_tx_desc(struct rt2661_softc *, 100 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 101 int, const bus_dma_segment_t *, int, int, int, 102 const struct ieee80211_key *, void *, 103 const struct ieee80211_crypto_iv *); 104 static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 105 struct ieee80211_frame *, uint16_t); 106 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 107 struct ieee80211_node *, int); 108 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 109 struct ieee80211_node *); 110 static void rt2661_start(struct ifnet *); 111 static void rt2661_watchdog(struct ifnet *); 112 static int rt2661_reset(struct ifnet *); 113 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 114 struct ucred *); 115 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 116 uint8_t); 117 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 118 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 119 uint32_t); 120 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 121 uint16_t); 122 static void rt2661_select_antenna(struct rt2661_softc *); 123 static void rt2661_enable_mrr(struct rt2661_softc *); 124 static void rt2661_set_txpreamble(struct rt2661_softc *); 125 static void rt2661_set_ackrates(struct rt2661_softc *, 126 const struct ieee80211_rateset *); 127 static void rt2661_select_band(struct rt2661_softc *, 128 struct ieee80211_channel *); 129 static void rt2661_set_chan(struct rt2661_softc *, 130 struct ieee80211_channel *); 131 static void rt2661_set_bssid(struct rt2661_softc *, 132 const uint8_t *); 133 static void rt2661_set_macaddr(struct rt2661_softc *, 134 const uint8_t *); 135 static void rt2661_update_promisc(struct rt2661_softc *); 136 static int rt2661_wme_update(struct ieee80211com *) __unused; 137 static void rt2661_update_slot(struct ifnet *); 138 static const char *rt2661_get_rf(int); 139 static void rt2661_read_config(struct rt2661_softc *); 140 static void rt2661_read_txpower_config(struct rt2661_softc *, 141 uint8_t, int, int *); 142 static int rt2661_bbp_init(struct rt2661_softc *); 143 static void rt2661_init(void *); 144 static void rt2661_stop(void *); 145 static void rt2661_intr(void *); 146 static int rt2661_load_microcode(struct rt2661_softc *, 147 const uint8_t *, int); 148 static int rt2661_prepare_beacon(struct rt2661_softc *); 149 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 150 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t, int); 151 static void rt2661_led_newstate(struct rt2661_softc *, 152 enum ieee80211_state); 153 static int rt2661_key_alloc(struct ieee80211com *, 154 const struct ieee80211_key *, 155 ieee80211_keyix *, ieee80211_keyix *); 156 static int rt2661_key_delete(struct ieee80211com *, 157 const struct ieee80211_key *); 158 static int rt2661_key_set(struct ieee80211com *, 159 const struct ieee80211_key *, 160 const uint8_t mac[IEEE80211_ADDR_LEN]); 161 static void *rt2661_ratectl_attach(struct ieee80211com *, u_int); 162 static void rt2661_set_txpower(struct rt2661_softc *, int8_t); 163 static void rt2661_calibrate(void *); 164 static void rt2661_calib_txpower(struct rt2661_softc *); 165 static void rt2661_calib_rxsensibility(struct rt2661_softc *, 166 uint32_t); 167 168 /* 169 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 170 */ 171 static const struct ieee80211_rateset rt2661_rateset_11a = 172 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 173 174 static const struct ieee80211_rateset rt2661_rateset_11b = 175 { 4, { 2, 4, 11, 22 } }; 176 177 static const struct ieee80211_rateset rt2661_rateset_11g = 178 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 179 180 static const struct { 181 uint32_t reg; 182 uint32_t val; 183 } rt2661_def_mac[] = { 184 RT2661_DEF_MAC 185 }; 186 187 static const struct { 188 uint8_t reg; 189 uint8_t val; 190 } rt2661_def_bbp[] = { 191 RT2661_DEF_BBP 192 }; 193 194 static const struct rt2661_rfprog rt2661_rf5225_1[] = { RT2661_RF5225_1 }; 195 static const struct rt2661_rfprog rt2661_rf5225_2[] = { RT2661_RF5225_2 }; 196 197 #define LED_EE2MCU(bit) { \ 198 .ee_bit = RT2661_EE_LED_##bit, \ 199 .mcu_bit = RT2661_MCU_LED_##bit \ 200 } 201 static const struct { 202 uint16_t ee_bit; 203 uint16_t mcu_bit; 204 } led_ee2mcu[] = { 205 LED_EE2MCU(RDYG), 206 LED_EE2MCU(RDYA), 207 LED_EE2MCU(ACT), 208 LED_EE2MCU(GPIO0), 209 LED_EE2MCU(GPIO1), 210 LED_EE2MCU(GPIO2), 211 LED_EE2MCU(GPIO3), 212 LED_EE2MCU(GPIO4) 213 }; 214 #undef LED_EE2MCU 215 216 struct rt2661_dmamap { 217 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 218 int nseg; 219 }; 220 221 static __inline int 222 rt2661_cipher(const struct ieee80211_key *k) 223 { 224 switch (k->wk_cipher->ic_cipher) { 225 case IEEE80211_CIPHER_WEP: 226 if (k->wk_keylen == (40 / NBBY)) 227 return RT2661_CIPHER_WEP40; 228 else 229 return RT2661_CIPHER_WEP104; 230 case IEEE80211_CIPHER_TKIP: 231 return RT2661_CIPHER_TKIP; 232 case IEEE80211_CIPHER_AES_CCM: 233 return RT2661_CIPHER_AES; 234 default: 235 return RT2661_CIPHER_NONE; 236 } 237 } 238 239 static __inline int8_t 240 rt2661_txpower(const struct rt2661_softc *sc, int8_t power) 241 { 242 if (sc->sc_txpwr_corr > 0) { 243 if (power > sc->sc_txpwr_corr) 244 power -= sc->sc_txpwr_corr; 245 else 246 power = 0; 247 } 248 return power; 249 } 250 251 static __inline int 252 rt2661_avgrssi(const struct rt2661_softc *sc) 253 { 254 int rssi_dbm; 255 256 rssi_dbm = sc->avg_rssi[0] + RT2661_NOISE_FLOOR; 257 if (sc->rf_rev == RT2661_RF_2529) { 258 if (sc->avg_rssi[1] > sc->avg_rssi[0]) 259 rssi_dbm = sc->avg_rssi[0] + RT2661_NOISE_FLOOR; 260 } 261 return rssi_dbm; 262 } 263 264 int 265 rt2661_attach(device_t dev, int id) 266 { 267 struct rt2661_softc *sc = device_get_softc(dev); 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ifnet *ifp = &ic->ic_if; 270 uint32_t val, bbp_type; 271 const uint8_t *ucode = NULL; 272 int error, i, ac, ntries, size = 0; 273 274 callout_init(&sc->scan_ch); 275 callout_init(&sc->calib_ch); 276 277 sc->sc_irq_rid = 0; 278 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid, 279 RF_ACTIVE | RF_SHAREABLE); 280 if (sc->sc_irq == NULL) { 281 device_printf(dev, "could not allocate interrupt resource\n"); 282 return ENXIO; 283 } 284 285 /* wait for NIC to initialize */ 286 for (ntries = 0; ntries < 1000; ntries++) { 287 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 288 break; 289 DELAY(1000); 290 } 291 if (ntries == 1000) { 292 device_printf(sc->sc_dev, 293 "timeout waiting for NIC to initialize\n"); 294 error = EIO; 295 goto fail; 296 } 297 bbp_type = val; 298 299 /* retrieve RF rev. no and various other things from EEPROM */ 300 rt2661_read_config(sc); 301 302 device_printf(dev, "MAC/BBP RT%X, RF %s\n", bbp_type, 303 rt2661_get_rf(sc->rf_rev)); 304 305 /* 306 * Load 8051 microcode into NIC. 307 */ 308 switch (id) { 309 case 0x0301: 310 ucode = rt2561s_ucode; 311 size = sizeof rt2561s_ucode; 312 break; 313 case 0x0302: 314 ucode = rt2561_ucode; 315 size = sizeof rt2561_ucode; 316 break; 317 case 0x0401: 318 ucode = rt2661_ucode; 319 size = sizeof rt2661_ucode; 320 break; 321 } 322 323 error = rt2661_load_microcode(sc, ucode, size); 324 if (error != 0) { 325 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 326 goto fail; 327 } 328 329 /* 330 * Allocate Tx and Rx rings. 331 */ 332 for (ac = 0; ac < 4; ac++) { 333 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 334 RT2661_TX_RING_COUNT); 335 if (error != 0) { 336 device_printf(sc->sc_dev, 337 "could not allocate Tx ring %d\n", ac); 338 goto fail; 339 } 340 } 341 342 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 343 if (error != 0) { 344 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 345 goto fail; 346 } 347 348 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 349 if (error != 0) { 350 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 351 goto fail; 352 } 353 354 STAILQ_INIT(&sc->tx_ratectl); 355 356 sysctl_ctx_init(&sc->sysctl_ctx); 357 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 358 SYSCTL_STATIC_CHILDREN(_hw), 359 OID_AUTO, 360 device_get_nameunit(dev), 361 CTLFLAG_RD, 0, ""); 362 if (sc->sysctl_tree == NULL) { 363 device_printf(dev, "could not add sysctl node\n"); 364 error = ENXIO; 365 goto fail; 366 } 367 368 ifp->if_softc = sc; 369 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 370 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 371 ifp->if_init = rt2661_init; 372 ifp->if_ioctl = rt2661_ioctl; 373 ifp->if_start = rt2661_start; 374 ifp->if_watchdog = rt2661_watchdog; 375 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 376 ifq_set_ready(&ifp->if_snd); 377 378 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 379 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 380 ic->ic_state = IEEE80211_S_INIT; 381 rt2661_led_newstate(sc, IEEE80211_S_INIT); 382 383 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param); 384 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE; 385 if (bbp_type == RT2661_BBP_2661D) { 386 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE; 387 } else { 388 IEEE80211_SAMPLE_PARAM_SETUP(&sc->sc_sample_param); 389 ic->ic_ratectl.rc_st_ratectl_cap |= 390 IEEE80211_RATECTL_CAP_SAMPLE; 391 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_SAMPLE; 392 } 393 ic->ic_ratectl.rc_st_attach = rt2661_ratectl_attach; 394 395 /* set device capabilities */ 396 ic->ic_caps = 397 IEEE80211_C_IBSS | /* IBSS mode supported */ 398 IEEE80211_C_MONITOR | /* monitor mode supported */ 399 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 400 IEEE80211_C_TXPMGT | /* tx power management */ 401 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 402 IEEE80211_C_SHSLOT | /* short slot time supported */ 403 #ifdef notyet 404 IEEE80211_C_WME | /* 802.11e */ 405 #endif 406 IEEE80211_C_WPA; /* 802.11i */ 407 408 /* Set hardware crypto capabilities. */ 409 ic->ic_caps |= IEEE80211_C_WEP | 410 IEEE80211_C_TKIP | 411 IEEE80211_C_TKIPMIC | 412 IEEE80211_C_AES_CCM; 413 414 ic->ic_caps_ext = IEEE80211_CEXT_CRYPTO_HDR | 415 IEEE80211_CEXT_STRIP_MIC; 416 417 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 418 /* set supported .11a rates */ 419 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 420 421 /* set supported .11a channels */ 422 for (i = 36; i <= 64; i += 4) { 423 ic->ic_channels[i].ic_freq = 424 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 425 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 426 } 427 for (i = 100; i <= 140; i += 4) { 428 ic->ic_channels[i].ic_freq = 429 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 430 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 431 } 432 for (i = 149; i <= 165; i += 4) { 433 ic->ic_channels[i].ic_freq = 434 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 435 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 436 } 437 } 438 439 /* set supported .11b and .11g rates */ 440 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 441 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 442 443 /* set supported .11b and .11g channels (1 through 14) */ 444 for (i = 1; i <= 14; i++) { 445 ic->ic_channels[i].ic_freq = 446 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 447 ic->ic_channels[i].ic_flags = 448 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 449 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 450 } 451 452 sc->sc_sifs = IEEE80211_DUR_SIFS; /* Default SIFS */ 453 454 ieee80211_ifattach(ic); 455 /* ic->ic_wme.wme_update = rt2661_wme_update;*/ 456 ic->ic_updateslot = rt2661_update_slot; 457 ic->ic_reset = rt2661_reset; 458 /* enable s/w bmiss handling in sta mode */ 459 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 460 461 sc->sc_key_alloc = ic->ic_crypto.cs_key_alloc; 462 sc->sc_key_delete = ic->ic_crypto.cs_key_delete; 463 sc->sc_key_set = ic->ic_crypto.cs_key_set; 464 465 ic->ic_crypto.cs_max_keyix = RT2661_KEY_MAX; 466 ic->ic_crypto.cs_key_alloc = rt2661_key_alloc; 467 ic->ic_crypto.cs_key_delete = rt2661_key_delete; 468 ic->ic_crypto.cs_key_set = rt2661_key_set; 469 470 /* override state transition machine */ 471 sc->sc_newstate = ic->ic_newstate; 472 ic->ic_newstate = rt2661_newstate; 473 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 474 475 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO, 476 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 477 478 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 479 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 480 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 481 482 sc->sc_txtap_len = sizeof sc->sc_txtapu; 483 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 484 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 485 486 /* 487 * Add a few sysctl knobs. 488 */ 489 sc->sc_dwelltime = 200; /* milliseconds */ 490 sc->sc_txpwr_corr = -1; /* Disable */ 491 sc->sc_calib_txpwr = 0; /* Disable */ 492 sc->sc_calib_rxsns = 0; /* Disable */ 493 494 SYSCTL_ADD_INT(&sc->sysctl_ctx, 495 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "dwell", 496 CTLFLAG_RW, &sc->sc_dwelltime, 0, 497 "Channel dwell time (ms) for AP/station scanning"); 498 499 SYSCTL_ADD_INT(&sc->sysctl_ctx, 500 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "txpwr_corr", 501 CTLFLAG_RW, &sc->sc_txpwr_corr, 0, 502 "TX power correction value (<0 no correction)"); 503 504 SYSCTL_ADD_INT(&sc->sysctl_ctx, 505 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "calib_txpwr", 506 CTLFLAG_RW, &sc->sc_calib_txpwr, 0, 507 "Enable TX power calibration (sta mode)"); 508 SYSCTL_ADD_INT(&sc->sysctl_ctx, 509 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "calib_rxsns", 510 CTLFLAG_RW, &sc->sc_calib_rxsns, 0, 511 "Enable RX sensibility calibration (sta mode)"); 512 513 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, rt2661_intr, 514 sc, &sc->sc_ih, ifp->if_serializer); 515 if (error != 0) { 516 device_printf(dev, "could not set up interrupt\n"); 517 bpfdetach(ifp); 518 ieee80211_ifdetach(ic); 519 goto fail; 520 } 521 522 if (bootverbose) 523 ieee80211_announce(ic); 524 return 0; 525 fail: 526 rt2661_detach(sc); 527 return error; 528 } 529 530 int 531 rt2661_detach(void *xsc) 532 { 533 struct rt2661_softc *sc = xsc; 534 struct ieee80211com *ic = &sc->sc_ic; 535 struct ifnet *ifp = &ic->ic_if; 536 537 if (device_is_attached(sc->sc_dev)) { 538 lwkt_serialize_enter(ifp->if_serializer); 539 540 callout_stop(&sc->scan_ch); 541 rt2661_stop(sc); 542 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih); 543 544 lwkt_serialize_exit(ifp->if_serializer); 545 546 bpfdetach(ifp); 547 ieee80211_ifdetach(ic); 548 } 549 550 rt2661_free_tx_ring(sc, &sc->txq[0]); 551 rt2661_free_tx_ring(sc, &sc->txq[1]); 552 rt2661_free_tx_ring(sc, &sc->txq[2]); 553 rt2661_free_tx_ring(sc, &sc->txq[3]); 554 rt2661_free_tx_ring(sc, &sc->mgtq); 555 rt2661_free_rx_ring(sc, &sc->rxq); 556 557 if (sc->sc_irq != NULL) { 558 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid, 559 sc->sc_irq); 560 } 561 562 if (sc->sysctl_tree != NULL) 563 sysctl_ctx_free(&sc->sysctl_ctx); 564 565 return 0; 566 } 567 568 void 569 rt2661_shutdown(void *xsc) 570 { 571 struct rt2661_softc *sc = xsc; 572 struct ifnet *ifp = &sc->sc_ic.ic_if; 573 574 lwkt_serialize_enter(ifp->if_serializer); 575 rt2661_stop(sc); 576 lwkt_serialize_exit(ifp->if_serializer); 577 } 578 579 void 580 rt2661_suspend(void *xsc) 581 { 582 struct rt2661_softc *sc = xsc; 583 struct ifnet *ifp = &sc->sc_ic.ic_if; 584 585 lwkt_serialize_enter(ifp->if_serializer); 586 rt2661_stop(sc); 587 lwkt_serialize_exit(ifp->if_serializer); 588 } 589 590 void 591 rt2661_resume(void *xsc) 592 { 593 struct rt2661_softc *sc = xsc; 594 struct ifnet *ifp = sc->sc_ic.ic_ifp; 595 596 lwkt_serialize_enter(ifp->if_serializer); 597 if (ifp->if_flags & IFF_UP) { 598 ifp->if_init(ifp->if_softc); 599 if (ifp->if_flags & IFF_RUNNING) 600 ifp->if_start(ifp); 601 } 602 lwkt_serialize_exit(ifp->if_serializer); 603 } 604 605 static void 606 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 607 { 608 if (error != 0) 609 return; 610 611 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 612 613 *(bus_addr_t *)arg = segs[0].ds_addr; 614 } 615 616 static int 617 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 618 int count) 619 { 620 int i, error; 621 622 ring->count = count; 623 ring->queued = 0; 624 ring->cur = ring->next = 0; 625 626 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 627 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 628 count * RT2661_TX_DESC_SIZE, 0, &ring->desc_dmat); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 631 goto fail; 632 } 633 634 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 635 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 638 goto fail; 639 } 640 641 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 642 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 643 0); 644 if (error != 0) { 645 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 646 647 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 648 ring->desc = NULL; 649 goto fail; 650 } 651 652 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF, 653 M_WAITOK | M_ZERO); 654 655 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 656 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * RT2661_MAX_SCATTER, 657 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 658 if (error != 0) { 659 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 660 goto fail; 661 } 662 663 for (i = 0; i < count; i++) { 664 error = bus_dmamap_create(ring->data_dmat, 0, 665 &ring->data[i].map); 666 if (error != 0) { 667 device_printf(sc->sc_dev, "could not create DMA map\n"); 668 goto fail; 669 } 670 } 671 return 0; 672 673 fail: rt2661_free_tx_ring(sc, ring); 674 return error; 675 } 676 677 static void 678 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 679 { 680 struct rt2661_tx_desc *desc; 681 struct rt2661_data *data; 682 int i; 683 684 for (i = 0; i < ring->count; i++) { 685 desc = &ring->desc[i]; 686 data = &ring->data[i]; 687 688 if (data->m != NULL) { 689 bus_dmamap_sync(ring->data_dmat, data->map, 690 BUS_DMASYNC_POSTWRITE); 691 bus_dmamap_unload(ring->data_dmat, data->map); 692 m_freem(data->m); 693 data->m = NULL; 694 } 695 696 desc->flags = 0; 697 } 698 699 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 700 701 ring->queued = 0; 702 ring->cur = ring->next = 0; 703 } 704 705 static void 706 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 707 { 708 struct rt2661_data *data; 709 int i; 710 711 if (ring->desc != NULL) { 712 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 713 BUS_DMASYNC_POSTWRITE); 714 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 715 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 716 ring->desc = NULL; 717 } 718 719 if (ring->desc_dmat != NULL) { 720 bus_dma_tag_destroy(ring->desc_dmat); 721 ring->desc_dmat = NULL; 722 } 723 724 if (ring->data != NULL) { 725 for (i = 0; i < ring->count; i++) { 726 data = &ring->data[i]; 727 728 if (data->m != NULL) { 729 bus_dmamap_sync(ring->data_dmat, data->map, 730 BUS_DMASYNC_POSTWRITE); 731 bus_dmamap_unload(ring->data_dmat, data->map); 732 m_freem(data->m); 733 data->m = NULL; 734 } 735 736 if (data->map != NULL) { 737 bus_dmamap_destroy(ring->data_dmat, data->map); 738 data->map = NULL; 739 } 740 } 741 742 kfree(ring->data, M_DEVBUF); 743 ring->data = NULL; 744 } 745 746 if (ring->data_dmat != NULL) { 747 bus_dma_tag_destroy(ring->data_dmat); 748 ring->data_dmat = NULL; 749 } 750 } 751 752 static int 753 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 754 int count) 755 { 756 struct rt2661_rx_desc *desc; 757 struct rt2661_data *data; 758 bus_addr_t physaddr; 759 int i, error; 760 761 ring->count = count; 762 ring->cur = ring->next = 0; 763 764 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 765 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 766 count * RT2661_RX_DESC_SIZE, 0, &ring->desc_dmat); 767 if (error != 0) { 768 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 769 goto fail; 770 } 771 772 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 773 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 774 if (error != 0) { 775 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 776 goto fail; 777 } 778 779 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 780 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 781 0); 782 if (error != 0) { 783 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 784 785 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 786 ring->desc = NULL; 787 goto fail; 788 } 789 790 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF, 791 M_WAITOK | M_ZERO); 792 793 /* 794 * Pre-allocate Rx buffers and populate Rx ring. 795 */ 796 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 797 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 798 &ring->data_dmat); 799 if (error != 0) { 800 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 801 goto fail; 802 } 803 804 for (i = 0; i < count; i++) { 805 desc = &sc->rxq.desc[i]; 806 data = &sc->rxq.data[i]; 807 808 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 809 if (error != 0) { 810 device_printf(sc->sc_dev, "could not create DMA map\n"); 811 goto fail; 812 } 813 814 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 815 if (data->m == NULL) { 816 device_printf(sc->sc_dev, 817 "could not allocate rx mbuf\n"); 818 error = ENOMEM; 819 goto fail; 820 } 821 822 error = bus_dmamap_load(ring->data_dmat, data->map, 823 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 824 &physaddr, 0); 825 if (error != 0) { 826 device_printf(sc->sc_dev, 827 "could not load rx buf DMA map"); 828 829 m_freem(data->m); 830 data->m = NULL; 831 goto fail; 832 } 833 834 desc->flags = htole32(RT2661_RX_BUSY); 835 desc->physaddr = htole32(physaddr); 836 } 837 838 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 839 840 return 0; 841 842 fail: rt2661_free_rx_ring(sc, ring); 843 return error; 844 } 845 846 static void 847 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 848 { 849 int i; 850 851 for (i = 0; i < ring->count; i++) 852 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 853 854 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 855 856 ring->cur = ring->next = 0; 857 } 858 859 static void 860 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 861 { 862 struct rt2661_data *data; 863 int i; 864 865 if (ring->desc != NULL) { 866 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 867 BUS_DMASYNC_POSTWRITE); 868 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 869 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 870 ring->desc = NULL; 871 } 872 873 if (ring->desc_dmat != NULL) { 874 bus_dma_tag_destroy(ring->desc_dmat); 875 ring->desc_dmat = NULL; 876 } 877 878 if (ring->data != NULL) { 879 for (i = 0; i < ring->count; i++) { 880 data = &ring->data[i]; 881 882 if (data->m != NULL) { 883 bus_dmamap_sync(ring->data_dmat, data->map, 884 BUS_DMASYNC_POSTREAD); 885 bus_dmamap_unload(ring->data_dmat, data->map); 886 m_freem(data->m); 887 data->m = NULL; 888 } 889 890 if (data->map != NULL) { 891 bus_dmamap_destroy(ring->data_dmat, data->map); 892 data->map = NULL; 893 } 894 } 895 896 kfree(ring->data, M_DEVBUF); 897 ring->data = NULL; 898 } 899 900 if (ring->data_dmat != NULL) { 901 bus_dma_tag_destroy(ring->data_dmat); 902 ring->data_dmat = NULL; 903 } 904 } 905 906 static int 907 rt2661_media_change(struct ifnet *ifp) 908 { 909 struct rt2661_softc *sc = ifp->if_softc; 910 int error; 911 912 error = ieee80211_media_change(ifp); 913 if (error != ENETRESET) 914 return error; 915 916 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 917 rt2661_init(sc); 918 return 0; 919 } 920 921 /* 922 * This function is called periodically (every 200ms) during scanning to 923 * switch from one channel to another. 924 */ 925 static void 926 rt2661_next_scan(void *arg) 927 { 928 struct rt2661_softc *sc = arg; 929 struct ieee80211com *ic = &sc->sc_ic; 930 struct ifnet *ifp = &ic->ic_if; 931 932 lwkt_serialize_enter(ifp->if_serializer); 933 if (ic->ic_state == IEEE80211_S_SCAN) 934 ieee80211_next_scan(ic); 935 lwkt_serialize_exit(ifp->if_serializer); 936 } 937 938 static int 939 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 940 { 941 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 942 enum ieee80211_state ostate; 943 struct ieee80211_node *ni; 944 uint32_t tmp; 945 int error = 0; 946 947 ostate = ic->ic_state; 948 callout_stop(&sc->scan_ch); 949 callout_stop(&sc->calib_ch); 950 951 if (ostate != nstate) 952 rt2661_led_newstate(sc, nstate); 953 954 ieee80211_ratectl_newstate(ic, nstate); 955 956 switch (nstate) { 957 case IEEE80211_S_INIT: 958 if (ostate == IEEE80211_S_RUN) { 959 /* abort TSF synchronization */ 960 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 961 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 962 } 963 break; 964 965 case IEEE80211_S_SCAN: 966 rt2661_set_chan(sc, ic->ic_curchan); 967 callout_reset(&sc->scan_ch, (sc->sc_dwelltime * hz) / 1000, 968 rt2661_next_scan, sc); 969 break; 970 971 case IEEE80211_S_AUTH: 972 case IEEE80211_S_ASSOC: 973 rt2661_set_chan(sc, ic->ic_curchan); 974 break; 975 976 case IEEE80211_S_RUN: 977 RT2661_RESET_AVG_RSSI(sc); 978 979 rt2661_set_chan(sc, ic->ic_curchan); 980 981 ni = ic->ic_bss; 982 983 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 984 rt2661_enable_mrr(sc); 985 rt2661_set_txpreamble(sc); 986 rt2661_set_ackrates(sc, &ni->ni_rates); 987 rt2661_set_bssid(sc, ni->ni_bssid); 988 } 989 990 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 991 ic->ic_opmode == IEEE80211_M_IBSS) { 992 if ((error = rt2661_prepare_beacon(sc)) != 0) 993 break; 994 } 995 996 if (ic->ic_opmode != IEEE80211_M_MONITOR) 997 rt2661_enable_tsf_sync(sc); 998 999 if (ic->ic_opmode == IEEE80211_M_STA) { 1000 uint32_t sta[4]; 1001 1002 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 1003 /* clear STA registers */ 1004 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 1005 #undef N 1006 sc->sc_txpwr_cnt = 0; 1007 callout_reset(&sc->calib_ch, hz, rt2661_calibrate, sc); 1008 } 1009 break; 1010 } 1011 1012 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 1013 } 1014 1015 /* 1016 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 1017 * 93C66). 1018 */ 1019 static uint16_t 1020 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 1021 { 1022 uint32_t tmp; 1023 uint16_t val; 1024 int n; 1025 1026 /* clock C once before the first command */ 1027 RT2661_EEPROM_CTL(sc, 0); 1028 1029 RT2661_EEPROM_CTL(sc, RT2661_S); 1030 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1031 RT2661_EEPROM_CTL(sc, RT2661_S); 1032 1033 /* write start bit (1) */ 1034 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1035 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1036 1037 /* write READ opcode (10) */ 1038 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1039 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1040 RT2661_EEPROM_CTL(sc, RT2661_S); 1041 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1042 1043 /* write address (A5-A0 or A7-A0) */ 1044 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 1045 for (; n >= 0; n--) { 1046 RT2661_EEPROM_CTL(sc, RT2661_S | 1047 (((addr >> n) & 1) << RT2661_SHIFT_D)); 1048 RT2661_EEPROM_CTL(sc, RT2661_S | 1049 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 1050 } 1051 1052 RT2661_EEPROM_CTL(sc, RT2661_S); 1053 1054 /* read data Q15-Q0 */ 1055 val = 0; 1056 for (n = 15; n >= 0; n--) { 1057 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1058 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1059 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1060 RT2661_EEPROM_CTL(sc, RT2661_S); 1061 } 1062 1063 RT2661_EEPROM_CTL(sc, 0); 1064 1065 /* clear Chip Select and clock C */ 1066 RT2661_EEPROM_CTL(sc, RT2661_S); 1067 RT2661_EEPROM_CTL(sc, 0); 1068 RT2661_EEPROM_CTL(sc, RT2661_C); 1069 1070 return val; 1071 } 1072 1073 static void 1074 rt2661_tx_intr(struct rt2661_softc *sc) 1075 { 1076 struct ieee80211com *ic = &sc->sc_ic; 1077 struct ifnet *ifp = ic->ic_ifp; 1078 struct rt2661_tx_ratectl *rctl; 1079 uint32_t val, result; 1080 int retrycnt; 1081 1082 for (;;) { 1083 struct ieee80211_ratectl_res res; 1084 1085 val = RAL_READ(sc, RT2661_STA_CSR4); 1086 if (!(val & RT2661_TX_STAT_VALID)) 1087 break; 1088 1089 /* Gather statistics */ 1090 result = RT2661_TX_RESULT(val); 1091 if (result == RT2661_TX_SUCCESS) 1092 ifp->if_opackets++; 1093 else 1094 ifp->if_oerrors++; 1095 1096 /* No rate control */ 1097 if (RT2661_TX_QID(val) == 0) 1098 continue; 1099 1100 /* retrieve rate control algorithm context */ 1101 rctl = STAILQ_FIRST(&sc->tx_ratectl); 1102 if (rctl == NULL) { 1103 /* 1104 * XXX 1105 * This really should not happen. Maybe we should 1106 * use assertion here? But why should we rely on 1107 * hardware to do the correct things? Even the 1108 * reference driver (RT61?) provided by Ralink does 1109 * not provide enough clue that this kind of interrupt 1110 * is promised to be generated for each packet. So 1111 * just print a message and keep going ... 1112 */ 1113 if_printf(ifp, "WARNING: no rate control information\n"); 1114 continue; 1115 } 1116 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link); 1117 1118 retrycnt = 7; 1119 switch (result) { 1120 case RT2661_TX_SUCCESS: 1121 retrycnt = RT2661_TX_RETRYCNT(val); 1122 DPRINTFN(10, ("data frame sent successfully after " 1123 "%d retries\n", retrycnt)); 1124 break; 1125 1126 case RT2661_TX_RETRY_FAIL: 1127 DPRINTFN(9, ("sending data frame failed (too much " 1128 "retries)\n")); 1129 break; 1130 1131 default: 1132 /* other failure */ 1133 device_printf(sc->sc_dev, 1134 "sending data frame failed 0x%08x\n", val); 1135 break; 1136 } 1137 1138 res.rc_res_rateidx = rctl->rateidx; 1139 res.rc_res_tries = retrycnt + 1; 1140 ieee80211_ratectl_tx_complete(rctl->ni, rctl->len, &res, 1, 1141 retrycnt, 0, result != RT2661_TX_SUCCESS); 1142 1143 ieee80211_free_node(rctl->ni); 1144 rctl->ni = NULL; 1145 kfree(rctl, M_RT2661); 1146 } 1147 } 1148 1149 static void 1150 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1151 { 1152 struct rt2661_tx_desc *desc; 1153 struct rt2661_data *data; 1154 1155 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1156 1157 for (;;) { 1158 desc = &txq->desc[txq->next]; 1159 data = &txq->data[txq->next]; 1160 1161 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1162 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1163 break; 1164 1165 bus_dmamap_sync(txq->data_dmat, data->map, 1166 BUS_DMASYNC_POSTWRITE); 1167 bus_dmamap_unload(txq->data_dmat, data->map); 1168 m_freem(data->m); 1169 data->m = NULL; 1170 1171 /* descriptor is no longer valid */ 1172 desc->flags &= ~htole32(RT2661_TX_VALID); 1173 1174 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1175 1176 txq->queued--; 1177 if (++txq->next >= txq->count) /* faster than % count */ 1178 txq->next = 0; 1179 } 1180 1181 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1182 1183 if (txq->queued < txq->count) { 1184 struct ifnet *ifp = &sc->sc_ic.ic_if; 1185 1186 sc->sc_tx_timer = 0; 1187 ifp->if_flags &= ~IFF_OACTIVE; 1188 rt2661_start(ifp); 1189 } 1190 } 1191 1192 static void 1193 rt2661_rx_intr(struct rt2661_softc *sc) 1194 { 1195 struct ieee80211com *ic = &sc->sc_ic; 1196 struct ifnet *ifp = ic->ic_ifp; 1197 struct rt2661_rx_desc *desc; 1198 struct rt2661_data *data; 1199 bus_addr_t physaddr; 1200 struct ieee80211_frame_min *wh; 1201 struct ieee80211_node *ni; 1202 struct mbuf *mnew, *m; 1203 int error; 1204 1205 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1206 BUS_DMASYNC_POSTREAD); 1207 1208 for (;;) { 1209 uint32_t flags; 1210 int rssi; 1211 1212 desc = &sc->rxq.desc[sc->rxq.cur]; 1213 data = &sc->rxq.data[sc->rxq.cur]; 1214 flags = le32toh(desc->flags); 1215 1216 if (flags & RT2661_RX_BUSY) 1217 break; 1218 1219 if (flags & RT2661_RX_CRC_ERROR) { 1220 /* 1221 * This should not happen since we did not request 1222 * to receive those frames when we filled TXRX_CSR0. 1223 */ 1224 DPRINTFN(5, ("CRC error flags 0x%08x\n", flags)); 1225 ifp->if_ierrors++; 1226 goto skip; 1227 } 1228 1229 if (flags & RT2661_RX_CIPHER_MASK) { 1230 DPRINTFN(5, ("cipher error 0x%08x\n", flags)); 1231 ifp->if_ierrors++; 1232 goto skip; 1233 } 1234 1235 /* 1236 * Try to allocate a new mbuf for this ring element and load it 1237 * before processing the current mbuf. If the ring element 1238 * cannot be loaded, drop the received packet and reuse the old 1239 * mbuf. In the unlikely case that the old mbuf can't be 1240 * reloaded either, explicitly panic. 1241 */ 1242 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1243 if (mnew == NULL) { 1244 ifp->if_ierrors++; 1245 goto skip; 1246 } 1247 1248 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1249 BUS_DMASYNC_POSTREAD); 1250 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1251 1252 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1253 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1254 &physaddr, 0); 1255 if (error != 0) { 1256 m_freem(mnew); 1257 1258 /* try to reload the old mbuf */ 1259 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1260 mtod(data->m, void *), MCLBYTES, 1261 rt2661_dma_map_addr, &physaddr, 0); 1262 if (error != 0) { 1263 /* very unlikely that it will fail... */ 1264 panic("%s: could not load old rx mbuf", 1265 device_get_name(sc->sc_dev)); 1266 } 1267 ifp->if_ierrors++; 1268 goto skip; 1269 } 1270 1271 /* 1272 * New mbuf successfully loaded, update Rx ring and continue 1273 * processing. 1274 */ 1275 m = data->m; 1276 data->m = mnew; 1277 desc->physaddr = htole32(physaddr); 1278 1279 /* finalize mbuf */ 1280 m->m_pkthdr.rcvif = ifp; 1281 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 1282 1283 rssi = rt2661_get_rssi(sc, desc->rssi, 0); 1284 if (sc->rf_rev == RT2661_RF_2529) 1285 rt2661_get_rssi(sc, desc->rssi, 1); 1286 1287 wh = mtod(m, struct ieee80211_frame_min *); 1288 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1289 DPRINTFN(5, ("keyix %d\n", RT2661_RX_KEYIX(flags))); 1290 1291 ni = ieee80211_find_rxnode(ic, wh); 1292 1293 /* Error happened during RSSI conversion. */ 1294 if (rssi < 0) 1295 rssi = ni->ni_rssi; 1296 1297 if (sc->sc_drvbpf != NULL) { 1298 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1299 uint32_t tsf_lo, tsf_hi; 1300 1301 /* get timestamp (low and high 32 bits) */ 1302 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1303 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1304 1305 tap->wr_tsf = 1306 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1307 tap->wr_flags = 0; 1308 tap->wr_rate = rt2661_rxrate(desc); 1309 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1310 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1311 tap->wr_antsignal = rssi; 1312 1313 bpf_ptap(sc->sc_drvbpf, m, tap, sc->sc_rxtap_len); 1314 } 1315 1316 /* send the frame to the 802.11 layer */ 1317 if (RT2661_RX_CIPHER(flags) != RT2661_CIPHER_NONE) { 1318 struct ieee80211_crypto_iv iv; 1319 1320 memcpy(iv.ic_iv, desc->iv, sizeof(iv.ic_iv)); 1321 memcpy(iv.ic_eiv, desc->eiv, sizeof(iv.ic_eiv)); 1322 ieee80211_input_withiv(ic, m, ni, rssi, 0, &iv); 1323 } else { 1324 ieee80211_input(ic, m, ni, rssi, 0); 1325 } 1326 1327 /* node is no longer needed */ 1328 ieee80211_free_node(ni); 1329 1330 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1331 1332 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1333 1334 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1335 } 1336 1337 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1338 BUS_DMASYNC_PREWRITE); 1339 } 1340 1341 /* ARGSUSED */ 1342 static void 1343 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1344 { 1345 /* do nothing */ 1346 } 1347 1348 static void 1349 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1350 { 1351 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1352 1353 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1354 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1355 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1356 1357 /* send wakeup command to MCU */ 1358 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1359 } 1360 1361 static void 1362 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1363 { 1364 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1365 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1366 } 1367 1368 static void 1369 rt2661_intr(void *arg) 1370 { 1371 struct rt2661_softc *sc = arg; 1372 struct ifnet *ifp = &sc->sc_ic.ic_if; 1373 uint32_t r1, r2; 1374 1375 /* disable MAC and MCU interrupts */ 1376 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1377 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1378 1379 /* don't re-enable interrupts if we're shutting down */ 1380 if (!(ifp->if_flags & IFF_RUNNING)) 1381 return; 1382 1383 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1384 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1385 1386 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1387 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1388 1389 if (r1 & RT2661_MGT_DONE) 1390 rt2661_tx_dma_intr(sc, &sc->mgtq); 1391 1392 if (r1 & RT2661_RX_DONE) 1393 rt2661_rx_intr(sc); 1394 1395 if (r1 & RT2661_TX0_DMA_DONE) 1396 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1397 1398 if (r1 & RT2661_TX1_DMA_DONE) 1399 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1400 1401 if (r1 & RT2661_TX2_DMA_DONE) 1402 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1403 1404 if (r1 & RT2661_TX3_DMA_DONE) 1405 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1406 1407 if (r1 & RT2661_TX_DONE) 1408 rt2661_tx_intr(sc); 1409 1410 if (r2 & RT2661_MCU_CMD_DONE) 1411 rt2661_mcu_cmd_intr(sc); 1412 1413 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1414 rt2661_mcu_beacon_expire(sc); 1415 1416 if (r2 & RT2661_MCU_WAKEUP) 1417 rt2661_mcu_wakeup(sc); 1418 1419 /* re-enable MAC and MCU interrupts */ 1420 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1421 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1422 } 1423 1424 /* quickly determine if a given rate is CCK or OFDM */ 1425 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1426 1427 #define RAL_ACK_SIZE (sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) 1428 #define RAL_CTS_SIZE (sizeof(struct ieee80211_frame_cts) + IEEE80211_CRC_LEN) 1429 1430 /* 1431 * This function is only used by the Rx radiotap code. It returns the rate at 1432 * which a given frame was received. 1433 */ 1434 static uint8_t 1435 rt2661_rxrate(struct rt2661_rx_desc *desc) 1436 { 1437 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1438 /* reverse function of rt2661_plcp_signal */ 1439 switch (desc->rate & 0xf) { 1440 case 0xb: return 12; 1441 case 0xf: return 18; 1442 case 0xa: return 24; 1443 case 0xe: return 36; 1444 case 0x9: return 48; 1445 case 0xd: return 72; 1446 case 0x8: return 96; 1447 case 0xc: return 108; 1448 } 1449 } else { 1450 if (desc->rate == 10) 1451 return 2; 1452 if (desc->rate == 20) 1453 return 4; 1454 if (desc->rate == 55) 1455 return 11; 1456 if (desc->rate == 110) 1457 return 22; 1458 } 1459 return 2; /* should not get there */ 1460 } 1461 1462 static uint8_t 1463 rt2661_plcp_signal(int rate) 1464 { 1465 switch (rate) { 1466 /* CCK rates (returned values are device-dependent) */ 1467 case 2: return 0x0; 1468 case 4: return 0x1; 1469 case 11: return 0x2; 1470 case 22: return 0x3; 1471 1472 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1473 case 12: return 0xb; 1474 case 18: return 0xf; 1475 case 24: return 0xa; 1476 case 36: return 0xe; 1477 case 48: return 0x9; 1478 case 72: return 0xd; 1479 case 96: return 0x8; 1480 case 108: return 0xc; 1481 1482 /* unsupported rates (should not get there) */ 1483 default: return 0xff; 1484 } 1485 } 1486 1487 static void 1488 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1489 uint32_t flags, uint16_t xflags, int len, int rate, 1490 const bus_dma_segment_t *segs, int nsegs, int ac, int ratectl, 1491 const struct ieee80211_key *key, void *buf, 1492 const struct ieee80211_crypto_iv *iv) 1493 { 1494 const struct ieee80211_cipher *cip = NULL; 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 uint16_t plcp_length; 1497 int i, remainder; 1498 1499 if (key != NULL) 1500 cip = key->wk_cipher; 1501 1502 desc->flags = htole32(flags); 1503 desc->flags |= htole32(len << 16); 1504 desc->flags |= htole32(RT2661_TX_VALID); 1505 if (key != NULL) { 1506 int cipher = rt2661_cipher(key); 1507 1508 desc->flags |= htole32(cipher << 29); 1509 desc->flags |= htole32(key->wk_keyix << 10); 1510 if (key->wk_keyix >= IEEE80211_WEP_NKID) 1511 desc->flags |= htole32(RT2661_TX_PAIRWISE_KEY); 1512 1513 /* XXX fragmentation */ 1514 desc->flags |= htole32(RT2661_TX_HWMIC); 1515 } 1516 1517 desc->xflags = htole16(xflags); 1518 desc->xflags |= htole16(nsegs << 13); 1519 if (key != NULL) { 1520 int hdrsize; 1521 1522 hdrsize = ieee80211_hdrspace(ic, buf); 1523 desc->xflags |= htole16(hdrsize); 1524 } 1525 1526 desc->wme = htole16( 1527 RT2661_QID(ac) | 1528 RT2661_AIFSN(2) | 1529 RT2661_LOGCWMIN(4) | 1530 RT2661_LOGCWMAX(10)); 1531 1532 if (key != NULL && iv != NULL) { 1533 memcpy(desc->iv, iv->ic_iv, sizeof(desc->iv)); 1534 memcpy(desc->eiv, iv->ic_eiv, sizeof(desc->eiv)); 1535 } 1536 1537 /* 1538 * Remember whether TX rate control information should be gathered. 1539 * This field is driver private data only. It will be made available 1540 * by the NIC in STA_CSR4 on Tx done interrupts. 1541 */ 1542 desc->qid = ratectl; 1543 1544 /* setup PLCP fields */ 1545 desc->plcp_signal = rt2661_plcp_signal(rate); 1546 desc->plcp_service = 4; 1547 1548 len += IEEE80211_CRC_LEN; 1549 if (cip != NULL) { 1550 len += cip->ic_header + cip->ic_trailer; 1551 1552 /* XXX fragmentation */ 1553 len += cip->ic_miclen; 1554 } 1555 1556 if (RAL_RATE_IS_OFDM(rate)) { 1557 desc->flags |= htole32(RT2661_TX_OFDM); 1558 1559 plcp_length = len & 0xfff; 1560 desc->plcp_length_hi = plcp_length >> 6; 1561 desc->plcp_length_lo = plcp_length & 0x3f; 1562 } else { 1563 plcp_length = (16 * len + rate - 1) / rate; 1564 if (rate == 22) { 1565 remainder = (16 * len) % 22; 1566 if (remainder != 0 && remainder < 7) 1567 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1568 } 1569 desc->plcp_length_hi = plcp_length >> 8; 1570 desc->plcp_length_lo = plcp_length & 0xff; 1571 1572 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1573 desc->plcp_signal |= 0x08; 1574 } 1575 1576 /* RT2x61 supports scatter with up to 5 segments */ 1577 for (i = 0; i < nsegs; i++) { 1578 desc->addr[i] = htole32(segs[i].ds_addr); 1579 desc->len [i] = htole16(segs[i].ds_len); 1580 } 1581 1582 desc->flags |= htole32(RT2661_TX_BUSY); 1583 } 1584 1585 static int 1586 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1587 struct ieee80211_node *ni) 1588 { 1589 struct ieee80211com *ic = &sc->sc_ic; 1590 struct rt2661_tx_desc *desc; 1591 struct rt2661_data *data; 1592 struct ieee80211_frame *wh; 1593 struct rt2661_dmamap map; 1594 uint16_t dur; 1595 uint32_t flags = 0; /* XXX HWSEQ */ 1596 int rate, error; 1597 1598 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1599 data = &sc->mgtq.data[sc->mgtq.cur]; 1600 1601 /* send mgt frames at the lowest available rate */ 1602 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1603 1604 error = bus_dmamap_load_mbuf(sc->mgtq.data_dmat, data->map, m0, 1605 rt2661_dma_map_mbuf, &map, 0); 1606 if (error != 0) { 1607 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1608 error); 1609 ieee80211_free_node(ni); 1610 m_freem(m0); 1611 return error; 1612 } 1613 1614 if (sc->sc_drvbpf != NULL) { 1615 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1616 1617 tap->wt_flags = 0; 1618 tap->wt_rate = rate; 1619 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1620 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1621 1622 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1623 } 1624 1625 data->m = m0; 1626 1627 wh = mtod(m0, struct ieee80211_frame *); 1628 1629 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1630 flags |= RT2661_TX_NEED_ACK; 1631 1632 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, rate, ic->ic_flags) + 1633 sc->sc_sifs; 1634 *(uint16_t *)wh->i_dur = htole16(dur); 1635 1636 /* tell hardware to add timestamp in probe responses */ 1637 if ((wh->i_fc[0] & 1638 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1639 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1640 flags |= RT2661_TX_TIMESTAMP; 1641 } 1642 1643 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1644 m0->m_pkthdr.len, rate, map.segs, map.nseg, RT2661_QID_MGT, 0, NULL, NULL, NULL); 1645 1646 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1647 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1648 BUS_DMASYNC_PREWRITE); 1649 1650 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1651 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1652 1653 /* kick mgt */ 1654 sc->mgtq.queued++; 1655 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1656 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1657 1658 ieee80211_free_node(ni); 1659 1660 return 0; 1661 } 1662 1663 /* 1664 * Build a RTS control frame. 1665 */ 1666 static struct mbuf * 1667 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1668 uint16_t dur) 1669 { 1670 struct ieee80211_frame_rts *rts; 1671 struct mbuf *m; 1672 1673 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1674 if (m == NULL) { 1675 sc->sc_ic.ic_stats.is_tx_nobuf++; 1676 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1677 return NULL; 1678 } 1679 1680 rts = mtod(m, struct ieee80211_frame_rts *); 1681 1682 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1683 IEEE80211_FC0_SUBTYPE_RTS; 1684 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1685 *(uint16_t *)rts->i_dur = htole16(dur); 1686 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1687 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1688 1689 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1690 1691 return m; 1692 } 1693 1694 static int 1695 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1696 struct ieee80211_node *ni, int ac) 1697 { 1698 struct ieee80211com *ic = &sc->sc_ic; 1699 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1700 struct rt2661_tx_desc *desc; 1701 struct rt2661_data *data; 1702 struct rt2661_tx_ratectl *rctl; 1703 struct ieee80211_frame *wh; 1704 struct ieee80211_key *k = NULL; 1705 const struct chanAccParams *cap; 1706 struct mbuf *mnew; 1707 struct rt2661_dmamap map; 1708 uint16_t dur; 1709 uint32_t flags = 0; 1710 int error, rate, ackrate, noack = 0, rateidx; 1711 struct ieee80211_crypto_iv iv, *ivp = NULL; 1712 1713 wh = mtod(m0, struct ieee80211_frame *); 1714 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1715 cap = &ic->ic_wme.wme_chanParams; 1716 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1717 } 1718 1719 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1720 k = ieee80211_crypto_findkey(ic, ni, m0); 1721 if (k == NULL) { 1722 m_freem(m0); 1723 return ENOBUFS; 1724 } 1725 1726 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1727 k = ieee80211_crypto_encap_withkey(ic, m0, k); 1728 } else { 1729 k = ieee80211_crypto_getiv(ic, &iv, k); 1730 ivp = &iv; 1731 } 1732 if (k == NULL) { 1733 m_freem(m0); 1734 return ENOBUFS; 1735 } 1736 1737 if (ivp == NULL) 1738 k = NULL; 1739 1740 /* packet header may have moved, reset our local pointer */ 1741 wh = mtod(m0, struct ieee80211_frame *); 1742 } 1743 1744 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len, &rateidx, 1); 1745 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx); 1746 1747 ackrate = ieee80211_ack_rate(ni, rate); 1748 1749 /* 1750 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1751 * for directed frames only when the length of the MPDU is greater 1752 * than the length threshold indicated by [...]" ic_rtsthreshold. 1753 */ 1754 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1755 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1756 struct mbuf *m; 1757 uint16_t dur; 1758 int rtsrate; 1759 1760 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1761 1762 /* XXX: noack (QoS)? */ 1763 dur = ieee80211_txtime(ni, m0->m_pkthdr.len + IEEE80211_CRC_LEN, 1764 rate, ic->ic_flags) + 1765 ieee80211_txtime(ni, RAL_CTS_SIZE, rtsrate, ic->ic_flags)+ 1766 ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+ 1767 3 * sc->sc_sifs; 1768 1769 m = rt2661_get_rts(sc, wh, dur); 1770 1771 desc = &txq->desc[txq->cur]; 1772 data = &txq->data[txq->cur]; 1773 1774 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m, 1775 rt2661_dma_map_mbuf, &map, 0); 1776 if (error != 0) { 1777 device_printf(sc->sc_dev, 1778 "could not map mbuf (error %d)\n", error); 1779 m_freem(m); 1780 m_freem(m0); 1781 return error; 1782 } 1783 1784 data->m = m; 1785 1786 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1787 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, 1788 rtsrate, map.segs, map.nseg, ac, 0, NULL, NULL, NULL); 1789 1790 bus_dmamap_sync(txq->data_dmat, data->map, 1791 BUS_DMASYNC_PREWRITE); 1792 1793 txq->queued++; 1794 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1795 1796 /* 1797 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1798 * asynchronous data frame shall be transmitted after the CTS 1799 * frame and a SIFS period. 1800 */ 1801 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1802 } 1803 1804 data = &txq->data[txq->cur]; 1805 desc = &txq->desc[txq->cur]; 1806 1807 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1808 rt2661_dma_map_mbuf, &map, 0); 1809 if (error != 0 && error != EFBIG) { 1810 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1811 error); 1812 m_freem(m0); 1813 return error; 1814 } 1815 if (error != 0) { 1816 mnew = m_defrag(m0, MB_DONTWAIT); 1817 if (mnew == NULL) { 1818 device_printf(sc->sc_dev, 1819 "could not defragment mbuf\n"); 1820 m_freem(m0); 1821 return ENOBUFS; 1822 } 1823 m0 = mnew; 1824 1825 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1826 rt2661_dma_map_mbuf, &map, 0); 1827 if (error != 0) { 1828 device_printf(sc->sc_dev, 1829 "could not map mbuf (error %d)\n", error); 1830 m_freem(m0); 1831 return error; 1832 } 1833 1834 /* packet header have moved, reset our local pointer */ 1835 wh = mtod(m0, struct ieee80211_frame *); 1836 } 1837 1838 if (sc->sc_drvbpf != NULL) { 1839 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1840 1841 tap->wt_flags = 0; 1842 tap->wt_rate = rate; 1843 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1844 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1845 1846 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1847 } 1848 1849 data->m = m0; 1850 1851 rctl = kmalloc(sizeof(*rctl), M_RT2661, M_NOWAIT); 1852 if (rctl != NULL) { 1853 rctl->ni = ni; 1854 rctl->len = m0->m_pkthdr.len; 1855 rctl->rateidx = rateidx; 1856 STAILQ_INSERT_TAIL(&sc->tx_ratectl, rctl, link); 1857 } 1858 1859 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1860 flags |= RT2661_TX_NEED_ACK; 1861 1862 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+ 1863 sc->sc_sifs; 1864 *(uint16_t *)wh->i_dur = htole16(dur); 1865 } 1866 1867 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1868 map.segs, map.nseg, ac, rctl != NULL, k, wh, ivp); 1869 1870 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1871 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1872 1873 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1874 m0->m_pkthdr.len, txq->cur, rate)); 1875 1876 /* kick Tx */ 1877 txq->queued++; 1878 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1879 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1880 1881 if (rctl == NULL) 1882 ieee80211_free_node(ni); 1883 1884 return 0; 1885 } 1886 1887 static void 1888 rt2661_start(struct ifnet *ifp) 1889 { 1890 struct rt2661_softc *sc = ifp->if_softc; 1891 struct ieee80211com *ic = &sc->sc_ic; 1892 struct mbuf *m0; 1893 struct ether_header *eh; 1894 struct ieee80211_node *ni; 1895 int ac; 1896 1897 /* prevent management frames from being sent if we're not ready */ 1898 if (!(ifp->if_flags & IFF_RUNNING)) 1899 return; 1900 1901 for (;;) { 1902 IF_POLL(&ic->ic_mgtq, m0); 1903 if (m0 != NULL) { 1904 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1905 ifp->if_flags |= IFF_OACTIVE; 1906 break; 1907 } 1908 IF_DEQUEUE(&ic->ic_mgtq, m0); 1909 1910 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1911 m0->m_pkthdr.rcvif = NULL; 1912 1913 if (ic->ic_rawbpf != NULL) 1914 bpf_mtap(ic->ic_rawbpf, m0); 1915 1916 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1917 break; 1918 } else { 1919 if (ic->ic_state != IEEE80211_S_RUN) 1920 break; 1921 1922 m0 = ifq_dequeue(&ifp->if_snd, NULL); 1923 if (m0 == NULL) 1924 break; 1925 1926 if (m0->m_len < sizeof (struct ether_header) && 1927 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1928 continue; 1929 1930 eh = mtod(m0, struct ether_header *); 1931 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1932 if (ni == NULL) { 1933 m_freem(m0); 1934 ifp->if_oerrors++; 1935 continue; 1936 } 1937 1938 /* classify mbuf so we can find which tx ring to use */ 1939 if (ieee80211_classify(ic, m0, ni) != 0) { 1940 m_freem(m0); 1941 ieee80211_free_node(ni); 1942 ifp->if_oerrors++; 1943 continue; 1944 } 1945 1946 /* no QoS encapsulation for EAPOL frames */ 1947 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1948 M_WME_GETAC(m0) : WME_AC_BE; 1949 1950 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1951 /* there is no place left in this ring */ 1952 ifp->if_flags |= IFF_OACTIVE; 1953 m_freem(m0); 1954 ieee80211_free_node(ni); 1955 break; 1956 } 1957 1958 BPF_MTAP(ifp, m0); 1959 1960 m0 = ieee80211_encap(ic, m0, ni); 1961 if (m0 == NULL) { 1962 ieee80211_free_node(ni); 1963 ifp->if_oerrors++; 1964 continue; 1965 } 1966 1967 if (ic->ic_rawbpf != NULL) 1968 bpf_mtap(ic->ic_rawbpf, m0); 1969 1970 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1971 ieee80211_free_node(ni); 1972 ifp->if_oerrors++; 1973 break; 1974 } 1975 } 1976 1977 sc->sc_tx_timer = 5; 1978 ifp->if_timer = 1; 1979 } 1980 } 1981 1982 static void 1983 rt2661_watchdog(struct ifnet *ifp) 1984 { 1985 struct rt2661_softc *sc = ifp->if_softc; 1986 struct ieee80211com *ic = &sc->sc_ic; 1987 1988 ifp->if_timer = 0; 1989 1990 if (sc->sc_tx_timer > 0) { 1991 if (--sc->sc_tx_timer == 0) { 1992 device_printf(sc->sc_dev, "device timeout\n"); 1993 rt2661_init(sc); 1994 ifp->if_oerrors++; 1995 return; 1996 } 1997 ifp->if_timer = 1; 1998 } 1999 2000 ieee80211_watchdog(ic); 2001 } 2002 2003 /* 2004 * This function allows for fast channel switching in monitor mode (used by 2005 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 2006 * generate a new beacon frame. 2007 */ 2008 static int 2009 rt2661_reset(struct ifnet *ifp) 2010 { 2011 struct rt2661_softc *sc = ifp->if_softc; 2012 struct ieee80211com *ic = &sc->sc_ic; 2013 2014 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2015 return ENETRESET; 2016 2017 rt2661_set_chan(sc, ic->ic_curchan); 2018 2019 return 0; 2020 } 2021 2022 static int 2023 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2024 { 2025 struct rt2661_softc *sc = ifp->if_softc; 2026 struct ieee80211com *ic = &sc->sc_ic; 2027 int error = 0; 2028 2029 switch (cmd) { 2030 case SIOCSIFFLAGS: 2031 if (ifp->if_flags & IFF_UP) { 2032 if (ifp->if_flags & IFF_RUNNING) 2033 rt2661_update_promisc(sc); 2034 else 2035 rt2661_init(sc); 2036 } else { 2037 if (ifp->if_flags & IFF_RUNNING) 2038 rt2661_stop(sc); 2039 } 2040 break; 2041 2042 default: 2043 error = ieee80211_ioctl(ic, cmd, data, cr); 2044 } 2045 2046 if (error == ENETRESET) { 2047 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2048 (IFF_UP | IFF_RUNNING) && 2049 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2050 rt2661_init(sc); 2051 error = 0; 2052 } 2053 return error; 2054 } 2055 2056 static void 2057 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2058 { 2059 uint32_t tmp; 2060 int ntries; 2061 2062 for (ntries = 0; ntries < 100; ntries++) { 2063 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2064 break; 2065 DELAY(1); 2066 } 2067 if (ntries == 100) { 2068 device_printf(sc->sc_dev, "could not write to BBP\n"); 2069 return; 2070 } 2071 2072 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2073 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2074 2075 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2076 2077 /* XXX */ 2078 if (reg == 17) { 2079 DPRINTF(("record bbp17 %#x\n", val)); 2080 sc->bbp17 = val; 2081 } 2082 } 2083 2084 static uint8_t 2085 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2086 { 2087 uint32_t val; 2088 int ntries; 2089 2090 for (ntries = 0; ntries < 100; ntries++) { 2091 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2092 break; 2093 DELAY(1); 2094 } 2095 if (ntries == 100) { 2096 device_printf(sc->sc_dev, "could not read from BBP\n"); 2097 return 0; 2098 } 2099 2100 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2101 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2102 2103 for (ntries = 0; ntries < 100; ntries++) { 2104 val = RAL_READ(sc, RT2661_PHY_CSR3); 2105 if (!(val & RT2661_BBP_BUSY)) 2106 return val & 0xff; 2107 DELAY(1); 2108 } 2109 2110 device_printf(sc->sc_dev, "could not read from BBP\n"); 2111 return 0; 2112 } 2113 2114 static void 2115 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2116 { 2117 uint32_t tmp; 2118 int ntries; 2119 2120 for (ntries = 0; ntries < 100; ntries++) { 2121 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2122 break; 2123 DELAY(1); 2124 } 2125 if (ntries == 100) { 2126 device_printf(sc->sc_dev, "could not write to RF\n"); 2127 return; 2128 } 2129 2130 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2131 (reg & 3); 2132 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2133 2134 /* remember last written value in sc */ 2135 sc->rf_regs[reg] = val; 2136 2137 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2138 } 2139 2140 static int 2141 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2142 { 2143 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2144 return EIO; /* there is already a command pending */ 2145 2146 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2147 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2148 2149 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2150 2151 return 0; 2152 } 2153 2154 static void 2155 rt2661_select_antenna(struct rt2661_softc *sc) 2156 { 2157 uint8_t bbp4, bbp77; 2158 uint32_t tmp; 2159 2160 bbp4 = rt2661_bbp_read(sc, 4); 2161 bbp77 = rt2661_bbp_read(sc, 77); 2162 2163 /* TBD */ 2164 2165 /* make sure Rx is disabled before switching antenna */ 2166 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2167 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2168 2169 rt2661_bbp_write(sc, 4, bbp4); 2170 rt2661_bbp_write(sc, 77, bbp77); 2171 2172 /* restore Rx filter */ 2173 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2174 } 2175 2176 /* 2177 * Enable multi-rate retries for frames sent at OFDM rates. 2178 * In 802.11b/g mode, allow fallback to CCK rates. 2179 */ 2180 static void 2181 rt2661_enable_mrr(struct rt2661_softc *sc) 2182 { 2183 struct ieee80211com *ic = &sc->sc_ic; 2184 uint32_t tmp; 2185 2186 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2187 2188 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2189 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2190 tmp |= RT2661_MRR_CCK_FALLBACK; 2191 tmp |= RT2661_MRR_ENABLED; 2192 tmp |= RT2661_SRETRY_LIMIT(7) | RT2661_LRETRY_LIMIT(4); 2193 2194 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2195 } 2196 2197 static void 2198 rt2661_set_txpreamble(struct rt2661_softc *sc) 2199 { 2200 uint32_t tmp; 2201 2202 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2203 2204 tmp &= ~RT2661_SHORT_PREAMBLE; 2205 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2206 tmp |= RT2661_SHORT_PREAMBLE; 2207 2208 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2209 } 2210 2211 static void 2212 rt2661_set_ackrates(struct rt2661_softc *sc, const struct ieee80211_rateset *rs) 2213 { 2214 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2215 struct ieee80211com *ic = &sc->sc_ic; 2216 uint32_t mask = 0; 2217 uint8_t rate; 2218 int i, j; 2219 2220 for (i = 0; i < rs->rs_nrates; i++) { 2221 rate = rs->rs_rates[i]; 2222 2223 if (!(rate & IEEE80211_RATE_BASIC)) 2224 continue; 2225 2226 /* 2227 * Find h/w rate index. We know it exists because the rate 2228 * set has already been negotiated. 2229 */ 2230 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++) 2231 ; /* EMPTY */ 2232 2233 mask |= 1 << j; 2234 } 2235 2236 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) && 2237 ic->ic_curmode != IEEE80211_MODE_11B && 2238 ieee80211_iserp_rateset(ic, rs)) { 2239 /* 2240 * Always set following rates as ACK rates to conform 2241 * IEEE Std 802.11g-2003 clause 9.6 2242 * 2243 * 24Mbits/s 0x100 2244 * 12Mbits/s 0x040 2245 * 6Mbits/s 0x010 2246 */ 2247 mask |= 0x150; 2248 } 2249 2250 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2251 2252 DPRINTF(("Setting ack rate mask to 0x%x\n", mask)); 2253 #undef RV 2254 } 2255 2256 /* 2257 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2258 * driver. 2259 */ 2260 static void 2261 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2262 { 2263 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2264 uint32_t tmp; 2265 2266 /* update all BBP registers that depend on the band */ 2267 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2268 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2269 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2270 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2271 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2272 } 2273 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2274 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2275 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2276 } 2277 2278 rt2661_bbp_write(sc, 17, bbp17); 2279 rt2661_bbp_write(sc, 96, bbp96); 2280 rt2661_bbp_write(sc, 104, bbp104); 2281 2282 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2283 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2284 rt2661_bbp_write(sc, 75, 0x80); 2285 rt2661_bbp_write(sc, 86, 0x80); 2286 rt2661_bbp_write(sc, 88, 0x80); 2287 } 2288 2289 rt2661_bbp_write(sc, 35, bbp35); 2290 rt2661_bbp_write(sc, 97, bbp97); 2291 rt2661_bbp_write(sc, 98, bbp98); 2292 2293 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2294 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2295 if (IEEE80211_IS_CHAN_2GHZ(c)) 2296 tmp |= RT2661_PA_PE_2GHZ; 2297 else 2298 tmp |= RT2661_PA_PE_5GHZ; 2299 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2300 } 2301 2302 static void 2303 rt2661_set_txpower(struct rt2661_softc *sc, int8_t power) 2304 { 2305 const struct rt2661_rfprog *rfprog = sc->rfprog; 2306 int i = sc->sc_curchan_idx; 2307 2308 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2309 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2310 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2311 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2312 2313 DELAY(200); 2314 2315 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2316 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2317 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2318 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2319 2320 DELAY(200); 2321 2322 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2323 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2324 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2325 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2326 2327 sc->sc_txpwr = power; 2328 } 2329 2330 static void 2331 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2332 { 2333 struct ieee80211com *ic = &sc->sc_ic; 2334 const struct rt2661_rfprog *rfprog = sc->rfprog; 2335 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2336 int8_t power; 2337 u_int i, chan; 2338 2339 chan = ieee80211_chan2ieee(ic, c); 2340 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2341 return; 2342 2343 /* find the settings for this channel (we know it exists) */ 2344 for (i = 0; rfprog[i].chan != chan; i++) 2345 ; /* EMPTY */ 2346 KASSERT(i < RT2661_NCHAN_MAX, ("invalid channel %d\n", chan)); 2347 sc->sc_curchan_idx = i; 2348 2349 power = sc->txpow[i]; 2350 if (power < 0) { 2351 bbp94 += power; 2352 power = 0; 2353 } else if (power > 31) { 2354 bbp94 += power - 31; 2355 power = 31; 2356 } 2357 2358 power = rt2661_txpower(sc, power); 2359 2360 /* 2361 * If we are switching from the 2GHz band to the 5GHz band or 2362 * vice-versa, BBP registers need to be reprogrammed. 2363 */ 2364 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2365 rt2661_select_band(sc, c); 2366 rt2661_select_antenna(sc); 2367 } 2368 sc->sc_curchan = c; 2369 2370 rt2661_set_txpower(sc, power); 2371 2372 /* enable smart mode for MIMO-capable RFs */ 2373 bbp3 = rt2661_bbp_read(sc, 3); 2374 2375 bbp3 &= ~RT2661_SMART_MODE; 2376 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2377 bbp3 |= RT2661_SMART_MODE; 2378 2379 rt2661_bbp_write(sc, 3, bbp3); 2380 2381 if (bbp94 != RT2661_BBPR94_DEFAULT) 2382 rt2661_bbp_write(sc, 94, bbp94); 2383 2384 /* 5GHz radio needs a 1ms delay here */ 2385 if (IEEE80211_IS_CHAN_5GHZ(c)) 2386 DELAY(1000); 2387 2388 sc->sc_sifs = IEEE80211_IS_CHAN_5GHZ(c) ? IEEE80211_DUR_OFDM_SIFS 2389 : IEEE80211_DUR_SIFS; 2390 } 2391 2392 static void 2393 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2394 { 2395 uint32_t tmp; 2396 2397 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2398 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2399 2400 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2401 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2402 } 2403 2404 static void 2405 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2406 { 2407 uint32_t tmp; 2408 2409 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2410 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2411 2412 tmp = addr[4] | addr[5] << 8; 2413 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2414 } 2415 2416 static void 2417 rt2661_update_promisc(struct rt2661_softc *sc) 2418 { 2419 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2420 uint32_t tmp; 2421 2422 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2423 2424 tmp &= ~RT2661_DROP_NOT_TO_ME; 2425 if (!(ifp->if_flags & IFF_PROMISC)) 2426 tmp |= RT2661_DROP_NOT_TO_ME; 2427 2428 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2429 2430 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2431 "entering" : "leaving")); 2432 } 2433 2434 /* 2435 * Update QoS (802.11e) settings for each h/w Tx ring. 2436 */ 2437 static int 2438 rt2661_wme_update(struct ieee80211com *ic) 2439 { 2440 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2441 const struct wmeParams *wmep; 2442 2443 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2444 2445 /* XXX: not sure about shifts. */ 2446 /* XXX: the reference driver plays with AC_VI settings too. */ 2447 2448 /* update TxOp */ 2449 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2450 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2451 wmep[WME_AC_BK].wmep_txopLimit); 2452 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2453 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2454 wmep[WME_AC_VO].wmep_txopLimit); 2455 2456 /* update CWmin */ 2457 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2458 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2459 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2460 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2461 wmep[WME_AC_VO].wmep_logcwmin); 2462 2463 /* update CWmax */ 2464 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2465 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2466 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2467 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2468 wmep[WME_AC_VO].wmep_logcwmax); 2469 2470 /* update Aifsn */ 2471 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2472 wmep[WME_AC_BE].wmep_aifsn << 12 | 2473 wmep[WME_AC_BK].wmep_aifsn << 8 | 2474 wmep[WME_AC_VI].wmep_aifsn << 4 | 2475 wmep[WME_AC_VO].wmep_aifsn); 2476 2477 return 0; 2478 } 2479 2480 static void 2481 rt2661_update_slot(struct ifnet *ifp) 2482 { 2483 struct rt2661_softc *sc = ifp->if_softc; 2484 struct ieee80211com *ic = &sc->sc_ic; 2485 uint8_t slottime; 2486 uint32_t tmp; 2487 2488 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2489 2490 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2491 tmp = (tmp & ~0xff) | slottime; 2492 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2493 } 2494 2495 static const char * 2496 rt2661_get_rf(int rev) 2497 { 2498 switch (rev) { 2499 case RT2661_RF_5225: return "RT5225"; 2500 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2501 case RT2661_RF_2527: return "RT2527"; 2502 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2503 default: return "unknown"; 2504 } 2505 } 2506 2507 static void 2508 rt2661_read_config(struct rt2661_softc *sc) 2509 { 2510 struct ieee80211com *ic = &sc->sc_ic; 2511 uint16_t val; 2512 uint8_t rfprog = 0; 2513 int i, start_chan; 2514 2515 /* read MAC address */ 2516 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2517 ic->ic_myaddr[0] = val & 0xff; 2518 ic->ic_myaddr[1] = val >> 8; 2519 2520 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2521 ic->ic_myaddr[2] = val & 0xff; 2522 ic->ic_myaddr[3] = val >> 8; 2523 2524 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2525 ic->ic_myaddr[4] = val & 0xff; 2526 ic->ic_myaddr[5] = val >> 8; 2527 2528 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2529 /* XXX: test if different from 0xffff? */ 2530 sc->rf_rev = (val >> 11) & 0x1f; 2531 sc->hw_radio = (val >> 10) & 0x1; 2532 sc->auto_txagc = (val >> 9) & 0x1; 2533 sc->rx_ant = (val >> 4) & 0x3; 2534 sc->tx_ant = (val >> 2) & 0x3; 2535 sc->nb_ant = val & 0x3; 2536 2537 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2538 DPRINTF(("Number of ant %d, rxant %d, txant %d\n", 2539 sc->nb_ant, sc->rx_ant, sc->tx_ant)); 2540 2541 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2542 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2543 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2544 2545 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2546 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2547 2548 if (sc->ext_2ghz_lna) { 2549 sc->bbp17_2ghz_min = 0x30; 2550 sc->bbp17_2ghz_max = 0x50; 2551 } else { 2552 sc->bbp17_2ghz_min = 0x20; 2553 sc->bbp17_2ghz_max = 0x40; 2554 } 2555 2556 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2557 sc->rssi_2ghz_corr[0] = (int8_t)(val & 0xff); /* signed */ 2558 sc->rssi_2ghz_corr[1] = (int8_t)(val >> 8); /* signed */ 2559 2560 /* Only [-10, 10] is valid */ 2561 for (i = 0; i < 2; ++i) { 2562 if (sc->rssi_2ghz_corr[i] < -10 || sc->rssi_2ghz_corr[i] > 10) 2563 sc->rssi_2ghz_corr[i] = 0; 2564 } 2565 2566 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2567 if ((val & 0xff) != 0xff) 2568 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2569 2570 /* Only [-10, 10] is valid */ 2571 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2572 sc->rssi_5ghz_corr = 0; 2573 2574 /* adjust RSSI correction for external low-noise amplifier */ 2575 if (sc->ext_2ghz_lna) { 2576 sc->rssi_2ghz_corr[0] -= 14; 2577 sc->rssi_2ghz_corr[1] -= 14; 2578 } 2579 if (sc->ext_5ghz_lna) 2580 sc->rssi_5ghz_corr -= 14; 2581 2582 DPRINTF(("RSSI 2GHz corr0=%d corr1=%d\nRSSI 5GHz corr=%d\n", 2583 sc->rssi_2ghz_corr[0], sc->rssi_2ghz_corr[1], sc->rssi_5ghz_corr)); 2584 2585 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2586 if ((val >> 8) != 0xff) 2587 rfprog = (val >> 8) & 0x3; 2588 if ((val & 0xff) != 0xff) 2589 sc->rffreq = val & 0xff; 2590 2591 DPRINTF(("RF prog=%d\nRF freq=%d\n", rfprog, sc->rffreq)); 2592 2593 sc->rfprog = rfprog == 0 ? rt2661_rf5225_1 : rt2661_rf5225_2; 2594 2595 #define NCHAN_2GHZ 14 2596 #define NCHAN_5GHZ 24 2597 /* 2598 * Read channel TX power 2599 */ 2600 start_chan = 0; 2601 rt2661_read_txpower_config(sc, RT2661_EEPROM_TXPOWER_2GHZ, 2602 NCHAN_2GHZ, &start_chan); 2603 rt2661_read_txpower_config(sc, RT2661_EEPROM_TXPOWER_5GHZ, 2604 NCHAN_5GHZ, &start_chan); 2605 #undef NCHAN_2GHZ 2606 #undef NCHAN_5GHZ 2607 2608 /* read vendor-specific BBP values */ 2609 for (i = 0; i < 16; i++) { 2610 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2611 if (val == 0 || val == 0xffff) 2612 continue; /* skip invalid entries */ 2613 sc->bbp_prom[i].reg = val >> 8; 2614 sc->bbp_prom[i].val = val & 0xff; 2615 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2616 sc->bbp_prom[i].val)); 2617 } 2618 2619 val = rt2661_eeprom_read(sc, RT2661_EEPROM_LED_OFFSET); 2620 DPRINTF(("LED %02x\n", val)); 2621 if (val == 0xffff) { 2622 sc->mcu_led = RT2661_MCU_LED_DEFAULT; 2623 } else { 2624 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 2625 2626 for (i = 0; i < N(led_ee2mcu); ++i) { 2627 if (val & led_ee2mcu[i].ee_bit) 2628 sc->mcu_led |= led_ee2mcu[i].mcu_bit; 2629 } 2630 2631 #undef N 2632 2633 sc->mcu_led |= ((val >> RT2661_EE_LED_MODE_SHIFT) & 2634 RT2661_EE_LED_MODE_MASK); 2635 } 2636 2637 /* TX power down step array */ 2638 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI1); 2639 sc->tssi_2ghz_down[3] = val & 0xff; 2640 sc->tssi_2ghz_down[2] = val >> 8; 2641 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI2); 2642 sc->tssi_2ghz_down[1] = val & 0xff; 2643 sc->tssi_2ghz_down[0] = val >> 8; 2644 DPRINTF(("2GHZ tssi down 0:%u 1:%u 2:%u 3:%u\n", 2645 sc->tssi_2ghz_down[0], sc->tssi_2ghz_down[1], 2646 sc->tssi_2ghz_down[2], sc->tssi_2ghz_down[3])); 2647 2648 /* TX power up step array */ 2649 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI3); 2650 sc->tssi_2ghz_up[0] = val & 0xff; 2651 sc->tssi_2ghz_up[1] = val >> 8; 2652 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI4); 2653 sc->tssi_2ghz_up[2] = val & 0xff; 2654 sc->tssi_2ghz_up[3] = val >> 8; 2655 DPRINTF(("2GHZ tssi up 0:%u 1:%u 2:%u 3:%u\n", 2656 sc->tssi_2ghz_up[0], sc->tssi_2ghz_up[1], 2657 sc->tssi_2ghz_up[2], sc->tssi_2ghz_up[3])); 2658 2659 /* TX power adjustment reference value and step */ 2660 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI5); 2661 sc->tssi_2ghz_ref = val & 0xff; 2662 sc->tssi_2ghz_step = val >> 8; 2663 DPRINTF(("2GHZ tssi ref %u, step %d\n", 2664 sc->tssi_2ghz_ref, sc->tssi_2ghz_step)); 2665 2666 if (sc->tssi_2ghz_ref == 0xff) 2667 sc->auto_txagc = 0; 2668 DPRINTF(("Auto TX AGC %d\n", sc->auto_txagc)); 2669 } 2670 2671 static int 2672 rt2661_bbp_init(struct rt2661_softc *sc) 2673 { 2674 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2675 int i, ntries; 2676 uint8_t val; 2677 2678 /* wait for BBP to be ready */ 2679 for (ntries = 0; ntries < 100; ntries++) { 2680 val = rt2661_bbp_read(sc, 0); 2681 if (val != 0 && val != 0xff) 2682 break; 2683 DELAY(100); 2684 } 2685 if (ntries == 100) { 2686 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2687 return EIO; 2688 } 2689 2690 /* initialize BBP registers to default values */ 2691 for (i = 0; i < N(rt2661_def_bbp); i++) { 2692 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2693 rt2661_def_bbp[i].val); 2694 } 2695 2696 /* write vendor-specific BBP values (from EEPROM) */ 2697 for (i = 0; i < 16; i++) { 2698 if (sc->bbp_prom[i].reg == 0) 2699 continue; 2700 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2701 } 2702 2703 return 0; 2704 #undef N 2705 } 2706 2707 static void 2708 rt2661_init(void *priv) 2709 { 2710 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2711 struct rt2661_softc *sc = priv; 2712 struct ieee80211com *ic = &sc->sc_ic; 2713 struct ifnet *ifp = ic->ic_ifp; 2714 uint32_t tmp, sta[3]; 2715 int i, ntries; 2716 2717 rt2661_stop(sc); 2718 2719 /* initialize Tx rings */ 2720 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2721 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2722 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2723 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2724 2725 /* initialize Mgt ring */ 2726 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2727 2728 /* initialize Rx ring */ 2729 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2730 2731 /* initialize Tx rings sizes */ 2732 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2733 RT2661_TX_RING_COUNT << 24 | 2734 RT2661_TX_RING_COUNT << 16 | 2735 RT2661_TX_RING_COUNT << 8 | 2736 RT2661_TX_RING_COUNT); 2737 2738 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2739 RT2661_TX_DESC_WSIZE << 16 | 2740 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2741 RT2661_MGT_RING_COUNT); 2742 2743 /* initialize Rx rings */ 2744 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2745 RT2661_RX_DESC_BACK << 16 | 2746 RT2661_RX_DESC_WSIZE << 8 | 2747 RT2661_RX_RING_COUNT); 2748 2749 /* XXX: some magic here */ 2750 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2751 2752 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2753 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2754 2755 /* load base address of Rx ring */ 2756 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2757 2758 /* initialize MAC registers to default values */ 2759 for (i = 0; i < N(rt2661_def_mac); i++) 2760 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2761 2762 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2763 rt2661_set_macaddr(sc, ic->ic_myaddr); 2764 2765 /* set host ready */ 2766 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2767 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2768 2769 /* wait for BBP/RF to wakeup */ 2770 for (ntries = 0; ntries < 1000; ntries++) { 2771 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2772 break; 2773 DELAY(1000); 2774 } 2775 if (ntries == 1000) { 2776 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2777 rt2661_stop(sc); 2778 return; 2779 } 2780 2781 if (rt2661_bbp_init(sc) != 0) { 2782 rt2661_stop(sc); 2783 return; 2784 } 2785 2786 /* select default channel */ 2787 sc->sc_curchan = ic->ic_curchan; 2788 rt2661_select_band(sc, sc->sc_curchan); 2789 rt2661_select_antenna(sc); 2790 rt2661_set_chan(sc, sc->sc_curchan); 2791 2792 /* update Rx filter */ 2793 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2794 2795 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2796 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2797 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2798 RT2661_DROP_ACKCTS; 2799 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2800 tmp |= RT2661_DROP_TODS; 2801 if (!(ifp->if_flags & IFF_PROMISC)) 2802 tmp |= RT2661_DROP_NOT_TO_ME; 2803 } 2804 2805 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2806 2807 /* clear STA registers */ 2808 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2809 2810 /* initialize ASIC */ 2811 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2812 2813 /* clear any pending interrupt */ 2814 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2815 2816 /* enable interrupts */ 2817 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2818 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2819 2820 /* kick Rx */ 2821 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2822 2823 ifp->if_flags &= ~IFF_OACTIVE; 2824 ifp->if_flags |= IFF_RUNNING; 2825 2826 for (i = 0; i < IEEE80211_WEP_NKID; ++i) { 2827 uint8_t mac[IEEE80211_ADDR_LEN]; 2828 const struct ieee80211_key *k = &ic->ic_nw_keys[i]; 2829 2830 if (k->wk_keyix != IEEE80211_KEYIX_NONE) 2831 rt2661_key_set(ic, k, mac); 2832 } 2833 2834 RT2661_RESET_AVG_RSSI(sc); 2835 2836 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2837 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2838 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2839 } else { 2840 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2841 } 2842 #undef N 2843 } 2844 2845 void 2846 rt2661_stop(void *priv) 2847 { 2848 struct rt2661_softc *sc = priv; 2849 struct ieee80211com *ic = &sc->sc_ic; 2850 struct ifnet *ifp = ic->ic_ifp; 2851 struct rt2661_tx_ratectl *rctl; 2852 uint32_t tmp; 2853 2854 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2855 2856 sc->sc_tx_timer = 0; 2857 ifp->if_timer = 0; 2858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2859 2860 /* abort Tx (for all 5 Tx rings) */ 2861 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2862 2863 /* disable Rx (value remains after reset!) */ 2864 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2865 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2866 2867 /* reset ASIC */ 2868 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2869 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2870 2871 /* disable interrupts */ 2872 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2873 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2874 2875 /* clear any pending interrupt */ 2876 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2877 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2878 2879 while ((rctl = STAILQ_FIRST(&sc->tx_ratectl)) != NULL) { 2880 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link); 2881 ieee80211_free_node(rctl->ni); 2882 rctl->ni = NULL; 2883 kfree(rctl, M_RT2661); 2884 } 2885 2886 /* reset Tx and Rx rings */ 2887 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2888 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2889 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2890 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2891 rt2661_reset_tx_ring(sc, &sc->mgtq); 2892 rt2661_reset_rx_ring(sc, &sc->rxq); 2893 2894 /* Clear key map. */ 2895 bzero(sc->sc_keymap, sizeof(sc->sc_keymap)); 2896 } 2897 2898 static int 2899 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2900 { 2901 int ntries; 2902 2903 /* reset 8051 */ 2904 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2905 2906 /* cancel any pending Host to MCU command */ 2907 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2908 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2909 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2910 2911 /* write 8051's microcode */ 2912 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2913 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2914 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2915 2916 /* kick 8051's ass */ 2917 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2918 2919 /* wait for 8051 to initialize */ 2920 for (ntries = 0; ntries < 500; ntries++) { 2921 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2922 break; 2923 DELAY(100); 2924 } 2925 if (ntries == 500) { 2926 kprintf("timeout waiting for MCU to initialize\n"); 2927 return EIO; 2928 } 2929 return 0; 2930 } 2931 2932 static int 2933 rt2661_prepare_beacon(struct rt2661_softc *sc) 2934 { 2935 struct ieee80211com *ic = &sc->sc_ic; 2936 struct ieee80211_beacon_offsets bo; 2937 struct rt2661_tx_desc desc; 2938 struct mbuf *m0; 2939 int rate; 2940 2941 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2942 if (m0 == NULL) { 2943 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2944 return ENOBUFS; 2945 } 2946 2947 /* send beacons at the lowest available rate */ 2948 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2949 2950 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2951 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT, 0, NULL, NULL, NULL); 2952 2953 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2954 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2955 2956 /* copy beacon header and payload into NIC memory */ 2957 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2958 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2959 2960 m_freem(m0); 2961 return 0; 2962 } 2963 2964 /* 2965 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2966 * and HostAP operating modes. 2967 */ 2968 static void 2969 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2970 { 2971 struct ieee80211com *ic = &sc->sc_ic; 2972 uint32_t tmp; 2973 2974 if (ic->ic_opmode != IEEE80211_M_STA) { 2975 /* 2976 * Change default 16ms TBTT adjustment to 8ms. 2977 * Must be done before enabling beacon generation. 2978 */ 2979 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2980 } 2981 2982 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2983 2984 /* set beacon interval (in 1/16ms unit) */ 2985 tmp |= ic->ic_bss->ni_intval * 16; 2986 2987 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2988 if (ic->ic_opmode == IEEE80211_M_STA) 2989 tmp |= RT2661_TSF_MODE(1); 2990 else 2991 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2992 2993 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2994 } 2995 2996 /* 2997 * Retrieve the "Received Signal Strength Indicator" from the raw values 2998 * contained in Rx descriptors. The computation depends on which band the 2999 * frame was received. Correction values taken from the reference driver. 3000 */ 3001 static int 3002 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw, int i) 3003 { 3004 int lna, agc, rssi; 3005 3006 lna = (raw >> 5) & 0x3; 3007 agc = raw & 0x1f; 3008 3009 if (lna == 0) { 3010 /* 3011 * No RSSI mapping 3012 * 3013 * NB: Since RSSI is relative to noise floor, -1 is 3014 * adequate for caller to know error happened. 3015 */ 3016 return -1; 3017 } 3018 3019 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 3020 3021 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3022 rssi += sc->rssi_2ghz_corr[i]; 3023 3024 if (lna == 1) 3025 rssi -= 64; 3026 else if (lna == 2) 3027 rssi -= 74; 3028 else if (lna == 3) 3029 rssi -= 90; 3030 } else { 3031 rssi += sc->rssi_5ghz_corr; 3032 3033 if (lna == 1) 3034 rssi -= 64; 3035 else if (lna == 2) 3036 rssi -= 86; 3037 else if (lna == 3) 3038 rssi -= 100; 3039 } 3040 3041 if (sc->avg_rssi[i] < 0) { 3042 sc->avg_rssi[i] = rssi; 3043 } else { 3044 sc->avg_rssi[i] = 3045 ((sc->avg_rssi[i] << 3) - sc->avg_rssi[i] + rssi) >> 3; 3046 } 3047 return rssi; 3048 } 3049 3050 static void 3051 rt2661_dma_map_mbuf(void *arg, bus_dma_segment_t *seg, int nseg, 3052 bus_size_t map_size __unused, int error) 3053 { 3054 struct rt2661_dmamap *map = arg; 3055 3056 if (error) 3057 return; 3058 3059 KASSERT(nseg <= RT2661_MAX_SCATTER, ("too many DMA segments")); 3060 3061 bcopy(seg, map->segs, nseg * sizeof(bus_dma_segment_t)); 3062 map->nseg = nseg; 3063 } 3064 3065 static void 3066 rt2661_led_newstate(struct rt2661_softc *sc, enum ieee80211_state nstate) 3067 { 3068 struct ieee80211com *ic = &sc->sc_ic; 3069 uint32_t off, on; 3070 uint32_t mail = sc->mcu_led; 3071 3072 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) { 3073 DPRINTF(("%s failed\n", __func__)); 3074 return; 3075 } 3076 3077 switch (nstate) { 3078 case IEEE80211_S_INIT: 3079 mail &= ~(RT2661_MCU_LED_LINKA | RT2661_MCU_LED_LINKG | 3080 RT2661_MCU_LED_RF); 3081 break; 3082 default: 3083 if (ic->ic_curchan == NULL) 3084 return; 3085 3086 on = RT2661_MCU_LED_LINKG; 3087 off = RT2661_MCU_LED_LINKA; 3088 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 3089 on = RT2661_MCU_LED_LINKA; 3090 off = RT2661_MCU_LED_LINKG; 3091 } 3092 3093 mail |= RT2661_MCU_LED_RF | on; 3094 mail &= ~off; 3095 break; 3096 } 3097 3098 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 3099 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | mail); 3100 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | RT2661_MCU_SET_LED); 3101 } 3102 3103 static void 3104 rt2661_read_txpower_config(struct rt2661_softc *sc, uint8_t txpwr_ofs, 3105 int nchan, int *start_chan0) 3106 { 3107 int i, loop_max; 3108 int start_chan = *start_chan0; 3109 3110 KASSERT(nchan % 2 == 0, ("number of channels %d is not even\n", nchan)); 3111 KASSERT(start_chan + nchan <= RT2661_NCHAN_MAX, ("too many channels")); 3112 3113 loop_max = nchan / 2; 3114 3115 for (i = 0; i < loop_max; i++) { 3116 int chan_idx, j; 3117 uint16_t val; 3118 3119 val = rt2661_eeprom_read(sc, txpwr_ofs + i); 3120 chan_idx = i * 2 + start_chan; 3121 3122 for (j = 0; j < 2; ++j) { 3123 int8_t tx_power; /* signed */ 3124 3125 tx_power = (int8_t)((val >> (8 * j)) & 0xff); 3126 if (tx_power > RT2661_TXPOWER_MAX) 3127 tx_power = RT2661_TXPOWER_DEFAULT; 3128 3129 sc->txpow[chan_idx] = tx_power; 3130 DPRINTF(("Channel=%d Tx power=%d\n", 3131 rt2661_rf5225_1[chan_idx].chan, sc->txpow[chan_idx])); 3132 3133 ++chan_idx; 3134 } 3135 } 3136 *start_chan0 += nchan; 3137 } 3138 3139 static int 3140 rt2661_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *key, 3141 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 3142 { 3143 struct rt2661_softc *sc = ic->ic_if.if_softc; 3144 3145 DPRINTF(("%s: ", __func__)); 3146 3147 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3148 DPRINTF(("alloc sw key\n")); 3149 return sc->sc_key_alloc(ic, key, keyix, rxkeyix); 3150 } 3151 3152 if (key->wk_flags & IEEE80211_KEY_GROUP) { /* Global key */ 3153 DPRINTF(("alloc group key\n")); 3154 3155 KASSERT(key >= &ic->ic_nw_keys[0] && 3156 key < &ic->ic_nw_keys[IEEE80211_WEP_NKID], 3157 ("bogus group key\n")); 3158 3159 *keyix = *rxkeyix = key - ic->ic_nw_keys; 3160 return 1; 3161 } else { /* Pairwise key */ 3162 int i; 3163 3164 DPRINTF(("alloc pairwise key\n")); 3165 3166 for (i = IEEE80211_WEP_NKID; i < RT2661_KEY_MAX; ++i) { 3167 if (!RT2661_KEY_ISSET(sc, i)) 3168 break; 3169 } 3170 #ifndef MIXED_KEY_TEST 3171 if (i == RT2661_KEY_MAX) 3172 return 0; 3173 #else 3174 if (i != IEEE80211_WEP_NKID) 3175 return 0; 3176 #endif 3177 3178 RT2661_KEY_SET(sc, i); 3179 *keyix = *rxkeyix = i; 3180 return 1; 3181 } 3182 } 3183 3184 static int 3185 rt2661_key_delete(struct ieee80211com *ic, const struct ieee80211_key *key) 3186 { 3187 struct rt2661_softc *sc = ic->ic_if.if_softc; 3188 uint32_t val; 3189 3190 DPRINTF(("%s: keyix %d, rxkeyix %d, ", __func__, 3191 key->wk_keyix, key->wk_rxkeyix)); 3192 3193 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3194 DPRINTF(("delete sw key\n")); 3195 return sc->sc_key_delete(ic, key); 3196 } 3197 3198 if (key->wk_keyix < IEEE80211_WEP_NKID) { /* Global key */ 3199 DPRINTF(("delete global key\n")); 3200 val = RAL_READ(sc, RT2661_SEC_CSR0); 3201 val &= ~(1 << key->wk_keyix); 3202 RAL_WRITE(sc, RT2661_SEC_CSR0, val); 3203 } else { /* Pairwise key */ 3204 DPRINTF(("delete pairwise key\n")); 3205 3206 RT2661_KEY_CLR(sc, key->wk_keyix); 3207 if (key->wk_keyix < 32) { 3208 val = RAL_READ(sc, RT2661_SEC_CSR2); 3209 val &= ~(1 << key->wk_keyix); 3210 RAL_WRITE(sc, RT2661_SEC_CSR2, val); 3211 } else { 3212 val = RAL_READ(sc, RT2661_SEC_CSR3); 3213 val &= ~(1 << (key->wk_keyix - 32)); 3214 RAL_WRITE(sc, RT2661_SEC_CSR3, val); 3215 } 3216 } 3217 return 1; 3218 } 3219 3220 static int 3221 rt2661_key_set(struct ieee80211com *ic, const struct ieee80211_key *key, 3222 const uint8_t mac[IEEE80211_ADDR_LEN]) 3223 { 3224 struct rt2661_softc *sc = ic->ic_if.if_softc; 3225 uint32_t addr, val; 3226 3227 DPRINTF(("%s: keyix %d, rxkeyix %d, flags 0x%04x, ", __func__, 3228 key->wk_keyix, key->wk_rxkeyix, key->wk_flags)); 3229 3230 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3231 DPRINTF(("set sw key\n")); 3232 return sc->sc_key_set(ic, key, mac); 3233 } 3234 3235 if (key->wk_keyix < IEEE80211_WEP_NKID) { /* Global Key */ 3236 int cipher, keyix_shift; 3237 3238 DPRINTF(("set global key\n")); 3239 3240 /* 3241 * Install key content. 3242 */ 3243 addr = RT2661_GLOBAL_KEY_BASE + 3244 (key->wk_keyix * sizeof(key->wk_key)); 3245 RAL_WRITE_REGION_1(sc, addr, key->wk_key, sizeof(key->wk_key)); 3246 3247 /* 3248 * Set key cipher. 3249 */ 3250 cipher = rt2661_cipher(key); 3251 keyix_shift = key->wk_keyix * 4; 3252 3253 val = RAL_READ(sc, RT2661_SEC_CSR1); 3254 val &= ~(0xf << keyix_shift); 3255 val |= cipher << keyix_shift; 3256 RAL_WRITE(sc, RT2661_SEC_CSR1, val); 3257 3258 /* 3259 * Enable key slot. 3260 */ 3261 val = RAL_READ(sc, RT2661_SEC_CSR0); 3262 val |= 1 << key->wk_keyix; 3263 RAL_WRITE(sc, RT2661_SEC_CSR0, val); 3264 } else { /* Pairwise key */ 3265 uint8_t mac_cipher[IEEE80211_ADDR_LEN + 1]; 3266 3267 DPRINTF(("set pairwise key\n")); 3268 3269 /* 3270 * Install key content. 3271 */ 3272 addr = RT2661_PAIRWISE_KEY_BASE + 3273 (key->wk_keyix * sizeof(key->wk_key)); 3274 RAL_WRITE_REGION_1(sc, addr, key->wk_key, sizeof(key->wk_key)); 3275 3276 /* 3277 * Set target address and key cipher. 3278 */ 3279 memcpy(mac_cipher, mac, IEEE80211_ADDR_LEN); 3280 mac_cipher[IEEE80211_ADDR_LEN] = rt2661_cipher(key); 3281 3282 /* XXX Actually slot size is 1 byte bigger than mac_cipher */ 3283 addr = RT2661_TARGET_ADDR_BASE + 3284 (key->wk_keyix * (IEEE80211_ADDR_LEN + 2)); 3285 RAL_WRITE_REGION_1(sc, addr, mac_cipher, sizeof(mac_cipher)); 3286 3287 /* 3288 * Enable key slot. 3289 */ 3290 if (key->wk_keyix < 32) { 3291 val = RAL_READ(sc, RT2661_SEC_CSR2); 3292 val |= 1 << key->wk_keyix; 3293 RAL_WRITE(sc, RT2661_SEC_CSR2, val); 3294 } else { 3295 val = RAL_READ(sc, RT2661_SEC_CSR3); 3296 val |= 1 << (key->wk_keyix - 32); 3297 RAL_WRITE(sc, RT2661_SEC_CSR3, val); 3298 } 3299 3300 /* 3301 * Enable pairwise key looking up when RX. 3302 */ 3303 RAL_WRITE(sc, RT2661_SEC_CSR4, 1); 3304 } 3305 return 1; 3306 } 3307 3308 static void * 3309 rt2661_ratectl_attach(struct ieee80211com *ic, u_int rc) 3310 { 3311 struct rt2661_softc *sc = ic->ic_if.if_softc; 3312 3313 switch (rc) { 3314 case IEEE80211_RATECTL_ONOE: 3315 return &sc->sc_onoe_param; 3316 3317 case IEEE80211_RATECTL_SAMPLE: 3318 if ((ic->ic_ratectl.rc_st_ratectl_cap & 3319 IEEE80211_RATECTL_CAP_SAMPLE) == 0) 3320 panic("sample rate control algo is not supported\n"); 3321 return &sc->sc_sample_param; 3322 3323 case IEEE80211_RATECTL_NONE: 3324 /* This could only happen during detaching */ 3325 return NULL; 3326 3327 default: 3328 panic("unknown rate control algo %u\n", rc); 3329 return NULL; 3330 } 3331 } 3332 3333 static void 3334 rt2661_calib_txpower(struct rt2661_softc *sc) 3335 { 3336 int8_t txpower; 3337 int rssi_dbm; 3338 3339 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 3340 return; 3341 3342 txpower = sc->txpow[sc->sc_curchan_idx]; 3343 if (txpower < 0) 3344 txpower = 0; 3345 else if (txpower > 31) 3346 txpower = 31; 3347 txpower = rt2661_txpower(sc, txpower); 3348 3349 if (sc->auto_txagc) { 3350 /* 3351 * Compensate TX power according to temperature change 3352 */ 3353 if (sc->sc_txpwr_cnt++ % 4 == 0) { 3354 uint8_t bbp1; 3355 int i; 3356 3357 /* 3358 * Adjust compensation very 4 seconds 3359 */ 3360 bbp1 = rt2661_bbp_read(sc, 1); 3361 if (bbp1 > sc->tssi_2ghz_ref) { 3362 for (i = 0; i < RT2661_TSSI_LIMSZ; ++i) { 3363 if (bbp1 <= sc->tssi_2ghz_down[i]) 3364 break; 3365 } 3366 if (txpower > (sc->tssi_2ghz_step * i)) { 3367 sc->tssi_2ghz_comp = 3368 -(sc->tssi_2ghz_step * i); 3369 } else { 3370 sc->tssi_2ghz_comp = -txpower; 3371 } 3372 } else if (bbp1 < sc->tssi_2ghz_ref) { 3373 for (i = 0; i < RT2661_TSSI_LIMSZ; ++i) { 3374 if (bbp1 >= sc->tssi_2ghz_up[i]) 3375 break; 3376 } 3377 sc->tssi_2ghz_comp = sc->tssi_2ghz_step * i; 3378 } 3379 } 3380 txpower += sc->tssi_2ghz_comp; 3381 } 3382 3383 /* 3384 * Adjust TX power according to RSSI 3385 */ 3386 rssi_dbm = rt2661_avgrssi(sc); 3387 DPRINTF(("dbm %d, txpower %d\n", rssi_dbm, txpower)); 3388 3389 if (rssi_dbm > -30) { 3390 if (txpower > 16) 3391 txpower -= 16; 3392 else 3393 txpower = 0; 3394 } else if (rssi_dbm > -45) { 3395 if (txpower > 6) 3396 txpower -= 6; 3397 else 3398 txpower = 0; 3399 } 3400 3401 if (txpower != sc->sc_txpwr) 3402 rt2661_set_txpower(sc, txpower); 3403 } 3404 3405 static void 3406 rt2661_calib_rxsensibility(struct rt2661_softc *sc, uint32_t false_cca) 3407 { 3408 #define MIDRANGE_RSSI -74 3409 3410 uint8_t bbp17; 3411 int rssi_dbm; 3412 3413 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 3414 return; 3415 3416 rssi_dbm = rt2661_avgrssi(sc); 3417 3418 if (rssi_dbm >= MIDRANGE_RSSI) { 3419 if (rssi_dbm >= -35) 3420 bbp17 = 0x60; 3421 else if (rssi_dbm >= -58) 3422 bbp17 = sc->bbp17_2ghz_max; 3423 else if (rssi_dbm >= -66) 3424 bbp17 = sc->bbp17_2ghz_min + 0x10; 3425 else 3426 bbp17 = sc->bbp17_2ghz_min + 0x8; 3427 3428 if (sc->bbp17 != bbp17) 3429 rt2661_bbp_write(sc, 17, bbp17); 3430 return; 3431 } 3432 3433 bbp17 = sc->bbp17_2ghz_max - (2 * (MIDRANGE_RSSI - rssi_dbm)); 3434 if (bbp17 < sc->bbp17_2ghz_min) 3435 bbp17 = sc->bbp17_2ghz_min; 3436 3437 if (sc->bbp17 > bbp17) { 3438 rt2661_bbp_write(sc, 17, bbp17); 3439 return; 3440 } 3441 3442 DPRINTF(("calibrate according to false CCA\n")); 3443 3444 if (false_cca > 512 && sc->bbp17 > sc->bbp17_2ghz_min) 3445 rt2661_bbp_write(sc, 17, sc->bbp17 - 1); 3446 else if (false_cca < 100 && sc->bbp17 < bbp17) 3447 rt2661_bbp_write(sc, 17, sc->bbp17 + 1); 3448 3449 #undef MIDRANGE_RSSI 3450 } 3451 3452 static void 3453 rt2661_calibrate(void *xsc) 3454 { 3455 struct rt2661_softc *sc = xsc; 3456 struct ifnet *ifp = &sc->sc_ic.ic_if; 3457 uint32_t false_cca; 3458 3459 lwkt_serialize_enter(ifp->if_serializer); 3460 3461 false_cca = (RAL_READ(sc, RT2661_STA_CSR1) >> 16); 3462 DPRINTF(("false cca %u\n", false_cca)); 3463 3464 if (sc->sc_calib_rxsns) 3465 rt2661_calib_rxsensibility(sc, false_cca); 3466 3467 if (sc->sc_calib_txpwr) 3468 rt2661_calib_txpower(sc); 3469 3470 callout_reset(&sc->calib_ch, hz, rt2661_calibrate, sc); 3471 3472 lwkt_serialize_exit(ifp->if_serializer); 3473 } 3474