1 /* 2 * Copyright (c) 2006 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: src/sys/dev/ral/rt2661.c,v 1.4 2006/03/21 21:15:43 damien Exp $ 18 * $DragonFly: src/sys/dev/netif/ral/rt2661.c,v 1.4 2006/10/25 20:55:58 dillon Exp $ 19 */ 20 21 /* 22 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/module.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/endian.h> 38 39 #include <machine/clock.h> 40 41 #include <net/bpf.h> 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_types.h> 48 #include <net/ifq_var.h> 49 50 #include <netproto/802_11/ieee80211_var.h> 51 #include <netproto/802_11/ieee80211_radiotap.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 #include <netinet/if_ether.h> 58 59 #include <dev/netif/ral/if_ralrate.h> 60 #include <dev/netif/ral/rt2661reg.h> 61 #include <dev/netif/ral/rt2661var.h> 62 #include <dev/netif/ral/rt2661_ucode.h> 63 64 #ifdef RAL_DEBUG 65 #define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) 67 int ral_debug = 0; 68 SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n, x) 72 #endif 73 74 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 75 int); 76 static void rt2661_dma_map_mbuf(void *, bus_dma_segment_t *, int, 77 bus_size_t, int); 78 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *, int); 80 static void rt2661_reset_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *); 82 static void rt2661_free_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *, int); 86 static void rt2661_reset_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *); 88 static void rt2661_free_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90 static struct ieee80211_node *rt2661_node_alloc( 91 struct ieee80211_node_table *); 92 static int rt2661_media_change(struct ifnet *); 93 static void rt2661_next_scan(void *); 94 static int rt2661_newstate(struct ieee80211com *, 95 enum ieee80211_state, int); 96 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 97 static void rt2661_rx_intr(struct rt2661_softc *); 98 static void rt2661_tx_intr(struct rt2661_softc *); 99 static void rt2661_tx_dma_intr(struct rt2661_softc *, 100 struct rt2661_tx_ring *); 101 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 102 static void rt2661_mcu_wakeup(struct rt2661_softc *); 103 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 104 static int rt2661_ack_rate(struct ieee80211com *, int); 105 static uint16_t rt2661_txtime(int, int, uint32_t); 106 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 107 static uint8_t rt2661_plcp_signal(int); 108 static void rt2661_setup_tx_desc(struct rt2661_softc *, 109 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 110 int, const bus_dma_segment_t *, int, int); 111 static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 112 struct ieee80211_frame *, uint16_t); 113 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 114 struct ieee80211_node *, int); 115 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 116 struct ieee80211_node *); 117 static void rt2661_start(struct ifnet *); 118 static void rt2661_watchdog(struct ifnet *); 119 static int rt2661_reset(struct ifnet *); 120 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 121 struct ucred *); 122 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 123 uint8_t); 124 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 125 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 126 uint32_t); 127 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 128 uint16_t); 129 static void rt2661_select_antenna(struct rt2661_softc *); 130 static void rt2661_enable_mrr(struct rt2661_softc *); 131 static void rt2661_set_txpreamble(struct rt2661_softc *); 132 static void rt2661_set_basicrates(struct rt2661_softc *, 133 const struct ieee80211_rateset *); 134 static void rt2661_select_band(struct rt2661_softc *, 135 struct ieee80211_channel *); 136 static void rt2661_set_chan(struct rt2661_softc *, 137 struct ieee80211_channel *); 138 static void rt2661_set_bssid(struct rt2661_softc *, 139 const uint8_t *); 140 static void rt2661_set_macaddr(struct rt2661_softc *, 141 const uint8_t *); 142 static void rt2661_update_promisc(struct rt2661_softc *); 143 static int rt2661_wme_update(struct ieee80211com *) __unused; 144 static void rt2661_update_slot(struct ifnet *); 145 static const char *rt2661_get_rf(int); 146 static void rt2661_read_eeprom(struct rt2661_softc *); 147 static int rt2661_bbp_init(struct rt2661_softc *); 148 static void rt2661_init(void *); 149 static void rt2661_stop(void *); 150 static void rt2661_intr(void *); 151 static int rt2661_load_microcode(struct rt2661_softc *, 152 const uint8_t *, int); 153 #ifdef notyet 154 static void rt2661_rx_tune(struct rt2661_softc *); 155 static void rt2661_radar_start(struct rt2661_softc *); 156 static int rt2661_radar_stop(struct rt2661_softc *); 157 #endif 158 static int rt2661_prepare_beacon(struct rt2661_softc *); 159 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 160 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 161 162 /* 163 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 164 */ 165 static const struct ieee80211_rateset rt2661_rateset_11a = 166 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 167 168 static const struct ieee80211_rateset rt2661_rateset_11b = 169 { 4, { 2, 4, 11, 22 } }; 170 171 static const struct ieee80211_rateset rt2661_rateset_11g = 172 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 173 174 static const struct { 175 uint32_t reg; 176 uint32_t val; 177 } rt2661_def_mac[] = { 178 RT2661_DEF_MAC 179 }; 180 181 static const struct { 182 uint8_t reg; 183 uint8_t val; 184 } rt2661_def_bbp[] = { 185 RT2661_DEF_BBP 186 }; 187 188 static const struct rfprog { 189 uint8_t chan; 190 uint32_t r1, r2, r3, r4; 191 } rt2661_rf5225_1[] = { 192 RT2661_RF5225_1 193 }, rt2661_rf5225_2[] = { 194 RT2661_RF5225_2 195 }; 196 197 struct rt2661_dmamap { 198 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 199 int nseg; 200 }; 201 202 int 203 rt2661_attach(device_t dev, int id) 204 { 205 struct rt2661_softc *sc = device_get_softc(dev); 206 struct ieee80211com *ic = &sc->sc_ic; 207 struct ifnet *ifp = &ic->ic_if; 208 uint32_t val; 209 const uint8_t *ucode = NULL; 210 int error, i, ac, ntries, size = 0; 211 212 callout_init(&sc->scan_ch); 213 callout_init(&sc->rssadapt_ch); 214 215 sc->sc_irq_rid = 0; 216 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid, 217 RF_ACTIVE | RF_SHAREABLE); 218 if (sc->sc_irq == NULL) { 219 device_printf(dev, "could not allocate interrupt resource\n"); 220 return ENXIO; 221 } 222 223 /* wait for NIC to initialize */ 224 for (ntries = 0; ntries < 1000; ntries++) { 225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 226 break; 227 DELAY(1000); 228 } 229 if (ntries == 1000) { 230 device_printf(sc->sc_dev, 231 "timeout waiting for NIC to initialize\n"); 232 error = EIO; 233 goto fail; 234 } 235 236 /* retrieve RF rev. no and various other things from EEPROM */ 237 rt2661_read_eeprom(sc); 238 239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 240 rt2661_get_rf(sc->rf_rev)); 241 242 /* 243 * Load 8051 microcode into NIC. 244 */ 245 switch (id) { 246 case 0x0301: 247 ucode = rt2561s_ucode; 248 size = sizeof rt2561s_ucode; 249 break; 250 case 0x0302: 251 ucode = rt2561_ucode; 252 size = sizeof rt2561_ucode; 253 break; 254 case 0x0401: 255 ucode = rt2661_ucode; 256 size = sizeof rt2661_ucode; 257 break; 258 } 259 260 error = rt2661_load_microcode(sc, ucode, size); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 263 goto fail; 264 } 265 266 /* 267 * Allocate Tx and Rx rings. 268 */ 269 for (ac = 0; ac < 4; ac++) { 270 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 271 RT2661_TX_RING_COUNT); 272 if (error != 0) { 273 device_printf(sc->sc_dev, 274 "could not allocate Tx ring %d\n", ac); 275 goto fail; 276 } 277 } 278 279 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 280 if (error != 0) { 281 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 282 goto fail; 283 } 284 285 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 286 if (error != 0) { 287 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 288 goto fail; 289 } 290 291 sysctl_ctx_init(&sc->sysctl_ctx); 292 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 293 SYSCTL_STATIC_CHILDREN(_hw), 294 OID_AUTO, 295 device_get_nameunit(dev), 296 CTLFLAG_RD, 0, ""); 297 if (sc->sysctl_tree == NULL) { 298 device_printf(dev, "could not add sysctl node\n"); 299 error = ENXIO; 300 goto fail; 301 } 302 303 ifp->if_softc = sc; 304 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 305 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 306 ifp->if_init = rt2661_init; 307 ifp->if_ioctl = rt2661_ioctl; 308 ifp->if_start = rt2661_start; 309 ifp->if_watchdog = rt2661_watchdog; 310 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 311 ifq_set_ready(&ifp->if_snd); 312 313 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 314 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 315 ic->ic_state = IEEE80211_S_INIT; 316 317 /* set device capabilities */ 318 ic->ic_caps = 319 IEEE80211_C_IBSS | /* IBSS mode supported */ 320 IEEE80211_C_MONITOR | /* monitor mode supported */ 321 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 322 IEEE80211_C_TXPMGT | /* tx power management */ 323 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 324 IEEE80211_C_SHSLOT | /* short slot time supported */ 325 #ifdef notyet 326 IEEE80211_C_WME | /* 802.11e */ 327 #endif 328 IEEE80211_C_WEP | /* WEP */ 329 IEEE80211_C_WPA; /* 802.11i */ 330 331 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 332 /* set supported .11a rates */ 333 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 334 335 /* set supported .11a channels */ 336 for (i = 36; i <= 64; i += 4) { 337 ic->ic_channels[i].ic_freq = 338 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 339 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 340 } 341 for (i = 100; i <= 140; i += 4) { 342 ic->ic_channels[i].ic_freq = 343 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 344 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 345 } 346 for (i = 149; i <= 165; i += 4) { 347 ic->ic_channels[i].ic_freq = 348 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 349 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 350 } 351 } 352 353 /* set supported .11b and .11g rates */ 354 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 355 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 356 357 /* set supported .11b and .11g channels (1 through 14) */ 358 for (i = 1; i <= 14; i++) { 359 ic->ic_channels[i].ic_freq = 360 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 361 ic->ic_channels[i].ic_flags = 362 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 363 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 364 } 365 366 ieee80211_ifattach(ic); 367 ic->ic_node_alloc = rt2661_node_alloc; 368 /* ic->ic_wme.wme_update = rt2661_wme_update;*/ 369 ic->ic_updateslot = rt2661_update_slot; 370 ic->ic_reset = rt2661_reset; 371 /* enable s/w bmiss handling in sta mode */ 372 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 373 374 /* override state transition machine */ 375 sc->sc_newstate = ic->ic_newstate; 376 ic->ic_newstate = rt2661_newstate; 377 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 378 379 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO, 380 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 381 382 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 383 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 384 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 385 386 sc->sc_txtap_len = sizeof sc->sc_txtapu; 387 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 388 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 389 390 /* 391 * Add a few sysctl knobs. 392 */ 393 sc->dwelltime = 200; 394 395 SYSCTL_ADD_INT(&sc->sysctl_ctx, 396 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "dwell", 397 CTLFLAG_RW, &sc->dwelltime, 0, 398 "channel dwell time (ms) for AP/station scanning"); 399 400 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, rt2661_intr, 401 sc, &sc->sc_ih, ifp->if_serializer); 402 if (error != 0) { 403 device_printf(dev, "could not set up interrupt\n"); 404 bpfdetach(ifp); 405 ieee80211_ifdetach(ic); 406 goto fail; 407 } 408 409 if (bootverbose) 410 ieee80211_announce(ic); 411 return 0; 412 fail: 413 rt2661_detach(sc); 414 return error; 415 } 416 417 int 418 rt2661_detach(void *xsc) 419 { 420 struct rt2661_softc *sc = xsc; 421 struct ieee80211com *ic = &sc->sc_ic; 422 struct ifnet *ifp = &ic->ic_if; 423 424 if (device_is_attached(sc->sc_dev)) { 425 lwkt_serialize_enter(ifp->if_serializer); 426 427 callout_stop(&sc->scan_ch); 428 callout_stop(&sc->rssadapt_ch); 429 rt2661_stop(sc); 430 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih); 431 432 lwkt_serialize_exit(ifp->if_serializer); 433 434 bpfdetach(ifp); 435 ieee80211_ifdetach(ic); 436 } 437 438 rt2661_free_tx_ring(sc, &sc->txq[0]); 439 rt2661_free_tx_ring(sc, &sc->txq[1]); 440 rt2661_free_tx_ring(sc, &sc->txq[2]); 441 rt2661_free_tx_ring(sc, &sc->txq[3]); 442 rt2661_free_tx_ring(sc, &sc->mgtq); 443 rt2661_free_rx_ring(sc, &sc->rxq); 444 445 if (sc->sc_irq != NULL) { 446 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid, 447 sc->sc_irq); 448 } 449 450 if (sc->sysctl_tree != NULL) 451 sysctl_ctx_free(&sc->sysctl_ctx); 452 453 return 0; 454 } 455 456 void 457 rt2661_shutdown(void *xsc) 458 { 459 struct rt2661_softc *sc = xsc; 460 struct ifnet *ifp = &sc->sc_ic.ic_if; 461 462 lwkt_serialize_enter(ifp->if_serializer); 463 rt2661_stop(sc); 464 lwkt_serialize_exit(ifp->if_serializer); 465 } 466 467 void 468 rt2661_suspend(void *xsc) 469 { 470 struct rt2661_softc *sc = xsc; 471 struct ifnet *ifp = &sc->sc_ic.ic_if; 472 473 lwkt_serialize_enter(ifp->if_serializer); 474 rt2661_stop(sc); 475 lwkt_serialize_exit(ifp->if_serializer); 476 } 477 478 void 479 rt2661_resume(void *xsc) 480 { 481 struct rt2661_softc *sc = xsc; 482 struct ifnet *ifp = sc->sc_ic.ic_ifp; 483 484 lwkt_serialize_enter(ifp->if_serializer); 485 if (ifp->if_flags & IFF_UP) { 486 ifp->if_init(ifp->if_softc); 487 if (ifp->if_flags & IFF_RUNNING) 488 ifp->if_start(ifp); 489 } 490 lwkt_serialize_exit(ifp->if_serializer); 491 } 492 493 static void 494 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 495 { 496 if (error != 0) 497 return; 498 499 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 500 501 *(bus_addr_t *)arg = segs[0].ds_addr; 502 } 503 504 static int 505 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 506 int count) 507 { 508 int i, error; 509 510 ring->count = count; 511 ring->queued = 0; 512 ring->cur = ring->next = ring->stat = 0; 513 514 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 515 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 516 count * RT2661_TX_DESC_SIZE, 0, &ring->desc_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 523 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 530 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 531 0); 532 if (error != 0) { 533 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 534 535 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 536 ring->desc = NULL; 537 goto fail; 538 } 539 540 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 541 M_WAITOK | M_ZERO); 542 543 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 544 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * RT2661_MAX_SCATTER, 545 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 546 if (error != 0) { 547 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 548 goto fail; 549 } 550 551 for (i = 0; i < count; i++) { 552 error = bus_dmamap_create(ring->data_dmat, 0, 553 &ring->data[i].map); 554 if (error != 0) { 555 device_printf(sc->sc_dev, "could not create DMA map\n"); 556 goto fail; 557 } 558 } 559 return 0; 560 561 fail: rt2661_free_tx_ring(sc, ring); 562 return error; 563 } 564 565 static void 566 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 567 { 568 struct rt2661_tx_desc *desc; 569 struct rt2661_tx_data *data; 570 int i; 571 572 for (i = 0; i < ring->count; i++) { 573 desc = &ring->desc[i]; 574 data = &ring->data[i]; 575 576 if (data->m != NULL) { 577 bus_dmamap_sync(ring->data_dmat, data->map, 578 BUS_DMASYNC_POSTWRITE); 579 bus_dmamap_unload(ring->data_dmat, data->map); 580 m_freem(data->m); 581 data->m = NULL; 582 } 583 584 if (data->ni != NULL) { 585 ieee80211_free_node(data->ni); 586 data->ni = NULL; 587 } 588 589 desc->flags = 0; 590 } 591 592 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 593 594 ring->queued = 0; 595 ring->cur = ring->next = ring->stat = 0; 596 } 597 598 static void 599 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 600 { 601 struct rt2661_tx_data *data; 602 int i; 603 604 if (ring->desc != NULL) { 605 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 606 BUS_DMASYNC_POSTWRITE); 607 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 608 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 609 ring->desc = NULL; 610 } 611 612 if (ring->desc_dmat != NULL) { 613 bus_dma_tag_destroy(ring->desc_dmat); 614 ring->desc_dmat = NULL; 615 } 616 617 if (ring->data != NULL) { 618 for (i = 0; i < ring->count; i++) { 619 data = &ring->data[i]; 620 621 if (data->m != NULL) { 622 bus_dmamap_sync(ring->data_dmat, data->map, 623 BUS_DMASYNC_POSTWRITE); 624 bus_dmamap_unload(ring->data_dmat, data->map); 625 m_freem(data->m); 626 data->m = NULL; 627 } 628 629 if (data->ni != NULL) { 630 ieee80211_free_node(data->ni); 631 data->ni = NULL; 632 } 633 634 if (data->map != NULL) { 635 bus_dmamap_destroy(ring->data_dmat, data->map); 636 data->map = NULL; 637 } 638 } 639 640 kfree(ring->data, M_DEVBUF); 641 ring->data = NULL; 642 } 643 644 if (ring->data_dmat != NULL) { 645 bus_dma_tag_destroy(ring->data_dmat); 646 ring->data_dmat = NULL; 647 } 648 } 649 650 static int 651 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 652 int count) 653 { 654 struct rt2661_rx_desc *desc; 655 struct rt2661_rx_data *data; 656 bus_addr_t physaddr; 657 int i, error; 658 659 ring->count = count; 660 ring->cur = ring->next = 0; 661 662 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 663 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 664 count * RT2661_RX_DESC_SIZE, 0, &ring->desc_dmat); 665 if (error != 0) { 666 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 667 goto fail; 668 } 669 670 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 671 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 672 if (error != 0) { 673 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 674 goto fail; 675 } 676 677 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 678 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 679 0); 680 if (error != 0) { 681 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 682 683 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 684 ring->desc = NULL; 685 goto fail; 686 } 687 688 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 689 M_WAITOK | M_ZERO); 690 691 /* 692 * Pre-allocate Rx buffers and populate Rx ring. 693 */ 694 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 696 &ring->data_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 699 goto fail; 700 } 701 702 for (i = 0; i < count; i++) { 703 desc = &sc->rxq.desc[i]; 704 data = &sc->rxq.data[i]; 705 706 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 707 if (error != 0) { 708 device_printf(sc->sc_dev, "could not create DMA map\n"); 709 goto fail; 710 } 711 712 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 713 if (data->m == NULL) { 714 device_printf(sc->sc_dev, 715 "could not allocate rx mbuf\n"); 716 error = ENOMEM; 717 goto fail; 718 } 719 720 error = bus_dmamap_load(ring->data_dmat, data->map, 721 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 722 &physaddr, 0); 723 if (error != 0) { 724 device_printf(sc->sc_dev, 725 "could not load rx buf DMA map"); 726 727 m_freem(data->m); 728 data->m = NULL; 729 goto fail; 730 } 731 732 desc->flags = htole32(RT2661_RX_BUSY); 733 desc->physaddr = htole32(physaddr); 734 } 735 736 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 737 738 return 0; 739 740 fail: rt2661_free_rx_ring(sc, ring); 741 return error; 742 } 743 744 static void 745 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 746 { 747 int i; 748 749 for (i = 0; i < ring->count; i++) 750 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 751 752 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 753 754 ring->cur = ring->next = 0; 755 } 756 757 static void 758 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 759 { 760 struct rt2661_rx_data *data; 761 int i; 762 763 if (ring->desc != NULL) { 764 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 765 BUS_DMASYNC_POSTWRITE); 766 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 767 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 768 ring->desc = NULL; 769 } 770 771 if (ring->desc_dmat != NULL) { 772 bus_dma_tag_destroy(ring->desc_dmat); 773 ring->desc_dmat = NULL; 774 } 775 776 if (ring->data != NULL) { 777 for (i = 0; i < ring->count; i++) { 778 data = &ring->data[i]; 779 780 if (data->m != NULL) { 781 bus_dmamap_sync(ring->data_dmat, data->map, 782 BUS_DMASYNC_POSTREAD); 783 bus_dmamap_unload(ring->data_dmat, data->map); 784 m_freem(data->m); 785 data->m = NULL; 786 } 787 788 if (data->map != NULL) { 789 bus_dmamap_destroy(ring->data_dmat, data->map); 790 data->map = NULL; 791 } 792 } 793 794 kfree(ring->data, M_DEVBUF); 795 ring->data = NULL; 796 } 797 798 if (ring->data_dmat != NULL) { 799 bus_dma_tag_destroy(ring->data_dmat); 800 ring->data_dmat = NULL; 801 } 802 } 803 804 static struct ieee80211_node * 805 rt2661_node_alloc(struct ieee80211_node_table *nt) 806 { 807 struct rt2661_node *rn; 808 809 rn = kmalloc(sizeof (struct rt2661_node), M_80211_NODE, 810 M_NOWAIT | M_ZERO); 811 812 return (rn != NULL) ? &rn->ni : NULL; 813 } 814 815 static int 816 rt2661_media_change(struct ifnet *ifp) 817 { 818 struct rt2661_softc *sc = ifp->if_softc; 819 int error; 820 821 error = ieee80211_media_change(ifp); 822 if (error != ENETRESET) 823 return error; 824 825 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 826 rt2661_init(sc); 827 return 0; 828 } 829 830 /* 831 * This function is called periodically (every 200ms) during scanning to 832 * switch from one channel to another. 833 */ 834 static void 835 rt2661_next_scan(void *arg) 836 { 837 struct rt2661_softc *sc = arg; 838 struct ieee80211com *ic = &sc->sc_ic; 839 struct ifnet *ifp = &ic->ic_if; 840 841 lwkt_serialize_enter(ifp->if_serializer); 842 if (ic->ic_state == IEEE80211_S_SCAN) 843 ieee80211_next_scan(ic); 844 lwkt_serialize_exit(ifp->if_serializer); 845 } 846 847 /* 848 * This function is called for each node present in the node station table. 849 */ 850 static void 851 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 852 { 853 struct rt2661_node *rn = (struct rt2661_node *)ni; 854 855 ral_rssadapt_updatestats(&rn->rssadapt); 856 } 857 858 /* 859 * This function is called periodically (every 100ms) in RUN state to update 860 * the rate adaptation statistics. 861 */ 862 static void 863 rt2661_update_rssadapt(void *arg) 864 { 865 struct rt2661_softc *sc = arg; 866 struct ieee80211com *ic = &sc->sc_ic; 867 struct ifnet *ifp = &ic->ic_if; 868 869 lwkt_serialize_enter(ifp->if_serializer); 870 871 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 872 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_update_rssadapt, sc); 873 874 lwkt_serialize_exit(ifp->if_serializer); 875 } 876 877 static int 878 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 879 { 880 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 881 enum ieee80211_state ostate; 882 struct ieee80211_node *ni; 883 uint32_t tmp; 884 int error = 0; 885 886 ostate = ic->ic_state; 887 callout_stop(&sc->scan_ch); 888 889 switch (nstate) { 890 case IEEE80211_S_INIT: 891 callout_stop(&sc->rssadapt_ch); 892 893 if (ostate == IEEE80211_S_RUN) { 894 /* abort TSF synchronization */ 895 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 896 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 897 } 898 break; 899 900 case IEEE80211_S_SCAN: 901 rt2661_set_chan(sc, ic->ic_curchan); 902 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000, 903 rt2661_next_scan, sc); 904 break; 905 906 case IEEE80211_S_AUTH: 907 case IEEE80211_S_ASSOC: 908 rt2661_set_chan(sc, ic->ic_curchan); 909 break; 910 911 case IEEE80211_S_RUN: 912 rt2661_set_chan(sc, ic->ic_curchan); 913 914 ni = ic->ic_bss; 915 916 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 917 rt2661_enable_mrr(sc); 918 rt2661_set_txpreamble(sc); 919 rt2661_set_basicrates(sc, &ni->ni_rates); 920 rt2661_set_bssid(sc, ni->ni_bssid); 921 } 922 923 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 924 ic->ic_opmode == IEEE80211_M_IBSS) { 925 if ((error = rt2661_prepare_beacon(sc)) != 0) 926 break; 927 } 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 callout_reset(&sc->rssadapt_ch, hz / 10, 931 rt2661_update_rssadapt, sc); 932 rt2661_enable_tsf_sync(sc); 933 } 934 break; 935 } 936 937 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 938 } 939 940 /* 941 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 942 * 93C66). 943 */ 944 static uint16_t 945 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 946 { 947 uint32_t tmp; 948 uint16_t val; 949 int n; 950 951 /* clock C once before the first command */ 952 RT2661_EEPROM_CTL(sc, 0); 953 954 RT2661_EEPROM_CTL(sc, RT2661_S); 955 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 956 RT2661_EEPROM_CTL(sc, RT2661_S); 957 958 /* write start bit (1) */ 959 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 960 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 961 962 /* write READ opcode (10) */ 963 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 964 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 965 RT2661_EEPROM_CTL(sc, RT2661_S); 966 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 967 968 /* write address (A5-A0 or A7-A0) */ 969 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 970 for (; n >= 0; n--) { 971 RT2661_EEPROM_CTL(sc, RT2661_S | 972 (((addr >> n) & 1) << RT2661_SHIFT_D)); 973 RT2661_EEPROM_CTL(sc, RT2661_S | 974 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 975 } 976 977 RT2661_EEPROM_CTL(sc, RT2661_S); 978 979 /* read data Q15-Q0 */ 980 val = 0; 981 for (n = 15; n >= 0; n--) { 982 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 983 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 984 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 985 RT2661_EEPROM_CTL(sc, RT2661_S); 986 } 987 988 RT2661_EEPROM_CTL(sc, 0); 989 990 /* clear Chip Select and clock C */ 991 RT2661_EEPROM_CTL(sc, RT2661_S); 992 RT2661_EEPROM_CTL(sc, 0); 993 RT2661_EEPROM_CTL(sc, RT2661_C); 994 995 return val; 996 } 997 998 static void 999 rt2661_tx_intr(struct rt2661_softc *sc) 1000 { 1001 struct ieee80211com *ic = &sc->sc_ic; 1002 struct ifnet *ifp = ic->ic_ifp; 1003 struct rt2661_tx_ring *txq; 1004 struct rt2661_tx_data *data; 1005 struct rt2661_node *rn; 1006 uint32_t val; 1007 int qid, retrycnt; 1008 1009 for (;;) { 1010 val = RAL_READ(sc, RT2661_STA_CSR4); 1011 if (!(val & RT2661_TX_STAT_VALID)) 1012 break; 1013 1014 /* retrieve the queue in which this frame was sent */ 1015 qid = RT2661_TX_QID(val); 1016 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 1017 1018 /* retrieve rate control algorithm context */ 1019 data = &txq->data[txq->stat]; 1020 rn = (struct rt2661_node *)data->ni; 1021 1022 switch (RT2661_TX_RESULT(val)) { 1023 case RT2661_TX_SUCCESS: 1024 retrycnt = RT2661_TX_RETRYCNT(val); 1025 1026 DPRINTFN(10, ("data frame sent successfully after " 1027 "%d retries\n", retrycnt)); 1028 if (retrycnt == 0 && data->id.id_node != NULL) { 1029 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 1030 &data->id); 1031 } 1032 ifp->if_opackets++; 1033 break; 1034 1035 case RT2661_TX_RETRY_FAIL: 1036 DPRINTFN(9, ("sending data frame failed (too much " 1037 "retries)\n")); 1038 if (data->id.id_node != NULL) { 1039 ral_rssadapt_lower_rate(ic, data->ni, 1040 &rn->rssadapt, &data->id); 1041 } 1042 ifp->if_oerrors++; 1043 break; 1044 1045 default: 1046 /* other failure */ 1047 device_printf(sc->sc_dev, 1048 "sending data frame failed 0x%08x\n", val); 1049 ifp->if_oerrors++; 1050 } 1051 1052 ieee80211_free_node(data->ni); 1053 data->ni = NULL; 1054 1055 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1056 1057 txq->queued--; 1058 if (++txq->stat >= txq->count) /* faster than % count */ 1059 txq->stat = 0; 1060 } 1061 1062 sc->sc_tx_timer = 0; 1063 ifp->if_flags &= ~IFF_OACTIVE; 1064 rt2661_start(ifp); 1065 } 1066 1067 static void 1068 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1069 { 1070 struct rt2661_tx_desc *desc; 1071 struct rt2661_tx_data *data; 1072 1073 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1074 1075 for (;;) { 1076 desc = &txq->desc[txq->next]; 1077 data = &txq->data[txq->next]; 1078 1079 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1080 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1081 break; 1082 1083 bus_dmamap_sync(txq->data_dmat, data->map, 1084 BUS_DMASYNC_POSTWRITE); 1085 bus_dmamap_unload(txq->data_dmat, data->map); 1086 m_freem(data->m); 1087 data->m = NULL; 1088 /* node reference is released in rt2661_tx_intr() */ 1089 1090 /* descriptor is no longer valid */ 1091 desc->flags &= ~htole32(RT2661_TX_VALID); 1092 1093 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1094 1095 if (++txq->next >= txq->count) /* faster than % count */ 1096 txq->next = 0; 1097 } 1098 1099 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1100 } 1101 1102 static void 1103 rt2661_rx_intr(struct rt2661_softc *sc) 1104 { 1105 struct ieee80211com *ic = &sc->sc_ic; 1106 struct ifnet *ifp = ic->ic_ifp; 1107 struct rt2661_rx_desc *desc; 1108 struct rt2661_rx_data *data; 1109 bus_addr_t physaddr; 1110 struct ieee80211_frame *wh; 1111 struct ieee80211_node *ni; 1112 struct rt2661_node *rn; 1113 struct mbuf *mnew, *m; 1114 int error; 1115 1116 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1117 BUS_DMASYNC_POSTREAD); 1118 1119 for (;;) { 1120 desc = &sc->rxq.desc[sc->rxq.cur]; 1121 data = &sc->rxq.data[sc->rxq.cur]; 1122 1123 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1124 break; 1125 1126 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1127 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1128 /* 1129 * This should not happen since we did not request 1130 * to receive those frames when we filled TXRX_CSR0. 1131 */ 1132 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1133 le32toh(desc->flags))); 1134 ifp->if_ierrors++; 1135 goto skip; 1136 } 1137 1138 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1139 ifp->if_ierrors++; 1140 goto skip; 1141 } 1142 1143 /* 1144 * Try to allocate a new mbuf for this ring element and load it 1145 * before processing the current mbuf. If the ring element 1146 * cannot be loaded, drop the received packet and reuse the old 1147 * mbuf. In the unlikely case that the old mbuf can't be 1148 * reloaded either, explicitly panic. 1149 */ 1150 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1151 if (mnew == NULL) { 1152 ifp->if_ierrors++; 1153 goto skip; 1154 } 1155 1156 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1157 BUS_DMASYNC_POSTREAD); 1158 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1159 1160 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1161 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1162 &physaddr, 0); 1163 if (error != 0) { 1164 m_freem(mnew); 1165 1166 /* try to reload the old mbuf */ 1167 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1168 mtod(data->m, void *), MCLBYTES, 1169 rt2661_dma_map_addr, &physaddr, 0); 1170 if (error != 0) { 1171 /* very unlikely that it will fail... */ 1172 panic("%s: could not load old rx mbuf", 1173 device_get_name(sc->sc_dev)); 1174 } 1175 ifp->if_ierrors++; 1176 goto skip; 1177 } 1178 1179 /* 1180 * New mbuf successfully loaded, update Rx ring and continue 1181 * processing. 1182 */ 1183 m = data->m; 1184 data->m = mnew; 1185 desc->physaddr = htole32(physaddr); 1186 1187 /* finalize mbuf */ 1188 m->m_pkthdr.rcvif = ifp; 1189 m->m_pkthdr.len = m->m_len = 1190 (le32toh(desc->flags) >> 16) & 0xfff; 1191 1192 if (sc->sc_drvbpf != NULL) { 1193 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1194 uint32_t tsf_lo, tsf_hi; 1195 1196 /* get timestamp (low and high 32 bits) */ 1197 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1198 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1199 1200 tap->wr_tsf = 1201 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1202 tap->wr_flags = 0; 1203 tap->wr_rate = rt2661_rxrate(desc); 1204 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1205 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1206 tap->wr_antsignal = desc->rssi; 1207 1208 bpf_ptap(sc->sc_drvbpf, m, tap, sc->sc_rxtap_len); 1209 } 1210 1211 wh = mtod(m, struct ieee80211_frame *); 1212 ni = ieee80211_find_rxnode(ic, 1213 (struct ieee80211_frame_min *)wh); 1214 1215 /* send the frame to the 802.11 layer */ 1216 ieee80211_input(ic, m, ni, desc->rssi, 0); 1217 1218 /* give rssi to the rate adatation algorithm */ 1219 rn = (struct rt2661_node *)ni; 1220 ral_rssadapt_input(ic, ni, &rn->rssadapt, 1221 rt2661_get_rssi(sc, desc->rssi)); 1222 1223 /* node is no longer needed */ 1224 ieee80211_free_node(ni); 1225 1226 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1227 1228 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1229 1230 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1231 } 1232 1233 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1234 BUS_DMASYNC_PREWRITE); 1235 } 1236 1237 /* ARGSUSED */ 1238 static void 1239 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1240 { 1241 /* do nothing */ 1242 } 1243 1244 static void 1245 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1246 { 1247 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1248 1249 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1250 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1251 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1252 1253 /* send wakeup command to MCU */ 1254 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1255 } 1256 1257 static void 1258 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1259 { 1260 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1261 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1262 } 1263 1264 static void 1265 rt2661_intr(void *arg) 1266 { 1267 struct rt2661_softc *sc = arg; 1268 struct ifnet *ifp = &sc->sc_ic.ic_if; 1269 uint32_t r1, r2; 1270 1271 /* disable MAC and MCU interrupts */ 1272 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1273 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1274 1275 /* don't re-enable interrupts if we're shutting down */ 1276 if (!(ifp->if_flags & IFF_RUNNING)) 1277 return; 1278 1279 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1280 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1281 1282 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1283 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1284 1285 if (r1 & RT2661_MGT_DONE) 1286 rt2661_tx_dma_intr(sc, &sc->mgtq); 1287 1288 if (r1 & RT2661_RX_DONE) 1289 rt2661_rx_intr(sc); 1290 1291 if (r1 & RT2661_TX0_DMA_DONE) 1292 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1293 1294 if (r1 & RT2661_TX1_DMA_DONE) 1295 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1296 1297 if (r1 & RT2661_TX2_DMA_DONE) 1298 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1299 1300 if (r1 & RT2661_TX3_DMA_DONE) 1301 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1302 1303 if (r1 & RT2661_TX_DONE) 1304 rt2661_tx_intr(sc); 1305 1306 if (r2 & RT2661_MCU_CMD_DONE) 1307 rt2661_mcu_cmd_intr(sc); 1308 1309 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1310 rt2661_mcu_beacon_expire(sc); 1311 1312 if (r2 & RT2661_MCU_WAKEUP) 1313 rt2661_mcu_wakeup(sc); 1314 1315 /* re-enable MAC and MCU interrupts */ 1316 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1317 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1318 } 1319 1320 /* quickly determine if a given rate is CCK or OFDM */ 1321 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1322 1323 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1324 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1325 1326 #define RAL_SIFS 10 /* us */ 1327 1328 /* 1329 * This function is only used by the Rx radiotap code. It returns the rate at 1330 * which a given frame was received. 1331 */ 1332 static uint8_t 1333 rt2661_rxrate(struct rt2661_rx_desc *desc) 1334 { 1335 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1336 /* reverse function of rt2661_plcp_signal */ 1337 switch (desc->rate & 0xf) { 1338 case 0xb: return 12; 1339 case 0xf: return 18; 1340 case 0xa: return 24; 1341 case 0xe: return 36; 1342 case 0x9: return 48; 1343 case 0xd: return 72; 1344 case 0x8: return 96; 1345 case 0xc: return 108; 1346 } 1347 } else { 1348 if (desc->rate == 10) 1349 return 2; 1350 if (desc->rate == 20) 1351 return 4; 1352 if (desc->rate == 55) 1353 return 11; 1354 if (desc->rate == 110) 1355 return 22; 1356 } 1357 return 2; /* should not get there */ 1358 } 1359 1360 /* 1361 * Return the expected ack rate for a frame transmitted at rate `rate'. 1362 * XXX: this should depend on the destination node basic rate set. 1363 */ 1364 static int 1365 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1366 { 1367 switch (rate) { 1368 /* CCK rates */ 1369 case 2: 1370 return 2; 1371 case 4: 1372 case 11: 1373 case 22: 1374 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1375 1376 /* OFDM rates */ 1377 case 12: 1378 case 18: 1379 return 12; 1380 case 24: 1381 case 36: 1382 return 24; 1383 case 48: 1384 case 72: 1385 case 96: 1386 case 108: 1387 return 48; 1388 } 1389 1390 /* default to 1Mbps */ 1391 return 2; 1392 } 1393 1394 /* 1395 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1396 * The function automatically determines the operating mode depending on the 1397 * given rate. `flags' indicates whether short preamble is in use or not. 1398 */ 1399 static uint16_t 1400 rt2661_txtime(int len, int rate, uint32_t flags) 1401 { 1402 uint16_t txtime; 1403 1404 if (RAL_RATE_IS_OFDM(rate)) { 1405 /* IEEE Std 802.11a-1999, pp. 37 */ 1406 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1407 txtime = 16 + 4 + 4 * txtime + 6; 1408 } else { 1409 /* IEEE Std 802.11b-1999, pp. 28 */ 1410 txtime = (16 * len + rate - 1) / rate; 1411 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1412 txtime += 72 + 24; 1413 else 1414 txtime += 144 + 48; 1415 } 1416 1417 return txtime; 1418 } 1419 1420 static uint8_t 1421 rt2661_plcp_signal(int rate) 1422 { 1423 switch (rate) { 1424 /* CCK rates (returned values are device-dependent) */ 1425 case 2: return 0x0; 1426 case 4: return 0x1; 1427 case 11: return 0x2; 1428 case 22: return 0x3; 1429 1430 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1431 case 12: return 0xb; 1432 case 18: return 0xf; 1433 case 24: return 0xa; 1434 case 36: return 0xe; 1435 case 48: return 0x9; 1436 case 72: return 0xd; 1437 case 96: return 0x8; 1438 case 108: return 0xc; 1439 1440 /* unsupported rates (should not get there) */ 1441 default: return 0xff; 1442 } 1443 } 1444 1445 static void 1446 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1447 uint32_t flags, uint16_t xflags, int len, int rate, 1448 const bus_dma_segment_t *segs, int nsegs, int ac) 1449 { 1450 struct ieee80211com *ic = &sc->sc_ic; 1451 uint16_t plcp_length; 1452 int i, remainder; 1453 1454 desc->flags = htole32(flags); 1455 desc->flags |= htole32(len << 16); 1456 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1457 1458 desc->xflags = htole16(xflags); 1459 desc->xflags |= htole16(nsegs << 13); 1460 1461 desc->wme = htole16( 1462 RT2661_QID(ac) | 1463 RT2661_AIFSN(2) | 1464 RT2661_LOGCWMIN(4) | 1465 RT2661_LOGCWMAX(10)); 1466 1467 /* 1468 * Remember in which queue this frame was sent. This field is driver 1469 * private data only. It will be made available by the NIC in STA_CSR4 1470 * on Tx interrupts. 1471 */ 1472 desc->qid = ac; 1473 1474 /* setup PLCP fields */ 1475 desc->plcp_signal = rt2661_plcp_signal(rate); 1476 desc->plcp_service = 4; 1477 1478 len += IEEE80211_CRC_LEN; 1479 if (RAL_RATE_IS_OFDM(rate)) { 1480 desc->flags |= htole32(RT2661_TX_OFDM); 1481 1482 plcp_length = len & 0xfff; 1483 desc->plcp_length_hi = plcp_length >> 6; 1484 desc->plcp_length_lo = plcp_length & 0x3f; 1485 } else { 1486 plcp_length = (16 * len + rate - 1) / rate; 1487 if (rate == 22) { 1488 remainder = (16 * len) % 22; 1489 if (remainder != 0 && remainder < 7) 1490 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1491 } 1492 desc->plcp_length_hi = plcp_length >> 8; 1493 desc->plcp_length_lo = plcp_length & 0xff; 1494 1495 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1496 desc->plcp_signal |= 0x08; 1497 } 1498 1499 /* RT2x61 supports scatter with up to 5 segments */ 1500 for (i = 0; i < nsegs; i++) { 1501 desc->addr[i] = htole32(segs[i].ds_addr); 1502 desc->len [i] = htole16(segs[i].ds_len); 1503 } 1504 } 1505 1506 static int 1507 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1508 struct ieee80211_node *ni) 1509 { 1510 struct ieee80211com *ic = &sc->sc_ic; 1511 struct rt2661_tx_desc *desc; 1512 struct rt2661_tx_data *data; 1513 struct ieee80211_frame *wh; 1514 struct rt2661_dmamap map; 1515 uint16_t dur; 1516 uint32_t flags = 0; /* XXX HWSEQ */ 1517 int rate, error; 1518 1519 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1520 data = &sc->mgtq.data[sc->mgtq.cur]; 1521 1522 /* send mgt frames at the lowest available rate */ 1523 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1524 1525 error = bus_dmamap_load_mbuf(sc->mgtq.data_dmat, data->map, m0, 1526 rt2661_dma_map_mbuf, &map, 0); 1527 if (error != 0) { 1528 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1529 error); 1530 m_freem(m0); 1531 return error; 1532 } 1533 1534 if (sc->sc_drvbpf != NULL) { 1535 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1536 1537 tap->wt_flags = 0; 1538 tap->wt_rate = rate; 1539 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1540 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1541 1542 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1543 } 1544 1545 data->m = m0; 1546 data->ni = ni; 1547 1548 wh = mtod(m0, struct ieee80211_frame *); 1549 1550 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1551 flags |= RT2661_TX_NEED_ACK; 1552 1553 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1554 RAL_SIFS; 1555 *(uint16_t *)wh->i_dur = htole16(dur); 1556 1557 /* tell hardware to add timestamp in probe responses */ 1558 if ((wh->i_fc[0] & 1559 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1560 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1561 flags |= RT2661_TX_TIMESTAMP; 1562 } 1563 1564 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1565 m0->m_pkthdr.len, rate, map.segs, map.nseg, RT2661_QID_MGT); 1566 1567 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1568 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1572 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1573 1574 /* kick mgt */ 1575 sc->mgtq.queued++; 1576 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1577 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1578 1579 return 0; 1580 } 1581 1582 /* 1583 * Build a RTS control frame. 1584 */ 1585 static struct mbuf * 1586 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1587 uint16_t dur) 1588 { 1589 struct ieee80211_frame_rts *rts; 1590 struct mbuf *m; 1591 1592 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1593 if (m == NULL) { 1594 sc->sc_ic.ic_stats.is_tx_nobuf++; 1595 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1596 return NULL; 1597 } 1598 1599 rts = mtod(m, struct ieee80211_frame_rts *); 1600 1601 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1602 IEEE80211_FC0_SUBTYPE_RTS; 1603 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1604 *(uint16_t *)rts->i_dur = htole16(dur); 1605 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1606 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1607 1608 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1609 1610 return m; 1611 } 1612 1613 static int 1614 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1615 struct ieee80211_node *ni, int ac) 1616 { 1617 struct ieee80211com *ic = &sc->sc_ic; 1618 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1619 struct rt2661_tx_desc *desc; 1620 struct rt2661_tx_data *data; 1621 struct rt2661_node *rn; 1622 struct ieee80211_rateset *rs; 1623 struct ieee80211_frame *wh; 1624 struct ieee80211_key *k; 1625 const struct chanAccParams *cap; 1626 struct mbuf *mnew; 1627 struct rt2661_dmamap map; 1628 uint16_t dur; 1629 uint32_t flags = 0; 1630 int error, rate, noack = 0; 1631 1632 wh = mtod(m0, struct ieee80211_frame *); 1633 1634 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1635 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1636 rate = rs->rs_rates[ic->ic_fixed_rate]; 1637 } else { 1638 rs = &ni->ni_rates; 1639 rn = (struct rt2661_node *)ni; 1640 ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, 1641 wh, m0->m_pkthdr.len, NULL, 0); 1642 rate = rs->rs_rates[ni->ni_txrate]; 1643 } 1644 rate &= IEEE80211_RATE_VAL; 1645 1646 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1647 cap = &ic->ic_wme.wme_chanParams; 1648 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1649 } 1650 1651 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1652 k = ieee80211_crypto_encap(ic, ni, m0); 1653 if (k == NULL) { 1654 m_freem(m0); 1655 return ENOBUFS; 1656 } 1657 1658 /* packet header may have moved, reset our local pointer */ 1659 wh = mtod(m0, struct ieee80211_frame *); 1660 } 1661 1662 /* 1663 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1664 * for directed frames only when the length of the MPDU is greater 1665 * than the length threshold indicated by [...]" ic_rtsthreshold. 1666 */ 1667 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1668 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1669 struct mbuf *m; 1670 uint16_t dur; 1671 int rtsrate, ackrate; 1672 1673 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1674 ackrate = rt2661_ack_rate(ic, rate); 1675 1676 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1677 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1678 /* XXX: noack (QoS)? */ 1679 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1680 3 * RAL_SIFS; 1681 1682 m = rt2661_get_rts(sc, wh, dur); 1683 1684 desc = &txq->desc[txq->cur]; 1685 data = &txq->data[txq->cur]; 1686 1687 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m, 1688 rt2661_dma_map_mbuf, &map, 0); 1689 if (error != 0) { 1690 device_printf(sc->sc_dev, 1691 "could not map mbuf (error %d)\n", error); 1692 m_freem(m); 1693 m_freem(m0); 1694 return error; 1695 } 1696 1697 /* avoid multiple free() of the same node for each fragment */ 1698 ieee80211_ref_node(ni); 1699 1700 data->m = m; 1701 data->ni = ni; 1702 1703 /* RTS frames are not taken into account for rssadapt */ 1704 data->id.id_node = NULL; 1705 1706 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1707 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, 1708 rtsrate, map.segs, map.nseg, ac); 1709 1710 bus_dmamap_sync(txq->data_dmat, data->map, 1711 BUS_DMASYNC_PREWRITE); 1712 1713 txq->queued++; 1714 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1715 1716 /* 1717 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1718 * asynchronous data frame shall be transmitted after the CTS 1719 * frame and a SIFS period. 1720 */ 1721 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1722 } 1723 1724 data = &txq->data[txq->cur]; 1725 desc = &txq->desc[txq->cur]; 1726 1727 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1728 rt2661_dma_map_mbuf, &map, 0); 1729 if (error != 0 && error != EFBIG) { 1730 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1731 error); 1732 m_freem(m0); 1733 return error; 1734 } 1735 if (error != 0) { 1736 mnew = m_defrag(m0, MB_DONTWAIT); 1737 if (mnew == NULL) { 1738 device_printf(sc->sc_dev, 1739 "could not defragment mbuf\n"); 1740 m_freem(m0); 1741 return ENOBUFS; 1742 } 1743 m0 = mnew; 1744 1745 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1746 rt2661_dma_map_mbuf, &map, 0); 1747 if (error != 0) { 1748 device_printf(sc->sc_dev, 1749 "could not map mbuf (error %d)\n", error); 1750 m_freem(m0); 1751 return error; 1752 } 1753 1754 /* packet header have moved, reset our local pointer */ 1755 wh = mtod(m0, struct ieee80211_frame *); 1756 } 1757 1758 if (sc->sc_drvbpf != NULL) { 1759 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1760 1761 tap->wt_flags = 0; 1762 tap->wt_rate = rate; 1763 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1764 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1765 1766 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1767 } 1768 1769 data->m = m0; 1770 data->ni = ni; 1771 1772 /* remember link conditions for rate adaptation algorithm */ 1773 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1774 data->id.id_len = m0->m_pkthdr.len; 1775 data->id.id_rateidx = ni->ni_txrate; 1776 data->id.id_node = ni; 1777 data->id.id_rssi = ni->ni_rssi; 1778 } else 1779 data->id.id_node = NULL; 1780 1781 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1782 flags |= RT2661_TX_NEED_ACK; 1783 1784 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1785 ic->ic_flags) + RAL_SIFS; 1786 *(uint16_t *)wh->i_dur = htole16(dur); 1787 } 1788 1789 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1790 map.segs, map.nseg, ac); 1791 1792 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1793 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1794 1795 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1796 m0->m_pkthdr.len, txq->cur, rate)); 1797 1798 /* kick Tx */ 1799 txq->queued++; 1800 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1801 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1802 1803 return 0; 1804 } 1805 1806 static void 1807 rt2661_start(struct ifnet *ifp) 1808 { 1809 struct rt2661_softc *sc = ifp->if_softc; 1810 struct ieee80211com *ic = &sc->sc_ic; 1811 struct mbuf *m0; 1812 struct ether_header *eh; 1813 struct ieee80211_node *ni; 1814 int ac; 1815 1816 /* prevent management frames from being sent if we're not ready */ 1817 if (!(ifp->if_flags & IFF_RUNNING)) 1818 return; 1819 1820 for (;;) { 1821 IF_POLL(&ic->ic_mgtq, m0); 1822 if (m0 != NULL) { 1823 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1824 ifp->if_flags |= IFF_OACTIVE; 1825 break; 1826 } 1827 IF_DEQUEUE(&ic->ic_mgtq, m0); 1828 1829 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1830 m0->m_pkthdr.rcvif = NULL; 1831 1832 if (ic->ic_rawbpf != NULL) 1833 bpf_mtap(ic->ic_rawbpf, m0); 1834 1835 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1836 break; 1837 1838 } else { 1839 if (ic->ic_state != IEEE80211_S_RUN) 1840 break; 1841 1842 m0 = ifq_dequeue(&ifp->if_snd, NULL); 1843 if (m0 == NULL) 1844 break; 1845 1846 if (m0->m_len < sizeof (struct ether_header) && 1847 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1848 continue; 1849 1850 eh = mtod(m0, struct ether_header *); 1851 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1852 if (ni == NULL) { 1853 m_freem(m0); 1854 ifp->if_oerrors++; 1855 continue; 1856 } 1857 1858 /* classify mbuf so we can find which tx ring to use */ 1859 if (ieee80211_classify(ic, m0, ni) != 0) { 1860 m_freem(m0); 1861 ieee80211_free_node(ni); 1862 ifp->if_oerrors++; 1863 continue; 1864 } 1865 1866 /* no QoS encapsulation for EAPOL frames */ 1867 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1868 M_WME_GETAC(m0) : WME_AC_BE; 1869 1870 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1871 /* there is no place left in this ring */ 1872 ifp->if_flags |= IFF_OACTIVE; 1873 m_freem(m0); 1874 ieee80211_free_node(ni); 1875 break; 1876 } 1877 1878 BPF_MTAP(ifp, m0); 1879 1880 m0 = ieee80211_encap(ic, m0, ni); 1881 if (m0 == NULL) { 1882 ieee80211_free_node(ni); 1883 ifp->if_oerrors++; 1884 continue; 1885 } 1886 1887 if (ic->ic_rawbpf != NULL) 1888 bpf_mtap(ic->ic_rawbpf, m0); 1889 1890 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1891 ieee80211_free_node(ni); 1892 ifp->if_oerrors++; 1893 break; 1894 } 1895 } 1896 1897 sc->sc_tx_timer = 5; 1898 ifp->if_timer = 1; 1899 } 1900 } 1901 1902 static void 1903 rt2661_watchdog(struct ifnet *ifp) 1904 { 1905 struct rt2661_softc *sc = ifp->if_softc; 1906 struct ieee80211com *ic = &sc->sc_ic; 1907 1908 ifp->if_timer = 0; 1909 1910 if (sc->sc_tx_timer > 0) { 1911 if (--sc->sc_tx_timer == 0) { 1912 device_printf(sc->sc_dev, "device timeout\n"); 1913 rt2661_init(sc); 1914 ifp->if_oerrors++; 1915 return; 1916 } 1917 ifp->if_timer = 1; 1918 } 1919 1920 ieee80211_watchdog(ic); 1921 } 1922 1923 /* 1924 * This function allows for fast channel switching in monitor mode (used by 1925 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 1926 * generate a new beacon frame. 1927 */ 1928 static int 1929 rt2661_reset(struct ifnet *ifp) 1930 { 1931 struct rt2661_softc *sc = ifp->if_softc; 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 1934 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1935 return ENETRESET; 1936 1937 rt2661_set_chan(sc, ic->ic_curchan); 1938 1939 return 0; 1940 } 1941 1942 static int 1943 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1944 { 1945 struct rt2661_softc *sc = ifp->if_softc; 1946 struct ieee80211com *ic = &sc->sc_ic; 1947 int error = 0; 1948 1949 switch (cmd) { 1950 case SIOCSIFFLAGS: 1951 if (ifp->if_flags & IFF_UP) { 1952 if (ifp->if_flags & IFF_RUNNING) 1953 rt2661_update_promisc(sc); 1954 else 1955 rt2661_init(sc); 1956 } else { 1957 if (ifp->if_flags & IFF_RUNNING) 1958 rt2661_stop(sc); 1959 } 1960 break; 1961 1962 default: 1963 error = ieee80211_ioctl(ic, cmd, data, cr); 1964 } 1965 1966 if (error == ENETRESET) { 1967 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1968 (IFF_UP | IFF_RUNNING) && 1969 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1970 rt2661_init(sc); 1971 error = 0; 1972 } 1973 return error; 1974 } 1975 1976 static void 1977 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1978 { 1979 uint32_t tmp; 1980 int ntries; 1981 1982 for (ntries = 0; ntries < 100; ntries++) { 1983 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1984 break; 1985 DELAY(1); 1986 } 1987 if (ntries == 100) { 1988 device_printf(sc->sc_dev, "could not write to BBP\n"); 1989 return; 1990 } 1991 1992 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1993 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1994 1995 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1996 } 1997 1998 static uint8_t 1999 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2000 { 2001 uint32_t val; 2002 int ntries; 2003 2004 for (ntries = 0; ntries < 100; ntries++) { 2005 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2006 break; 2007 DELAY(1); 2008 } 2009 if (ntries == 100) { 2010 device_printf(sc->sc_dev, "could not read from BBP\n"); 2011 return 0; 2012 } 2013 2014 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2015 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2016 2017 for (ntries = 0; ntries < 100; ntries++) { 2018 val = RAL_READ(sc, RT2661_PHY_CSR3); 2019 if (!(val & RT2661_BBP_BUSY)) 2020 return val & 0xff; 2021 DELAY(1); 2022 } 2023 2024 device_printf(sc->sc_dev, "could not read from BBP\n"); 2025 return 0; 2026 } 2027 2028 static void 2029 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2030 { 2031 uint32_t tmp; 2032 int ntries; 2033 2034 for (ntries = 0; ntries < 100; ntries++) { 2035 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2036 break; 2037 DELAY(1); 2038 } 2039 if (ntries == 100) { 2040 device_printf(sc->sc_dev, "could not write to RF\n"); 2041 return; 2042 } 2043 2044 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2045 (reg & 3); 2046 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2047 2048 /* remember last written value in sc */ 2049 sc->rf_regs[reg] = val; 2050 2051 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2052 } 2053 2054 static int 2055 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2056 { 2057 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2058 return EIO; /* there is already a command pending */ 2059 2060 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2061 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2062 2063 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2064 2065 return 0; 2066 } 2067 2068 static void 2069 rt2661_select_antenna(struct rt2661_softc *sc) 2070 { 2071 uint8_t bbp4, bbp77; 2072 uint32_t tmp; 2073 2074 bbp4 = rt2661_bbp_read(sc, 4); 2075 bbp77 = rt2661_bbp_read(sc, 77); 2076 2077 /* TBD */ 2078 2079 /* make sure Rx is disabled before switching antenna */ 2080 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2081 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2082 2083 rt2661_bbp_write(sc, 4, bbp4); 2084 rt2661_bbp_write(sc, 77, bbp77); 2085 2086 /* restore Rx filter */ 2087 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2088 } 2089 2090 /* 2091 * Enable multi-rate retries for frames sent at OFDM rates. 2092 * In 802.11b/g mode, allow fallback to CCK rates. 2093 */ 2094 static void 2095 rt2661_enable_mrr(struct rt2661_softc *sc) 2096 { 2097 struct ieee80211com *ic = &sc->sc_ic; 2098 uint32_t tmp; 2099 2100 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2101 2102 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2103 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2104 tmp |= RT2661_MRR_CCK_FALLBACK; 2105 tmp |= RT2661_MRR_ENABLED; 2106 2107 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2108 } 2109 2110 static void 2111 rt2661_set_txpreamble(struct rt2661_softc *sc) 2112 { 2113 uint32_t tmp; 2114 2115 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2116 2117 tmp &= ~RT2661_SHORT_PREAMBLE; 2118 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2119 tmp |= RT2661_SHORT_PREAMBLE; 2120 2121 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2122 } 2123 2124 static void 2125 rt2661_set_basicrates(struct rt2661_softc *sc, 2126 const struct ieee80211_rateset *rs) 2127 { 2128 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2129 uint32_t mask = 0; 2130 uint8_t rate; 2131 int i, j; 2132 2133 for (i = 0; i < rs->rs_nrates; i++) { 2134 rate = rs->rs_rates[i]; 2135 2136 if (!(rate & IEEE80211_RATE_BASIC)) 2137 continue; 2138 2139 /* 2140 * Find h/w rate index. We know it exists because the rate 2141 * set has already been negotiated. 2142 */ 2143 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2144 2145 mask |= 1 << j; 2146 } 2147 2148 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2149 2150 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2151 #undef RV 2152 } 2153 2154 /* 2155 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2156 * driver. 2157 */ 2158 static void 2159 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2160 { 2161 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2162 uint32_t tmp; 2163 2164 /* update all BBP registers that depend on the band */ 2165 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2166 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2167 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2168 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2169 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2170 } 2171 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2172 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2173 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2174 } 2175 2176 rt2661_bbp_write(sc, 17, bbp17); 2177 rt2661_bbp_write(sc, 96, bbp96); 2178 rt2661_bbp_write(sc, 104, bbp104); 2179 2180 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2181 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2182 rt2661_bbp_write(sc, 75, 0x80); 2183 rt2661_bbp_write(sc, 86, 0x80); 2184 rt2661_bbp_write(sc, 88, 0x80); 2185 } 2186 2187 rt2661_bbp_write(sc, 35, bbp35); 2188 rt2661_bbp_write(sc, 97, bbp97); 2189 rt2661_bbp_write(sc, 98, bbp98); 2190 2191 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2192 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2193 if (IEEE80211_IS_CHAN_2GHZ(c)) 2194 tmp |= RT2661_PA_PE_2GHZ; 2195 else 2196 tmp |= RT2661_PA_PE_5GHZ; 2197 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2198 } 2199 2200 static void 2201 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2202 { 2203 struct ieee80211com *ic = &sc->sc_ic; 2204 const struct rfprog *rfprog; 2205 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2206 int8_t power; 2207 u_int i, chan; 2208 2209 chan = ieee80211_chan2ieee(ic, c); 2210 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2211 return; 2212 2213 /* select the appropriate RF settings based on what EEPROM says */ 2214 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2215 2216 /* find the settings for this channel (we know it exists) */ 2217 for (i = 0; rfprog[i].chan != chan; i++); 2218 2219 power = sc->txpow[i]; 2220 if (power < 0) { 2221 bbp94 += power; 2222 power = 0; 2223 } else if (power > 31) { 2224 bbp94 += power - 31; 2225 power = 31; 2226 } 2227 2228 /* 2229 * If we are switching from the 2GHz band to the 5GHz band or 2230 * vice-versa, BBP registers need to be reprogrammed. 2231 */ 2232 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2233 rt2661_select_band(sc, c); 2234 rt2661_select_antenna(sc); 2235 } 2236 sc->sc_curchan = c; 2237 2238 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2239 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2240 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2241 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2242 2243 DELAY(200); 2244 2245 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2246 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2247 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2248 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2249 2250 DELAY(200); 2251 2252 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2253 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2254 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2255 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2256 2257 /* enable smart mode for MIMO-capable RFs */ 2258 bbp3 = rt2661_bbp_read(sc, 3); 2259 2260 bbp3 &= ~RT2661_SMART_MODE; 2261 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2262 bbp3 |= RT2661_SMART_MODE; 2263 2264 rt2661_bbp_write(sc, 3, bbp3); 2265 2266 if (bbp94 != RT2661_BBPR94_DEFAULT) 2267 rt2661_bbp_write(sc, 94, bbp94); 2268 2269 /* 5GHz radio needs a 1ms delay here */ 2270 if (IEEE80211_IS_CHAN_5GHZ(c)) 2271 DELAY(1000); 2272 } 2273 2274 static void 2275 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2276 { 2277 uint32_t tmp; 2278 2279 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2280 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2281 2282 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2283 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2284 } 2285 2286 static void 2287 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2288 { 2289 uint32_t tmp; 2290 2291 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2292 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2293 2294 tmp = addr[4] | addr[5] << 8; 2295 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2296 } 2297 2298 static void 2299 rt2661_update_promisc(struct rt2661_softc *sc) 2300 { 2301 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2302 uint32_t tmp; 2303 2304 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2305 2306 tmp &= ~RT2661_DROP_NOT_TO_ME; 2307 if (!(ifp->if_flags & IFF_PROMISC)) 2308 tmp |= RT2661_DROP_NOT_TO_ME; 2309 2310 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2311 2312 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2313 "entering" : "leaving")); 2314 } 2315 2316 /* 2317 * Update QoS (802.11e) settings for each h/w Tx ring. 2318 */ 2319 static int 2320 rt2661_wme_update(struct ieee80211com *ic) 2321 { 2322 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2323 const struct wmeParams *wmep; 2324 2325 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2326 2327 /* XXX: not sure about shifts. */ 2328 /* XXX: the reference driver plays with AC_VI settings too. */ 2329 2330 /* update TxOp */ 2331 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2332 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2333 wmep[WME_AC_BK].wmep_txopLimit); 2334 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2335 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2336 wmep[WME_AC_VO].wmep_txopLimit); 2337 2338 /* update CWmin */ 2339 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2340 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2341 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2342 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2343 wmep[WME_AC_VO].wmep_logcwmin); 2344 2345 /* update CWmax */ 2346 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2347 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2348 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2349 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2350 wmep[WME_AC_VO].wmep_logcwmax); 2351 2352 /* update Aifsn */ 2353 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2354 wmep[WME_AC_BE].wmep_aifsn << 12 | 2355 wmep[WME_AC_BK].wmep_aifsn << 8 | 2356 wmep[WME_AC_VI].wmep_aifsn << 4 | 2357 wmep[WME_AC_VO].wmep_aifsn); 2358 2359 return 0; 2360 } 2361 2362 static void 2363 rt2661_update_slot(struct ifnet *ifp) 2364 { 2365 struct rt2661_softc *sc = ifp->if_softc; 2366 struct ieee80211com *ic = &sc->sc_ic; 2367 uint8_t slottime; 2368 uint32_t tmp; 2369 2370 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2371 2372 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2373 tmp = (tmp & ~0xff) | slottime; 2374 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2375 } 2376 2377 static const char * 2378 rt2661_get_rf(int rev) 2379 { 2380 switch (rev) { 2381 case RT2661_RF_5225: return "RT5225"; 2382 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2383 case RT2661_RF_2527: return "RT2527"; 2384 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2385 default: return "unknown"; 2386 } 2387 } 2388 2389 static void 2390 rt2661_read_eeprom(struct rt2661_softc *sc) 2391 { 2392 struct ieee80211com *ic = &sc->sc_ic; 2393 uint16_t val; 2394 int i; 2395 2396 /* read MAC address */ 2397 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2398 ic->ic_myaddr[0] = val & 0xff; 2399 ic->ic_myaddr[1] = val >> 8; 2400 2401 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2402 ic->ic_myaddr[2] = val & 0xff; 2403 ic->ic_myaddr[3] = val >> 8; 2404 2405 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2406 ic->ic_myaddr[4] = val & 0xff; 2407 ic->ic_myaddr[5] = val >> 8; 2408 2409 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2410 /* XXX: test if different from 0xffff? */ 2411 sc->rf_rev = (val >> 11) & 0x1f; 2412 sc->hw_radio = (val >> 10) & 0x1; 2413 sc->rx_ant = (val >> 4) & 0x3; 2414 sc->tx_ant = (val >> 2) & 0x3; 2415 sc->nb_ant = val & 0x3; 2416 2417 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2418 2419 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2420 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2421 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2422 2423 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2424 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2425 2426 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2427 if ((val & 0xff) != 0xff) 2428 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2429 2430 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2431 if ((val & 0xff) != 0xff) 2432 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2433 2434 /* adjust RSSI correction for external low-noise amplifier */ 2435 if (sc->ext_2ghz_lna) 2436 sc->rssi_2ghz_corr -= 14; 2437 if (sc->ext_5ghz_lna) 2438 sc->rssi_5ghz_corr -= 14; 2439 2440 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2441 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2442 2443 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2444 if ((val >> 8) != 0xff) 2445 sc->rfprog = (val >> 8) & 0x3; 2446 if ((val & 0xff) != 0xff) 2447 sc->rffreq = val & 0xff; 2448 2449 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2450 2451 /* read Tx power for all a/b/g channels */ 2452 for (i = 0; i < 19; i++) { 2453 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2454 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2455 DPRINTF(("Channel=%d Tx power=%d\n", 2456 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2457 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2458 DPRINTF(("Channel=%d Tx power=%d\n", 2459 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2460 } 2461 2462 /* read vendor-specific BBP values */ 2463 for (i = 0; i < 16; i++) { 2464 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2465 if (val == 0 || val == 0xffff) 2466 continue; /* skip invalid entries */ 2467 sc->bbp_prom[i].reg = val >> 8; 2468 sc->bbp_prom[i].val = val & 0xff; 2469 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2470 sc->bbp_prom[i].val)); 2471 } 2472 } 2473 2474 static int 2475 rt2661_bbp_init(struct rt2661_softc *sc) 2476 { 2477 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2478 int i, ntries; 2479 uint8_t val; 2480 2481 /* wait for BBP to be ready */ 2482 for (ntries = 0; ntries < 100; ntries++) { 2483 val = rt2661_bbp_read(sc, 0); 2484 if (val != 0 && val != 0xff) 2485 break; 2486 DELAY(100); 2487 } 2488 if (ntries == 100) { 2489 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2490 return EIO; 2491 } 2492 2493 /* initialize BBP registers to default values */ 2494 for (i = 0; i < N(rt2661_def_bbp); i++) { 2495 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2496 rt2661_def_bbp[i].val); 2497 } 2498 2499 /* write vendor-specific BBP values (from EEPROM) */ 2500 for (i = 0; i < 16; i++) { 2501 if (sc->bbp_prom[i].reg == 0) 2502 continue; 2503 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2504 } 2505 2506 return 0; 2507 #undef N 2508 } 2509 2510 static void 2511 rt2661_init(void *priv) 2512 { 2513 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2514 struct rt2661_softc *sc = priv; 2515 struct ieee80211com *ic = &sc->sc_ic; 2516 struct ifnet *ifp = ic->ic_ifp; 2517 uint32_t tmp, sta[3]; 2518 int i, ntries; 2519 2520 rt2661_stop(sc); 2521 2522 /* initialize Tx rings */ 2523 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2524 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2525 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2526 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2527 2528 /* initialize Mgt ring */ 2529 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2530 2531 /* initialize Rx ring */ 2532 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2533 2534 /* initialize Tx rings sizes */ 2535 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2536 RT2661_TX_RING_COUNT << 24 | 2537 RT2661_TX_RING_COUNT << 16 | 2538 RT2661_TX_RING_COUNT << 8 | 2539 RT2661_TX_RING_COUNT); 2540 2541 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2542 RT2661_TX_DESC_WSIZE << 16 | 2543 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2544 RT2661_MGT_RING_COUNT); 2545 2546 /* initialize Rx rings */ 2547 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2548 RT2661_RX_DESC_BACK << 16 | 2549 RT2661_RX_DESC_WSIZE << 8 | 2550 RT2661_RX_RING_COUNT); 2551 2552 /* XXX: some magic here */ 2553 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2554 2555 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2556 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2557 2558 /* load base address of Rx ring */ 2559 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2560 2561 /* initialize MAC registers to default values */ 2562 for (i = 0; i < N(rt2661_def_mac); i++) 2563 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2564 2565 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2566 rt2661_set_macaddr(sc, ic->ic_myaddr); 2567 2568 /* set host ready */ 2569 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2570 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2571 2572 /* wait for BBP/RF to wakeup */ 2573 for (ntries = 0; ntries < 1000; ntries++) { 2574 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2575 break; 2576 DELAY(1000); 2577 } 2578 if (ntries == 1000) { 2579 printf("timeout waiting for BBP/RF to wakeup\n"); 2580 rt2661_stop(sc); 2581 return; 2582 } 2583 2584 if (rt2661_bbp_init(sc) != 0) { 2585 rt2661_stop(sc); 2586 return; 2587 } 2588 2589 /* select default channel */ 2590 sc->sc_curchan = ic->ic_curchan; 2591 rt2661_select_band(sc, sc->sc_curchan); 2592 rt2661_select_antenna(sc); 2593 rt2661_set_chan(sc, sc->sc_curchan); 2594 2595 /* update Rx filter */ 2596 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2597 2598 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2599 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2600 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2601 RT2661_DROP_ACKCTS; 2602 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2603 tmp |= RT2661_DROP_TODS; 2604 if (!(ifp->if_flags & IFF_PROMISC)) 2605 tmp |= RT2661_DROP_NOT_TO_ME; 2606 } 2607 2608 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2609 2610 /* clear STA registers */ 2611 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2612 2613 /* initialize ASIC */ 2614 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2615 2616 /* clear any pending interrupt */ 2617 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2618 2619 /* enable interrupts */ 2620 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2621 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2622 2623 /* kick Rx */ 2624 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2625 2626 ifp->if_flags &= ~IFF_OACTIVE; 2627 ifp->if_flags |= IFF_RUNNING; 2628 2629 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2630 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2631 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2632 } else 2633 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2634 #undef N 2635 } 2636 2637 void 2638 rt2661_stop(void *priv) 2639 { 2640 struct rt2661_softc *sc = priv; 2641 struct ieee80211com *ic = &sc->sc_ic; 2642 struct ifnet *ifp = ic->ic_ifp; 2643 uint32_t tmp; 2644 2645 sc->sc_tx_timer = 0; 2646 ifp->if_timer = 0; 2647 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2648 2649 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2650 2651 /* abort Tx (for all 5 Tx rings) */ 2652 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2653 2654 /* disable Rx (value remains after reset!) */ 2655 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2656 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2657 2658 /* reset ASIC */ 2659 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2660 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2661 2662 /* disable interrupts */ 2663 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2664 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2665 2666 /* clear any pending interrupt */ 2667 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2668 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2669 2670 /* reset Tx and Rx rings */ 2671 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2672 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2673 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2674 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2675 rt2661_reset_tx_ring(sc, &sc->mgtq); 2676 rt2661_reset_rx_ring(sc, &sc->rxq); 2677 } 2678 2679 static int 2680 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2681 { 2682 int ntries; 2683 2684 /* reset 8051 */ 2685 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2686 2687 /* cancel any pending Host to MCU command */ 2688 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2689 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2690 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2691 2692 /* write 8051's microcode */ 2693 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2694 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2695 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2696 2697 /* kick 8051's ass */ 2698 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2699 2700 /* wait for 8051 to initialize */ 2701 for (ntries = 0; ntries < 500; ntries++) { 2702 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2703 break; 2704 DELAY(100); 2705 } 2706 if (ntries == 500) { 2707 printf("timeout waiting for MCU to initialize\n"); 2708 return EIO; 2709 } 2710 return 0; 2711 } 2712 2713 #ifdef notyet 2714 /* 2715 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2716 * false CCA count. This function is called periodically (every seconds) when 2717 * in the RUN state. Values taken from the reference driver. 2718 */ 2719 static void 2720 rt2661_rx_tune(struct rt2661_softc *sc) 2721 { 2722 uint8_t bbp17; 2723 uint16_t cca; 2724 int lo, hi, dbm; 2725 2726 /* 2727 * Tuning range depends on operating band and on the presence of an 2728 * external low-noise amplifier. 2729 */ 2730 lo = 0x20; 2731 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2732 lo += 0x08; 2733 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2734 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2735 lo += 0x10; 2736 hi = lo + 0x20; 2737 2738 /* retrieve false CCA count since last call (clear on read) */ 2739 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2740 2741 if (dbm >= -35) { 2742 bbp17 = 0x60; 2743 } else if (dbm >= -58) { 2744 bbp17 = hi; 2745 } else if (dbm >= -66) { 2746 bbp17 = lo + 0x10; 2747 } else if (dbm >= -74) { 2748 bbp17 = lo + 0x08; 2749 } else { 2750 /* RSSI < -74dBm, tune using false CCA count */ 2751 2752 bbp17 = sc->bbp17; /* current value */ 2753 2754 hi -= 2 * (-74 - dbm); 2755 if (hi < lo) 2756 hi = lo; 2757 2758 if (bbp17 > hi) { 2759 bbp17 = hi; 2760 2761 } else if (cca > 512) { 2762 if (++bbp17 > hi) 2763 bbp17 = hi; 2764 } else if (cca < 100) { 2765 if (--bbp17 < lo) 2766 bbp17 = lo; 2767 } 2768 } 2769 2770 if (bbp17 != sc->bbp17) { 2771 rt2661_bbp_write(sc, 17, bbp17); 2772 sc->bbp17 = bbp17; 2773 } 2774 } 2775 2776 /* 2777 * Enter/Leave radar detection mode. 2778 * This is for 802.11h additional regulatory domains. 2779 */ 2780 static void 2781 rt2661_radar_start(struct rt2661_softc *sc) 2782 { 2783 uint32_t tmp; 2784 2785 /* disable Rx */ 2786 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2787 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2788 2789 rt2661_bbp_write(sc, 82, 0x20); 2790 rt2661_bbp_write(sc, 83, 0x00); 2791 rt2661_bbp_write(sc, 84, 0x40); 2792 2793 /* save current BBP registers values */ 2794 sc->bbp18 = rt2661_bbp_read(sc, 18); 2795 sc->bbp21 = rt2661_bbp_read(sc, 21); 2796 sc->bbp22 = rt2661_bbp_read(sc, 22); 2797 sc->bbp16 = rt2661_bbp_read(sc, 16); 2798 sc->bbp17 = rt2661_bbp_read(sc, 17); 2799 sc->bbp64 = rt2661_bbp_read(sc, 64); 2800 2801 rt2661_bbp_write(sc, 18, 0xff); 2802 rt2661_bbp_write(sc, 21, 0x3f); 2803 rt2661_bbp_write(sc, 22, 0x3f); 2804 rt2661_bbp_write(sc, 16, 0xbd); 2805 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2806 rt2661_bbp_write(sc, 64, 0x21); 2807 2808 /* restore Rx filter */ 2809 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2810 } 2811 2812 static int 2813 rt2661_radar_stop(struct rt2661_softc *sc) 2814 { 2815 uint8_t bbp66; 2816 2817 /* read radar detection result */ 2818 bbp66 = rt2661_bbp_read(sc, 66); 2819 2820 /* restore BBP registers values */ 2821 rt2661_bbp_write(sc, 16, sc->bbp16); 2822 rt2661_bbp_write(sc, 17, sc->bbp17); 2823 rt2661_bbp_write(sc, 18, sc->bbp18); 2824 rt2661_bbp_write(sc, 21, sc->bbp21); 2825 rt2661_bbp_write(sc, 22, sc->bbp22); 2826 rt2661_bbp_write(sc, 64, sc->bbp64); 2827 2828 return bbp66 == 1; 2829 } 2830 #endif 2831 2832 static int 2833 rt2661_prepare_beacon(struct rt2661_softc *sc) 2834 { 2835 struct ieee80211com *ic = &sc->sc_ic; 2836 struct ieee80211_beacon_offsets bo; 2837 struct rt2661_tx_desc desc; 2838 struct mbuf *m0; 2839 int rate; 2840 2841 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2842 if (m0 == NULL) { 2843 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2844 return ENOBUFS; 2845 } 2846 2847 /* send beacons at the lowest available rate */ 2848 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2849 2850 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2851 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2852 2853 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2854 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2855 2856 /* copy beacon header and payload into NIC memory */ 2857 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2858 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2859 2860 m_freem(m0); 2861 return 0; 2862 } 2863 2864 /* 2865 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2866 * and HostAP operating modes. 2867 */ 2868 static void 2869 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2870 { 2871 struct ieee80211com *ic = &sc->sc_ic; 2872 uint32_t tmp; 2873 2874 if (ic->ic_opmode != IEEE80211_M_STA) { 2875 /* 2876 * Change default 16ms TBTT adjustment to 8ms. 2877 * Must be done before enabling beacon generation. 2878 */ 2879 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2880 } 2881 2882 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2883 2884 /* set beacon interval (in 1/16ms unit) */ 2885 tmp |= ic->ic_bss->ni_intval * 16; 2886 2887 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2888 if (ic->ic_opmode == IEEE80211_M_STA) 2889 tmp |= RT2661_TSF_MODE(1); 2890 else 2891 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2892 2893 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2894 } 2895 2896 /* 2897 * Retrieve the "Received Signal Strength Indicator" from the raw values 2898 * contained in Rx descriptors. The computation depends on which band the 2899 * frame was received. Correction values taken from the reference driver. 2900 */ 2901 static int 2902 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2903 { 2904 int lna, agc, rssi; 2905 2906 lna = (raw >> 5) & 0x3; 2907 agc = raw & 0x1f; 2908 2909 rssi = 2 * agc; 2910 2911 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2912 rssi += sc->rssi_2ghz_corr; 2913 2914 if (lna == 1) 2915 rssi -= 64; 2916 else if (lna == 2) 2917 rssi -= 74; 2918 else if (lna == 3) 2919 rssi -= 90; 2920 } else { 2921 rssi += sc->rssi_5ghz_corr; 2922 2923 if (lna == 1) 2924 rssi -= 64; 2925 else if (lna == 2) 2926 rssi -= 86; 2927 else if (lna == 3) 2928 rssi -= 100; 2929 } 2930 return rssi; 2931 } 2932 2933 static void 2934 rt2661_dma_map_mbuf(void *arg, bus_dma_segment_t *seg, int nseg, 2935 bus_size_t map_size __unused, int error) 2936 { 2937 struct rt2661_dmamap *map = arg; 2938 2939 if (error) 2940 return; 2941 2942 KASSERT(nseg <= RT2661_MAX_SCATTER, ("too many DMA segments")); 2943 2944 bcopy(seg, map->segs, nseg * sizeof(bus_dma_segment_t)); 2945 map->nseg = nseg; 2946 } 2947