1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.20 2005/05/27 15:36:09 joerg Exp $ 35 */ 36 37 /* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * Written by Bill Paul <wpaul@osd.bsdi.com> 42 */ 43 44 /* 45 * The AMD PCnet/PCI controllers are more advanced and functional 46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 47 * backwards compatibility with the LANCE and thus can be made 48 * to work with older LANCE drivers. This is in fact how the 49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 50 * is that the PCnet/PCI devices offer several performance enhancements 51 * which can't be exploited in LANCE compatibility mode. Chief among 52 * these enhancements is the ability to perform PCI DMA operations 53 * using 32-bit addressing (which eliminates the need for ISA 54 * bounce-buffering), and special receive buffer alignment (which 55 * allows the receive handler to pass packets to the upper protocol 56 * layers without copying on both the x86 and alpha platforms). 57 */ 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/kernel.h> 65 #include <sys/socket.h> 66 67 #include <net/if.h> 68 #include <net/ifq_var.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 74 #include <net/bpf.h> 75 76 #include <vm/vm.h> /* for vtophys */ 77 #include <vm/pmap.h> /* for vtophys */ 78 #include <machine/clock.h> /* for DELAY */ 79 #include <machine/bus_pio.h> 80 #include <machine/bus_memio.h> 81 #include <machine/bus.h> 82 #include <machine/resource.h> 83 #include <sys/bus.h> 84 #include <sys/rman.h> 85 86 #include "../mii_layer/mii.h" 87 #include "../mii_layer/miivar.h" 88 89 #include <bus/pci/pcireg.h> 90 #include <bus/pci/pcivar.h> 91 92 #define PCN_USEIOSPACE 93 94 #include "if_pcnreg.h" 95 96 /* "controller miibus0" required. See GENERIC if you get errors here. */ 97 #include "miibus_if.h" 98 99 /* 100 * Various supported device vendors/types and their names. 101 */ 102 static struct pcn_type pcn_devs[] = { 103 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 104 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 105 { 0, 0, NULL } 106 }; 107 108 static u_int32_t pcn_csr_read (struct pcn_softc *, int); 109 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 110 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 111 static void pcn_csr_write (struct pcn_softc *, int, int); 112 static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 113 static void pcn_bcr_write (struct pcn_softc *, int, int); 114 115 static int pcn_probe (device_t); 116 static int pcn_attach (device_t); 117 static int pcn_detach (device_t); 118 119 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 120 static int pcn_encap (struct pcn_softc *, 121 struct mbuf *, u_int32_t *); 122 static void pcn_rxeof (struct pcn_softc *); 123 static void pcn_txeof (struct pcn_softc *); 124 static void pcn_intr (void *); 125 static void pcn_tick (void *); 126 static void pcn_start (struct ifnet *); 127 static int pcn_ioctl (struct ifnet *, u_long, caddr_t, 128 struct ucred *); 129 static void pcn_init (void *); 130 static void pcn_stop (struct pcn_softc *); 131 static void pcn_watchdog (struct ifnet *); 132 static void pcn_shutdown (device_t); 133 static int pcn_ifmedia_upd (struct ifnet *); 134 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136 static int pcn_miibus_readreg (device_t, int, int); 137 static int pcn_miibus_writereg (device_t, int, int, int); 138 static void pcn_miibus_statchg (device_t); 139 140 static void pcn_setfilt (struct ifnet *); 141 static void pcn_setmulti (struct pcn_softc *); 142 static u_int32_t pcn_crc (caddr_t); 143 static void pcn_reset (struct pcn_softc *); 144 static int pcn_list_rx_init (struct pcn_softc *); 145 static int pcn_list_tx_init (struct pcn_softc *); 146 147 #ifdef PCN_USEIOSPACE 148 #define PCN_RES SYS_RES_IOPORT 149 #define PCN_RID PCN_PCI_LOIO 150 #else 151 #define PCN_RES SYS_RES_MEMORY 152 #define PCN_RID PCN_PCI_LOMEM 153 #endif 154 155 static device_method_t pcn_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, pcn_probe), 158 DEVMETHOD(device_attach, pcn_attach), 159 DEVMETHOD(device_detach, pcn_detach), 160 DEVMETHOD(device_shutdown, pcn_shutdown), 161 162 /* bus interface */ 163 DEVMETHOD(bus_print_child, bus_generic_print_child), 164 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 165 166 /* MII interface */ 167 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 168 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 169 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 170 171 { 0, 0 } 172 }; 173 174 static driver_t pcn_driver = { 175 "pcn", 176 pcn_methods, 177 sizeof(struct pcn_softc) 178 }; 179 180 static devclass_t pcn_devclass; 181 182 DECLARE_DUMMY_MODULE(if_pcn); 183 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186 #define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189 #define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192 #define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195 #define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198 static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201 { 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204 } 205 206 static u_int16_t pcn_csr_read16(sc, reg) 207 struct pcn_softc *sc; 208 int reg; 209 { 210 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 211 return(CSR_READ_2(sc, PCN_IO16_RDP)); 212 } 213 214 static void pcn_csr_write(sc, reg, val) 215 struct pcn_softc *sc; 216 int reg; 217 { 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221 } 222 223 static u_int32_t pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226 { 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229 } 230 231 static u_int16_t pcn_bcr_read16(sc, reg) 232 struct pcn_softc *sc; 233 int reg; 234 { 235 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 236 return(CSR_READ_2(sc, PCN_IO16_BDP)); 237 } 238 239 static void pcn_bcr_write(sc, reg, val) 240 struct pcn_softc *sc; 241 int reg; 242 { 243 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 244 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 245 return; 246 } 247 248 static int pcn_miibus_readreg(dev, phy, reg) 249 device_t dev; 250 int phy, reg; 251 { 252 struct pcn_softc *sc; 253 int val; 254 255 sc = device_get_softc(dev); 256 257 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 258 return(0); 259 260 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 261 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 262 if (val == 0xFFFF) 263 return(0); 264 265 sc->pcn_phyaddr = phy; 266 267 return(val); 268 } 269 270 static int pcn_miibus_writereg(dev, phy, reg, data) 271 device_t dev; 272 int phy, reg, data; 273 { 274 struct pcn_softc *sc; 275 276 sc = device_get_softc(dev); 277 278 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 279 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 280 281 return(0); 282 } 283 284 static void pcn_miibus_statchg(dev) 285 device_t dev; 286 { 287 struct pcn_softc *sc; 288 struct mii_data *mii; 289 290 sc = device_get_softc(dev); 291 mii = device_get_softc(sc->pcn_miibus); 292 293 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 294 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 295 } else { 296 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 297 } 298 299 return; 300 } 301 302 #define DC_POLY 0xEDB88320 303 304 static u_int32_t pcn_crc(addr) 305 caddr_t addr; 306 { 307 u_int32_t idx, bit, data, crc; 308 309 /* Compute CRC for the address value. */ 310 crc = 0xFFFFFFFF; /* initial value */ 311 312 for (idx = 0; idx < 6; idx++) { 313 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 314 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 315 } 316 317 return ((crc >> 26) & 0x3F); 318 } 319 320 static void pcn_setmulti(sc) 321 struct pcn_softc *sc; 322 { 323 struct ifnet *ifp; 324 struct ifmultiaddr *ifma; 325 u_int32_t h, i; 326 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 327 328 ifp = &sc->arpcom.ac_if; 329 330 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 331 332 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 333 for (i = 0; i < 4; i++) 334 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 335 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 336 return; 337 } 338 339 /* first, zot all the existing hash bits */ 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 342 343 /* now program new ones */ 344 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 345 ifma = ifma->ifma_link.le_next) { 346 if (ifma->ifma_addr->sa_family != AF_LINK) 347 continue; 348 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 349 hashes[h >> 4] |= 1 << (h & 0xF); 350 } 351 352 for (i = 0; i < 4; i++) 353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 354 355 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 356 357 return; 358 } 359 360 static void pcn_reset(sc) 361 struct pcn_softc *sc; 362 { 363 /* 364 * Issue a reset by reading from the RESET register. 365 * Note that we don't know if the chip is operating in 366 * 16-bit or 32-bit mode at this point, so we attempt 367 * to reset the chip both ways. If one fails, the other 368 * will succeed. 369 */ 370 CSR_READ_2(sc, PCN_IO16_RESET); 371 CSR_READ_4(sc, PCN_IO32_RESET); 372 373 /* Wait a little while for the chip to get its brains in order. */ 374 DELAY(1000); 375 376 /* Select 32-bit (DWIO) mode */ 377 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 378 379 /* Select software style 3. */ 380 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 381 382 return; 383 } 384 385 /* 386 * Probe for an AMD chip. Check the PCI vendor and device 387 * IDs against our list and return a device name if we find a match. 388 */ 389 static int pcn_probe(dev) 390 device_t dev; 391 { 392 struct pcn_type *t; 393 struct pcn_softc *sc; 394 int rid; 395 u_int32_t chip_id; 396 397 t = pcn_devs; 398 sc = device_get_softc(dev); 399 400 while(t->pcn_name != NULL) { 401 if ((pci_get_vendor(dev) == t->pcn_vid) && 402 (pci_get_device(dev) == t->pcn_did)) { 403 /* 404 * Temporarily map the I/O space 405 * so we can read the chip ID register. 406 */ 407 rid = PCN_RID; 408 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, 409 &rid, RF_ACTIVE); 410 if (sc->pcn_res == NULL) { 411 device_printf(dev, 412 "couldn't map ports/memory\n"); 413 return(ENXIO); 414 } 415 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 416 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 417 /* 418 * Note: we can *NOT* put the chip into 419 * 32-bit mode yet. The lnc driver will only 420 * work in 16-bit mode, and once the chip 421 * goes into 32-bit mode, the only way to 422 * get it out again is with a hardware reset. 423 * So if pcn_probe() is called before the 424 * lnc driver's probe routine, the chip will 425 * be locked into 32-bit operation and the lnc 426 * driver will be unable to attach to it. 427 * Note II: if the chip happens to already 428 * be in 32-bit mode, we still need to check 429 * the chip ID, but first we have to detect 430 * 32-bit mode using only 16-bit operations. 431 * The safest way to do this is to read the 432 * PCI subsystem ID from BCR23/24 and compare 433 * that with the value read from PCI config 434 * space. 435 */ 436 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 437 chip_id <<= 16; 438 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 439 /* 440 * Note III: the test for 0x10001000 is a hack to 441 * pacify VMware, who's pseudo-PCnet interface is 442 * broken. Reading the subsystem register from PCI 443 * config space yeilds 0x00000000 while reading the 444 * same value from I/O space yeilds 0x10001000. It's 445 * not supposed to be that way. 446 */ 447 if (chip_id == pci_read_config(dev, 448 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 449 /* We're in 16-bit mode. */ 450 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 451 chip_id <<= 16; 452 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 453 } else { 454 /* We're in 32-bit mode. */ 455 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 456 chip_id <<= 16; 457 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 458 } 459 bus_release_resource(dev, PCN_RES, 460 PCN_RID, sc->pcn_res); 461 chip_id >>= 12; 462 sc->pcn_type = chip_id & PART_MASK; 463 switch(sc->pcn_type) { 464 case Am79C971: 465 case Am79C972: 466 case Am79C973: 467 case Am79C975: 468 case Am79C976: 469 case Am79C978: 470 break; 471 default: 472 return(ENXIO); 473 break; 474 } 475 device_set_desc(dev, t->pcn_name); 476 return(0); 477 } 478 t++; 479 } 480 481 return(ENXIO); 482 } 483 484 /* 485 * Attach the interface. Allocate softc structures, do ifmedia 486 * setup and ethernet/BPF attach. 487 */ 488 static int pcn_attach(dev) 489 device_t dev; 490 { 491 int s; 492 uint8_t eaddr[ETHER_ADDR_LEN]; 493 u_int32_t command; 494 struct pcn_softc *sc; 495 struct ifnet *ifp; 496 int unit, error = 0, rid; 497 498 s = splimp(); 499 500 sc = device_get_softc(dev); 501 unit = device_get_unit(dev); 502 503 /* 504 * Handle power management nonsense. 505 */ 506 507 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 508 if (command == 0x01) { 509 510 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 511 if (command & PCN_PSTATE_MASK) { 512 u_int32_t iobase, membase, irq; 513 514 /* Save important PCI config data. */ 515 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 516 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 517 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 518 519 /* Reset the power state. */ 520 printf("pcn%d: chip is in D%d power mode " 521 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 522 command &= 0xFFFFFFFC; 523 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 524 525 /* Restore PCI config data. */ 526 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 527 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 528 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 529 } 530 } 531 532 /* 533 * Map control/status registers. 534 */ 535 command = pci_read_config(dev, PCIR_COMMAND, 4); 536 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 537 pci_write_config(dev, PCIR_COMMAND, command, 4); 538 command = pci_read_config(dev, PCIR_COMMAND, 4); 539 540 #ifdef PCN_USEIOSPACE 541 if (!(command & PCIM_CMD_PORTEN)) { 542 printf("pcn%d: failed to enable I/O ports!\n", unit); 543 error = ENXIO;; 544 goto fail; 545 } 546 #else 547 if (!(command & PCIM_CMD_MEMEN)) { 548 printf("pcn%d: failed to enable memory mapping!\n", unit); 549 error = ENXIO;; 550 goto fail; 551 } 552 #endif 553 554 rid = PCN_RID; 555 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 556 557 if (sc->pcn_res == NULL) { 558 printf("pcn%d: couldn't map ports/memory\n", unit); 559 error = ENXIO; 560 goto fail; 561 } 562 563 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 564 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 565 566 /* Allocate interrupt */ 567 rid = 0; 568 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 569 RF_SHAREABLE | RF_ACTIVE); 570 571 if (sc->pcn_irq == NULL) { 572 printf("pcn%d: couldn't map interrupt\n", unit); 573 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 574 error = ENXIO; 575 goto fail; 576 } 577 578 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 579 pcn_intr, sc, &sc->pcn_intrhand, NULL); 580 581 if (error) { 582 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 583 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 584 printf("pcn%d: couldn't set up irq\n", unit); 585 goto fail; 586 } 587 588 /* Reset the adapter. */ 589 pcn_reset(sc); 590 591 /* 592 * Get station address from the EEPROM. 593 */ 594 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00); 595 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); 596 597 sc->pcn_unit = unit; 598 callout_init(&sc->pcn_stat_timer); 599 600 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 601 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 602 603 if (sc->pcn_ldata == NULL) { 604 printf("pcn%d: no memory for list buffers!\n", unit); 605 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 606 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 607 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 608 error = ENXIO; 609 goto fail; 610 } 611 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 612 613 ifp = &sc->arpcom.ac_if; 614 ifp->if_softc = sc; 615 if_initname(ifp, "pcn", unit); 616 ifp->if_mtu = ETHERMTU; 617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 618 ifp->if_ioctl = pcn_ioctl; 619 ifp->if_start = pcn_start; 620 ifp->if_watchdog = pcn_watchdog; 621 ifp->if_init = pcn_init; 622 ifp->if_baudrate = 10000000; 623 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1); 624 ifq_set_ready(&ifp->if_snd); 625 626 /* 627 * Do MII setup. 628 */ 629 if (mii_phy_probe(dev, &sc->pcn_miibus, 630 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 631 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 632 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 633 M_DEVBUF); 634 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 636 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 637 error = ENXIO; 638 goto fail; 639 } 640 641 /* 642 * Call MI attach routine. 643 */ 644 ether_ifattach(ifp, eaddr); 645 646 fail: 647 splx(s); 648 return(error); 649 } 650 651 static int pcn_detach(dev) 652 device_t dev; 653 { 654 struct pcn_softc *sc; 655 struct ifnet *ifp; 656 int s; 657 658 s = splimp(); 659 660 sc = device_get_softc(dev); 661 ifp = &sc->arpcom.ac_if; 662 663 pcn_reset(sc); 664 pcn_stop(sc); 665 ether_ifdetach(ifp); 666 667 if (sc->pcn_miibus != NULL) { 668 bus_generic_detach(dev); 669 device_delete_child(dev, sc->pcn_miibus); 670 } 671 672 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 674 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 675 676 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 677 678 splx(s); 679 680 return(0); 681 } 682 683 /* 684 * Initialize the transmit descriptors. 685 */ 686 static int pcn_list_tx_init(sc) 687 struct pcn_softc *sc; 688 { 689 struct pcn_list_data *ld; 690 struct pcn_ring_data *cd; 691 int i; 692 693 cd = &sc->pcn_cdata; 694 ld = sc->pcn_ldata; 695 696 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 697 cd->pcn_tx_chain[i] = NULL; 698 ld->pcn_tx_list[i].pcn_tbaddr = 0; 699 ld->pcn_tx_list[i].pcn_txctl = 0; 700 ld->pcn_tx_list[i].pcn_txstat = 0; 701 } 702 703 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 704 705 return(0); 706 } 707 708 709 /* 710 * Initialize the RX descriptors and allocate mbufs for them. 711 */ 712 static int pcn_list_rx_init(sc) 713 struct pcn_softc *sc; 714 { 715 struct pcn_list_data *ld; 716 struct pcn_ring_data *cd; 717 int i; 718 719 ld = sc->pcn_ldata; 720 cd = &sc->pcn_cdata; 721 722 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 723 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 724 return(ENOBUFS); 725 } 726 727 cd->pcn_rx_prod = 0; 728 729 return(0); 730 } 731 732 /* 733 * Initialize an RX descriptor and attach an MBUF cluster. 734 */ 735 static int pcn_newbuf(sc, idx, m) 736 struct pcn_softc *sc; 737 int idx; 738 struct mbuf *m; 739 { 740 struct mbuf *m_new = NULL; 741 struct pcn_rx_desc *c; 742 743 c = &sc->pcn_ldata->pcn_rx_list[idx]; 744 745 if (m == NULL) { 746 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 747 if (m_new == NULL) 748 return(ENOBUFS); 749 750 MCLGET(m_new, MB_DONTWAIT); 751 if (!(m_new->m_flags & M_EXT)) { 752 m_freem(m_new); 753 return(ENOBUFS); 754 } 755 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 756 } else { 757 m_new = m; 758 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 759 m_new->m_data = m_new->m_ext.ext_buf; 760 } 761 762 m_adj(m_new, ETHER_ALIGN); 763 764 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 765 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 766 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 767 c->pcn_bufsz |= PCN_RXLEN_MBO; 768 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 769 770 return(0); 771 } 772 773 /* 774 * A frame has been uploaded: pass the resulting mbuf chain up to 775 * the higher level protocols. 776 */ 777 static void pcn_rxeof(sc) 778 struct pcn_softc *sc; 779 { 780 struct mbuf *m; 781 struct ifnet *ifp; 782 struct pcn_rx_desc *cur_rx; 783 int i; 784 785 ifp = &sc->arpcom.ac_if; 786 i = sc->pcn_cdata.pcn_rx_prod; 787 788 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 789 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 790 m = sc->pcn_cdata.pcn_rx_chain[i]; 791 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 792 793 /* 794 * If an error occurs, update stats, clear the 795 * status word and leave the mbuf cluster in place: 796 * it should simply get re-used next time this descriptor 797 * comes up in the ring. 798 */ 799 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 800 ifp->if_ierrors++; 801 pcn_newbuf(sc, i, m); 802 PCN_INC(i, PCN_RX_LIST_CNT); 803 continue; 804 } 805 806 if (pcn_newbuf(sc, i, NULL)) { 807 /* Ran out of mbufs; recycle this one. */ 808 pcn_newbuf(sc, i, m); 809 ifp->if_ierrors++; 810 PCN_INC(i, PCN_RX_LIST_CNT); 811 continue; 812 } 813 814 PCN_INC(i, PCN_RX_LIST_CNT); 815 816 /* No errors; receive the packet. */ 817 ifp->if_ipackets++; 818 m->m_len = m->m_pkthdr.len = 819 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 820 m->m_pkthdr.rcvif = ifp; 821 822 (*ifp->if_input)(ifp, m); 823 } 824 825 sc->pcn_cdata.pcn_rx_prod = i; 826 827 return; 828 } 829 830 /* 831 * A frame was downloaded to the chip. It's safe for us to clean up 832 * the list buffers. 833 */ 834 835 static void pcn_txeof(sc) 836 struct pcn_softc *sc; 837 { 838 struct pcn_tx_desc *cur_tx = NULL; 839 struct ifnet *ifp; 840 u_int32_t idx; 841 842 ifp = &sc->arpcom.ac_if; 843 844 /* 845 * Go through our tx list and free mbufs for those 846 * frames that have been transmitted. 847 */ 848 idx = sc->pcn_cdata.pcn_tx_cons; 849 while (idx != sc->pcn_cdata.pcn_tx_prod) { 850 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 851 852 if (!PCN_OWN_TXDESC(cur_tx)) 853 break; 854 855 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 856 sc->pcn_cdata.pcn_tx_cnt--; 857 PCN_INC(idx, PCN_TX_LIST_CNT); 858 continue; 859 } 860 861 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 862 ifp->if_oerrors++; 863 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 864 ifp->if_collisions++; 865 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 866 ifp->if_collisions++; 867 } 868 869 ifp->if_collisions += 870 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 871 872 ifp->if_opackets++; 873 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 874 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 875 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 876 } 877 878 sc->pcn_cdata.pcn_tx_cnt--; 879 PCN_INC(idx, PCN_TX_LIST_CNT); 880 } 881 882 if (idx != sc->pcn_cdata.pcn_tx_cons) { 883 /* Some buffers have been freed. */ 884 sc->pcn_cdata.pcn_tx_cons = idx; 885 ifp->if_flags &= ~IFF_OACTIVE; 886 } 887 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 888 889 return; 890 } 891 892 static void pcn_tick(xsc) 893 void *xsc; 894 { 895 struct pcn_softc *sc; 896 struct mii_data *mii; 897 struct ifnet *ifp; 898 int s; 899 900 s = splimp(); 901 902 sc = xsc; 903 ifp = &sc->arpcom.ac_if; 904 905 mii = device_get_softc(sc->pcn_miibus); 906 mii_tick(mii); 907 908 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 909 sc->pcn_link = 0; 910 911 if (!sc->pcn_link) { 912 mii_pollstat(mii); 913 if (mii->mii_media_status & IFM_ACTIVE && 914 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 915 sc->pcn_link++; 916 if (!ifq_is_empty(&ifp->if_snd)) 917 pcn_start(ifp); 918 } 919 920 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 921 922 splx(s); 923 924 return; 925 } 926 927 static void pcn_intr(arg) 928 void *arg; 929 { 930 struct pcn_softc *sc; 931 struct ifnet *ifp; 932 u_int32_t status; 933 934 sc = arg; 935 ifp = &sc->arpcom.ac_if; 936 937 /* Supress unwanted interrupts */ 938 if (!(ifp->if_flags & IFF_UP)) { 939 pcn_stop(sc); 940 return; 941 } 942 943 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 944 945 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 946 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 947 948 if (status & PCN_CSR_RINT) 949 pcn_rxeof(sc); 950 951 if (status & PCN_CSR_TINT) 952 pcn_txeof(sc); 953 954 if (status & PCN_CSR_ERR) { 955 pcn_init(sc); 956 break; 957 } 958 } 959 960 if (!ifq_is_empty(&ifp->if_snd)) 961 pcn_start(ifp); 962 963 return; 964 } 965 966 /* 967 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 968 * pointers to the fragment pointers. 969 */ 970 static int pcn_encap(sc, m_head, txidx) 971 struct pcn_softc *sc; 972 struct mbuf *m_head; 973 u_int32_t *txidx; 974 { 975 struct pcn_tx_desc *f = NULL; 976 struct mbuf *m; 977 int frag, cur, cnt = 0; 978 979 /* 980 * Start packing the mbufs in this chain into 981 * the fragment pointers. Stop when we run out 982 * of fragments or hit the end of the mbuf chain. 983 */ 984 m = m_head; 985 cur = frag = *txidx; 986 987 for (m = m_head; m != NULL; m = m->m_next) { 988 if (m->m_len != 0) { 989 if ((PCN_TX_LIST_CNT - 990 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 991 return(ENOBUFS); 992 f = &sc->pcn_ldata->pcn_tx_list[frag]; 993 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 994 f->pcn_txctl |= PCN_TXCTL_MBO; 995 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 996 if (cnt == 0) 997 f->pcn_txctl |= PCN_TXCTL_STP; 998 else 999 f->pcn_txctl |= PCN_TXCTL_OWN; 1000 cur = frag; 1001 PCN_INC(frag, PCN_TX_LIST_CNT); 1002 cnt++; 1003 } 1004 } 1005 1006 if (m != NULL) 1007 return(ENOBUFS); 1008 1009 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1010 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1011 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1012 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1013 sc->pcn_cdata.pcn_tx_cnt += cnt; 1014 *txidx = frag; 1015 1016 return(0); 1017 } 1018 1019 /* 1020 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1021 * to the mbuf data regions directly in the transmit lists. We also save a 1022 * copy of the pointers since the transmit list fragment pointers are 1023 * physical addresses. 1024 */ 1025 static void pcn_start(ifp) 1026 struct ifnet *ifp; 1027 { 1028 struct pcn_softc *sc; 1029 struct mbuf *m_head = NULL; 1030 u_int32_t idx; 1031 1032 sc = ifp->if_softc; 1033 1034 if (!sc->pcn_link) 1035 return; 1036 1037 idx = sc->pcn_cdata.pcn_tx_prod; 1038 1039 if (ifp->if_flags & IFF_OACTIVE) 1040 return; 1041 1042 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1043 m_head = ifq_poll(&ifp->if_snd); 1044 if (m_head == NULL) 1045 break; 1046 1047 if (pcn_encap(sc, m_head, &idx)) { 1048 ifp->if_flags |= IFF_OACTIVE; 1049 break; 1050 } 1051 m_head = ifq_dequeue(&ifp->if_snd); 1052 1053 BPF_MTAP(ifp, m_head); 1054 } 1055 1056 /* Transmit */ 1057 sc->pcn_cdata.pcn_tx_prod = idx; 1058 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1059 1060 /* 1061 * Set a timeout in case the chip goes out to lunch. 1062 */ 1063 ifp->if_timer = 5; 1064 1065 return; 1066 } 1067 1068 void pcn_setfilt(ifp) 1069 struct ifnet *ifp; 1070 { 1071 struct pcn_softc *sc; 1072 1073 sc = ifp->if_softc; 1074 1075 /* If we want promiscuous mode, set the allframes bit. */ 1076 if (ifp->if_flags & IFF_PROMISC) { 1077 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1078 } else { 1079 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1080 } 1081 1082 /* Set the capture broadcast bit to capture broadcast frames. */ 1083 if (ifp->if_flags & IFF_BROADCAST) { 1084 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1085 } else { 1086 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1087 } 1088 1089 return; 1090 } 1091 1092 static void pcn_init(xsc) 1093 void *xsc; 1094 { 1095 struct pcn_softc *sc = xsc; 1096 struct ifnet *ifp = &sc->arpcom.ac_if; 1097 struct mii_data *mii = NULL; 1098 int s; 1099 1100 s = splimp(); 1101 1102 /* 1103 * Cancel pending I/O and free all RX/TX buffers. 1104 */ 1105 pcn_stop(sc); 1106 pcn_reset(sc); 1107 1108 mii = device_get_softc(sc->pcn_miibus); 1109 1110 /* Set MAC address */ 1111 pcn_csr_write(sc, PCN_CSR_PAR0, 1112 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1113 pcn_csr_write(sc, PCN_CSR_PAR1, 1114 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1115 pcn_csr_write(sc, PCN_CSR_PAR2, 1116 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1117 1118 /* Init circular RX list. */ 1119 if (pcn_list_rx_init(sc) == ENOBUFS) { 1120 printf("pcn%d: initialization failed: no " 1121 "memory for rx buffers\n", sc->pcn_unit); 1122 pcn_stop(sc); 1123 (void)splx(s); 1124 return; 1125 } 1126 1127 /* Set up RX filter. */ 1128 pcn_setfilt(ifp); 1129 1130 /* 1131 * Init tx descriptors. 1132 */ 1133 pcn_list_tx_init(sc); 1134 1135 /* Set up the mode register. */ 1136 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1137 1138 /* 1139 * Load the multicast filter. 1140 */ 1141 pcn_setmulti(sc); 1142 1143 /* 1144 * Load the addresses of the RX and TX lists. 1145 */ 1146 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1147 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1148 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1149 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1150 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1151 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1152 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1153 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1154 1155 /* Set the RX and TX ring sizes. */ 1156 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1157 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1158 1159 /* We're not using the initialization block. */ 1160 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1161 1162 /* Enable fast suspend mode. */ 1163 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1164 1165 /* 1166 * Enable burst read and write. Also set the no underflow 1167 * bit. This will avoid transmit underruns in certain 1168 * conditions while still providing decent performance. 1169 */ 1170 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1171 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1172 1173 /* Enable graceful recovery from underflow. */ 1174 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1175 1176 /* Enable auto-padding of short TX frames. */ 1177 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1178 1179 /* Disable MII autoneg (we handle this ourselves). */ 1180 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1181 1182 if (sc->pcn_type == Am79C978) 1183 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1184 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1185 1186 /* Enable interrupts and start the controller running. */ 1187 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1188 1189 mii_mediachg(mii); 1190 1191 ifp->if_flags |= IFF_RUNNING; 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 1194 (void)splx(s); 1195 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 1196 } 1197 1198 /* 1199 * Set media options. 1200 */ 1201 static int pcn_ifmedia_upd(ifp) 1202 struct ifnet *ifp; 1203 { 1204 struct pcn_softc *sc; 1205 struct mii_data *mii; 1206 1207 sc = ifp->if_softc; 1208 mii = device_get_softc(sc->pcn_miibus); 1209 1210 sc->pcn_link = 0; 1211 if (mii->mii_instance) { 1212 struct mii_softc *miisc; 1213 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1214 miisc = LIST_NEXT(miisc, mii_list)) 1215 mii_phy_reset(miisc); 1216 } 1217 mii_mediachg(mii); 1218 1219 return(0); 1220 } 1221 1222 /* 1223 * Report current media status. 1224 */ 1225 static void pcn_ifmedia_sts(ifp, ifmr) 1226 struct ifnet *ifp; 1227 struct ifmediareq *ifmr; 1228 { 1229 struct pcn_softc *sc; 1230 struct mii_data *mii; 1231 1232 sc = ifp->if_softc; 1233 1234 mii = device_get_softc(sc->pcn_miibus); 1235 mii_pollstat(mii); 1236 ifmr->ifm_active = mii->mii_media_active; 1237 ifmr->ifm_status = mii->mii_media_status; 1238 1239 return; 1240 } 1241 1242 static int pcn_ioctl(ifp, command, data, cr) 1243 struct ifnet *ifp; 1244 u_long command; 1245 caddr_t data; 1246 struct ucred *cr; 1247 { 1248 struct pcn_softc *sc = ifp->if_softc; 1249 struct ifreq *ifr = (struct ifreq *) data; 1250 struct mii_data *mii = NULL; 1251 int s, error = 0; 1252 1253 s = splimp(); 1254 1255 switch(command) { 1256 case SIOCSIFFLAGS: 1257 if (ifp->if_flags & IFF_UP) { 1258 if (ifp->if_flags & IFF_RUNNING && 1259 ifp->if_flags & IFF_PROMISC && 1260 !(sc->pcn_if_flags & IFF_PROMISC)) { 1261 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1262 PCN_EXTCTL1_SPND); 1263 pcn_setfilt(ifp); 1264 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1265 PCN_EXTCTL1_SPND); 1266 pcn_csr_write(sc, PCN_CSR_CSR, 1267 PCN_CSR_INTEN|PCN_CSR_START); 1268 } else if (ifp->if_flags & IFF_RUNNING && 1269 !(ifp->if_flags & IFF_PROMISC) && 1270 sc->pcn_if_flags & IFF_PROMISC) { 1271 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1272 PCN_EXTCTL1_SPND); 1273 pcn_setfilt(ifp); 1274 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1275 PCN_EXTCTL1_SPND); 1276 pcn_csr_write(sc, PCN_CSR_CSR, 1277 PCN_CSR_INTEN|PCN_CSR_START); 1278 } else if (!(ifp->if_flags & IFF_RUNNING)) 1279 pcn_init(sc); 1280 } else { 1281 if (ifp->if_flags & IFF_RUNNING) 1282 pcn_stop(sc); 1283 } 1284 sc->pcn_if_flags = ifp->if_flags; 1285 error = 0; 1286 break; 1287 case SIOCADDMULTI: 1288 case SIOCDELMULTI: 1289 pcn_setmulti(sc); 1290 error = 0; 1291 break; 1292 case SIOCGIFMEDIA: 1293 case SIOCSIFMEDIA: 1294 mii = device_get_softc(sc->pcn_miibus); 1295 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1296 break; 1297 default: 1298 error = ether_ioctl(ifp, command, data); 1299 break; 1300 } 1301 1302 (void)splx(s); 1303 1304 return(error); 1305 } 1306 1307 static void pcn_watchdog(ifp) 1308 struct ifnet *ifp; 1309 { 1310 struct pcn_softc *sc; 1311 1312 sc = ifp->if_softc; 1313 1314 ifp->if_oerrors++; 1315 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1316 1317 pcn_stop(sc); 1318 pcn_reset(sc); 1319 pcn_init(sc); 1320 1321 if (!ifq_is_empty(&ifp->if_snd)) 1322 pcn_start(ifp); 1323 1324 return; 1325 } 1326 1327 /* 1328 * Stop the adapter and free any mbufs allocated to the 1329 * RX and TX lists. 1330 */ 1331 static void pcn_stop(sc) 1332 struct pcn_softc *sc; 1333 { 1334 int i; 1335 struct ifnet *ifp; 1336 1337 ifp = &sc->arpcom.ac_if; 1338 ifp->if_timer = 0; 1339 1340 callout_stop(&sc->pcn_stat_timer); 1341 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1342 sc->pcn_link = 0; 1343 1344 /* 1345 * Free data in the RX lists. 1346 */ 1347 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1348 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1349 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1350 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1351 } 1352 } 1353 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1354 sizeof(sc->pcn_ldata->pcn_rx_list)); 1355 1356 /* 1357 * Free the TX list buffers. 1358 */ 1359 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1360 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1361 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1362 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1363 } 1364 } 1365 1366 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1367 sizeof(sc->pcn_ldata->pcn_tx_list)); 1368 1369 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1370 1371 return; 1372 } 1373 1374 /* 1375 * Stop all chip I/O so that the kernel's probe routines don't 1376 * get confused by errant DMAs when rebooting. 1377 */ 1378 static void pcn_shutdown(dev) 1379 device_t dev; 1380 { 1381 struct pcn_softc *sc; 1382 1383 sc = device_get_softc(dev); 1384 1385 pcn_reset(sc); 1386 pcn_stop(sc); 1387 1388 return; 1389 } 1390