1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.17 2005/02/21 18:40:36 joerg Exp $ 35 */ 36 37 /* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * Written by Bill Paul <wpaul@osd.bsdi.com> 42 */ 43 44 /* 45 * The AMD PCnet/PCI controllers are more advanced and functional 46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 47 * backwards compatibility with the LANCE and thus can be made 48 * to work with older LANCE drivers. This is in fact how the 49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 50 * is that the PCnet/PCI devices offer several performance enhancements 51 * which can't be exploited in LANCE compatibility mode. Chief among 52 * these enhancements is the ability to perform PCI DMA operations 53 * using 32-bit addressing (which eliminates the need for ISA 54 * bounce-buffering), and special receive buffer alignment (which 55 * allows the receive handler to pass packets to the upper protocol 56 * layers without copying on both the x86 and alpha platforms). 57 */ 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/kernel.h> 65 #include <sys/socket.h> 66 67 #include <net/if.h> 68 #include <net/ifq_var.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 74 #include <net/bpf.h> 75 76 #include <vm/vm.h> /* for vtophys */ 77 #include <vm/pmap.h> /* for vtophys */ 78 #include <machine/clock.h> /* for DELAY */ 79 #include <machine/bus_pio.h> 80 #include <machine/bus_memio.h> 81 #include <machine/bus.h> 82 #include <machine/resource.h> 83 #include <sys/bus.h> 84 #include <sys/rman.h> 85 86 #include "../mii_layer/mii.h" 87 #include "../mii_layer/miivar.h" 88 89 #include <bus/pci/pcireg.h> 90 #include <bus/pci/pcivar.h> 91 92 #define PCN_USEIOSPACE 93 94 #include "if_pcnreg.h" 95 96 /* "controller miibus0" required. See GENERIC if you get errors here. */ 97 #include "miibus_if.h" 98 99 /* 100 * Various supported device vendors/types and their names. 101 */ 102 static struct pcn_type pcn_devs[] = { 103 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 104 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 105 { 0, 0, NULL } 106 }; 107 108 static u_int32_t pcn_csr_read (struct pcn_softc *, int); 109 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 110 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 111 static void pcn_csr_write (struct pcn_softc *, int, int); 112 static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 113 static void pcn_bcr_write (struct pcn_softc *, int, int); 114 115 static int pcn_probe (device_t); 116 static int pcn_attach (device_t); 117 static int pcn_detach (device_t); 118 119 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 120 static int pcn_encap (struct pcn_softc *, 121 struct mbuf *, u_int32_t *); 122 static void pcn_rxeof (struct pcn_softc *); 123 static void pcn_txeof (struct pcn_softc *); 124 static void pcn_intr (void *); 125 static void pcn_tick (void *); 126 static void pcn_start (struct ifnet *); 127 static int pcn_ioctl (struct ifnet *, u_long, caddr_t, 128 struct ucred *); 129 static void pcn_init (void *); 130 static void pcn_stop (struct pcn_softc *); 131 static void pcn_watchdog (struct ifnet *); 132 static void pcn_shutdown (device_t); 133 static int pcn_ifmedia_upd (struct ifnet *); 134 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136 static int pcn_miibus_readreg (device_t, int, int); 137 static int pcn_miibus_writereg (device_t, int, int, int); 138 static void pcn_miibus_statchg (device_t); 139 140 static void pcn_setfilt (struct ifnet *); 141 static void pcn_setmulti (struct pcn_softc *); 142 static u_int32_t pcn_crc (caddr_t); 143 static void pcn_reset (struct pcn_softc *); 144 static int pcn_list_rx_init (struct pcn_softc *); 145 static int pcn_list_tx_init (struct pcn_softc *); 146 147 #ifdef PCN_USEIOSPACE 148 #define PCN_RES SYS_RES_IOPORT 149 #define PCN_RID PCN_PCI_LOIO 150 #else 151 #define PCN_RES SYS_RES_MEMORY 152 #define PCN_RID PCN_PCI_LOMEM 153 #endif 154 155 static device_method_t pcn_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, pcn_probe), 158 DEVMETHOD(device_attach, pcn_attach), 159 DEVMETHOD(device_detach, pcn_detach), 160 DEVMETHOD(device_shutdown, pcn_shutdown), 161 162 /* bus interface */ 163 DEVMETHOD(bus_print_child, bus_generic_print_child), 164 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 165 166 /* MII interface */ 167 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 168 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 169 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 170 171 { 0, 0 } 172 }; 173 174 static driver_t pcn_driver = { 175 "pcn", 176 pcn_methods, 177 sizeof(struct pcn_softc) 178 }; 179 180 static devclass_t pcn_devclass; 181 182 DECLARE_DUMMY_MODULE(if_pcn); 183 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186 #define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189 #define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192 #define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195 #define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198 static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201 { 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204 } 205 206 static u_int16_t pcn_csr_read16(sc, reg) 207 struct pcn_softc *sc; 208 int reg; 209 { 210 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 211 return(CSR_READ_2(sc, PCN_IO16_RDP)); 212 } 213 214 static void pcn_csr_write(sc, reg, val) 215 struct pcn_softc *sc; 216 int reg; 217 { 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221 } 222 223 static u_int32_t pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226 { 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229 } 230 231 static u_int16_t pcn_bcr_read16(sc, reg) 232 struct pcn_softc *sc; 233 int reg; 234 { 235 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 236 return(CSR_READ_2(sc, PCN_IO16_BDP)); 237 } 238 239 static void pcn_bcr_write(sc, reg, val) 240 struct pcn_softc *sc; 241 int reg; 242 { 243 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 244 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 245 return; 246 } 247 248 static int pcn_miibus_readreg(dev, phy, reg) 249 device_t dev; 250 int phy, reg; 251 { 252 struct pcn_softc *sc; 253 int val; 254 255 sc = device_get_softc(dev); 256 257 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 258 return(0); 259 260 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 261 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 262 if (val == 0xFFFF) 263 return(0); 264 265 sc->pcn_phyaddr = phy; 266 267 return(val); 268 } 269 270 static int pcn_miibus_writereg(dev, phy, reg, data) 271 device_t dev; 272 int phy, reg, data; 273 { 274 struct pcn_softc *sc; 275 276 sc = device_get_softc(dev); 277 278 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 279 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 280 281 return(0); 282 } 283 284 static void pcn_miibus_statchg(dev) 285 device_t dev; 286 { 287 struct pcn_softc *sc; 288 struct mii_data *mii; 289 290 sc = device_get_softc(dev); 291 mii = device_get_softc(sc->pcn_miibus); 292 293 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 294 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 295 } else { 296 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 297 } 298 299 return; 300 } 301 302 #define DC_POLY 0xEDB88320 303 304 static u_int32_t pcn_crc(addr) 305 caddr_t addr; 306 { 307 u_int32_t idx, bit, data, crc; 308 309 /* Compute CRC for the address value. */ 310 crc = 0xFFFFFFFF; /* initial value */ 311 312 for (idx = 0; idx < 6; idx++) { 313 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 314 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 315 } 316 317 return ((crc >> 26) & 0x3F); 318 } 319 320 static void pcn_setmulti(sc) 321 struct pcn_softc *sc; 322 { 323 struct ifnet *ifp; 324 struct ifmultiaddr *ifma; 325 u_int32_t h, i; 326 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 327 328 ifp = &sc->arpcom.ac_if; 329 330 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 331 332 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 333 for (i = 0; i < 4; i++) 334 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 335 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 336 return; 337 } 338 339 /* first, zot all the existing hash bits */ 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 342 343 /* now program new ones */ 344 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 345 ifma = ifma->ifma_link.le_next) { 346 if (ifma->ifma_addr->sa_family != AF_LINK) 347 continue; 348 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 349 hashes[h >> 4] |= 1 << (h & 0xF); 350 } 351 352 for (i = 0; i < 4; i++) 353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 354 355 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 356 357 return; 358 } 359 360 static void pcn_reset(sc) 361 struct pcn_softc *sc; 362 { 363 /* 364 * Issue a reset by reading from the RESET register. 365 * Note that we don't know if the chip is operating in 366 * 16-bit or 32-bit mode at this point, so we attempt 367 * to reset the chip both ways. If one fails, the other 368 * will succeed. 369 */ 370 CSR_READ_2(sc, PCN_IO16_RESET); 371 CSR_READ_4(sc, PCN_IO32_RESET); 372 373 /* Wait a little while for the chip to get its brains in order. */ 374 DELAY(1000); 375 376 /* Select 32-bit (DWIO) mode */ 377 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 378 379 /* Select software style 3. */ 380 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 381 382 return; 383 } 384 385 /* 386 * Probe for an AMD chip. Check the PCI vendor and device 387 * IDs against our list and return a device name if we find a match. 388 */ 389 static int pcn_probe(dev) 390 device_t dev; 391 { 392 struct pcn_type *t; 393 struct pcn_softc *sc; 394 int rid; 395 u_int32_t chip_id; 396 397 t = pcn_devs; 398 sc = device_get_softc(dev); 399 400 while(t->pcn_name != NULL) { 401 if ((pci_get_vendor(dev) == t->pcn_vid) && 402 (pci_get_device(dev) == t->pcn_did)) { 403 /* 404 * Temporarily map the I/O space 405 * so we can read the chip ID register. 406 */ 407 rid = PCN_RID; 408 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 409 0, ~0, 1, RF_ACTIVE); 410 if (sc->pcn_res == NULL) { 411 device_printf(dev, 412 "couldn't map ports/memory\n"); 413 return(ENXIO); 414 } 415 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 416 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 417 /* 418 * Note: we can *NOT* put the chip into 419 * 32-bit mode yet. The lnc driver will only 420 * work in 16-bit mode, and once the chip 421 * goes into 32-bit mode, the only way to 422 * get it out again is with a hardware reset. 423 * So if pcn_probe() is called before the 424 * lnc driver's probe routine, the chip will 425 * be locked into 32-bit operation and the lnc 426 * driver will be unable to attach to it. 427 * Note II: if the chip happens to already 428 * be in 32-bit mode, we still need to check 429 * the chip ID, but first we have to detect 430 * 32-bit mode using only 16-bit operations. 431 * The safest way to do this is to read the 432 * PCI subsystem ID from BCR23/24 and compare 433 * that with the value read from PCI config 434 * space. 435 */ 436 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 437 chip_id <<= 16; 438 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 439 /* 440 * Note III: the test for 0x10001000 is a hack to 441 * pacify VMware, who's pseudo-PCnet interface is 442 * broken. Reading the subsystem register from PCI 443 * config space yeilds 0x00000000 while reading the 444 * same value from I/O space yeilds 0x10001000. It's 445 * not supposed to be that way. 446 */ 447 if (chip_id == pci_read_config(dev, 448 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 449 /* We're in 16-bit mode. */ 450 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 451 chip_id <<= 16; 452 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 453 } else { 454 /* We're in 32-bit mode. */ 455 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 456 chip_id <<= 16; 457 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 458 } 459 bus_release_resource(dev, PCN_RES, 460 PCN_RID, sc->pcn_res); 461 chip_id >>= 12; 462 sc->pcn_type = chip_id & PART_MASK; 463 switch(sc->pcn_type) { 464 case Am79C971: 465 case Am79C972: 466 case Am79C973: 467 case Am79C975: 468 case Am79C976: 469 case Am79C978: 470 break; 471 default: 472 return(ENXIO); 473 break; 474 } 475 device_set_desc(dev, t->pcn_name); 476 return(0); 477 } 478 t++; 479 } 480 481 return(ENXIO); 482 } 483 484 /* 485 * Attach the interface. Allocate softc structures, do ifmedia 486 * setup and ethernet/BPF attach. 487 */ 488 static int pcn_attach(dev) 489 device_t dev; 490 { 491 int s; 492 uint8_t eaddr[ETHER_ADDR_LEN]; 493 u_int32_t command; 494 struct pcn_softc *sc; 495 struct ifnet *ifp; 496 int unit, error = 0, rid; 497 498 s = splimp(); 499 500 sc = device_get_softc(dev); 501 unit = device_get_unit(dev); 502 503 /* 504 * Handle power management nonsense. 505 */ 506 507 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 508 if (command == 0x01) { 509 510 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 511 if (command & PCN_PSTATE_MASK) { 512 u_int32_t iobase, membase, irq; 513 514 /* Save important PCI config data. */ 515 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 516 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 517 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 518 519 /* Reset the power state. */ 520 printf("pcn%d: chip is in D%d power mode " 521 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 522 command &= 0xFFFFFFFC; 523 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 524 525 /* Restore PCI config data. */ 526 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 527 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 528 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 529 } 530 } 531 532 /* 533 * Map control/status registers. 534 */ 535 command = pci_read_config(dev, PCIR_COMMAND, 4); 536 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 537 pci_write_config(dev, PCIR_COMMAND, command, 4); 538 command = pci_read_config(dev, PCIR_COMMAND, 4); 539 540 #ifdef PCN_USEIOSPACE 541 if (!(command & PCIM_CMD_PORTEN)) { 542 printf("pcn%d: failed to enable I/O ports!\n", unit); 543 error = ENXIO;; 544 goto fail; 545 } 546 #else 547 if (!(command & PCIM_CMD_MEMEN)) { 548 printf("pcn%d: failed to enable memory mapping!\n", unit); 549 error = ENXIO;; 550 goto fail; 551 } 552 #endif 553 554 rid = PCN_RID; 555 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 556 0, ~0, 1, RF_ACTIVE); 557 558 if (sc->pcn_res == NULL) { 559 printf("pcn%d: couldn't map ports/memory\n", unit); 560 error = ENXIO; 561 goto fail; 562 } 563 564 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 565 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 566 567 /* Allocate interrupt */ 568 rid = 0; 569 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 570 RF_SHAREABLE | RF_ACTIVE); 571 572 if (sc->pcn_irq == NULL) { 573 printf("pcn%d: couldn't map interrupt\n", unit); 574 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 575 error = ENXIO; 576 goto fail; 577 } 578 579 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 580 pcn_intr, sc, &sc->pcn_intrhand); 581 582 if (error) { 583 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 584 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 585 printf("pcn%d: couldn't set up irq\n", unit); 586 goto fail; 587 } 588 589 /* Reset the adapter. */ 590 pcn_reset(sc); 591 592 /* 593 * Get station address from the EEPROM. 594 */ 595 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00); 596 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); 597 598 sc->pcn_unit = unit; 599 callout_init(&sc->pcn_stat_timer); 600 601 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 602 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 603 604 if (sc->pcn_ldata == NULL) { 605 printf("pcn%d: no memory for list buffers!\n", unit); 606 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 608 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 609 error = ENXIO; 610 goto fail; 611 } 612 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 613 614 ifp = &sc->arpcom.ac_if; 615 ifp->if_softc = sc; 616 if_initname(ifp, "pcn", unit); 617 ifp->if_mtu = ETHERMTU; 618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 619 ifp->if_ioctl = pcn_ioctl; 620 ifp->if_start = pcn_start; 621 ifp->if_watchdog = pcn_watchdog; 622 ifp->if_init = pcn_init; 623 ifp->if_baudrate = 10000000; 624 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1); 625 ifq_set_ready(&ifp->if_snd); 626 627 /* 628 * Do MII setup. 629 */ 630 if (mii_phy_probe(dev, &sc->pcn_miibus, 631 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 632 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 633 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 634 M_DEVBUF); 635 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 636 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 637 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 638 error = ENXIO; 639 goto fail; 640 } 641 642 /* 643 * Call MI attach routine. 644 */ 645 ether_ifattach(ifp, eaddr); 646 647 fail: 648 splx(s); 649 return(error); 650 } 651 652 static int pcn_detach(dev) 653 device_t dev; 654 { 655 struct pcn_softc *sc; 656 struct ifnet *ifp; 657 int s; 658 659 s = splimp(); 660 661 sc = device_get_softc(dev); 662 ifp = &sc->arpcom.ac_if; 663 664 pcn_reset(sc); 665 pcn_stop(sc); 666 ether_ifdetach(ifp); 667 668 if (sc->pcn_miibus != NULL) { 669 bus_generic_detach(dev); 670 device_delete_child(dev, sc->pcn_miibus); 671 } 672 673 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 674 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 675 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 676 677 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 678 679 splx(s); 680 681 return(0); 682 } 683 684 /* 685 * Initialize the transmit descriptors. 686 */ 687 static int pcn_list_tx_init(sc) 688 struct pcn_softc *sc; 689 { 690 struct pcn_list_data *ld; 691 struct pcn_ring_data *cd; 692 int i; 693 694 cd = &sc->pcn_cdata; 695 ld = sc->pcn_ldata; 696 697 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 698 cd->pcn_tx_chain[i] = NULL; 699 ld->pcn_tx_list[i].pcn_tbaddr = 0; 700 ld->pcn_tx_list[i].pcn_txctl = 0; 701 ld->pcn_tx_list[i].pcn_txstat = 0; 702 } 703 704 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 705 706 return(0); 707 } 708 709 710 /* 711 * Initialize the RX descriptors and allocate mbufs for them. 712 */ 713 static int pcn_list_rx_init(sc) 714 struct pcn_softc *sc; 715 { 716 struct pcn_list_data *ld; 717 struct pcn_ring_data *cd; 718 int i; 719 720 ld = sc->pcn_ldata; 721 cd = &sc->pcn_cdata; 722 723 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 724 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 725 return(ENOBUFS); 726 } 727 728 cd->pcn_rx_prod = 0; 729 730 return(0); 731 } 732 733 /* 734 * Initialize an RX descriptor and attach an MBUF cluster. 735 */ 736 static int pcn_newbuf(sc, idx, m) 737 struct pcn_softc *sc; 738 int idx; 739 struct mbuf *m; 740 { 741 struct mbuf *m_new = NULL; 742 struct pcn_rx_desc *c; 743 744 c = &sc->pcn_ldata->pcn_rx_list[idx]; 745 746 if (m == NULL) { 747 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 748 if (m_new == NULL) 749 return(ENOBUFS); 750 751 MCLGET(m_new, MB_DONTWAIT); 752 if (!(m_new->m_flags & M_EXT)) { 753 m_freem(m_new); 754 return(ENOBUFS); 755 } 756 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 757 } else { 758 m_new = m; 759 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 760 m_new->m_data = m_new->m_ext.ext_buf; 761 } 762 763 m_adj(m_new, ETHER_ALIGN); 764 765 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 766 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 767 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 768 c->pcn_bufsz |= PCN_RXLEN_MBO; 769 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 770 771 return(0); 772 } 773 774 /* 775 * A frame has been uploaded: pass the resulting mbuf chain up to 776 * the higher level protocols. 777 */ 778 static void pcn_rxeof(sc) 779 struct pcn_softc *sc; 780 { 781 struct mbuf *m; 782 struct ifnet *ifp; 783 struct pcn_rx_desc *cur_rx; 784 int i; 785 786 ifp = &sc->arpcom.ac_if; 787 i = sc->pcn_cdata.pcn_rx_prod; 788 789 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 790 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 791 m = sc->pcn_cdata.pcn_rx_chain[i]; 792 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 793 794 /* 795 * If an error occurs, update stats, clear the 796 * status word and leave the mbuf cluster in place: 797 * it should simply get re-used next time this descriptor 798 * comes up in the ring. 799 */ 800 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 801 ifp->if_ierrors++; 802 pcn_newbuf(sc, i, m); 803 PCN_INC(i, PCN_RX_LIST_CNT); 804 continue; 805 } 806 807 if (pcn_newbuf(sc, i, NULL)) { 808 /* Ran out of mbufs; recycle this one. */ 809 pcn_newbuf(sc, i, m); 810 ifp->if_ierrors++; 811 PCN_INC(i, PCN_RX_LIST_CNT); 812 continue; 813 } 814 815 PCN_INC(i, PCN_RX_LIST_CNT); 816 817 /* No errors; receive the packet. */ 818 ifp->if_ipackets++; 819 m->m_len = m->m_pkthdr.len = 820 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 821 m->m_pkthdr.rcvif = ifp; 822 823 (*ifp->if_input)(ifp, m); 824 } 825 826 sc->pcn_cdata.pcn_rx_prod = i; 827 828 return; 829 } 830 831 /* 832 * A frame was downloaded to the chip. It's safe for us to clean up 833 * the list buffers. 834 */ 835 836 static void pcn_txeof(sc) 837 struct pcn_softc *sc; 838 { 839 struct pcn_tx_desc *cur_tx = NULL; 840 struct ifnet *ifp; 841 u_int32_t idx; 842 843 ifp = &sc->arpcom.ac_if; 844 845 /* 846 * Go through our tx list and free mbufs for those 847 * frames that have been transmitted. 848 */ 849 idx = sc->pcn_cdata.pcn_tx_cons; 850 while (idx != sc->pcn_cdata.pcn_tx_prod) { 851 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 852 853 if (!PCN_OWN_TXDESC(cur_tx)) 854 break; 855 856 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 857 sc->pcn_cdata.pcn_tx_cnt--; 858 PCN_INC(idx, PCN_TX_LIST_CNT); 859 continue; 860 } 861 862 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 863 ifp->if_oerrors++; 864 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 865 ifp->if_collisions++; 866 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 867 ifp->if_collisions++; 868 } 869 870 ifp->if_collisions += 871 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 872 873 ifp->if_opackets++; 874 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 875 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 876 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 877 } 878 879 sc->pcn_cdata.pcn_tx_cnt--; 880 PCN_INC(idx, PCN_TX_LIST_CNT); 881 } 882 883 if (idx != sc->pcn_cdata.pcn_tx_cons) { 884 /* Some buffers have been freed. */ 885 sc->pcn_cdata.pcn_tx_cons = idx; 886 ifp->if_flags &= ~IFF_OACTIVE; 887 } 888 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 889 890 return; 891 } 892 893 static void pcn_tick(xsc) 894 void *xsc; 895 { 896 struct pcn_softc *sc; 897 struct mii_data *mii; 898 struct ifnet *ifp; 899 int s; 900 901 s = splimp(); 902 903 sc = xsc; 904 ifp = &sc->arpcom.ac_if; 905 906 mii = device_get_softc(sc->pcn_miibus); 907 mii_tick(mii); 908 909 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 910 sc->pcn_link = 0; 911 912 if (!sc->pcn_link) { 913 mii_pollstat(mii); 914 if (mii->mii_media_status & IFM_ACTIVE && 915 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 916 sc->pcn_link++; 917 if (!ifq_is_empty(&ifp->if_snd)) 918 pcn_start(ifp); 919 } 920 921 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 922 923 splx(s); 924 925 return; 926 } 927 928 static void pcn_intr(arg) 929 void *arg; 930 { 931 struct pcn_softc *sc; 932 struct ifnet *ifp; 933 u_int32_t status; 934 935 sc = arg; 936 ifp = &sc->arpcom.ac_if; 937 938 /* Supress unwanted interrupts */ 939 if (!(ifp->if_flags & IFF_UP)) { 940 pcn_stop(sc); 941 return; 942 } 943 944 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 945 946 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 947 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 948 949 if (status & PCN_CSR_RINT) 950 pcn_rxeof(sc); 951 952 if (status & PCN_CSR_TINT) 953 pcn_txeof(sc); 954 955 if (status & PCN_CSR_ERR) { 956 pcn_init(sc); 957 break; 958 } 959 } 960 961 if (!ifq_is_empty(&ifp->if_snd)) 962 pcn_start(ifp); 963 964 return; 965 } 966 967 /* 968 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 969 * pointers to the fragment pointers. 970 */ 971 static int pcn_encap(sc, m_head, txidx) 972 struct pcn_softc *sc; 973 struct mbuf *m_head; 974 u_int32_t *txidx; 975 { 976 struct pcn_tx_desc *f = NULL; 977 struct mbuf *m; 978 int frag, cur, cnt = 0; 979 980 /* 981 * Start packing the mbufs in this chain into 982 * the fragment pointers. Stop when we run out 983 * of fragments or hit the end of the mbuf chain. 984 */ 985 m = m_head; 986 cur = frag = *txidx; 987 988 for (m = m_head; m != NULL; m = m->m_next) { 989 if (m->m_len != 0) { 990 if ((PCN_TX_LIST_CNT - 991 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 992 return(ENOBUFS); 993 f = &sc->pcn_ldata->pcn_tx_list[frag]; 994 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 995 f->pcn_txctl |= PCN_TXCTL_MBO; 996 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 997 if (cnt == 0) 998 f->pcn_txctl |= PCN_TXCTL_STP; 999 else 1000 f->pcn_txctl |= PCN_TXCTL_OWN; 1001 cur = frag; 1002 PCN_INC(frag, PCN_TX_LIST_CNT); 1003 cnt++; 1004 } 1005 } 1006 1007 if (m != NULL) 1008 return(ENOBUFS); 1009 1010 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1011 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1012 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1013 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1014 sc->pcn_cdata.pcn_tx_cnt += cnt; 1015 *txidx = frag; 1016 1017 return(0); 1018 } 1019 1020 /* 1021 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1022 * to the mbuf data regions directly in the transmit lists. We also save a 1023 * copy of the pointers since the transmit list fragment pointers are 1024 * physical addresses. 1025 */ 1026 static void pcn_start(ifp) 1027 struct ifnet *ifp; 1028 { 1029 struct pcn_softc *sc; 1030 struct mbuf *m_head = NULL; 1031 u_int32_t idx; 1032 1033 sc = ifp->if_softc; 1034 1035 if (!sc->pcn_link) 1036 return; 1037 1038 idx = sc->pcn_cdata.pcn_tx_prod; 1039 1040 if (ifp->if_flags & IFF_OACTIVE) 1041 return; 1042 1043 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1044 m_head = ifq_poll(&ifp->if_snd); 1045 if (m_head == NULL) 1046 break; 1047 1048 if (pcn_encap(sc, m_head, &idx)) { 1049 ifp->if_flags |= IFF_OACTIVE; 1050 break; 1051 } 1052 m_head = ifq_dequeue(&ifp->if_snd); 1053 1054 BPF_MTAP(ifp, m_head); 1055 } 1056 1057 /* Transmit */ 1058 sc->pcn_cdata.pcn_tx_prod = idx; 1059 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1060 1061 /* 1062 * Set a timeout in case the chip goes out to lunch. 1063 */ 1064 ifp->if_timer = 5; 1065 1066 return; 1067 } 1068 1069 void pcn_setfilt(ifp) 1070 struct ifnet *ifp; 1071 { 1072 struct pcn_softc *sc; 1073 1074 sc = ifp->if_softc; 1075 1076 /* If we want promiscuous mode, set the allframes bit. */ 1077 if (ifp->if_flags & IFF_PROMISC) { 1078 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1079 } else { 1080 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1081 } 1082 1083 /* Set the capture broadcast bit to capture broadcast frames. */ 1084 if (ifp->if_flags & IFF_BROADCAST) { 1085 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1086 } else { 1087 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1088 } 1089 1090 return; 1091 } 1092 1093 static void pcn_init(xsc) 1094 void *xsc; 1095 { 1096 struct pcn_softc *sc = xsc; 1097 struct ifnet *ifp = &sc->arpcom.ac_if; 1098 struct mii_data *mii = NULL; 1099 int s; 1100 1101 s = splimp(); 1102 1103 /* 1104 * Cancel pending I/O and free all RX/TX buffers. 1105 */ 1106 pcn_stop(sc); 1107 pcn_reset(sc); 1108 1109 mii = device_get_softc(sc->pcn_miibus); 1110 1111 /* Set MAC address */ 1112 pcn_csr_write(sc, PCN_CSR_PAR0, 1113 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1114 pcn_csr_write(sc, PCN_CSR_PAR1, 1115 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1116 pcn_csr_write(sc, PCN_CSR_PAR2, 1117 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1118 1119 /* Init circular RX list. */ 1120 if (pcn_list_rx_init(sc) == ENOBUFS) { 1121 printf("pcn%d: initialization failed: no " 1122 "memory for rx buffers\n", sc->pcn_unit); 1123 pcn_stop(sc); 1124 (void)splx(s); 1125 return; 1126 } 1127 1128 /* Set up RX filter. */ 1129 pcn_setfilt(ifp); 1130 1131 /* 1132 * Init tx descriptors. 1133 */ 1134 pcn_list_tx_init(sc); 1135 1136 /* Set up the mode register. */ 1137 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1138 1139 /* 1140 * Load the multicast filter. 1141 */ 1142 pcn_setmulti(sc); 1143 1144 /* 1145 * Load the addresses of the RX and TX lists. 1146 */ 1147 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1148 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1149 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1150 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1151 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1152 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1153 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1154 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1155 1156 /* Set the RX and TX ring sizes. */ 1157 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1158 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1159 1160 /* We're not using the initialization block. */ 1161 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1162 1163 /* Enable fast suspend mode. */ 1164 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1165 1166 /* 1167 * Enable burst read and write. Also set the no underflow 1168 * bit. This will avoid transmit underruns in certain 1169 * conditions while still providing decent performance. 1170 */ 1171 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1172 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1173 1174 /* Enable graceful recovery from underflow. */ 1175 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1176 1177 /* Enable auto-padding of short TX frames. */ 1178 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1179 1180 /* Disable MII autoneg (we handle this ourselves). */ 1181 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1182 1183 if (sc->pcn_type == Am79C978) 1184 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1185 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1186 1187 /* Enable interrupts and start the controller running. */ 1188 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1189 1190 mii_mediachg(mii); 1191 1192 ifp->if_flags |= IFF_RUNNING; 1193 ifp->if_flags &= ~IFF_OACTIVE; 1194 1195 (void)splx(s); 1196 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 1197 } 1198 1199 /* 1200 * Set media options. 1201 */ 1202 static int pcn_ifmedia_upd(ifp) 1203 struct ifnet *ifp; 1204 { 1205 struct pcn_softc *sc; 1206 struct mii_data *mii; 1207 1208 sc = ifp->if_softc; 1209 mii = device_get_softc(sc->pcn_miibus); 1210 1211 sc->pcn_link = 0; 1212 if (mii->mii_instance) { 1213 struct mii_softc *miisc; 1214 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1215 miisc = LIST_NEXT(miisc, mii_list)) 1216 mii_phy_reset(miisc); 1217 } 1218 mii_mediachg(mii); 1219 1220 return(0); 1221 } 1222 1223 /* 1224 * Report current media status. 1225 */ 1226 static void pcn_ifmedia_sts(ifp, ifmr) 1227 struct ifnet *ifp; 1228 struct ifmediareq *ifmr; 1229 { 1230 struct pcn_softc *sc; 1231 struct mii_data *mii; 1232 1233 sc = ifp->if_softc; 1234 1235 mii = device_get_softc(sc->pcn_miibus); 1236 mii_pollstat(mii); 1237 ifmr->ifm_active = mii->mii_media_active; 1238 ifmr->ifm_status = mii->mii_media_status; 1239 1240 return; 1241 } 1242 1243 static int pcn_ioctl(ifp, command, data, cr) 1244 struct ifnet *ifp; 1245 u_long command; 1246 caddr_t data; 1247 struct ucred *cr; 1248 { 1249 struct pcn_softc *sc = ifp->if_softc; 1250 struct ifreq *ifr = (struct ifreq *) data; 1251 struct mii_data *mii = NULL; 1252 int s, error = 0; 1253 1254 s = splimp(); 1255 1256 switch(command) { 1257 case SIOCSIFADDR: 1258 case SIOCGIFADDR: 1259 case SIOCSIFMTU: 1260 error = ether_ioctl(ifp, command, data); 1261 break; 1262 case SIOCSIFFLAGS: 1263 if (ifp->if_flags & IFF_UP) { 1264 if (ifp->if_flags & IFF_RUNNING && 1265 ifp->if_flags & IFF_PROMISC && 1266 !(sc->pcn_if_flags & IFF_PROMISC)) { 1267 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1268 PCN_EXTCTL1_SPND); 1269 pcn_setfilt(ifp); 1270 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1271 PCN_EXTCTL1_SPND); 1272 pcn_csr_write(sc, PCN_CSR_CSR, 1273 PCN_CSR_INTEN|PCN_CSR_START); 1274 } else if (ifp->if_flags & IFF_RUNNING && 1275 !(ifp->if_flags & IFF_PROMISC) && 1276 sc->pcn_if_flags & IFF_PROMISC) { 1277 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1278 PCN_EXTCTL1_SPND); 1279 pcn_setfilt(ifp); 1280 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1281 PCN_EXTCTL1_SPND); 1282 pcn_csr_write(sc, PCN_CSR_CSR, 1283 PCN_CSR_INTEN|PCN_CSR_START); 1284 } else if (!(ifp->if_flags & IFF_RUNNING)) 1285 pcn_init(sc); 1286 } else { 1287 if (ifp->if_flags & IFF_RUNNING) 1288 pcn_stop(sc); 1289 } 1290 sc->pcn_if_flags = ifp->if_flags; 1291 error = 0; 1292 break; 1293 case SIOCADDMULTI: 1294 case SIOCDELMULTI: 1295 pcn_setmulti(sc); 1296 error = 0; 1297 break; 1298 case SIOCGIFMEDIA: 1299 case SIOCSIFMEDIA: 1300 mii = device_get_softc(sc->pcn_miibus); 1301 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1302 break; 1303 default: 1304 error = EINVAL; 1305 break; 1306 } 1307 1308 (void)splx(s); 1309 1310 return(error); 1311 } 1312 1313 static void pcn_watchdog(ifp) 1314 struct ifnet *ifp; 1315 { 1316 struct pcn_softc *sc; 1317 1318 sc = ifp->if_softc; 1319 1320 ifp->if_oerrors++; 1321 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1322 1323 pcn_stop(sc); 1324 pcn_reset(sc); 1325 pcn_init(sc); 1326 1327 if (!ifq_is_empty(&ifp->if_snd)) 1328 pcn_start(ifp); 1329 1330 return; 1331 } 1332 1333 /* 1334 * Stop the adapter and free any mbufs allocated to the 1335 * RX and TX lists. 1336 */ 1337 static void pcn_stop(sc) 1338 struct pcn_softc *sc; 1339 { 1340 int i; 1341 struct ifnet *ifp; 1342 1343 ifp = &sc->arpcom.ac_if; 1344 ifp->if_timer = 0; 1345 1346 callout_stop(&sc->pcn_stat_timer); 1347 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1348 sc->pcn_link = 0; 1349 1350 /* 1351 * Free data in the RX lists. 1352 */ 1353 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1354 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1355 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1356 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1357 } 1358 } 1359 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1360 sizeof(sc->pcn_ldata->pcn_rx_list)); 1361 1362 /* 1363 * Free the TX list buffers. 1364 */ 1365 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1366 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1367 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1368 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1369 } 1370 } 1371 1372 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1373 sizeof(sc->pcn_ldata->pcn_tx_list)); 1374 1375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1376 1377 return; 1378 } 1379 1380 /* 1381 * Stop all chip I/O so that the kernel's probe routines don't 1382 * get confused by errant DMAs when rebooting. 1383 */ 1384 static void pcn_shutdown(dev) 1385 device_t dev; 1386 { 1387 struct pcn_softc *sc; 1388 1389 sc = device_get_softc(dev); 1390 1391 pcn_reset(sc); 1392 pcn_stop(sc); 1393 1394 return; 1395 } 1396