1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.27 2005/05/31 14:11:42 joerg Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 #include <net/vlan/if_vlan_var.h> 107 108 #include <net/bpf.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <dev/netif/mii_layer/mii.h> 118 #include <dev/netif/mii_layer/miivar.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 #define NGE_USEIOSPACE 124 125 #include "if_ngereg.h" 126 127 128 /* "controller miibus0" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 133 /* 134 * Various supported device vendors/types and their names. 135 */ 136 static struct nge_type nge_devs[] = { 137 { NGE_VENDORID, NGE_DEVICEID, 138 "National Semiconductor Gigabit Ethernet" }, 139 { 0, 0, NULL } 140 }; 141 142 static int nge_probe(device_t); 143 static int nge_attach(device_t); 144 static int nge_detach(device_t); 145 146 static int nge_alloc_jumbo_mem(struct nge_softc *); 147 static void nge_free_jumbo_mem(struct nge_softc *); 148 static struct nge_jslot 149 *nge_jalloc(struct nge_softc *); 150 static void nge_jfree(void *); 151 static void nge_jref(void *); 152 153 static int nge_newbuf(struct nge_softc *, struct nge_desc *, 154 struct mbuf *); 155 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *); 156 static void nge_rxeof(struct nge_softc *); 157 static void nge_txeof(struct nge_softc *); 158 static void nge_intr(void *); 159 static void nge_tick(void *); 160 static void nge_start(struct ifnet *); 161 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 162 static void nge_init(void *); 163 static void nge_stop(struct nge_softc *); 164 static void nge_watchdog(struct ifnet *); 165 static void nge_shutdown(device_t); 166 static int nge_ifmedia_upd(struct ifnet *); 167 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 168 169 static void nge_delay(struct nge_softc *); 170 static void nge_eeprom_idle(struct nge_softc *); 171 static void nge_eeprom_putbyte(struct nge_softc *, int); 172 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 173 static void nge_read_eeprom(struct nge_softc *, void *, int, int); 174 175 static void nge_mii_sync(struct nge_softc *); 176 static void nge_mii_send(struct nge_softc *, uint32_t, int); 177 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 178 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 179 180 static int nge_miibus_readreg(device_t, int, int); 181 static int nge_miibus_writereg(device_t, int, int, int); 182 static void nge_miibus_statchg(device_t); 183 184 static void nge_setmulti(struct nge_softc *); 185 static void nge_reset(struct nge_softc *); 186 static int nge_list_rx_init(struct nge_softc *); 187 static int nge_list_tx_init(struct nge_softc *); 188 #ifdef DEVICE_POLLING 189 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 190 #endif 191 192 #ifdef NGE_USEIOSPACE 193 #define NGE_RES SYS_RES_IOPORT 194 #define NGE_RID NGE_PCI_LOIO 195 #else 196 #define NGE_RES SYS_RES_MEMORY 197 #define NGE_RID NGE_PCI_LOMEM 198 #endif 199 200 static device_method_t nge_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, nge_probe), 203 DEVMETHOD(device_attach, nge_attach), 204 DEVMETHOD(device_detach, nge_detach), 205 DEVMETHOD(device_shutdown, nge_shutdown), 206 207 /* bus interface */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 213 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 214 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 215 216 { 0, 0 } 217 }; 218 219 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc)); 220 static devclass_t nge_devclass; 221 222 DECLARE_DUMMY_MODULE(if_nge); 223 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 224 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 225 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 226 227 #define NGE_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 229 230 #define NGE_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 235 236 #define SIO_CLR(x) \ 237 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 238 239 static void 240 nge_delay(struct nge_softc *sc) 241 { 242 int idx; 243 244 for (idx = (300 / 33) + 1; idx > 0; idx--) 245 CSR_READ_4(sc, NGE_CSR); 246 } 247 248 static void 249 nge_eeprom_idle(struct nge_softc *sc) 250 { 251 int i; 252 253 SIO_SET(NGE_MEAR_EE_CSEL); 254 nge_delay(sc); 255 SIO_SET(NGE_MEAR_EE_CLK); 256 nge_delay(sc); 257 258 for (i = 0; i < 25; i++) { 259 SIO_CLR(NGE_MEAR_EE_CLK); 260 nge_delay(sc); 261 SIO_SET(NGE_MEAR_EE_CLK); 262 nge_delay(sc); 263 } 264 265 SIO_CLR(NGE_MEAR_EE_CLK); 266 nge_delay(sc); 267 SIO_CLR(NGE_MEAR_EE_CSEL); 268 nge_delay(sc); 269 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 270 } 271 272 /* 273 * Send a read command and address to the EEPROM, check for ACK. 274 */ 275 static void 276 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 277 { 278 int d, i; 279 280 d = addr | NGE_EECMD_READ; 281 282 /* 283 * Feed in each bit and stobe the clock. 284 */ 285 for (i = 0x400; i; i >>= 1) { 286 if (d & i) 287 SIO_SET(NGE_MEAR_EE_DIN); 288 else 289 SIO_CLR(NGE_MEAR_EE_DIN); 290 nge_delay(sc); 291 SIO_SET(NGE_MEAR_EE_CLK); 292 nge_delay(sc); 293 SIO_CLR(NGE_MEAR_EE_CLK); 294 nge_delay(sc); 295 } 296 } 297 298 /* 299 * Read a word of data stored in the EEPROM at address 'addr.' 300 */ 301 static void 302 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 303 { 304 int i; 305 uint16_t word = 0; 306 307 /* Force EEPROM to idle state. */ 308 nge_eeprom_idle(sc); 309 310 /* Enter EEPROM access mode. */ 311 nge_delay(sc); 312 SIO_CLR(NGE_MEAR_EE_CLK); 313 nge_delay(sc); 314 SIO_SET(NGE_MEAR_EE_CSEL); 315 nge_delay(sc); 316 317 /* 318 * Send address of word we want to read. 319 */ 320 nge_eeprom_putbyte(sc, addr); 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 for (i = 0x8000; i; i >>= 1) { 326 SIO_SET(NGE_MEAR_EE_CLK); 327 nge_delay(sc); 328 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 329 word |= i; 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 } 334 335 /* Turn off EEPROM access mode. */ 336 nge_eeprom_idle(sc); 337 338 *dest = word; 339 } 340 341 /* 342 * Read a sequence of words from the EEPROM. 343 */ 344 static void 345 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt) 346 { 347 int i; 348 uint16_t word = 0, *ptr; 349 350 for (i = 0; i < cnt; i++) { 351 nge_eeprom_getword(sc, off + i, &word); 352 ptr = (uint16_t *)((uint8_t *)dest + (i * 2)); 353 *ptr = word; 354 } 355 } 356 357 /* 358 * Sync the PHYs by setting data bit and strobing the clock 32 times. 359 */ 360 static void 361 nge_mii_sync(struct nge_softc *sc) 362 { 363 int i; 364 365 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA); 366 367 for (i = 0; i < 32; i++) { 368 SIO_SET(NGE_MEAR_MII_CLK); 369 DELAY(1); 370 SIO_CLR(NGE_MEAR_MII_CLK); 371 DELAY(1); 372 } 373 } 374 375 /* 376 * Clock a series of bits through the MII. 377 */ 378 static void 379 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 380 { 381 int i; 382 383 SIO_CLR(NGE_MEAR_MII_CLK); 384 385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 386 if (bits & i) 387 SIO_SET(NGE_MEAR_MII_DATA); 388 else 389 SIO_CLR(NGE_MEAR_MII_DATA); 390 DELAY(1); 391 SIO_CLR(NGE_MEAR_MII_CLK); 392 DELAY(1); 393 SIO_SET(NGE_MEAR_MII_CLK); 394 } 395 } 396 397 /* 398 * Read an PHY register through the MII. 399 */ 400 static int 401 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 402 { 403 int ack, i, s; 404 405 s = splimp(); 406 407 /* 408 * Set up frame for RX. 409 */ 410 frame->mii_stdelim = NGE_MII_STARTDELIM; 411 frame->mii_opcode = NGE_MII_READOP; 412 frame->mii_turnaround = 0; 413 frame->mii_data = 0; 414 415 CSR_WRITE_4(sc, NGE_MEAR, 0); 416 417 /* 418 * Turn on data xmit. 419 */ 420 SIO_SET(NGE_MEAR_MII_DIR); 421 422 nge_mii_sync(sc); 423 424 /* 425 * Send command/address info. 426 */ 427 nge_mii_send(sc, frame->mii_stdelim, 2); 428 nge_mii_send(sc, frame->mii_opcode, 2); 429 nge_mii_send(sc, frame->mii_phyaddr, 5); 430 nge_mii_send(sc, frame->mii_regaddr, 5); 431 432 /* Idle bit */ 433 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA)); 434 DELAY(1); 435 SIO_SET(NGE_MEAR_MII_CLK); 436 DELAY(1); 437 438 /* Turn off xmit. */ 439 SIO_CLR(NGE_MEAR_MII_DIR); 440 /* Check for ack */ 441 SIO_CLR(NGE_MEAR_MII_CLK); 442 DELAY(1); 443 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 444 SIO_SET(NGE_MEAR_MII_CLK); 445 DELAY(1); 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 SIO_CLR(NGE_MEAR_MII_CLK); 454 DELAY(1); 455 SIO_SET(NGE_MEAR_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 SIO_CLR(NGE_MEAR_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 SIO_SET(NGE_MEAR_MII_CLK); 470 DELAY(1); 471 } 472 473 fail: 474 SIO_CLR(NGE_MEAR_MII_CLK); 475 DELAY(1); 476 SIO_SET(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 479 splx(s); 480 481 if (ack) 482 return(1); 483 return(0); 484 } 485 486 /* 487 * Write to a PHY register through the MII. 488 */ 489 static int 490 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 491 { 492 int s; 493 494 s = splimp(); 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = NGE_MII_STARTDELIM; 500 frame->mii_opcode = NGE_MII_WRITEOP; 501 frame->mii_turnaround = NGE_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(NGE_MEAR_MII_DIR); 507 508 nge_mii_sync(sc); 509 510 nge_mii_send(sc, frame->mii_stdelim, 2); 511 nge_mii_send(sc, frame->mii_opcode, 2); 512 nge_mii_send(sc, frame->mii_phyaddr, 5); 513 nge_mii_send(sc, frame->mii_regaddr, 5); 514 nge_mii_send(sc, frame->mii_turnaround, 2); 515 nge_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 SIO_CLR(NGE_MEAR_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(NGE_MEAR_MII_DIR); 527 528 splx(s); 529 530 return(0); 531 } 532 533 static int 534 nge_miibus_readreg(device_t dev, int phy, int reg) 535 { 536 struct nge_softc *sc = device_get_softc(dev); 537 struct nge_mii_frame frame; 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = phy; 542 frame.mii_regaddr = reg; 543 nge_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546 } 547 548 static int 549 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 550 { 551 struct nge_softc *sc = device_get_softc(dev); 552 struct nge_mii_frame frame; 553 554 bzero((char *)&frame, sizeof(frame)); 555 556 frame.mii_phyaddr = phy; 557 frame.mii_regaddr = reg; 558 frame.mii_data = data; 559 nge_mii_writereg(sc, &frame); 560 561 return(0); 562 } 563 564 static void 565 nge_miibus_statchg(device_t dev) 566 { 567 struct nge_softc *sc = device_get_softc(dev); 568 struct mii_data *mii; 569 int status; 570 571 if (sc->nge_tbi) { 572 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 573 == IFM_AUTO) { 574 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 575 if (status == 0 || status & NGE_TBIANAR_FDX) { 576 NGE_SETBIT(sc, NGE_TX_CFG, 577 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 578 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 579 } else { 580 NGE_CLRBIT(sc, NGE_TX_CFG, 581 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 582 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 583 } 584 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 585 != IFM_FDX) { 586 NGE_CLRBIT(sc, NGE_TX_CFG, 587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 588 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 589 } else { 590 NGE_SETBIT(sc, NGE_TX_CFG, 591 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 592 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 593 } 594 } else { 595 mii = device_get_softc(sc->nge_miibus); 596 597 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 598 NGE_SETBIT(sc, NGE_TX_CFG, 599 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 600 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 601 } else { 602 NGE_CLRBIT(sc, NGE_TX_CFG, 603 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 604 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 605 } 606 607 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 608 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 609 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 610 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 611 } else { 612 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 613 } 614 } 615 } 616 617 static void 618 nge_setmulti(struct nge_softc *sc) 619 { 620 struct ifnet *ifp = &sc->arpcom.ac_if; 621 struct ifmultiaddr *ifma; 622 uint32_t filtsave, h = 0, i; 623 int bit, index; 624 625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 626 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 627 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 628 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 629 return; 630 } 631 632 /* 633 * We have to explicitly enable the multicast hash table 634 * on the NatSemi chip if we want to use it, which we do. 635 * We also have to tell it that we don't want to use the 636 * hash table for matching unicast addresses. 637 */ 638 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 639 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 640 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH); 641 642 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 643 644 /* first, zot all the existing hash bits */ 645 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 646 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 647 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 648 } 649 650 /* 651 * From the 11 bits returned by the crc routine, the top 7 652 * bits represent the 16-bit word in the mcast hash table 653 * that needs to be updated, and the lower 4 bits represent 654 * which bit within that byte needs to be set. 655 */ 656 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 657 if (ifma->ifma_addr->sa_family != AF_LINK) 658 continue; 659 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 660 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 661 index = (h >> 4) & 0x7F; 662 bit = h & 0xF; 663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 664 NGE_FILTADDR_MCAST_LO + (index * 2)); 665 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 666 } 667 668 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 669 } 670 671 static void 672 nge_reset(struct nge_softc *sc) 673 { 674 int i; 675 676 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 677 678 for (i = 0; i < NGE_TIMEOUT; i++) { 679 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0) 680 break; 681 } 682 683 if (i == NGE_TIMEOUT) 684 printf("nge%d: reset never completed\n", sc->nge_unit); 685 686 /* Wait a little while for the chip to get its brains in order. */ 687 DELAY(1000); 688 689 /* 690 * If this is a NetSemi chip, make sure to clear 691 * PME mode. 692 */ 693 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 694 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 695 } 696 697 /* 698 * Probe for an NatSemi chip. Check the PCI vendor and device 699 * IDs against our list and return a device name if we find a match. 700 */ 701 static int 702 nge_probe(device_t dev) 703 { 704 struct nge_type *t; 705 uint16_t vendor, product; 706 707 vendor = pci_get_vendor(dev); 708 product = pci_get_device(dev); 709 710 for (t = nge_devs; t->nge_name != NULL; t++) { 711 if (vendor == t->nge_vid && product == t->nge_did) { 712 device_set_desc(dev, t->nge_name); 713 return(0); 714 } 715 } 716 717 return(ENXIO); 718 } 719 720 /* 721 * Attach the interface. Allocate softc structures, do ifmedia 722 * setup and ethernet/BPF attach. 723 */ 724 static int 725 nge_attach(device_t dev) 726 { 727 struct nge_softc *sc; 728 struct ifnet *ifp; 729 uint8_t eaddr[ETHER_ADDR_LEN]; 730 uint32_t command; 731 int error = 0, rid, s, unit; 732 const char *sep = ""; 733 734 s = splimp(); 735 736 sc = device_get_softc(dev); 737 unit = device_get_unit(dev); 738 callout_init(&sc->nge_stat_timer); 739 740 /* 741 * Handle power management nonsense. 742 */ 743 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 744 if (command == 0x01) { 745 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 746 if (command & NGE_PSTATE_MASK) { 747 uint32_t iobase, membase, irq; 748 749 /* Save important PCI config data. */ 750 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 751 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 752 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 753 754 /* Reset the power state. */ 755 printf("nge%d: chip is in D%d power mode " 756 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 757 command &= 0xFFFFFFFC; 758 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 759 760 /* Restore PCI config data. */ 761 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 762 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 763 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 764 } 765 } 766 767 /* 768 * Map control/status registers. 769 */ 770 command = pci_read_config(dev, PCIR_COMMAND, 4); 771 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 772 pci_write_config(dev, PCIR_COMMAND, command, 4); 773 command = pci_read_config(dev, PCIR_COMMAND, 4); 774 775 #ifdef NGE_USEIOSPACE 776 if (!(command & PCIM_CMD_PORTEN)) { 777 printf("nge%d: failed to enable I/O ports!\n", unit); 778 error = ENXIO;; 779 goto fail; 780 } 781 #else 782 if (!(command & PCIM_CMD_MEMEN)) { 783 printf("nge%d: failed to enable memory mapping!\n", unit); 784 error = ENXIO;; 785 goto fail; 786 } 787 #endif 788 789 rid = NGE_RID; 790 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 791 792 if (sc->nge_res == NULL) { 793 printf("nge%d: couldn't map ports/memory\n", unit); 794 error = ENXIO; 795 goto fail; 796 } 797 798 sc->nge_btag = rman_get_bustag(sc->nge_res); 799 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 800 801 /* Allocate interrupt */ 802 rid = 0; 803 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 804 RF_SHAREABLE | RF_ACTIVE); 805 806 if (sc->nge_irq == NULL) { 807 printf("nge%d: couldn't map interrupt\n", unit); 808 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 809 error = ENXIO; 810 goto fail; 811 } 812 813 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 814 nge_intr, sc, &sc->nge_intrhand, NULL); 815 816 if (error) { 817 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 818 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 819 printf("nge%d: couldn't set up irq\n", unit); 820 goto fail; 821 } 822 823 /* Reset the adapter. */ 824 nge_reset(sc); 825 826 /* 827 * Get station address from the EEPROM. 828 */ 829 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1); 830 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1); 831 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1); 832 833 sc->nge_unit = unit; 834 835 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 836 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 837 838 if (sc->nge_ldata == NULL) { 839 printf("nge%d: no memory for list buffers!\n", unit); 840 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 842 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 843 error = ENXIO; 844 goto fail; 845 } 846 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 847 848 /* Try to allocate memory for jumbo buffers. */ 849 if (nge_alloc_jumbo_mem(sc)) { 850 printf("nge%d: jumbo buffer allocation failed\n", 851 sc->nge_unit); 852 contigfree(sc->nge_ldata, 853 sizeof(struct nge_list_data), M_DEVBUF); 854 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 856 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 857 error = ENXIO; 858 goto fail; 859 } 860 861 ifp = &sc->arpcom.ac_if; 862 ifp->if_softc = sc; 863 if_initname(ifp, "nge", unit); 864 ifp->if_mtu = ETHERMTU; 865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 866 ifp->if_ioctl = nge_ioctl; 867 ifp->if_start = nge_start; 868 #ifdef DEVICE_POLLING 869 ifp->if_poll = nge_poll; 870 #endif 871 ifp->if_watchdog = nge_watchdog; 872 ifp->if_init = nge_init; 873 ifp->if_baudrate = 1000000000; 874 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 875 ifq_set_ready(&ifp->if_snd); 876 ifp->if_hwassist = NGE_CSUM_FEATURES; 877 ifp->if_capabilities = IFCAP_HWCSUM; 878 ifp->if_capenable = ifp->if_capabilities; 879 880 /* 881 * Do MII setup. 882 */ 883 if (mii_phy_probe(dev, &sc->nge_miibus, 884 nge_ifmedia_upd, nge_ifmedia_sts)) { 885 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 886 sc->nge_tbi = 1; 887 device_printf(dev, "Using TBI\n"); 888 889 sc->nge_miibus = dev; 890 891 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 892 nge_ifmedia_sts); 893 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 894 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 895 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 896 device_printf(dev, " "); 897 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 898 PRINT("1000baseSX"); 899 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 900 PRINT("1000baseSX-FDX"); 901 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 902 PRINT("auto"); 903 904 printf("\n"); 905 #undef ADD 906 #undef PRINT 907 ifmedia_set(&sc->nge_ifmedia, 908 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 909 910 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 911 | NGE_GPIO_GP4_OUT 912 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 913 | NGE_GPIO_GP3_OUTENB 914 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 915 916 } else { 917 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 918 nge_free_jumbo_mem(sc); 919 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 920 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 921 bus_release_resource(dev, NGE_RES, NGE_RID, 922 sc->nge_res); 923 error = ENXIO; 924 goto fail; 925 } 926 } 927 928 /* 929 * Call MI attach routine. 930 */ 931 ether_ifattach(ifp, eaddr); 932 933 fail: 934 935 splx(s); 936 return(error); 937 } 938 939 static int 940 nge_detach(device_t dev) 941 { 942 struct nge_softc *sc; 943 struct ifnet *ifp; 944 int s; 945 946 s = splimp(); 947 948 sc = device_get_softc(dev); 949 ifp = &sc->arpcom.ac_if; 950 951 nge_reset(sc); 952 nge_stop(sc); 953 ether_ifdetach(ifp); 954 955 bus_generic_detach(dev); 956 if (!sc->nge_tbi) 957 device_delete_child(dev, sc->nge_miibus); 958 959 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 961 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 962 963 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 964 nge_free_jumbo_mem(sc); 965 966 splx(s); 967 968 return(0); 969 } 970 971 /* 972 * Initialize the transmit descriptors. 973 */ 974 static int 975 nge_list_tx_init(struct nge_softc *sc) 976 { 977 struct nge_list_data *ld; 978 struct nge_ring_data *cd; 979 int i; 980 981 cd = &sc->nge_cdata; 982 ld = sc->nge_ldata; 983 984 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 985 if (i == (NGE_TX_LIST_CNT - 1)) { 986 ld->nge_tx_list[i].nge_nextdesc = 987 &ld->nge_tx_list[0]; 988 ld->nge_tx_list[i].nge_next = 989 vtophys(&ld->nge_tx_list[0]); 990 } else { 991 ld->nge_tx_list[i].nge_nextdesc = 992 &ld->nge_tx_list[i + 1]; 993 ld->nge_tx_list[i].nge_next = 994 vtophys(&ld->nge_tx_list[i + 1]); 995 } 996 ld->nge_tx_list[i].nge_mbuf = NULL; 997 ld->nge_tx_list[i].nge_ptr = 0; 998 ld->nge_tx_list[i].nge_ctl = 0; 999 } 1000 1001 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1002 1003 return(0); 1004 } 1005 1006 1007 /* 1008 * Initialize the RX descriptors and allocate mbufs for them. Note that 1009 * we arrange the descriptors in a closed ring, so that the last descriptor 1010 * points back to the first. 1011 */ 1012 static int 1013 nge_list_rx_init(struct nge_softc *sc) 1014 { 1015 struct nge_list_data *ld; 1016 struct nge_ring_data *cd; 1017 int i; 1018 1019 ld = sc->nge_ldata; 1020 cd = &sc->nge_cdata; 1021 1022 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1023 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1024 return(ENOBUFS); 1025 if (i == (NGE_RX_LIST_CNT - 1)) { 1026 ld->nge_rx_list[i].nge_nextdesc = 1027 &ld->nge_rx_list[0]; 1028 ld->nge_rx_list[i].nge_next = 1029 vtophys(&ld->nge_rx_list[0]); 1030 } else { 1031 ld->nge_rx_list[i].nge_nextdesc = 1032 &ld->nge_rx_list[i + 1]; 1033 ld->nge_rx_list[i].nge_next = 1034 vtophys(&ld->nge_rx_list[i + 1]); 1035 } 1036 } 1037 1038 cd->nge_rx_prod = 0; 1039 1040 return(0); 1041 } 1042 1043 /* 1044 * Initialize an RX descriptor and attach an MBUF cluster. 1045 */ 1046 static int 1047 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 1048 { 1049 struct mbuf *m_new = NULL; 1050 struct nge_jslot *buf; 1051 1052 if (m == NULL) { 1053 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1054 if (m_new == NULL) { 1055 printf("nge%d: no memory for rx list " 1056 "-- packet dropped!\n", sc->nge_unit); 1057 return(ENOBUFS); 1058 } 1059 1060 /* Allocate the jumbo buffer */ 1061 buf = nge_jalloc(sc); 1062 if (buf == NULL) { 1063 #ifdef NGE_VERBOSE 1064 printf("nge%d: jumbo allocation failed " 1065 "-- packet dropped!\n", sc->nge_unit); 1066 #endif 1067 m_freem(m_new); 1068 return(ENOBUFS); 1069 } 1070 /* Attach the buffer to the mbuf */ 1071 m_new->m_ext.ext_arg = buf; 1072 m_new->m_ext.ext_buf = buf->nge_buf; 1073 m_new->m_ext.ext_free = nge_jfree; 1074 m_new->m_ext.ext_ref = nge_jref; 1075 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN; 1076 1077 m_new->m_data = m_new->m_ext.ext_buf; 1078 m_new->m_flags |= M_EXT; 1079 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1080 } else { 1081 m_new = m; 1082 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN; 1083 m_new->m_data = m_new->m_ext.ext_buf; 1084 } 1085 1086 m_adj(m_new, sizeof(uint64_t)); 1087 1088 c->nge_mbuf = m_new; 1089 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1090 c->nge_ctl = m_new->m_len; 1091 c->nge_extsts = 0; 1092 1093 return(0); 1094 } 1095 1096 static int 1097 nge_alloc_jumbo_mem(struct nge_softc *sc) 1098 { 1099 caddr_t ptr; 1100 int i; 1101 struct nge_jslot *entry; 1102 1103 /* Grab a big chunk o' storage. */ 1104 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1105 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1106 1107 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1108 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1109 return(ENOBUFS); 1110 } 1111 1112 SLIST_INIT(&sc->nge_jfree_listhead); 1113 1114 /* 1115 * Now divide it up into 9K pieces and save the addresses 1116 * in an array. 1117 */ 1118 ptr = sc->nge_cdata.nge_jumbo_buf; 1119 for (i = 0; i < NGE_JSLOTS; i++) { 1120 entry = &sc->nge_cdata.nge_jslots[i]; 1121 entry->nge_sc = sc; 1122 entry->nge_buf = ptr; 1123 entry->nge_inuse = 0; 1124 entry->nge_slot = i; 1125 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1126 ptr += NGE_JLEN; 1127 } 1128 1129 return(0); 1130 } 1131 1132 static void 1133 nge_free_jumbo_mem(struct nge_softc *sc) 1134 { 1135 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1136 } 1137 1138 /* 1139 * Allocate a jumbo buffer. 1140 */ 1141 static struct nge_jslot * 1142 nge_jalloc(struct nge_softc *sc) 1143 { 1144 struct nge_jslot *entry; 1145 1146 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1147 1148 if (entry == NULL) { 1149 #ifdef NGE_VERBOSE 1150 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1151 #endif 1152 return(NULL); 1153 } 1154 1155 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link); 1156 entry->nge_inuse = 1; 1157 1158 return(entry); 1159 } 1160 1161 /* 1162 * Adjust usage count on a jumbo buffer. In general this doesn't 1163 * get used much because our jumbo buffers don't get passed around 1164 * a lot, but it's implemented for correctness. 1165 */ 1166 static void 1167 nge_jref(void *arg) 1168 { 1169 struct nge_jslot *entry = (struct nge_jslot *)arg; 1170 struct nge_softc *sc = entry->nge_sc; 1171 1172 if (sc == NULL) 1173 panic("nge_jref: can't find softc pointer!"); 1174 1175 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1176 panic("nge_jref: asked to reference buffer " 1177 "that we don't manage!"); 1178 else if (entry->nge_inuse == 0) 1179 panic("nge_jref: buffer already free!"); 1180 else 1181 entry->nge_inuse++; 1182 } 1183 1184 /* 1185 * Release a jumbo buffer. 1186 */ 1187 static void 1188 nge_jfree(void *arg) 1189 { 1190 struct nge_jslot *entry = (struct nge_jslot *)arg; 1191 struct nge_softc *sc = entry->nge_sc; 1192 1193 if (sc == NULL) 1194 panic("nge_jref: can't find softc pointer!"); 1195 1196 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1197 panic("nge_jref: asked to reference buffer " 1198 "that we don't manage!"); 1199 else if (entry->nge_inuse == 0) 1200 panic("nge_jref: buffer already free!"); 1201 else if (--entry->nge_inuse == 0) 1202 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1203 } 1204 /* 1205 * A frame has been uploaded: pass the resulting mbuf chain up to 1206 * the higher level protocols. 1207 */ 1208 static void 1209 nge_rxeof(struct nge_softc *sc) 1210 { 1211 struct mbuf *m; 1212 struct ifnet *ifp = &sc->arpcom.ac_if; 1213 struct nge_desc *cur_rx; 1214 int i, total_len = 0; 1215 uint32_t rxstat; 1216 1217 i = sc->nge_cdata.nge_rx_prod; 1218 1219 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1220 struct mbuf *m0 = NULL; 1221 uint32_t extsts; 1222 1223 #ifdef DEVICE_POLLING 1224 if (ifp->if_flags & IFF_POLLING) { 1225 if (sc->rxcycles <= 0) 1226 break; 1227 sc->rxcycles--; 1228 } 1229 #endif /* DEVICE_POLLING */ 1230 1231 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1232 rxstat = cur_rx->nge_rxstat; 1233 extsts = cur_rx->nge_extsts; 1234 m = cur_rx->nge_mbuf; 1235 cur_rx->nge_mbuf = NULL; 1236 total_len = NGE_RXBYTES(cur_rx); 1237 NGE_INC(i, NGE_RX_LIST_CNT); 1238 /* 1239 * If an error occurs, update stats, clear the 1240 * status word and leave the mbuf cluster in place: 1241 * it should simply get re-used next time this descriptor 1242 * comes up in the ring. 1243 */ 1244 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) { 1245 ifp->if_ierrors++; 1246 nge_newbuf(sc, cur_rx, m); 1247 continue; 1248 } 1249 1250 /* 1251 * Ok. NatSemi really screwed up here. This is the 1252 * only gigE chip I know of with alignment constraints 1253 * on receive buffers. RX buffers must be 64-bit aligned. 1254 */ 1255 #ifdef __i386__ 1256 /* 1257 * By popular demand, ignore the alignment problems 1258 * on the Intel x86 platform. The performance hit 1259 * incurred due to unaligned accesses is much smaller 1260 * than the hit produced by forcing buffer copies all 1261 * the time, especially with jumbo frames. We still 1262 * need to fix up the alignment everywhere else though. 1263 */ 1264 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1265 #endif 1266 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1267 total_len + ETHER_ALIGN, 0, ifp, NULL); 1268 nge_newbuf(sc, cur_rx, m); 1269 if (m0 == NULL) { 1270 printf("nge%d: no receive buffers " 1271 "available -- packet dropped!\n", 1272 sc->nge_unit); 1273 ifp->if_ierrors++; 1274 continue; 1275 } 1276 m_adj(m0, ETHER_ALIGN); 1277 m = m0; 1278 #ifdef __i386__ 1279 } else { 1280 m->m_pkthdr.rcvif = ifp; 1281 m->m_pkthdr.len = m->m_len = total_len; 1282 } 1283 #endif 1284 1285 ifp->if_ipackets++; 1286 1287 /* Do IP checksum checking. */ 1288 if (extsts & NGE_RXEXTSTS_IPPKT) 1289 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1290 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1291 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1292 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1293 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) || 1294 (extsts & NGE_RXEXTSTS_UDPPKT && 1295 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) { 1296 m->m_pkthdr.csum_flags |= 1297 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1298 m->m_pkthdr.csum_data = 0xffff; 1299 } 1300 1301 /* 1302 * If we received a packet with a vlan tag, pass it 1303 * to vlan_input() instead of ether_input(). 1304 */ 1305 if (extsts & NGE_RXEXTSTS_VLANPKT) 1306 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1307 else 1308 (*ifp->if_input)(ifp, m); 1309 } 1310 1311 sc->nge_cdata.nge_rx_prod = i; 1312 } 1313 1314 /* 1315 * A frame was downloaded to the chip. It's safe for us to clean up 1316 * the list buffers. 1317 */ 1318 static void 1319 nge_txeof(struct nge_softc *sc) 1320 { 1321 struct ifnet *ifp = &sc->arpcom.ac_if; 1322 struct nge_desc *cur_tx = NULL; 1323 uint32_t idx; 1324 1325 /* Clear the timeout timer. */ 1326 ifp->if_timer = 0; 1327 1328 /* 1329 * Go through our tx list and free mbufs for those 1330 * frames that have been transmitted. 1331 */ 1332 idx = sc->nge_cdata.nge_tx_cons; 1333 while (idx != sc->nge_cdata.nge_tx_prod) { 1334 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1335 1336 if (NGE_OWNDESC(cur_tx)) 1337 break; 1338 1339 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1340 sc->nge_cdata.nge_tx_cnt--; 1341 NGE_INC(idx, NGE_TX_LIST_CNT); 1342 continue; 1343 } 1344 1345 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1346 ifp->if_oerrors++; 1347 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1348 ifp->if_collisions++; 1349 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1350 ifp->if_collisions++; 1351 } 1352 1353 ifp->if_collisions += 1354 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1355 1356 ifp->if_opackets++; 1357 if (cur_tx->nge_mbuf != NULL) { 1358 m_freem(cur_tx->nge_mbuf); 1359 cur_tx->nge_mbuf = NULL; 1360 } 1361 1362 sc->nge_cdata.nge_tx_cnt--; 1363 NGE_INC(idx, NGE_TX_LIST_CNT); 1364 ifp->if_timer = 0; 1365 } 1366 1367 sc->nge_cdata.nge_tx_cons = idx; 1368 1369 if (cur_tx != NULL) 1370 ifp->if_flags &= ~IFF_OACTIVE; 1371 } 1372 1373 static void 1374 nge_tick(void *xsc) 1375 { 1376 struct nge_softc *sc = xsc; 1377 struct ifnet *ifp = &sc->arpcom.ac_if; 1378 struct mii_data *mii; 1379 int s; 1380 1381 s = splimp(); 1382 1383 if (sc->nge_tbi) { 1384 if (sc->nge_link == 0) { 1385 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1386 & NGE_TBIBMSR_ANEG_DONE) { 1387 printf("nge%d: gigabit link up\n", 1388 sc->nge_unit); 1389 nge_miibus_statchg(sc->nge_miibus); 1390 sc->nge_link++; 1391 if (!ifq_is_empty(&ifp->if_snd)) 1392 nge_start(ifp); 1393 } 1394 } 1395 } else { 1396 mii = device_get_softc(sc->nge_miibus); 1397 mii_tick(mii); 1398 1399 if (sc->nge_link == 0) { 1400 if (mii->mii_media_status & IFM_ACTIVE && 1401 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1402 sc->nge_link++; 1403 if (IFM_SUBTYPE(mii->mii_media_active) 1404 == IFM_1000_T) 1405 printf("nge%d: gigabit link up\n", 1406 sc->nge_unit); 1407 if (!ifq_is_empty(&ifp->if_snd)) 1408 nge_start(ifp); 1409 } 1410 } 1411 } 1412 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1413 1414 splx(s); 1415 } 1416 1417 #ifdef DEVICE_POLLING 1418 1419 static void 1420 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1421 { 1422 struct nge_softc *sc = ifp->if_softc; 1423 1424 switch(cmd) { 1425 case POLL_REGISTER: 1426 /* disable interrupts */ 1427 CSR_WRITE_4(sc, NGE_IER, 0); 1428 break; 1429 case POLL_DEREGISTER: 1430 /* enable interrupts */ 1431 CSR_WRITE_4(sc, NGE_IER, 1); 1432 break; 1433 default: 1434 /* 1435 * On the nge, reading the status register also clears it. 1436 * So before returning to intr mode we must make sure that all 1437 * possible pending sources of interrupts have been served. 1438 * In practice this means run to completion the *eof routines, 1439 * and then call the interrupt routine 1440 */ 1441 sc->rxcycles = count; 1442 nge_rxeof(sc); 1443 nge_txeof(sc); 1444 if (!ifq_is_empty(&ifp->if_snd)) 1445 nge_start(ifp); 1446 1447 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1448 uint32_t status; 1449 1450 /* Reading the ISR register clears all interrupts. */ 1451 status = CSR_READ_4(sc, NGE_ISR); 1452 1453 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1454 nge_rxeof(sc); 1455 1456 if (status & (NGE_ISR_RX_IDLE)) 1457 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1458 1459 if (status & NGE_ISR_SYSERR) { 1460 nge_reset(sc); 1461 nge_init(sc); 1462 } 1463 } 1464 break; 1465 } 1466 } 1467 1468 #endif /* DEVICE_POLLING */ 1469 1470 static void 1471 nge_intr(void *arg) 1472 { 1473 struct nge_softc *sc = arg; 1474 struct ifnet *ifp = &sc->arpcom.ac_if; 1475 uint32_t status; 1476 1477 /* Supress unwanted interrupts */ 1478 if (!(ifp->if_flags & IFF_UP)) { 1479 nge_stop(sc); 1480 return; 1481 } 1482 1483 /* Disable interrupts. */ 1484 CSR_WRITE_4(sc, NGE_IER, 0); 1485 1486 /* Data LED on for TBI mode */ 1487 if(sc->nge_tbi) 1488 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1489 | NGE_GPIO_GP3_OUT); 1490 1491 for (;;) { 1492 /* Reading the ISR register clears all interrupts. */ 1493 status = CSR_READ_4(sc, NGE_ISR); 1494 1495 if ((status & NGE_INTRS) == 0) 1496 break; 1497 1498 if ((status & NGE_ISR_TX_DESC_OK) || 1499 (status & NGE_ISR_TX_ERR) || 1500 (status & NGE_ISR_TX_OK) || 1501 (status & NGE_ISR_TX_IDLE)) 1502 nge_txeof(sc); 1503 1504 if ((status & NGE_ISR_RX_DESC_OK) || 1505 (status & NGE_ISR_RX_ERR) || 1506 (status & NGE_ISR_RX_OFLOW) || 1507 (status & NGE_ISR_RX_FIFO_OFLOW) || 1508 (status & NGE_ISR_RX_IDLE) || 1509 (status & NGE_ISR_RX_OK)) 1510 nge_rxeof(sc); 1511 1512 if ((status & NGE_ISR_RX_IDLE)) 1513 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1514 1515 if (status & NGE_ISR_SYSERR) { 1516 nge_reset(sc); 1517 ifp->if_flags &= ~IFF_RUNNING; 1518 nge_init(sc); 1519 } 1520 1521 #ifdef notyet 1522 /* mii_tick should only be called once per second */ 1523 if (status & NGE_ISR_PHY_INTR) { 1524 sc->nge_link = 0; 1525 nge_tick(sc); 1526 } 1527 #endif 1528 } 1529 1530 /* Re-enable interrupts. */ 1531 CSR_WRITE_4(sc, NGE_IER, 1); 1532 1533 if (!ifq_is_empty(&ifp->if_snd)) 1534 nge_start(ifp); 1535 1536 /* Data LED off for TBI mode */ 1537 1538 if(sc->nge_tbi) 1539 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1540 & ~NGE_GPIO_GP3_OUT); 1541 } 1542 1543 /* 1544 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1545 * pointers to the fragment pointers. 1546 */ 1547 static int 1548 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1549 { 1550 struct nge_desc *f = NULL; 1551 struct mbuf *m; 1552 int frag, cur, cnt = 0; 1553 struct ifvlan *ifv = NULL; 1554 1555 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1556 m_head->m_pkthdr.rcvif != NULL && 1557 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1558 ifv = m_head->m_pkthdr.rcvif->if_softc; 1559 1560 /* 1561 * Start packing the mbufs in this chain into 1562 * the fragment pointers. Stop when we run out 1563 * of fragments or hit the end of the mbuf chain. 1564 */ 1565 m = m_head; 1566 cur = frag = *txidx; 1567 1568 for (m = m_head; m != NULL; m = m->m_next) { 1569 if (m->m_len != 0) { 1570 if ((NGE_TX_LIST_CNT - 1571 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1572 return(ENOBUFS); 1573 f = &sc->nge_ldata->nge_tx_list[frag]; 1574 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1575 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1576 if (cnt != 0) 1577 f->nge_ctl |= NGE_CMDSTS_OWN; 1578 cur = frag; 1579 NGE_INC(frag, NGE_TX_LIST_CNT); 1580 cnt++; 1581 } 1582 } 1583 1584 if (m != NULL) 1585 return(ENOBUFS); 1586 1587 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1588 if (m_head->m_pkthdr.csum_flags) { 1589 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1590 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1591 NGE_TXEXTSTS_IPCSUM; 1592 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1593 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1594 NGE_TXEXTSTS_TCPCSUM; 1595 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1596 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1597 NGE_TXEXTSTS_UDPCSUM; 1598 } 1599 1600 if (ifv != NULL) { 1601 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1602 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1603 } 1604 1605 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1606 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1607 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1608 sc->nge_cdata.nge_tx_cnt += cnt; 1609 *txidx = frag; 1610 1611 return(0); 1612 } 1613 1614 /* 1615 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1616 * to the mbuf data regions directly in the transmit lists. We also save a 1617 * copy of the pointers since the transmit list fragment pointers are 1618 * physical addresses. 1619 */ 1620 1621 static void 1622 nge_start(struct ifnet *ifp) 1623 { 1624 struct nge_softc *sc = ifp->if_softc; 1625 struct mbuf *m_head = NULL; 1626 uint32_t idx; 1627 1628 if (!sc->nge_link) 1629 return; 1630 1631 idx = sc->nge_cdata.nge_tx_prod; 1632 1633 if (ifp->if_flags & IFF_OACTIVE) 1634 return; 1635 1636 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1637 m_head = ifq_poll(&ifp->if_snd); 1638 if (m_head == NULL) 1639 break; 1640 1641 if (nge_encap(sc, m_head, &idx)) { 1642 ifp->if_flags |= IFF_OACTIVE; 1643 break; 1644 } 1645 m_head = ifq_dequeue(&ifp->if_snd); 1646 1647 BPF_MTAP(ifp, m_head); 1648 } 1649 1650 /* Transmit */ 1651 sc->nge_cdata.nge_tx_prod = idx; 1652 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1653 1654 /* 1655 * Set a timeout in case the chip goes out to lunch. 1656 */ 1657 ifp->if_timer = 5; 1658 } 1659 1660 static void 1661 nge_init(void *xsc) 1662 { 1663 struct nge_softc *sc = xsc; 1664 struct ifnet *ifp = &sc->arpcom.ac_if; 1665 struct mii_data *mii; 1666 int s; 1667 1668 if (ifp->if_flags & IFF_RUNNING) 1669 return; 1670 1671 s = splimp(); 1672 1673 /* 1674 * Cancel pending I/O and free all RX/TX buffers. 1675 */ 1676 nge_stop(sc); 1677 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1678 1679 if (sc->nge_tbi) 1680 mii = NULL; 1681 else 1682 mii = device_get_softc(sc->nge_miibus); 1683 1684 /* Set MAC address */ 1685 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1686 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1687 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1688 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1689 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1690 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1691 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1692 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1693 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1694 1695 /* Init circular RX list. */ 1696 if (nge_list_rx_init(sc) == ENOBUFS) { 1697 printf("nge%d: initialization failed: no " 1698 "memory for rx buffers\n", sc->nge_unit); 1699 nge_stop(sc); 1700 splx(s); 1701 return; 1702 } 1703 1704 /* 1705 * Init tx descriptors. 1706 */ 1707 nge_list_tx_init(sc); 1708 1709 /* 1710 * For the NatSemi chip, we have to explicitly enable the 1711 * reception of ARP frames, as well as turn on the 'perfect 1712 * match' filter where we store the station address, otherwise 1713 * we won't receive unicasts meant for this host. 1714 */ 1715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1716 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1717 1718 /* If we want promiscuous mode, set the allframes bit. */ 1719 if (ifp->if_flags & IFF_PROMISC) 1720 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1721 else 1722 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1723 1724 /* 1725 * Set the capture broadcast bit to capture broadcast frames. 1726 */ 1727 if (ifp->if_flags & IFF_BROADCAST) 1728 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1729 else 1730 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1731 1732 /* 1733 * Load the multicast filter. 1734 */ 1735 nge_setmulti(sc); 1736 1737 /* Turn the receive filter on */ 1738 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1739 1740 /* 1741 * Load the address of the RX and TX lists. 1742 */ 1743 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1744 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1745 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1746 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1747 1748 /* Set RX configuration */ 1749 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1750 /* 1751 * Enable hardware checksum validation for all IPv4 1752 * packets, do not reject packets with bad checksums. 1753 */ 1754 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1755 1756 /* 1757 * Tell the chip to detect and strip VLAN tag info from 1758 * received frames. The tag will be provided in the extsts 1759 * field in the RX descriptors. 1760 */ 1761 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1762 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1763 1764 /* Set TX configuration */ 1765 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1766 1767 /* 1768 * Enable TX IPv4 checksumming on a per-packet basis. 1769 */ 1770 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1771 1772 /* 1773 * Tell the chip to insert VLAN tags on a per-packet basis as 1774 * dictated by the code in the frame encapsulation routine. 1775 */ 1776 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1777 1778 /* Set full/half duplex mode. */ 1779 if (sc->nge_tbi) { 1780 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1781 == IFM_FDX) { 1782 NGE_SETBIT(sc, NGE_TX_CFG, 1783 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1784 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1785 } else { 1786 NGE_CLRBIT(sc, NGE_TX_CFG, 1787 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1788 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1789 } 1790 } else { 1791 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1792 NGE_SETBIT(sc, NGE_TX_CFG, 1793 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1795 } else { 1796 NGE_CLRBIT(sc, NGE_TX_CFG, 1797 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1799 } 1800 } 1801 1802 /* 1803 * Enable the delivery of PHY interrupts based on 1804 * link/speed/duplex status changes. Also enable the 1805 * extsts field in the DMA descriptors (needed for 1806 * TCP/IP checksum offload on transmit). 1807 */ 1808 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 1809 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 1810 1811 /* 1812 * Configure interrupt holdoff (moderation). We can 1813 * have the chip delay interrupt delivery for a certain 1814 * period. Units are in 100us, and the max setting 1815 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1816 */ 1817 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1818 1819 /* 1820 * Enable interrupts. 1821 */ 1822 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1823 #ifdef DEVICE_POLLING 1824 /* 1825 * ... only enable interrupts if we are not polling, make sure 1826 * they are off otherwise. 1827 */ 1828 if (ifp->if_flags & IFF_POLLING) 1829 CSR_WRITE_4(sc, NGE_IER, 0); 1830 else 1831 #endif /* DEVICE_POLLING */ 1832 CSR_WRITE_4(sc, NGE_IER, 1); 1833 1834 /* Enable receiver and transmitter. */ 1835 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE); 1836 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1837 1838 nge_ifmedia_upd(ifp); 1839 1840 ifp->if_flags |= IFF_RUNNING; 1841 ifp->if_flags &= ~IFF_OACTIVE; 1842 1843 splx(s); 1844 } 1845 1846 /* 1847 * Set media options. 1848 */ 1849 static int 1850 nge_ifmedia_upd(struct ifnet *ifp) 1851 { 1852 struct nge_softc *sc = ifp->if_softc; 1853 struct mii_data *mii; 1854 1855 if (sc->nge_tbi) { 1856 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1857 == IFM_AUTO) { 1858 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1859 CSR_READ_4(sc, NGE_TBI_ANAR) 1860 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1861 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1862 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1863 | NGE_TBIBMCR_RESTART_ANEG); 1864 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1865 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1866 & IFM_GMASK) == IFM_FDX) { 1867 NGE_SETBIT(sc, NGE_TX_CFG, 1868 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1869 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1870 1871 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1872 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1873 } else { 1874 NGE_CLRBIT(sc, NGE_TX_CFG, 1875 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1876 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1877 1878 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1879 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1880 } 1881 1882 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1883 & ~NGE_GPIO_GP3_OUT); 1884 } else { 1885 mii = device_get_softc(sc->nge_miibus); 1886 sc->nge_link = 0; 1887 if (mii->mii_instance) { 1888 struct mii_softc *miisc; 1889 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1890 miisc = LIST_NEXT(miisc, mii_list)) 1891 mii_phy_reset(miisc); 1892 } 1893 mii_mediachg(mii); 1894 } 1895 1896 return(0); 1897 } 1898 1899 /* 1900 * Report current media status. 1901 */ 1902 static void 1903 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1904 { 1905 struct nge_softc *sc = ifp->if_softc; 1906 struct mii_data *mii; 1907 1908 if (sc->nge_tbi) { 1909 ifmr->ifm_status = IFM_AVALID; 1910 ifmr->ifm_active = IFM_ETHER; 1911 1912 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) 1913 ifmr->ifm_status |= IFM_ACTIVE; 1914 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1915 ifmr->ifm_active |= IFM_LOOP; 1916 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1917 ifmr->ifm_active |= IFM_NONE; 1918 ifmr->ifm_status = 0; 1919 return; 1920 } 1921 ifmr->ifm_active |= IFM_1000_SX; 1922 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1923 == IFM_AUTO) { 1924 ifmr->ifm_active |= IFM_AUTO; 1925 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1926 & NGE_TBIANAR_FDX) { 1927 ifmr->ifm_active |= IFM_FDX; 1928 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1929 & NGE_TBIANAR_HDX) { 1930 ifmr->ifm_active |= IFM_HDX; 1931 } 1932 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1933 == IFM_FDX) 1934 ifmr->ifm_active |= IFM_FDX; 1935 else 1936 ifmr->ifm_active |= IFM_HDX; 1937 1938 } else { 1939 mii = device_get_softc(sc->nge_miibus); 1940 mii_pollstat(mii); 1941 ifmr->ifm_active = mii->mii_media_active; 1942 ifmr->ifm_status = mii->mii_media_status; 1943 } 1944 } 1945 1946 static int 1947 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1948 { 1949 struct nge_softc *sc = ifp->if_softc; 1950 struct ifreq *ifr = (struct ifreq *) data; 1951 struct mii_data *mii; 1952 int error = 0, s; 1953 1954 s = splimp(); 1955 1956 switch(command) { 1957 case SIOCSIFMTU: 1958 if (ifr->ifr_mtu > NGE_JUMBO_MTU) { 1959 error = EINVAL; 1960 } else { 1961 ifp->if_mtu = ifr->ifr_mtu; 1962 /* 1963 * Workaround: if the MTU is larger than 1964 * 8152 (TX FIFO size minus 64 minus 18), turn off 1965 * TX checksum offloading. 1966 */ 1967 if (ifr->ifr_mtu >= 8152) 1968 ifp->if_hwassist = 0; 1969 else 1970 ifp->if_hwassist = NGE_CSUM_FEATURES; 1971 } 1972 break; 1973 case SIOCSIFFLAGS: 1974 if (ifp->if_flags & IFF_UP) { 1975 if (ifp->if_flags & IFF_RUNNING && 1976 ifp->if_flags & IFF_PROMISC && 1977 !(sc->nge_if_flags & IFF_PROMISC)) { 1978 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1979 NGE_RXFILTCTL_ALLPHYS| 1980 NGE_RXFILTCTL_ALLMULTI); 1981 } else if (ifp->if_flags & IFF_RUNNING && 1982 !(ifp->if_flags & IFF_PROMISC) && 1983 sc->nge_if_flags & IFF_PROMISC) { 1984 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1985 NGE_RXFILTCTL_ALLPHYS); 1986 if (!(ifp->if_flags & IFF_ALLMULTI)) 1987 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1988 NGE_RXFILTCTL_ALLMULTI); 1989 } else { 1990 ifp->if_flags &= ~IFF_RUNNING; 1991 nge_init(sc); 1992 } 1993 } else { 1994 if (ifp->if_flags & IFF_RUNNING) 1995 nge_stop(sc); 1996 } 1997 sc->nge_if_flags = ifp->if_flags; 1998 error = 0; 1999 break; 2000 case SIOCADDMULTI: 2001 case SIOCDELMULTI: 2002 nge_setmulti(sc); 2003 error = 0; 2004 break; 2005 case SIOCGIFMEDIA: 2006 case SIOCSIFMEDIA: 2007 if (sc->nge_tbi) { 2008 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2009 command); 2010 } else { 2011 mii = device_get_softc(sc->nge_miibus); 2012 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2013 command); 2014 } 2015 break; 2016 default: 2017 error = ether_ioctl(ifp, command, data); 2018 break; 2019 } 2020 2021 splx(s); 2022 2023 return(error); 2024 } 2025 2026 static void 2027 nge_watchdog(struct ifnet *ifp) 2028 { 2029 struct nge_softc *sc = ifp->if_softc; 2030 2031 ifp->if_oerrors++; 2032 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2033 2034 nge_stop(sc); 2035 nge_reset(sc); 2036 ifp->if_flags &= ~IFF_RUNNING; 2037 nge_init(sc); 2038 2039 if (!ifq_is_empty(&ifp->if_snd)) 2040 nge_start(ifp); 2041 } 2042 2043 /* 2044 * Stop the adapter and free any mbufs allocated to the 2045 * RX and TX lists. 2046 */ 2047 static void 2048 nge_stop(struct nge_softc *sc) 2049 { 2050 struct ifnet *ifp = &sc->arpcom.ac_if; 2051 struct ifmedia_entry *ifm; 2052 struct mii_data *mii; 2053 int i, itmp, mtmp; 2054 2055 ifp->if_timer = 0; 2056 if (sc->nge_tbi) 2057 mii = NULL; 2058 else 2059 mii = device_get_softc(sc->nge_miibus); 2060 2061 callout_stop(&sc->nge_stat_timer); 2062 CSR_WRITE_4(sc, NGE_IER, 0); 2063 CSR_WRITE_4(sc, NGE_IMR, 0); 2064 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2065 DELAY(1000); 2066 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2067 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2068 2069 /* 2070 * Isolate/power down the PHY, but leave the media selection 2071 * unchanged so that things will be put back to normal when 2072 * we bring the interface back up. 2073 */ 2074 itmp = ifp->if_flags; 2075 ifp->if_flags |= IFF_UP; 2076 2077 if (sc->nge_tbi) 2078 ifm = sc->nge_ifmedia.ifm_cur; 2079 else 2080 ifm = mii->mii_media.ifm_cur; 2081 2082 mtmp = ifm->ifm_media; 2083 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2084 2085 if (!sc->nge_tbi) 2086 mii_mediachg(mii); 2087 ifm->ifm_media = mtmp; 2088 ifp->if_flags = itmp; 2089 2090 sc->nge_link = 0; 2091 2092 /* 2093 * Free data in the RX lists. 2094 */ 2095 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2096 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2097 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2098 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2099 } 2100 } 2101 bzero(&sc->nge_ldata->nge_rx_list, 2102 sizeof(sc->nge_ldata->nge_rx_list)); 2103 2104 /* 2105 * Free the TX list buffers. 2106 */ 2107 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2108 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2109 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2110 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2111 } 2112 } 2113 2114 bzero(&sc->nge_ldata->nge_tx_list, 2115 sizeof(sc->nge_ldata->nge_tx_list)); 2116 2117 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2118 } 2119 2120 /* 2121 * Stop all chip I/O so that the kernel's probe routines don't 2122 * get confused by errant DMAs when rebooting. 2123 */ 2124 static void 2125 nge_shutdown(device_t dev) 2126 { 2127 struct nge_softc *sc = device_get_softc(dev); 2128 2129 nge_reset(sc); 2130 nge_stop(sc); 2131 } 2132