1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.19 2005/02/21 18:40:36 joerg Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 #include <net/vlan/if_vlan_var.h> 107 108 #include <net/bpf.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 #include <machine/clock.h> /* for DELAY */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include "../mii_layer/mii.h" 121 #include "../mii_layer/miivar.h" 122 123 #include <bus/pci/pcireg.h> 124 #include <bus/pci/pcivar.h> 125 126 #define NGE_USEIOSPACE 127 128 #include "if_ngereg.h" 129 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static struct nge_type nge_devs[] = { 140 { NGE_VENDORID, NGE_DEVICEID, 141 "National Semiconductor Gigabit Ethernet" }, 142 { 0, 0, NULL } 143 }; 144 145 static int nge_probe (device_t); 146 static int nge_attach (device_t); 147 static int nge_detach (device_t); 148 149 static int nge_alloc_jumbo_mem (struct nge_softc *); 150 static void nge_free_jumbo_mem (struct nge_softc *); 151 static void *nge_jalloc (struct nge_softc *); 152 static void nge_jfree (caddr_t, u_int); 153 static void nge_jref (caddr_t, u_int); 154 155 static int nge_newbuf (struct nge_softc *, 156 struct nge_desc *, struct mbuf *); 157 static int nge_encap (struct nge_softc *, 158 struct mbuf *, u_int32_t *); 159 static void nge_rxeof (struct nge_softc *); 160 static void nge_txeof (struct nge_softc *); 161 static void nge_intr (void *); 162 static void nge_tick (void *); 163 static void nge_start (struct ifnet *); 164 static int nge_ioctl (struct ifnet *, u_long, caddr_t, 165 struct ucred *); 166 static void nge_init (void *); 167 static void nge_stop (struct nge_softc *); 168 static void nge_watchdog (struct ifnet *); 169 static void nge_shutdown (device_t); 170 static int nge_ifmedia_upd (struct ifnet *); 171 static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 172 173 static void nge_delay (struct nge_softc *); 174 static void nge_eeprom_idle (struct nge_softc *); 175 static void nge_eeprom_putbyte (struct nge_softc *, int); 176 static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *); 177 static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int); 178 179 static void nge_mii_sync (struct nge_softc *); 180 static void nge_mii_send (struct nge_softc *, u_int32_t, int); 181 static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *); 182 static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *); 183 184 static int nge_miibus_readreg (device_t, int, int); 185 static int nge_miibus_writereg (device_t, int, int, int); 186 static void nge_miibus_statchg (device_t); 187 188 static void nge_setmulti (struct nge_softc *); 189 static u_int32_t nge_crc (struct nge_softc *, caddr_t); 190 static void nge_reset (struct nge_softc *); 191 static int nge_list_rx_init (struct nge_softc *); 192 static int nge_list_tx_init (struct nge_softc *); 193 194 #ifdef NGE_USEIOSPACE 195 #define NGE_RES SYS_RES_IOPORT 196 #define NGE_RID NGE_PCI_LOIO 197 #else 198 #define NGE_RES SYS_RES_MEMORY 199 #define NGE_RID NGE_PCI_LOMEM 200 #endif 201 202 static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219 }; 220 221 static driver_t nge_driver = { 222 "nge", 223 nge_methods, 224 sizeof(struct nge_softc) 225 }; 226 227 static devclass_t nge_devclass; 228 229 DECLARE_DUMMY_MODULE(if_nge); 230 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 231 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 232 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 233 234 #define NGE_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238 #define NGE_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242 #define SIO_SET(x) \ 243 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 244 245 #define SIO_CLR(x) \ 246 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 247 248 static void nge_delay(sc) 249 struct nge_softc *sc; 250 { 251 int idx; 252 253 for (idx = (300 / 33) + 1; idx > 0; idx--) 254 CSR_READ_4(sc, NGE_CSR); 255 256 return; 257 } 258 259 static void nge_eeprom_idle(sc) 260 struct nge_softc *sc; 261 { 262 int i; 263 264 SIO_SET(NGE_MEAR_EE_CSEL); 265 nge_delay(sc); 266 SIO_SET(NGE_MEAR_EE_CLK); 267 nge_delay(sc); 268 269 for (i = 0; i < 25; i++) { 270 SIO_CLR(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_SET(NGE_MEAR_EE_CLK); 273 nge_delay(sc); 274 } 275 276 SIO_CLR(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 SIO_CLR(NGE_MEAR_EE_CSEL); 279 nge_delay(sc); 280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 281 282 return; 283 } 284 285 /* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288 static void nge_eeprom_putbyte(sc, addr) 289 struct nge_softc *sc; 290 int addr; 291 { 292 int d, i; 293 294 d = addr | NGE_EECMD_READ; 295 296 /* 297 * Feed in each bit and stobe the clock. 298 */ 299 for (i = 0x400; i; i >>= 1) { 300 if (d & i) { 301 SIO_SET(NGE_MEAR_EE_DIN); 302 } else { 303 SIO_CLR(NGE_MEAR_EE_DIN); 304 } 305 nge_delay(sc); 306 SIO_SET(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 SIO_CLR(NGE_MEAR_EE_CLK); 309 nge_delay(sc); 310 } 311 312 return; 313 } 314 315 /* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318 static void nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void nge_read_eeprom(sc, dest, off, cnt, swap) 366 struct nge_softc *sc; 367 caddr_t dest; 368 int off; 369 int cnt; 370 int swap; 371 { 372 int i; 373 u_int16_t word = 0, *ptr; 374 375 for (i = 0; i < cnt; i++) { 376 nge_eeprom_getword(sc, off + i, &word); 377 ptr = (u_int16_t *)(dest + (i * 2)); 378 if (swap) 379 *ptr = ntohs(word); 380 else 381 *ptr = word; 382 } 383 384 return; 385 } 386 387 /* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390 static void nge_mii_sync(sc) 391 struct nge_softc *sc; 392 { 393 int i; 394 395 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 396 397 for (i = 0; i < 32; i++) { 398 SIO_SET(NGE_MEAR_MII_CLK); 399 DELAY(1); 400 SIO_CLR(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 } 403 404 return; 405 } 406 407 /* 408 * Clock a series of bits through the MII. 409 */ 410 static void nge_mii_send(sc, bits, cnt) 411 struct nge_softc *sc; 412 u_int32_t bits; 413 int cnt; 414 { 415 int i; 416 417 SIO_CLR(NGE_MEAR_MII_CLK); 418 419 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 420 if (bits & i) { 421 SIO_SET(NGE_MEAR_MII_DATA); 422 } else { 423 SIO_CLR(NGE_MEAR_MII_DATA); 424 } 425 DELAY(1); 426 SIO_CLR(NGE_MEAR_MII_CLK); 427 DELAY(1); 428 SIO_SET(NGE_MEAR_MII_CLK); 429 } 430 } 431 432 /* 433 * Read an PHY register through the MII. 434 */ 435 static int nge_mii_readreg(sc, frame) 436 struct nge_softc *sc; 437 struct nge_mii_frame *frame; 438 439 { 440 int i, ack, s; 441 442 s = splimp(); 443 444 /* 445 * Set up frame for RX. 446 */ 447 frame->mii_stdelim = NGE_MII_STARTDELIM; 448 frame->mii_opcode = NGE_MII_READOP; 449 frame->mii_turnaround = 0; 450 frame->mii_data = 0; 451 452 CSR_WRITE_4(sc, NGE_MEAR, 0); 453 454 /* 455 * Turn on data xmit. 456 */ 457 SIO_SET(NGE_MEAR_MII_DIR); 458 459 nge_mii_sync(sc); 460 461 /* 462 * Send command/address info. 463 */ 464 nge_mii_send(sc, frame->mii_stdelim, 2); 465 nge_mii_send(sc, frame->mii_opcode, 2); 466 nge_mii_send(sc, frame->mii_phyaddr, 5); 467 nge_mii_send(sc, frame->mii_regaddr, 5); 468 469 /* Idle bit */ 470 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 471 DELAY(1); 472 SIO_SET(NGE_MEAR_MII_CLK); 473 DELAY(1); 474 475 /* Turn off xmit. */ 476 SIO_CLR(NGE_MEAR_MII_DIR); 477 /* Check for ack */ 478 SIO_CLR(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 481 SIO_SET(NGE_MEAR_MII_CLK); 482 DELAY(1); 483 484 /* 485 * Now try reading data bits. If the ack failed, we still 486 * need to clock through 16 cycles to keep the PHY(s) in sync. 487 */ 488 if (ack) { 489 for(i = 0; i < 16; i++) { 490 SIO_CLR(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 SIO_SET(NGE_MEAR_MII_CLK); 493 DELAY(1); 494 } 495 goto fail; 496 } 497 498 for (i = 0x8000; i; i >>= 1) { 499 SIO_CLR(NGE_MEAR_MII_CLK); 500 DELAY(1); 501 if (!ack) { 502 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 503 frame->mii_data |= i; 504 DELAY(1); 505 } 506 SIO_SET(NGE_MEAR_MII_CLK); 507 DELAY(1); 508 } 509 510 fail: 511 512 SIO_CLR(NGE_MEAR_MII_CLK); 513 DELAY(1); 514 SIO_SET(NGE_MEAR_MII_CLK); 515 DELAY(1); 516 517 splx(s); 518 519 if (ack) 520 return(1); 521 return(0); 522 } 523 524 /* 525 * Write to a PHY register through the MII. 526 */ 527 static int nge_mii_writereg(sc, frame) 528 struct nge_softc *sc; 529 struct nge_mii_frame *frame; 530 531 { 532 int s; 533 534 s = splimp(); 535 /* 536 * Set up frame for TX. 537 */ 538 539 frame->mii_stdelim = NGE_MII_STARTDELIM; 540 frame->mii_opcode = NGE_MII_WRITEOP; 541 frame->mii_turnaround = NGE_MII_TURNAROUND; 542 543 /* 544 * Turn on data output. 545 */ 546 SIO_SET(NGE_MEAR_MII_DIR); 547 548 nge_mii_sync(sc); 549 550 nge_mii_send(sc, frame->mii_stdelim, 2); 551 nge_mii_send(sc, frame->mii_opcode, 2); 552 nge_mii_send(sc, frame->mii_phyaddr, 5); 553 nge_mii_send(sc, frame->mii_regaddr, 5); 554 nge_mii_send(sc, frame->mii_turnaround, 2); 555 nge_mii_send(sc, frame->mii_data, 16); 556 557 /* Idle bit. */ 558 SIO_SET(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 SIO_CLR(NGE_MEAR_MII_CLK); 561 DELAY(1); 562 563 /* 564 * Turn off xmit. 565 */ 566 SIO_CLR(NGE_MEAR_MII_DIR); 567 568 splx(s); 569 570 return(0); 571 } 572 573 static int nge_miibus_readreg(dev, phy, reg) 574 device_t dev; 575 int phy, reg; 576 { 577 struct nge_softc *sc; 578 struct nge_mii_frame frame; 579 580 sc = device_get_softc(dev); 581 582 bzero((char *)&frame, sizeof(frame)); 583 584 frame.mii_phyaddr = phy; 585 frame.mii_regaddr = reg; 586 nge_mii_readreg(sc, &frame); 587 588 return(frame.mii_data); 589 } 590 591 static int nge_miibus_writereg(dev, phy, reg, data) 592 device_t dev; 593 int phy, reg, data; 594 { 595 struct nge_softc *sc; 596 struct nge_mii_frame frame; 597 598 sc = device_get_softc(dev); 599 600 bzero((char *)&frame, sizeof(frame)); 601 602 frame.mii_phyaddr = phy; 603 frame.mii_regaddr = reg; 604 frame.mii_data = data; 605 nge_mii_writereg(sc, &frame); 606 607 return(0); 608 } 609 610 static void nge_miibus_statchg(dev) 611 device_t dev; 612 { 613 int status; 614 struct nge_softc *sc; 615 struct mii_data *mii; 616 617 sc = device_get_softc(dev); 618 if (sc->nge_tbi) { 619 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 620 == IFM_AUTO) { 621 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 622 if (status == 0 || status & NGE_TBIANAR_FDX) { 623 NGE_SETBIT(sc, NGE_TX_CFG, 624 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 625 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 626 } else { 627 NGE_CLRBIT(sc, NGE_TX_CFG, 628 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 629 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 630 } 631 632 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 633 != IFM_FDX) { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } else { 638 NGE_SETBIT(sc, NGE_TX_CFG, 639 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 640 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 641 } 642 } else { 643 mii = device_get_softc(sc->nge_miibus); 644 645 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } else { 650 NGE_CLRBIT(sc, NGE_TX_CFG, 651 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 652 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 653 } 654 655 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 656 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 657 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 658 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 659 } else { 660 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 661 } 662 } 663 return; 664 } 665 666 static u_int32_t nge_crc(sc, addr) 667 struct nge_softc *sc; 668 caddr_t addr; 669 { 670 u_int32_t crc, carry; 671 int i, j; 672 u_int8_t c; 673 674 /* Compute CRC for the address value. */ 675 crc = 0xFFFFFFFF; /* initial value */ 676 677 for (i = 0; i < 6; i++) { 678 c = *(addr + i); 679 for (j = 0; j < 8; j++) { 680 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 681 crc <<= 1; 682 c >>= 1; 683 if (carry) 684 crc = (crc ^ 0x04c11db6) | carry; 685 } 686 } 687 688 /* 689 * return the filter bit position 690 */ 691 692 return((crc >> 21) & 0x00000FFF); 693 } 694 695 static void nge_setmulti(sc) 696 struct nge_softc *sc; 697 { 698 struct ifnet *ifp; 699 struct ifmultiaddr *ifma; 700 u_int32_t h = 0, i, filtsave; 701 int bit, index; 702 703 ifp = &sc->arpcom.ac_if; 704 705 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 706 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 707 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 708 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 709 return; 710 } 711 712 /* 713 * We have to explicitly enable the multicast hash table 714 * on the NatSemi chip if we want to use it, which we do. 715 * We also have to tell it that we don't want to use the 716 * hash table for matching unicast addresses. 717 */ 718 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 719 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 720 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 721 722 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 723 724 /* first, zot all the existing hash bits */ 725 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 727 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 728 } 729 730 /* 731 * From the 11 bits returned by the crc routine, the top 7 732 * bits represent the 16-bit word in the mcast hash table 733 * that needs to be updated, and the lower 4 bits represent 734 * which bit within that byte needs to be set. 735 */ 736 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 737 if (ifma->ifma_addr->sa_family != AF_LINK) 738 continue; 739 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 740 index = (h >> 4) & 0x7F; 741 bit = h & 0xF; 742 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 743 NGE_FILTADDR_MCAST_LO + (index * 2)); 744 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 745 } 746 747 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 748 749 return; 750 } 751 752 static void nge_reset(sc) 753 struct nge_softc *sc; 754 { 755 int i; 756 757 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 758 759 for (i = 0; i < NGE_TIMEOUT; i++) { 760 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 761 break; 762 } 763 764 if (i == NGE_TIMEOUT) 765 printf("nge%d: reset never completed\n", sc->nge_unit); 766 767 /* Wait a little while for the chip to get its brains in order. */ 768 DELAY(1000); 769 770 /* 771 * If this is a NetSemi chip, make sure to clear 772 * PME mode. 773 */ 774 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 775 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 776 777 return; 778 } 779 780 /* 781 * Probe for an NatSemi chip. Check the PCI vendor and device 782 * IDs against our list and return a device name if we find a match. 783 */ 784 static int nge_probe(dev) 785 device_t dev; 786 { 787 struct nge_type *t; 788 789 t = nge_devs; 790 791 while(t->nge_name != NULL) { 792 if ((pci_get_vendor(dev) == t->nge_vid) && 793 (pci_get_device(dev) == t->nge_did)) { 794 device_set_desc(dev, t->nge_name); 795 return(0); 796 } 797 t++; 798 } 799 800 return(ENXIO); 801 } 802 803 /* 804 * Attach the interface. Allocate softc structures, do ifmedia 805 * setup and ethernet/BPF attach. 806 */ 807 static int nge_attach(dev) 808 device_t dev; 809 { 810 int s; 811 u_char eaddr[ETHER_ADDR_LEN]; 812 u_int32_t command; 813 struct nge_softc *sc; 814 struct ifnet *ifp; 815 int unit, error = 0, rid; 816 const char *sep = ""; 817 818 s = splimp(); 819 820 sc = device_get_softc(dev); 821 unit = device_get_unit(dev); 822 bzero(sc, sizeof(struct nge_softc)); 823 callout_init(&sc->nge_stat_timer); 824 825 /* 826 * Handle power management nonsense. 827 */ 828 829 830 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 831 if (command == 0x01) { 832 833 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 834 if (command & NGE_PSTATE_MASK) { 835 u_int32_t iobase, membase, irq; 836 837 /* Save important PCI config data. */ 838 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 839 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 840 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 841 842 /* Reset the power state. */ 843 printf("nge%d: chip is in D%d power mode " 844 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 845 command &= 0xFFFFFFFC; 846 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 847 848 /* Restore PCI config data. */ 849 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 850 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 851 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 852 } 853 } 854 855 /* 856 * Map control/status registers. 857 */ 858 command = pci_read_config(dev, PCIR_COMMAND, 4); 859 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 860 pci_write_config(dev, PCIR_COMMAND, command, 4); 861 command = pci_read_config(dev, PCIR_COMMAND, 4); 862 863 #ifdef NGE_USEIOSPACE 864 if (!(command & PCIM_CMD_PORTEN)) { 865 printf("nge%d: failed to enable I/O ports!\n", unit); 866 error = ENXIO;; 867 goto fail; 868 } 869 #else 870 if (!(command & PCIM_CMD_MEMEN)) { 871 printf("nge%d: failed to enable memory mapping!\n", unit); 872 error = ENXIO;; 873 goto fail; 874 } 875 #endif 876 877 rid = NGE_RID; 878 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 879 0, ~0, 1, RF_ACTIVE); 880 881 if (sc->nge_res == NULL) { 882 printf("nge%d: couldn't map ports/memory\n", unit); 883 error = ENXIO; 884 goto fail; 885 } 886 887 sc->nge_btag = rman_get_bustag(sc->nge_res); 888 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 889 890 /* Allocate interrupt */ 891 rid = 0; 892 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 893 RF_SHAREABLE | RF_ACTIVE); 894 895 if (sc->nge_irq == NULL) { 896 printf("nge%d: couldn't map interrupt\n", unit); 897 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 898 error = ENXIO; 899 goto fail; 900 } 901 902 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 903 nge_intr, sc, &sc->nge_intrhand); 904 905 if (error) { 906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 907 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 908 printf("nge%d: couldn't set up irq\n", unit); 909 goto fail; 910 } 911 912 /* Reset the adapter. */ 913 nge_reset(sc); 914 915 /* 916 * Get station address from the EEPROM. 917 */ 918 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 919 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 920 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 921 922 sc->nge_unit = unit; 923 924 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 925 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 926 927 if (sc->nge_ldata == NULL) { 928 printf("nge%d: no memory for list buffers!\n", unit); 929 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 930 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 931 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 932 error = ENXIO; 933 goto fail; 934 } 935 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 936 937 /* Try to allocate memory for jumbo buffers. */ 938 if (nge_alloc_jumbo_mem(sc)) { 939 printf("nge%d: jumbo buffer allocation failed\n", 940 sc->nge_unit); 941 contigfree(sc->nge_ldata, 942 sizeof(struct nge_list_data), M_DEVBUF); 943 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 944 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 945 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 946 error = ENXIO; 947 goto fail; 948 } 949 950 ifp = &sc->arpcom.ac_if; 951 ifp->if_softc = sc; 952 if_initname(ifp, "nge", unit); 953 ifp->if_mtu = ETHERMTU; 954 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 955 ifp->if_ioctl = nge_ioctl; 956 ifp->if_start = nge_start; 957 ifp->if_watchdog = nge_watchdog; 958 ifp->if_init = nge_init; 959 ifp->if_baudrate = 1000000000; 960 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 961 ifq_set_ready(&ifp->if_snd); 962 ifp->if_hwassist = NGE_CSUM_FEATURES; 963 ifp->if_capabilities = IFCAP_HWCSUM; 964 ifp->if_capenable = ifp->if_capabilities; 965 966 /* 967 * Do MII setup. 968 */ 969 if (mii_phy_probe(dev, &sc->nge_miibus, 970 nge_ifmedia_upd, nge_ifmedia_sts)) { 971 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 972 sc->nge_tbi = 1; 973 device_printf(dev, "Using TBI\n"); 974 975 sc->nge_miibus = dev; 976 977 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 978 nge_ifmedia_sts); 979 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 980 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 981 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 982 device_printf(dev, " "); 983 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 984 PRINT("1000baseSX"); 985 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 986 PRINT("1000baseSX-FDX"); 987 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 988 PRINT("auto"); 989 990 printf("\n"); 991 #undef ADD 992 #undef PRINT 993 ifmedia_set(&sc->nge_ifmedia, 994 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 995 996 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 997 | NGE_GPIO_GP4_OUT 998 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 999 | NGE_GPIO_GP3_OUTENB 1000 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1001 1002 } else { 1003 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1004 nge_free_jumbo_mem(sc); 1005 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1007 bus_release_resource(dev, NGE_RES, NGE_RID, 1008 sc->nge_res); 1009 error = ENXIO; 1010 goto fail; 1011 } 1012 } 1013 1014 /* 1015 * Call MI attach routine. 1016 */ 1017 ether_ifattach(ifp, eaddr); 1018 1019 fail: 1020 1021 splx(s); 1022 return(error); 1023 } 1024 1025 static int nge_detach(dev) 1026 device_t dev; 1027 { 1028 struct nge_softc *sc; 1029 struct ifnet *ifp; 1030 int s; 1031 1032 s = splimp(); 1033 1034 sc = device_get_softc(dev); 1035 ifp = &sc->arpcom.ac_if; 1036 1037 nge_reset(sc); 1038 nge_stop(sc); 1039 ether_ifdetach(ifp); 1040 1041 bus_generic_detach(dev); 1042 if (!sc->nge_tbi) { 1043 device_delete_child(dev, sc->nge_miibus); 1044 } 1045 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1046 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1047 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1048 1049 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1050 nge_free_jumbo_mem(sc); 1051 1052 splx(s); 1053 1054 return(0); 1055 } 1056 1057 /* 1058 * Initialize the transmit descriptors. 1059 */ 1060 static int nge_list_tx_init(sc) 1061 struct nge_softc *sc; 1062 { 1063 struct nge_list_data *ld; 1064 struct nge_ring_data *cd; 1065 int i; 1066 1067 cd = &sc->nge_cdata; 1068 ld = sc->nge_ldata; 1069 1070 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1071 if (i == (NGE_TX_LIST_CNT - 1)) { 1072 ld->nge_tx_list[i].nge_nextdesc = 1073 &ld->nge_tx_list[0]; 1074 ld->nge_tx_list[i].nge_next = 1075 vtophys(&ld->nge_tx_list[0]); 1076 } else { 1077 ld->nge_tx_list[i].nge_nextdesc = 1078 &ld->nge_tx_list[i + 1]; 1079 ld->nge_tx_list[i].nge_next = 1080 vtophys(&ld->nge_tx_list[i + 1]); 1081 } 1082 ld->nge_tx_list[i].nge_mbuf = NULL; 1083 ld->nge_tx_list[i].nge_ptr = 0; 1084 ld->nge_tx_list[i].nge_ctl = 0; 1085 } 1086 1087 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1088 1089 return(0); 1090 } 1091 1092 1093 /* 1094 * Initialize the RX descriptors and allocate mbufs for them. Note that 1095 * we arrange the descriptors in a closed ring, so that the last descriptor 1096 * points back to the first. 1097 */ 1098 static int nge_list_rx_init(sc) 1099 struct nge_softc *sc; 1100 { 1101 struct nge_list_data *ld; 1102 struct nge_ring_data *cd; 1103 int i; 1104 1105 ld = sc->nge_ldata; 1106 cd = &sc->nge_cdata; 1107 1108 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1109 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1110 return(ENOBUFS); 1111 if (i == (NGE_RX_LIST_CNT - 1)) { 1112 ld->nge_rx_list[i].nge_nextdesc = 1113 &ld->nge_rx_list[0]; 1114 ld->nge_rx_list[i].nge_next = 1115 vtophys(&ld->nge_rx_list[0]); 1116 } else { 1117 ld->nge_rx_list[i].nge_nextdesc = 1118 &ld->nge_rx_list[i + 1]; 1119 ld->nge_rx_list[i].nge_next = 1120 vtophys(&ld->nge_rx_list[i + 1]); 1121 } 1122 } 1123 1124 cd->nge_rx_prod = 0; 1125 1126 return(0); 1127 } 1128 1129 /* 1130 * Initialize an RX descriptor and attach an MBUF cluster. 1131 */ 1132 static int nge_newbuf(sc, c, m) 1133 struct nge_softc *sc; 1134 struct nge_desc *c; 1135 struct mbuf *m; 1136 { 1137 struct mbuf *m_new = NULL; 1138 caddr_t *buf = NULL; 1139 1140 if (m == NULL) { 1141 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1142 if (m_new == NULL) { 1143 printf("nge%d: no memory for rx list " 1144 "-- packet dropped!\n", sc->nge_unit); 1145 return(ENOBUFS); 1146 } 1147 1148 /* Allocate the jumbo buffer */ 1149 buf = nge_jalloc(sc); 1150 if (buf == NULL) { 1151 #ifdef NGE_VERBOSE 1152 printf("nge%d: jumbo allocation failed " 1153 "-- packet dropped!\n", sc->nge_unit); 1154 #endif 1155 m_freem(m_new); 1156 return(ENOBUFS); 1157 } 1158 /* Attach the buffer to the mbuf */ 1159 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 1160 m_new->m_flags |= M_EXT | M_EXT_OLD; 1161 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1162 m_new->m_len = NGE_MCLBYTES; 1163 m_new->m_ext.ext_nfree.old = nge_jfree; 1164 m_new->m_ext.ext_nref.old = nge_jref; 1165 } else { 1166 m_new = m; 1167 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1168 m_new->m_data = m_new->m_ext.ext_buf; 1169 } 1170 1171 m_adj(m_new, sizeof(u_int64_t)); 1172 1173 c->nge_mbuf = m_new; 1174 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1175 c->nge_ctl = m_new->m_len; 1176 c->nge_extsts = 0; 1177 1178 return(0); 1179 } 1180 1181 static int nge_alloc_jumbo_mem(sc) 1182 struct nge_softc *sc; 1183 { 1184 caddr_t ptr; 1185 int i; 1186 struct nge_jpool_entry *entry; 1187 1188 /* Grab a big chunk o' storage. */ 1189 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1190 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1191 1192 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1193 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1194 return(ENOBUFS); 1195 } 1196 1197 SLIST_INIT(&sc->nge_jfree_listhead); 1198 SLIST_INIT(&sc->nge_jinuse_listhead); 1199 1200 /* 1201 * Now divide it up into 9K pieces and save the addresses 1202 * in an array. 1203 */ 1204 ptr = sc->nge_cdata.nge_jumbo_buf; 1205 for (i = 0; i < NGE_JSLOTS; i++) { 1206 u_int64_t **aptr; 1207 aptr = (u_int64_t **)ptr; 1208 aptr[0] = (u_int64_t *)sc; 1209 ptr += sizeof(u_int64_t); 1210 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1211 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1212 ptr += NGE_MCLBYTES; 1213 entry = malloc(sizeof(struct nge_jpool_entry), 1214 M_DEVBUF, M_WAITOK); 1215 if (entry == NULL) { 1216 printf("nge%d: no memory for jumbo " 1217 "buffer queue!\n", sc->nge_unit); 1218 return(ENOBUFS); 1219 } 1220 entry->slot = i; 1221 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1222 entry, jpool_entries); 1223 } 1224 1225 return(0); 1226 } 1227 1228 static void nge_free_jumbo_mem(sc) 1229 struct nge_softc *sc; 1230 { 1231 int i; 1232 struct nge_jpool_entry *entry; 1233 1234 for (i = 0; i < NGE_JSLOTS; i++) { 1235 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1236 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1237 free(entry, M_DEVBUF); 1238 } 1239 1240 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1241 1242 return; 1243 } 1244 1245 /* 1246 * Allocate a jumbo buffer. 1247 */ 1248 static void *nge_jalloc(sc) 1249 struct nge_softc *sc; 1250 { 1251 struct nge_jpool_entry *entry; 1252 1253 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1254 1255 if (entry == NULL) { 1256 #ifdef NGE_VERBOSE 1257 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1258 #endif 1259 return(NULL); 1260 } 1261 1262 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1263 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1264 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1265 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1266 } 1267 1268 /* 1269 * Adjust usage count on a jumbo buffer. In general this doesn't 1270 * get used much because our jumbo buffers don't get passed around 1271 * a lot, but it's implemented for correctness. 1272 */ 1273 static void nge_jref(buf, size) 1274 caddr_t buf; 1275 u_int size; 1276 { 1277 struct nge_softc *sc; 1278 u_int64_t **aptr; 1279 int i; 1280 1281 /* Extract the softc struct pointer. */ 1282 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1283 sc = (struct nge_softc *)(aptr[0]); 1284 1285 if (sc == NULL) 1286 panic("nge_jref: can't find softc pointer!"); 1287 1288 if (size != NGE_MCLBYTES) 1289 panic("nge_jref: adjusting refcount of buf of wrong size!"); 1290 1291 /* calculate the slot this buffer belongs to */ 1292 1293 i = ((vm_offset_t)aptr 1294 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1295 1296 if ((i < 0) || (i >= NGE_JSLOTS)) 1297 panic("nge_jref: asked to reference buffer " 1298 "that we don't manage!"); 1299 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1300 panic("nge_jref: buffer already free!"); 1301 else 1302 sc->nge_cdata.nge_jslots[i].nge_inuse++; 1303 1304 return; 1305 } 1306 1307 /* 1308 * Release a jumbo buffer. 1309 */ 1310 static void nge_jfree(buf, size) 1311 caddr_t buf; 1312 u_int size; 1313 { 1314 struct nge_softc *sc; 1315 u_int64_t **aptr; 1316 int i; 1317 struct nge_jpool_entry *entry; 1318 1319 /* Extract the softc struct pointer. */ 1320 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1321 sc = (struct nge_softc *)(aptr[0]); 1322 1323 if (sc == NULL) 1324 panic("nge_jfree: can't find softc pointer!"); 1325 1326 if (size != NGE_MCLBYTES) 1327 panic("nge_jfree: freeing buffer of wrong size!"); 1328 1329 /* calculate the slot this buffer belongs to */ 1330 1331 i = ((vm_offset_t)aptr 1332 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1333 1334 if ((i < 0) || (i >= NGE_JSLOTS)) 1335 panic("nge_jfree: asked to free buffer that we don't manage!"); 1336 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1337 panic("nge_jfree: buffer already free!"); 1338 else { 1339 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1340 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1341 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1342 if (entry == NULL) 1343 panic("nge_jfree: buffer not in use!"); 1344 entry->slot = i; 1345 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, 1346 jpool_entries); 1347 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1348 entry, jpool_entries); 1349 } 1350 } 1351 1352 return; 1353 } 1354 /* 1355 * A frame has been uploaded: pass the resulting mbuf chain up to 1356 * the higher level protocols. 1357 */ 1358 static void nge_rxeof(sc) 1359 struct nge_softc *sc; 1360 { 1361 struct mbuf *m; 1362 struct ifnet *ifp; 1363 struct nge_desc *cur_rx; 1364 int i, total_len = 0; 1365 u_int32_t rxstat; 1366 1367 ifp = &sc->arpcom.ac_if; 1368 i = sc->nge_cdata.nge_rx_prod; 1369 1370 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1371 struct mbuf *m0 = NULL; 1372 u_int32_t extsts; 1373 1374 #ifdef DEVICE_POLLING 1375 if (ifp->if_flags & IFF_POLLING) { 1376 if (sc->rxcycles <= 0) 1377 break; 1378 sc->rxcycles--; 1379 } 1380 #endif /* DEVICE_POLLING */ 1381 1382 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1383 rxstat = cur_rx->nge_rxstat; 1384 extsts = cur_rx->nge_extsts; 1385 m = cur_rx->nge_mbuf; 1386 cur_rx->nge_mbuf = NULL; 1387 total_len = NGE_RXBYTES(cur_rx); 1388 NGE_INC(i, NGE_RX_LIST_CNT); 1389 /* 1390 * If an error occurs, update stats, clear the 1391 * status word and leave the mbuf cluster in place: 1392 * it should simply get re-used next time this descriptor 1393 * comes up in the ring. 1394 */ 1395 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1396 ifp->if_ierrors++; 1397 nge_newbuf(sc, cur_rx, m); 1398 continue; 1399 } 1400 1401 /* 1402 * Ok. NatSemi really screwed up here. This is the 1403 * only gigE chip I know of with alignment constraints 1404 * on receive buffers. RX buffers must be 64-bit aligned. 1405 */ 1406 #ifdef __i386__ 1407 /* 1408 * By popular demand, ignore the alignment problems 1409 * on the Intel x86 platform. The performance hit 1410 * incurred due to unaligned accesses is much smaller 1411 * than the hit produced by forcing buffer copies all 1412 * the time, especially with jumbo frames. We still 1413 * need to fix up the alignment everywhere else though. 1414 */ 1415 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1416 #endif 1417 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1418 total_len + ETHER_ALIGN, 0, ifp, NULL); 1419 nge_newbuf(sc, cur_rx, m); 1420 if (m0 == NULL) { 1421 printf("nge%d: no receive buffers " 1422 "available -- packet dropped!\n", 1423 sc->nge_unit); 1424 ifp->if_ierrors++; 1425 continue; 1426 } 1427 m_adj(m0, ETHER_ALIGN); 1428 m = m0; 1429 #ifdef __i386__ 1430 } else { 1431 m->m_pkthdr.rcvif = ifp; 1432 m->m_pkthdr.len = m->m_len = total_len; 1433 } 1434 #endif 1435 1436 ifp->if_ipackets++; 1437 1438 /* Do IP checksum checking. */ 1439 if (extsts & NGE_RXEXTSTS_IPPKT) 1440 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1441 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1442 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1443 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1444 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1445 (extsts & NGE_RXEXTSTS_UDPPKT && 1446 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1447 m->m_pkthdr.csum_flags |= 1448 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1449 m->m_pkthdr.csum_data = 0xffff; 1450 } 1451 1452 /* 1453 * If we received a packet with a vlan tag, pass it 1454 * to vlan_input() instead of ether_input(). 1455 */ 1456 if (extsts & NGE_RXEXTSTS_VLANPKT) 1457 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1458 else 1459 (*ifp->if_input)(ifp, m); 1460 } 1461 1462 sc->nge_cdata.nge_rx_prod = i; 1463 1464 return; 1465 } 1466 1467 /* 1468 * A frame was downloaded to the chip. It's safe for us to clean up 1469 * the list buffers. 1470 */ 1471 1472 static void nge_txeof(sc) 1473 struct nge_softc *sc; 1474 { 1475 struct nge_desc *cur_tx = NULL; 1476 struct ifnet *ifp; 1477 u_int32_t idx; 1478 1479 ifp = &sc->arpcom.ac_if; 1480 1481 /* Clear the timeout timer. */ 1482 ifp->if_timer = 0; 1483 1484 /* 1485 * Go through our tx list and free mbufs for those 1486 * frames that have been transmitted. 1487 */ 1488 idx = sc->nge_cdata.nge_tx_cons; 1489 while (idx != sc->nge_cdata.nge_tx_prod) { 1490 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1491 1492 if (NGE_OWNDESC(cur_tx)) 1493 break; 1494 1495 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1496 sc->nge_cdata.nge_tx_cnt--; 1497 NGE_INC(idx, NGE_TX_LIST_CNT); 1498 continue; 1499 } 1500 1501 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1502 ifp->if_oerrors++; 1503 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1504 ifp->if_collisions++; 1505 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1506 ifp->if_collisions++; 1507 } 1508 1509 ifp->if_collisions += 1510 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1511 1512 ifp->if_opackets++; 1513 if (cur_tx->nge_mbuf != NULL) { 1514 m_freem(cur_tx->nge_mbuf); 1515 cur_tx->nge_mbuf = NULL; 1516 } 1517 1518 sc->nge_cdata.nge_tx_cnt--; 1519 NGE_INC(idx, NGE_TX_LIST_CNT); 1520 ifp->if_timer = 0; 1521 } 1522 1523 sc->nge_cdata.nge_tx_cons = idx; 1524 1525 if (cur_tx != NULL) 1526 ifp->if_flags &= ~IFF_OACTIVE; 1527 1528 return; 1529 } 1530 1531 static void nge_tick(xsc) 1532 void *xsc; 1533 { 1534 struct nge_softc *sc; 1535 struct mii_data *mii; 1536 struct ifnet *ifp; 1537 int s; 1538 1539 s = splimp(); 1540 1541 sc = xsc; 1542 ifp = &sc->arpcom.ac_if; 1543 1544 if (sc->nge_tbi) { 1545 if (!sc->nge_link) { 1546 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1547 & NGE_TBIBMSR_ANEG_DONE) { 1548 printf("nge%d: gigabit link up\n", 1549 sc->nge_unit); 1550 nge_miibus_statchg(sc->nge_miibus); 1551 sc->nge_link++; 1552 if (!ifq_is_empty(&ifp->if_snd)) 1553 nge_start(ifp); 1554 } 1555 } 1556 } else { 1557 mii = device_get_softc(sc->nge_miibus); 1558 mii_tick(mii); 1559 1560 if (!sc->nge_link) { 1561 if (mii->mii_media_status & IFM_ACTIVE && 1562 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1563 sc->nge_link++; 1564 if (IFM_SUBTYPE(mii->mii_media_active) 1565 == IFM_1000_T) 1566 printf("nge%d: gigabit link up\n", 1567 sc->nge_unit); 1568 if (!ifq_is_empty(&ifp->if_snd)) 1569 nge_start(ifp); 1570 } 1571 } 1572 } 1573 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1574 1575 splx(s); 1576 1577 return; 1578 } 1579 1580 #ifdef DEVICE_POLLING 1581 static poll_handler_t nge_poll; 1582 1583 static void 1584 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1585 { 1586 struct nge_softc *sc = ifp->if_softc; 1587 1588 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1589 CSR_WRITE_4(sc, NGE_IER, 1); 1590 return; 1591 } 1592 1593 /* 1594 * On the nge, reading the status register also clears it. 1595 * So before returning to intr mode we must make sure that all 1596 * possible pending sources of interrupts have been served. 1597 * In practice this means run to completion the *eof routines, 1598 * and then call the interrupt routine 1599 */ 1600 sc->rxcycles = count; 1601 nge_rxeof(sc); 1602 nge_txeof(sc); 1603 if (!ifq_is_empty(&ifp->if_snd)) 1604 nge_start(ifp); 1605 1606 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1607 u_int32_t status; 1608 1609 /* Reading the ISR register clears all interrupts. */ 1610 status = CSR_READ_4(sc, NGE_ISR); 1611 1612 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1613 nge_rxeof(sc); 1614 1615 if (status & (NGE_ISR_RX_IDLE)) 1616 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1617 1618 if (status & NGE_ISR_SYSERR) { 1619 nge_reset(sc); 1620 nge_init(sc); 1621 } 1622 } 1623 } 1624 #endif /* DEVICE_POLLING */ 1625 1626 static void nge_intr(arg) 1627 void *arg; 1628 { 1629 struct nge_softc *sc; 1630 struct ifnet *ifp; 1631 u_int32_t status; 1632 1633 sc = arg; 1634 ifp = &sc->arpcom.ac_if; 1635 1636 #ifdef DEVICE_POLLING 1637 if (ifp->if_flags & IFF_POLLING) 1638 return; 1639 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1640 CSR_WRITE_4(sc, NGE_IER, 0); 1641 nge_poll(ifp, 0, 1); 1642 return; 1643 } 1644 #endif /* DEVICE_POLLING */ 1645 1646 /* Supress unwanted interrupts */ 1647 if (!(ifp->if_flags & IFF_UP)) { 1648 nge_stop(sc); 1649 return; 1650 } 1651 1652 /* Disable interrupts. */ 1653 CSR_WRITE_4(sc, NGE_IER, 0); 1654 1655 /* Data LED on for TBI mode */ 1656 if(sc->nge_tbi) 1657 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1658 | NGE_GPIO_GP3_OUT); 1659 1660 for (;;) { 1661 /* Reading the ISR register clears all interrupts. */ 1662 status = CSR_READ_4(sc, NGE_ISR); 1663 1664 if ((status & NGE_INTRS) == 0) 1665 break; 1666 1667 if ((status & NGE_ISR_TX_DESC_OK) || 1668 (status & NGE_ISR_TX_ERR) || 1669 (status & NGE_ISR_TX_OK) || 1670 (status & NGE_ISR_TX_IDLE)) 1671 nge_txeof(sc); 1672 1673 if ((status & NGE_ISR_RX_DESC_OK) || 1674 (status & NGE_ISR_RX_ERR) || 1675 (status & NGE_ISR_RX_OFLOW) || 1676 (status & NGE_ISR_RX_FIFO_OFLOW) || 1677 (status & NGE_ISR_RX_IDLE) || 1678 (status & NGE_ISR_RX_OK)) 1679 nge_rxeof(sc); 1680 1681 if ((status & NGE_ISR_RX_IDLE)) 1682 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1683 1684 if (status & NGE_ISR_SYSERR) { 1685 nge_reset(sc); 1686 ifp->if_flags &= ~IFF_RUNNING; 1687 nge_init(sc); 1688 } 1689 1690 #ifdef notyet 1691 /* mii_tick should only be called once per second */ 1692 if (status & NGE_ISR_PHY_INTR) { 1693 sc->nge_link = 0; 1694 nge_tick(sc); 1695 } 1696 #endif 1697 } 1698 1699 /* Re-enable interrupts. */ 1700 CSR_WRITE_4(sc, NGE_IER, 1); 1701 1702 if (!ifq_is_empty(&ifp->if_snd)) 1703 nge_start(ifp); 1704 1705 /* Data LED off for TBI mode */ 1706 1707 if(sc->nge_tbi) 1708 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1709 & ~NGE_GPIO_GP3_OUT); 1710 1711 return; 1712 } 1713 1714 /* 1715 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1716 * pointers to the fragment pointers. 1717 */ 1718 static int nge_encap(sc, m_head, txidx) 1719 struct nge_softc *sc; 1720 struct mbuf *m_head; 1721 u_int32_t *txidx; 1722 { 1723 struct nge_desc *f = NULL; 1724 struct mbuf *m; 1725 int frag, cur, cnt = 0; 1726 struct ifvlan *ifv = NULL; 1727 1728 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1729 m_head->m_pkthdr.rcvif != NULL && 1730 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1731 ifv = m_head->m_pkthdr.rcvif->if_softc; 1732 1733 /* 1734 * Start packing the mbufs in this chain into 1735 * the fragment pointers. Stop when we run out 1736 * of fragments or hit the end of the mbuf chain. 1737 */ 1738 m = m_head; 1739 cur = frag = *txidx; 1740 1741 for (m = m_head; m != NULL; m = m->m_next) { 1742 if (m->m_len != 0) { 1743 if ((NGE_TX_LIST_CNT - 1744 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1745 return(ENOBUFS); 1746 f = &sc->nge_ldata->nge_tx_list[frag]; 1747 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1748 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1749 if (cnt != 0) 1750 f->nge_ctl |= NGE_CMDSTS_OWN; 1751 cur = frag; 1752 NGE_INC(frag, NGE_TX_LIST_CNT); 1753 cnt++; 1754 } 1755 } 1756 1757 if (m != NULL) 1758 return(ENOBUFS); 1759 1760 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1761 if (m_head->m_pkthdr.csum_flags) { 1762 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1763 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1764 NGE_TXEXTSTS_IPCSUM; 1765 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1766 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1767 NGE_TXEXTSTS_TCPCSUM; 1768 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1769 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1770 NGE_TXEXTSTS_UDPCSUM; 1771 } 1772 1773 if (ifv != NULL) { 1774 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1775 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1776 } 1777 1778 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1779 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1780 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1781 sc->nge_cdata.nge_tx_cnt += cnt; 1782 *txidx = frag; 1783 1784 return(0); 1785 } 1786 1787 /* 1788 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1789 * to the mbuf data regions directly in the transmit lists. We also save a 1790 * copy of the pointers since the transmit list fragment pointers are 1791 * physical addresses. 1792 */ 1793 1794 static void nge_start(ifp) 1795 struct ifnet *ifp; 1796 { 1797 struct nge_softc *sc; 1798 struct mbuf *m_head = NULL; 1799 u_int32_t idx; 1800 1801 sc = ifp->if_softc; 1802 1803 if (!sc->nge_link) 1804 return; 1805 1806 idx = sc->nge_cdata.nge_tx_prod; 1807 1808 if (ifp->if_flags & IFF_OACTIVE) 1809 return; 1810 1811 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1812 m_head = ifq_poll(&ifp->if_snd); 1813 if (m_head == NULL) 1814 break; 1815 1816 if (nge_encap(sc, m_head, &idx)) { 1817 ifp->if_flags |= IFF_OACTIVE; 1818 break; 1819 } 1820 m_head = ifq_dequeue(&ifp->if_snd); 1821 1822 BPF_MTAP(ifp, m_head); 1823 } 1824 1825 /* Transmit */ 1826 sc->nge_cdata.nge_tx_prod = idx; 1827 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1828 1829 /* 1830 * Set a timeout in case the chip goes out to lunch. 1831 */ 1832 ifp->if_timer = 5; 1833 1834 return; 1835 } 1836 1837 static void nge_init(xsc) 1838 void *xsc; 1839 { 1840 struct nge_softc *sc = xsc; 1841 struct ifnet *ifp = &sc->arpcom.ac_if; 1842 struct mii_data *mii; 1843 int s; 1844 1845 if (ifp->if_flags & IFF_RUNNING) 1846 return; 1847 1848 s = splimp(); 1849 1850 /* 1851 * Cancel pending I/O and free all RX/TX buffers. 1852 */ 1853 nge_stop(sc); 1854 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1855 1856 if (sc->nge_tbi) { 1857 mii = NULL; 1858 } else { 1859 mii = device_get_softc(sc->nge_miibus); 1860 } 1861 1862 /* Set MAC address */ 1863 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1864 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1865 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1866 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1867 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1868 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1869 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1870 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1871 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1872 1873 /* Init circular RX list. */ 1874 if (nge_list_rx_init(sc) == ENOBUFS) { 1875 printf("nge%d: initialization failed: no " 1876 "memory for rx buffers\n", sc->nge_unit); 1877 nge_stop(sc); 1878 (void)splx(s); 1879 return; 1880 } 1881 1882 /* 1883 * Init tx descriptors. 1884 */ 1885 nge_list_tx_init(sc); 1886 1887 /* 1888 * For the NatSemi chip, we have to explicitly enable the 1889 * reception of ARP frames, as well as turn on the 'perfect 1890 * match' filter where we store the station address, otherwise 1891 * we won't receive unicasts meant for this host. 1892 */ 1893 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1894 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1895 1896 /* If we want promiscuous mode, set the allframes bit. */ 1897 if (ifp->if_flags & IFF_PROMISC) { 1898 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1899 } else { 1900 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1901 } 1902 1903 /* 1904 * Set the capture broadcast bit to capture broadcast frames. 1905 */ 1906 if (ifp->if_flags & IFF_BROADCAST) { 1907 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1908 } else { 1909 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1910 } 1911 1912 /* 1913 * Load the multicast filter. 1914 */ 1915 nge_setmulti(sc); 1916 1917 /* Turn the receive filter on */ 1918 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1919 1920 /* 1921 * Load the address of the RX and TX lists. 1922 */ 1923 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1924 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1925 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1926 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1927 1928 /* Set RX configuration */ 1929 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1930 /* 1931 * Enable hardware checksum validation for all IPv4 1932 * packets, do not reject packets with bad checksums. 1933 */ 1934 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1935 1936 /* 1937 * Tell the chip to detect and strip VLAN tag info from 1938 * received frames. The tag will be provided in the extsts 1939 * field in the RX descriptors. 1940 */ 1941 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1942 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1943 1944 /* Set TX configuration */ 1945 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1946 1947 /* 1948 * Enable TX IPv4 checksumming on a per-packet basis. 1949 */ 1950 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1951 1952 /* 1953 * Tell the chip to insert VLAN tags on a per-packet basis as 1954 * dictated by the code in the frame encapsulation routine. 1955 */ 1956 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1957 1958 /* Set full/half duplex mode. */ 1959 if (sc->nge_tbi) { 1960 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1961 == IFM_FDX) { 1962 NGE_SETBIT(sc, NGE_TX_CFG, 1963 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1964 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1965 } else { 1966 NGE_CLRBIT(sc, NGE_TX_CFG, 1967 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1968 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1969 } 1970 } else { 1971 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1972 NGE_SETBIT(sc, NGE_TX_CFG, 1973 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1974 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1975 } else { 1976 NGE_CLRBIT(sc, NGE_TX_CFG, 1977 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1978 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1979 } 1980 } 1981 1982 /* 1983 * Enable the delivery of PHY interrupts based on 1984 * link/speed/duplex status changes. Also enable the 1985 * extsts field in the DMA descriptors (needed for 1986 * TCP/IP checksum offload on transmit). 1987 */ 1988 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1989 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1990 1991 /* 1992 * Configure interrupt holdoff (moderation). We can 1993 * have the chip delay interrupt delivery for a certain 1994 * period. Units are in 100us, and the max setting 1995 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1996 */ 1997 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1998 1999 /* 2000 * Enable interrupts. 2001 */ 2002 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2003 #ifdef DEVICE_POLLING 2004 /* 2005 * ... only enable interrupts if we are not polling, make sure 2006 * they are off otherwise. 2007 */ 2008 if (ifp->if_flags & IFF_POLLING) 2009 CSR_WRITE_4(sc, NGE_IER, 0); 2010 else 2011 #endif /* DEVICE_POLLING */ 2012 CSR_WRITE_4(sc, NGE_IER, 1); 2013 2014 /* Enable receiver and transmitter. */ 2015 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2016 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2017 2018 nge_ifmedia_upd(ifp); 2019 2020 ifp->if_flags |= IFF_RUNNING; 2021 ifp->if_flags &= ~IFF_OACTIVE; 2022 2023 (void)splx(s); 2024 2025 return; 2026 } 2027 2028 /* 2029 * Set media options. 2030 */ 2031 static int nge_ifmedia_upd(ifp) 2032 struct ifnet *ifp; 2033 { 2034 struct nge_softc *sc; 2035 struct mii_data *mii; 2036 2037 sc = ifp->if_softc; 2038 2039 if (sc->nge_tbi) { 2040 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2041 == IFM_AUTO) { 2042 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2043 CSR_READ_4(sc, NGE_TBI_ANAR) 2044 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2045 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2046 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2047 | NGE_TBIBMCR_RESTART_ANEG); 2048 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2049 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2050 & IFM_GMASK) == IFM_FDX) { 2051 NGE_SETBIT(sc, NGE_TX_CFG, 2052 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2053 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2054 2055 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2056 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2057 } else { 2058 NGE_CLRBIT(sc, NGE_TX_CFG, 2059 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2060 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2061 2062 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2063 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2064 } 2065 2066 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2067 & ~NGE_GPIO_GP3_OUT); 2068 } else { 2069 mii = device_get_softc(sc->nge_miibus); 2070 sc->nge_link = 0; 2071 if (mii->mii_instance) { 2072 struct mii_softc *miisc; 2073 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2074 miisc = LIST_NEXT(miisc, mii_list)) 2075 mii_phy_reset(miisc); 2076 } 2077 mii_mediachg(mii); 2078 } 2079 2080 return(0); 2081 } 2082 2083 /* 2084 * Report current media status. 2085 */ 2086 static void nge_ifmedia_sts(ifp, ifmr) 2087 struct ifnet *ifp; 2088 struct ifmediareq *ifmr; 2089 { 2090 struct nge_softc *sc; 2091 struct mii_data *mii; 2092 2093 sc = ifp->if_softc; 2094 2095 if (sc->nge_tbi) { 2096 ifmr->ifm_status = IFM_AVALID; 2097 ifmr->ifm_active = IFM_ETHER; 2098 2099 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2100 ifmr->ifm_status |= IFM_ACTIVE; 2101 } 2102 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2103 ifmr->ifm_active |= IFM_LOOP; 2104 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2105 ifmr->ifm_active |= IFM_NONE; 2106 ifmr->ifm_status = 0; 2107 return; 2108 } 2109 ifmr->ifm_active |= IFM_1000_SX; 2110 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2111 == IFM_AUTO) { 2112 ifmr->ifm_active |= IFM_AUTO; 2113 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2114 & NGE_TBIANAR_FDX) { 2115 ifmr->ifm_active |= IFM_FDX; 2116 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2117 & NGE_TBIANAR_HDX) { 2118 ifmr->ifm_active |= IFM_HDX; 2119 } 2120 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2121 == IFM_FDX) 2122 ifmr->ifm_active |= IFM_FDX; 2123 else 2124 ifmr->ifm_active |= IFM_HDX; 2125 2126 } else { 2127 mii = device_get_softc(sc->nge_miibus); 2128 mii_pollstat(mii); 2129 ifmr->ifm_active = mii->mii_media_active; 2130 ifmr->ifm_status = mii->mii_media_status; 2131 } 2132 2133 return; 2134 } 2135 2136 static int nge_ioctl(ifp, command, data, cr) 2137 struct ifnet *ifp; 2138 u_long command; 2139 caddr_t data; 2140 struct ucred *cr; 2141 { 2142 struct nge_softc *sc = ifp->if_softc; 2143 struct ifreq *ifr = (struct ifreq *) data; 2144 struct mii_data *mii; 2145 int s, error = 0; 2146 2147 s = splimp(); 2148 2149 switch(command) { 2150 case SIOCSIFADDR: 2151 case SIOCGIFADDR: 2152 error = ether_ioctl(ifp, command, data); 2153 break; 2154 case SIOCSIFMTU: 2155 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2156 error = EINVAL; 2157 else { 2158 ifp->if_mtu = ifr->ifr_mtu; 2159 /* 2160 * Workaround: if the MTU is larger than 2161 * 8152 (TX FIFO size minus 64 minus 18), turn off 2162 * TX checksum offloading. 2163 */ 2164 if (ifr->ifr_mtu >= 8152) 2165 ifp->if_hwassist = 0; 2166 else 2167 ifp->if_hwassist = NGE_CSUM_FEATURES; 2168 } 2169 break; 2170 case SIOCSIFFLAGS: 2171 if (ifp->if_flags & IFF_UP) { 2172 if (ifp->if_flags & IFF_RUNNING && 2173 ifp->if_flags & IFF_PROMISC && 2174 !(sc->nge_if_flags & IFF_PROMISC)) { 2175 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2176 NGE_RXFILTCTL_ALLPHYS| 2177 NGE_RXFILTCTL_ALLMULTI); 2178 } else if (ifp->if_flags & IFF_RUNNING && 2179 !(ifp->if_flags & IFF_PROMISC) && 2180 sc->nge_if_flags & IFF_PROMISC) { 2181 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2182 NGE_RXFILTCTL_ALLPHYS); 2183 if (!(ifp->if_flags & IFF_ALLMULTI)) 2184 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2185 NGE_RXFILTCTL_ALLMULTI); 2186 } else { 2187 ifp->if_flags &= ~IFF_RUNNING; 2188 nge_init(sc); 2189 } 2190 } else { 2191 if (ifp->if_flags & IFF_RUNNING) 2192 nge_stop(sc); 2193 } 2194 sc->nge_if_flags = ifp->if_flags; 2195 error = 0; 2196 break; 2197 case SIOCADDMULTI: 2198 case SIOCDELMULTI: 2199 nge_setmulti(sc); 2200 error = 0; 2201 break; 2202 case SIOCGIFMEDIA: 2203 case SIOCSIFMEDIA: 2204 if (sc->nge_tbi) { 2205 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2206 command); 2207 } else { 2208 mii = device_get_softc(sc->nge_miibus); 2209 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2210 command); 2211 } 2212 break; 2213 default: 2214 error = EINVAL; 2215 break; 2216 } 2217 2218 (void)splx(s); 2219 2220 return(error); 2221 } 2222 2223 static void nge_watchdog(ifp) 2224 struct ifnet *ifp; 2225 { 2226 struct nge_softc *sc; 2227 2228 sc = ifp->if_softc; 2229 2230 ifp->if_oerrors++; 2231 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2232 2233 nge_stop(sc); 2234 nge_reset(sc); 2235 ifp->if_flags &= ~IFF_RUNNING; 2236 nge_init(sc); 2237 2238 if (!ifq_is_empty(&ifp->if_snd)) 2239 nge_start(ifp); 2240 2241 return; 2242 } 2243 2244 /* 2245 * Stop the adapter and free any mbufs allocated to the 2246 * RX and TX lists. 2247 */ 2248 static void nge_stop(sc) 2249 struct nge_softc *sc; 2250 { 2251 int i; 2252 struct ifnet *ifp; 2253 struct ifmedia_entry *ifm; 2254 struct mii_data *mii; 2255 int mtmp, itmp; 2256 2257 ifp = &sc->arpcom.ac_if; 2258 ifp->if_timer = 0; 2259 if (sc->nge_tbi) { 2260 mii = NULL; 2261 } else { 2262 mii = device_get_softc(sc->nge_miibus); 2263 } 2264 2265 callout_stop(&sc->nge_stat_timer); 2266 #ifdef DEVICE_POLLING 2267 ether_poll_deregister(ifp); 2268 #endif 2269 CSR_WRITE_4(sc, NGE_IER, 0); 2270 CSR_WRITE_4(sc, NGE_IMR, 0); 2271 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2272 DELAY(1000); 2273 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2274 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2275 2276 /* 2277 * Isolate/power down the PHY, but leave the media selection 2278 * unchanged so that things will be put back to normal when 2279 * we bring the interface back up. 2280 */ 2281 itmp = ifp->if_flags; 2282 ifp->if_flags |= IFF_UP; 2283 2284 if (sc->nge_tbi) 2285 ifm = sc->nge_ifmedia.ifm_cur; 2286 else 2287 ifm = mii->mii_media.ifm_cur; 2288 2289 mtmp = ifm->ifm_media; 2290 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2291 2292 if (!sc->nge_tbi) 2293 mii_mediachg(mii); 2294 ifm->ifm_media = mtmp; 2295 ifp->if_flags = itmp; 2296 2297 sc->nge_link = 0; 2298 2299 /* 2300 * Free data in the RX lists. 2301 */ 2302 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2303 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2304 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2305 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2306 } 2307 } 2308 bzero((char *)&sc->nge_ldata->nge_rx_list, 2309 sizeof(sc->nge_ldata->nge_rx_list)); 2310 2311 /* 2312 * Free the TX list buffers. 2313 */ 2314 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2315 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2316 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2317 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2318 } 2319 } 2320 2321 bzero((char *)&sc->nge_ldata->nge_tx_list, 2322 sizeof(sc->nge_ldata->nge_tx_list)); 2323 2324 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2325 2326 return; 2327 } 2328 2329 /* 2330 * Stop all chip I/O so that the kernel's probe routines don't 2331 * get confused by errant DMAs when rebooting. 2332 */ 2333 static void nge_shutdown(dev) 2334 device_t dev; 2335 { 2336 struct nge_softc *sc; 2337 2338 sc = device_get_softc(dev); 2339 2340 nge_reset(sc); 2341 nge_stop(sc); 2342 2343 return; 2344 } 2345