1 /* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $ 35 * $DragonFly: src/sys/dev/netif/mii_layer/rgephy.c,v 1.3 2006/08/19 09:33:37 sephe Exp $ 36 */ 37 38 /* 39 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 49 #include <machine/bus.h> 50 #include <machine/clock.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_media.h> 55 56 #include <dev/netif/mii_layer/mii.h> 57 #include <dev/netif/mii_layer/miivar.h> 58 #include <dev/netif/mii_layer/miidevs.h> 59 60 #include <dev/netif/re/if_rereg.h> 61 #include <dev/netif/mii_layer/rgephyreg.h> 62 63 #include "miibus_if.h" 64 65 #include <machine/bus.h> 66 67 static int rgephy_probe(device_t); 68 static int rgephy_attach(device_t); 69 70 static device_method_t rgephy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, rgephy_probe), 73 DEVMETHOD(device_attach, rgephy_attach), 74 DEVMETHOD(device_detach, ukphy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 MII_PHYDESC(REALTEK2, RTL8169S), 81 MII_PHYDESC(xxREALTEK, RTL8169S), 82 MII_PHYDESC_NULL 83 }; 84 85 static devclass_t rgephy_devclass; 86 87 static driver_t rgephy_driver = { 88 "rgephy", 89 rgephy_methods, 90 sizeof(struct mii_softc) 91 }; 92 93 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 94 95 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 96 static void rgephy_status(struct mii_softc *); 97 static int rgephy_mii_phy_auto(struct mii_softc *); 98 static void rgephy_reset(struct mii_softc *); 99 static void rgephy_loop(struct mii_softc *); 100 static void rgephy_load_dspcode(struct mii_softc *); 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 struct mii_attach_args *ma = device_get_ivars(dev); 106 const struct mii_phydesc *mpd; 107 108 mpd = mii_phy_match(ma, rgephys); 109 if (mpd != NULL) { 110 device_set_desc(dev, mpd->mpd_name); 111 if (bootverbose) 112 device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2)); 113 return (0); 114 } 115 return(ENXIO); 116 } 117 118 static int 119 rgephy_attach(device_t dev) 120 { 121 struct mii_softc *sc; 122 struct mii_attach_args *ma; 123 struct mii_data *mii; 124 125 sc = device_get_softc(dev); 126 ma = device_get_ivars(dev); 127 mii_softc_init(sc, ma); 128 sc->mii_dev = device_get_parent(dev); 129 130 mii = device_get_softc(sc->mii_dev); 131 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 132 133 sc->mii_inst = mii->mii_instance; 134 sc->mii_service = rgephy_service; 135 sc->mii_reset = rgephy_reset; 136 sc->mii_pdata = mii; 137 138 sc->mii_flags |= MIIF_NOISOLATE; 139 mii->mii_instance++; 140 141 rgephy_reset(sc); 142 143 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 144 if (sc->mii_capabilities & BMSR_EXTSTAT) 145 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 146 147 device_printf(dev, " "); 148 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 149 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 150 printf("no media present"); 151 else 152 mii_phy_add_media(sc); 153 printf("\n"); 154 155 MIIBUS_MEDIAINIT(sc->mii_dev); 156 return(0); 157 } 158 159 static int 160 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 161 { 162 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 163 int reg, speed, gig; 164 165 switch (cmd) { 166 case MII_POLLSTAT: 167 /* 168 * If we're not polling our PHY instance, just return. 169 */ 170 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 171 return (0); 172 break; 173 174 case MII_MEDIACHG: 175 /* 176 * If the media indicates a different PHY instance, 177 * isolate ourselves. 178 */ 179 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 180 reg = PHY_READ(sc, MII_BMCR); 181 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 182 return (0); 183 } 184 185 /* 186 * If the interface is not up, don't do anything. 187 */ 188 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 189 break; 190 191 rgephy_reset(sc); /* XXX hardware bug work-around */ 192 193 switch (IFM_SUBTYPE(ife->ifm_media)) { 194 case IFM_AUTO: 195 #ifdef foo 196 /* 197 * If we're already in auto mode, just return. 198 */ 199 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 200 return (0); 201 #endif 202 rgephy_mii_phy_auto(sc); 203 break; 204 case IFM_1000_T: 205 speed = RGEPHY_S1000; 206 goto setit; 207 case IFM_100_TX: 208 speed = RGEPHY_S100; 209 goto setit; 210 case IFM_10_T: 211 speed = RGEPHY_S10; 212 setit: 213 rgephy_loop(sc); 214 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 215 speed |= RGEPHY_BMCR_FDX; 216 gig = RGEPHY_1000CTL_AFD; 217 } else { 218 gig = RGEPHY_1000CTL_AHD; 219 } 220 221 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 222 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 223 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 224 225 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 226 break; 227 228 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 229 PHY_WRITE(sc, RGEPHY_MII_BMCR, 230 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 231 232 /* 233 * When settning the link manually, one side must 234 * be the master and the other the slave. However 235 * ifmedia doesn't give us a good way to specify 236 * this, so we fake it by using one of the LINK 237 * flags. If LINK0 is set, we program the PHY to 238 * be a master, otherwise it's a slave. 239 */ 240 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 241 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 242 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 243 } else { 244 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 245 gig|RGEPHY_1000CTL_MSE); 246 } 247 break; 248 #ifdef foo 249 case IFM_NONE: 250 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 251 break; 252 #endif 253 case IFM_100_T4: 254 default: 255 return (EINVAL); 256 } 257 break; 258 259 case MII_TICK: 260 /* 261 * If we're not currently selected, just return. 262 */ 263 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 264 return (0); 265 266 /* 267 * Is the interface even up? 268 */ 269 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 270 return (0); 271 272 /* 273 * Only used for autonegotiation. 274 */ 275 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 276 break; 277 278 /* 279 * Check to see if we have link. If we do, we don't 280 * need to restart the autonegotiation process. 281 * 282 * XXX Read the BMSR twice in case it's latched? 283 */ 284 reg = PHY_READ(sc, RE_GMEDIASTAT); 285 if (reg & RE_GMEDIASTAT_LINK) 286 break; 287 288 /* 289 * Only retry autonegotiation every mii_anegticks seconds. 290 */ 291 if (++sc->mii_ticks <= sc->mii_anegticks) 292 break; 293 294 sc->mii_ticks = 0; 295 296 /* 297 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN, 298 * we should not rely on that. 299 */ 300 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN) 301 return (0); 302 break; 303 } 304 305 /* Update the media status. */ 306 rgephy_status(sc); 307 308 /* 309 * Callback if something changed. Note that we need to poke 310 * the DSP on the RealTek PHYs if the media changes. 311 */ 312 if (sc->mii_media_active != mii->mii_media_active || 313 sc->mii_media_status != mii->mii_media_status || 314 cmd == MII_MEDIACHG) 315 rgephy_load_dspcode(sc); 316 mii_phy_update(sc, cmd); 317 return (0); 318 } 319 320 static void 321 rgephy_status(struct mii_softc *sc) 322 { 323 struct mii_data *mii = sc->mii_pdata; 324 int bmsr, bmcr; 325 326 mii->mii_media_status = IFM_AVALID; 327 mii->mii_media_active = IFM_ETHER; 328 329 bmsr = PHY_READ(sc, RE_GMEDIASTAT); 330 331 if (bmsr & RE_GMEDIASTAT_LINK) 332 mii->mii_media_status |= IFM_ACTIVE; 333 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 334 335 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 336 337 if (bmcr & RGEPHY_BMCR_LOOP) 338 mii->mii_media_active |= IFM_LOOP; 339 340 if (bmcr & RGEPHY_BMCR_AUTOEN) { 341 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 342 /* Erg, still trying, I guess... */ 343 mii->mii_media_active |= IFM_NONE; 344 return; 345 } 346 } 347 348 bmsr = PHY_READ(sc, RE_GMEDIASTAT); 349 350 if (bmsr & RE_GMEDIASTAT_1000MBPS) { 351 mii->mii_media_active |= IFM_1000_T; 352 } else if (bmsr & RE_GMEDIASTAT_100MBPS) { 353 mii->mii_media_active |= IFM_100_TX; 354 } else if (bmsr & RE_GMEDIASTAT_10MBPS) { 355 mii->mii_media_active |= IFM_10_T; 356 } else { 357 mii->mii_media_active |= IFM_NONE; 358 return; 359 } 360 361 if (bmsr & RE_GMEDIASTAT_FDX) 362 mii->mii_media_active |= IFM_FDX; 363 } 364 365 static int 366 rgephy_mii_phy_auto(struct mii_softc *sc) 367 { 368 rgephy_loop(sc); 369 rgephy_reset(sc); 370 371 PHY_WRITE(sc, RGEPHY_MII_ANAR, 372 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 373 DELAY(1000); 374 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 375 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 376 DELAY(1000); 377 PHY_WRITE(sc, RGEPHY_MII_BMCR, 378 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 379 DELAY(100); 380 381 return (EJUSTRETURN); 382 } 383 384 static void 385 rgephy_loop(struct mii_softc *sc) 386 { 387 uint32_t bmsr; 388 int i; 389 390 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 391 DELAY(1000); 392 393 for (i = 0; i < 15000; i++) { 394 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 395 if (!(bmsr & RGEPHY_BMSR_LINK)) { 396 #if 0 397 device_printf(sc->mii_dev, "looped %d\n", i); 398 #endif 399 break; 400 } 401 DELAY(10); 402 } 403 } 404 405 #define PHY_SETBIT(x, y, z) \ 406 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 407 #define PHY_CLRBIT(x, y, z) \ 408 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 409 410 /* 411 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 412 * existing revisions of the 8169S/8110S chips need to be tuned in 413 * order to reliably negotiate a 1000Mbps link. This is only needed 414 * for rev 0 and rev 1 of the PHY. Later versions work without 415 * any fixups. 416 */ 417 static void 418 rgephy_load_dspcode(struct mii_softc *sc) 419 { 420 int val; 421 422 if (sc->mii_rev > 1) 423 return; 424 425 PHY_WRITE(sc, 31, 0x0001); 426 PHY_WRITE(sc, 21, 0x1000); 427 PHY_WRITE(sc, 24, 0x65C7); 428 PHY_CLRBIT(sc, 4, 0x0800); 429 val = PHY_READ(sc, 4) & 0xFFF; 430 PHY_WRITE(sc, 4, val); 431 PHY_WRITE(sc, 3, 0x00A1); 432 PHY_WRITE(sc, 2, 0x0008); 433 PHY_WRITE(sc, 1, 0x1020); 434 PHY_WRITE(sc, 0, 0x1000); 435 PHY_SETBIT(sc, 4, 0x0800); 436 PHY_CLRBIT(sc, 4, 0x0800); 437 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 438 PHY_WRITE(sc, 4, val); 439 PHY_WRITE(sc, 3, 0xFF41); 440 PHY_WRITE(sc, 2, 0xDE60); 441 PHY_WRITE(sc, 1, 0x0140); 442 PHY_WRITE(sc, 0, 0x0077); 443 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 444 PHY_WRITE(sc, 4, val); 445 PHY_WRITE(sc, 3, 0xDF01); 446 PHY_WRITE(sc, 2, 0xDF20); 447 PHY_WRITE(sc, 1, 0xFF95); 448 PHY_WRITE(sc, 0, 0xFA00); 449 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0xFF41); 452 PHY_WRITE(sc, 2, 0xDE20); 453 PHY_WRITE(sc, 1, 0x0140); 454 PHY_WRITE(sc, 0, 0x00BB); 455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 456 PHY_WRITE(sc, 4, val); 457 PHY_WRITE(sc, 3, 0xDF01); 458 PHY_WRITE(sc, 2, 0xDF20); 459 PHY_WRITE(sc, 1, 0xFF95); 460 PHY_WRITE(sc, 0, 0xBF00); 461 PHY_SETBIT(sc, 4, 0x0800); 462 PHY_CLRBIT(sc, 4, 0x0800); 463 PHY_WRITE(sc, 31, 0x0000); 464 465 DELAY(40); 466 } 467 468 static void 469 rgephy_reset(struct mii_softc *sc) 470 { 471 mii_phy_reset(sc); 472 DELAY(1000); 473 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN); 474 DELAY(1000); 475 rgephy_load_dspcode(sc); 476 } 477