1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 33 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.11 2005/10/31 12:49:05 sephe Exp $ 34 */ 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <machine/bus.h> 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 #include <net/if_arp.h> 53 54 #include "mii.h" 55 #include "miivar.h" 56 #include "miidevs.h" 57 58 #include "brgphyreg.h" 59 #include <dev/netif/bge/if_bgereg.h> 60 61 #include "miibus_if.h" 62 63 static int brgphy_probe(device_t); 64 static int brgphy_attach(device_t); 65 static int brgphy_detach(device_t); 66 67 static device_method_t brgphy_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, brgphy_probe), 70 DEVMETHOD(device_attach, brgphy_attach), 71 DEVMETHOD(device_detach, brgphy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 { 0, 0 } 74 }; 75 76 static devclass_t brgphy_devclass; 77 78 static driver_t brgphy_driver = { 79 "brgphy", 80 brgphy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 85 86 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 87 static void brgphy_status(struct mii_softc *); 88 static int brgphy_mii_phy_auto(struct mii_softc *); 89 static void brgphy_reset(struct mii_softc *); 90 static void brgphy_loop(struct mii_softc *); 91 static void bcm5401_load_dspcode(struct mii_softc *); 92 static void bcm5411_load_dspcode(struct mii_softc *); 93 static void bcm5703_load_dspcode(struct mii_softc *); 94 static int brgphy_mii_model; 95 96 static int brgphy_probe(dev) 97 device_t dev; 98 { 99 struct mii_attach_args *ma; 100 101 ma = device_get_ivars(dev); 102 103 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 104 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 105 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 106 return(0); 107 } 108 109 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 110 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 111 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 112 return(0); 113 } 114 115 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 116 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 117 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 118 return(0); 119 } 120 121 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 122 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 123 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 124 return(0); 125 } 126 127 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 128 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 129 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 130 return(0); 131 } 132 133 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 134 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 135 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 136 return(0); 137 } 138 139 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 140 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 141 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 142 return(0); 143 } 144 145 return(ENXIO); 146 } 147 148 static int 149 brgphy_attach(dev) 150 device_t dev; 151 { 152 struct mii_softc *sc; 153 struct mii_attach_args *ma; 154 struct mii_data *mii; 155 const char *sep = ""; 156 157 sc = device_get_softc(dev); 158 ma = device_get_ivars(dev); 159 mii_softc_init(sc, ma); 160 sc->mii_dev = device_get_parent(dev); 161 mii = device_get_softc(sc->mii_dev); 162 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 163 164 sc->mii_inst = mii->mii_instance; 165 sc->mii_service = brgphy_service; 166 sc->mii_pdata = mii; 167 168 sc->mii_flags |= MIIF_NOISOLATE; 169 mii->mii_instance++; 170 171 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 172 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 173 174 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 175 BMCR_ISO); 176 #if 0 177 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 178 BMCR_LOOP|BMCR_S100); 179 #endif 180 181 brgphy_mii_model = MII_MODEL(ma->mii_id2); 182 brgphy_reset(sc); 183 184 sc->mii_capabilities = 185 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 186 device_printf(dev, " "); 187 if (sc->mii_capabilities & BMSR_MEDIAMASK) 188 mii_add_media(sc, (sc->mii_capabilities & ~BMSR_ANEG)); 189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 190 BRGPHY_BMCR_FDX); 191 PRINT(", 1000baseTX"); 192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 193 PRINT("1000baseTX-FDX"); 194 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 195 PRINT("auto"); 196 197 printf("\n"); 198 #undef ADD 199 #undef PRINT 200 201 MIIBUS_MEDIAINIT(sc->mii_dev); 202 return(0); 203 } 204 205 static int 206 brgphy_detach(dev) 207 device_t dev; 208 { 209 struct mii_softc *sc; 210 struct mii_data *mii; 211 212 sc = device_get_softc(dev); 213 mii = device_get_softc(device_get_parent(dev)); 214 sc->mii_dev = NULL; 215 LIST_REMOVE(sc, mii_list); 216 217 return(0); 218 } 219 220 static int 221 brgphy_service(sc, mii, cmd) 222 struct mii_softc *sc; 223 struct mii_data *mii; 224 int cmd; 225 { 226 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 227 int reg, speed, gig; 228 229 switch (cmd) { 230 case MII_POLLSTAT: 231 /* 232 * If we're not polling our PHY instance, just return. 233 */ 234 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 235 return (0); 236 break; 237 238 case MII_MEDIACHG: 239 /* 240 * If the media indicates a different PHY instance, 241 * isolate ourselves. 242 */ 243 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 244 reg = PHY_READ(sc, MII_BMCR); 245 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 246 return (0); 247 } 248 249 /* 250 * If the interface is not up, don't do anything. 251 */ 252 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 253 break; 254 255 brgphy_reset(sc); /* XXX hardware bug work-around */ 256 257 switch (IFM_SUBTYPE(ife->ifm_media)) { 258 case IFM_AUTO: 259 #ifdef foo 260 /* 261 * If we're already in auto mode, just return. 262 */ 263 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 264 return (0); 265 #endif 266 (void) brgphy_mii_phy_auto(sc); 267 break; 268 case IFM_1000_T: 269 speed = BRGPHY_S1000; 270 goto setit; 271 case IFM_100_TX: 272 speed = BRGPHY_S100; 273 goto setit; 274 case IFM_10_T: 275 speed = BRGPHY_S10; 276 setit: 277 brgphy_loop(sc); 278 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 279 speed |= BRGPHY_BMCR_FDX; 280 gig = BRGPHY_1000CTL_AFD; 281 } else { 282 gig = BRGPHY_1000CTL_AHD; 283 } 284 285 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 286 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 287 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 288 289 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 290 break; 291 292 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 293 PHY_WRITE(sc, BRGPHY_MII_BMCR, 294 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 295 296 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 297 break; 298 299 /* 300 * When settning the link manually, one side must 301 * be the master and the other the slave. However 302 * ifmedia doesn't give us a good way to specify 303 * this, so we fake it by using one of the LINK 304 * flags. If LINK0 is set, we program the PHY to 305 * be a master, otherwise it's a slave. 306 */ 307 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 308 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 309 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 310 } else { 311 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 312 gig|BRGPHY_1000CTL_MSE); 313 } 314 break; 315 #ifdef foo 316 case IFM_NONE: 317 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 318 break; 319 #endif 320 case IFM_100_T4: 321 default: 322 return (EINVAL); 323 } 324 break; 325 326 case MII_TICK: 327 /* 328 * If we're not currently selected, just return. 329 */ 330 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 331 return (0); 332 333 /* 334 * Only used for autonegotiation. 335 */ 336 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 337 return (0); 338 339 /* 340 * Is the interface even up? 341 */ 342 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 343 return (0); 344 345 /* 346 * Check to see if we have link. If we do, we don't 347 * need to restart the autonegotiation process. Read 348 * the BMSR twice in case it's latched. 349 */ 350 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 351 if (reg & BRGPHY_AUXSTS_LINK) 352 break; 353 354 /* 355 * Only retry autonegotiation every 5 seconds. 356 */ 357 if (++sc->mii_ticks != 5) 358 return (0); 359 360 sc->mii_ticks = 0; 361 brgphy_mii_phy_auto(sc); 362 return (0); 363 } 364 365 /* Update the media status. */ 366 brgphy_status(sc); 367 368 /* 369 * Callback if something changed. Note that we need to poke 370 * the DSP on the Broadcom PHYs if the media changes. 371 */ 372 if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 373 MIIBUS_STATCHG(sc->mii_dev); 374 sc->mii_active = mii->mii_media_active; 375 switch (brgphy_mii_model) { 376 case MII_MODEL_xxBROADCOM_BCM5401: 377 bcm5401_load_dspcode(sc); 378 break; 379 case MII_MODEL_xxBROADCOM_BCM5411: 380 bcm5411_load_dspcode(sc); 381 break; 382 } 383 } 384 return (0); 385 } 386 387 void 388 brgphy_status(sc) 389 struct mii_softc *sc; 390 { 391 struct mii_data *mii = sc->mii_pdata; 392 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 393 int bmsr, bmcr; 394 395 mii->mii_media_status = IFM_AVALID; 396 mii->mii_media_active = IFM_ETHER; 397 398 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 399 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 400 mii->mii_media_status |= IFM_ACTIVE; 401 402 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 403 404 if (bmcr & BRGPHY_BMCR_LOOP) 405 mii->mii_media_active |= IFM_LOOP; 406 407 if (bmcr & BRGPHY_BMCR_AUTOEN) { 408 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 409 /* Erg, still trying, I guess... */ 410 mii->mii_media_active |= IFM_NONE; 411 return; 412 } 413 414 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 415 BRGPHY_AUXSTS_AN_RES) { 416 case BRGPHY_RES_1000FD: 417 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 418 break; 419 case BRGPHY_RES_1000HD: 420 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 421 break; 422 case BRGPHY_RES_100FD: 423 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 424 break; 425 case BRGPHY_RES_100T4: 426 mii->mii_media_active |= IFM_100_T4; 427 break; 428 case BRGPHY_RES_100HD: 429 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 430 break; 431 case BRGPHY_RES_10FD: 432 mii->mii_media_active |= IFM_10_T | IFM_FDX; 433 break; 434 case BRGPHY_RES_10HD: 435 mii->mii_media_active |= IFM_10_T | IFM_HDX; 436 break; 437 default: 438 mii->mii_media_active |= IFM_NONE; 439 break; 440 } 441 return; 442 } 443 444 mii->mii_media_active = ife->ifm_media; 445 446 return; 447 } 448 449 450 static int 451 brgphy_mii_phy_auto(mii) 452 struct mii_softc *mii; 453 { 454 int ktcr = 0; 455 456 brgphy_loop(mii); 457 brgphy_reset(mii); 458 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 459 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 460 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 461 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 462 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 463 DELAY(1000); 464 PHY_WRITE(mii, BRGPHY_MII_ANAR, mii_bmsr_media_to_anar(mii)); 465 DELAY(1000); 466 PHY_WRITE(mii, BRGPHY_MII_BMCR, 467 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 468 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 469 return (EJUSTRETURN); 470 } 471 472 static void 473 brgphy_loop(struct mii_softc *sc) 474 { 475 u_int32_t bmsr; 476 int i; 477 478 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 479 for (i = 0; i < 15000; i++) { 480 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 481 if (!(bmsr & BRGPHY_BMSR_LINK)) { 482 #if 0 483 device_printf(sc->mii_dev, "looped %d\n", i); 484 #endif 485 break; 486 } 487 DELAY(10); 488 } 489 } 490 491 /* Turn off tap power management on 5401. */ 492 static void 493 bcm5401_load_dspcode(struct mii_softc *sc) 494 { 495 static const struct { 496 int reg; 497 uint16_t val; 498 } dspcode[] = { 499 { BRGPHY_MII_AUXCTL, 0x0c20 }, 500 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 501 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 502 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 503 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 504 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 505 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 506 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 507 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 508 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 509 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 510 { 0, 0 }, 511 }; 512 int i; 513 514 for (i = 0; dspcode[i].reg != 0; i++) 515 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 516 DELAY(40); 517 } 518 519 static void 520 bcm5411_load_dspcode(struct mii_softc *sc) 521 { 522 static const struct { 523 int reg; 524 uint16_t val; 525 } dspcode[] = { 526 { 0x1c, 0x8c23 }, 527 { 0x1c, 0x8ca3 }, 528 { 0x1c, 0x8c23 }, 529 { 0, 0 }, 530 }; 531 int i; 532 533 for (i = 0; dspcode[i].reg != 0; i++) 534 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 535 } 536 537 static void 538 bcm5703_load_dspcode(struct mii_softc *sc) 539 { 540 static const struct { 541 int reg; 542 uint16_t val; 543 } dspcode[] = { 544 { BRGPHY_MII_AUXCTL, 0x0c00 }, 545 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 546 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 547 { 0, 0 }, 548 }; 549 int i; 550 551 for (i = 0; dspcode[i].reg != 0; i++) 552 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 553 } 554 555 static void 556 bcm5704_load_dspcode(struct mii_softc *sc) 557 { 558 static const struct { 559 int reg; 560 u_int16_t val; 561 } dspcode[] = { 562 { 0x1c, 0x8d68 }, 563 { 0x1c, 0x8d68 }, 564 { 0, 0 }, 565 }; 566 int i; 567 568 for (i = 0; dspcode[i].reg != 0; i++) 569 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 570 } 571 572 static void 573 brgphy_reset(struct mii_softc *sc) 574 { 575 u_int32_t val; 576 struct ifnet *ifp; 577 struct bge_softc *bge_sc; 578 579 mii_phy_reset(sc); 580 581 switch (brgphy_mii_model) { 582 case MII_MODEL_xxBROADCOM_BCM5401: 583 bcm5401_load_dspcode(sc); 584 break; 585 case MII_MODEL_xxBROADCOM_BCM5411: 586 bcm5411_load_dspcode(sc); 587 break; 588 case MII_MODEL_xxBROADCOM_BCM5703: 589 bcm5703_load_dspcode(sc); 590 break; 591 case MII_MODEL_xxBROADCOM_BCM5704: 592 bcm5704_load_dspcode(sc); 593 break; 594 } 595 596 ifp = sc->mii_pdata->mii_ifp; 597 bge_sc = ifp->if_softc; 598 599 /* 600 * Don't enable Ethernet@WireSpeed for the 5700 or the 601 * 5705 A1 and A2 chips. Make sure we only do this test 602 * on "bge" NICs, since other drivers may use this same 603 * PHY subdriver. 604 */ 605 if (strcmp(ifp->if_dname, "bge") == 0 && 606 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 607 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 608 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 609 return; 610 611 /* Enable Ethernet@WireSpeed. */ 612 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 613 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 614 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 615 616 /* Enable Link LED on Dell boxes */ 617 if (bge_sc->bge_no_3_led) { 618 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 619 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 620 & ~BRGPHY_PHY_EXTCTL_3_LED); 621 } 622 } 623