1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.27 2005/05/31 14:11:42 joerg Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 85 #include <net/if.h> 86 #include <net/ifq_var.h> 87 #include <net/if_arp.h> 88 #include <net/ethernet.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #include <net/bpf.h> 93 94 #include <vm/vm.h> /* for vtophys */ 95 #include <vm/pmap.h> /* for vtophys */ 96 #include <machine/bus.h> 97 #include <machine/resource.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/netif/mii_layer/mii.h> 102 #include <dev/netif/mii_layer/miivar.h> 103 104 #include <bus/pci/pcireg.h> 105 #include <bus/pci/pcivar.h> 106 107 #define LGE_USEIOSPACE 108 109 #include "if_lgereg.h" 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 /* 115 * Various supported device vendors/types and their names. 116 */ 117 static struct lge_type lge_devs[] = { 118 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 119 { 0, 0, NULL } 120 }; 121 122 static int lge_probe(device_t); 123 static int lge_attach(device_t); 124 static int lge_detach(device_t); 125 126 static int lge_alloc_jumbo_mem(struct lge_softc *); 127 static void lge_free_jumbo_mem(struct lge_softc *); 128 static struct lge_jslot 129 *lge_jalloc(struct lge_softc *); 130 static void lge_jfree(void *); 131 static void lge_jref(void *); 132 133 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 134 struct mbuf *); 135 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 136 static void lge_rxeof(struct lge_softc *, int); 137 static void lge_rxeoc(struct lge_softc *); 138 static void lge_txeof(struct lge_softc *); 139 static void lge_intr(void *); 140 static void lge_tick(void *); 141 static void lge_start(struct ifnet *); 142 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 143 static void lge_init(void *); 144 static void lge_stop(struct lge_softc *); 145 static void lge_watchdog(struct ifnet *); 146 static void lge_shutdown(device_t); 147 static int lge_ifmedia_upd(struct ifnet *); 148 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 151 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 152 153 static int lge_miibus_readreg(device_t, int, int); 154 static int lge_miibus_writereg(device_t, int, int, int); 155 static void lge_miibus_statchg(device_t); 156 157 static void lge_setmulti(struct lge_softc *); 158 static void lge_reset(struct lge_softc *); 159 static int lge_list_rx_init(struct lge_softc *); 160 static int lge_list_tx_init(struct lge_softc *); 161 162 #ifdef LGE_USEIOSPACE 163 #define LGE_RES SYS_RES_IOPORT 164 #define LGE_RID LGE_PCI_LOIO 165 #else 166 #define LGE_RES SYS_RES_MEMORY 167 #define LGE_RID LGE_PCI_LOMEM 168 #endif 169 170 static device_method_t lge_methods[] = { 171 /* Device interface */ 172 DEVMETHOD(device_probe, lge_probe), 173 DEVMETHOD(device_attach, lge_attach), 174 DEVMETHOD(device_detach, lge_detach), 175 DEVMETHOD(device_shutdown, lge_shutdown), 176 177 /* bus interface */ 178 DEVMETHOD(bus_print_child, bus_generic_print_child), 179 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 180 181 /* MII interface */ 182 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 183 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 184 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 185 186 { 0, 0 } 187 }; 188 189 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 190 static devclass_t lge_devclass; 191 192 DECLARE_DUMMY_MODULE(if_lge); 193 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 194 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 195 196 #define LGE_SETBIT(sc, reg, x) \ 197 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 198 199 #define LGE_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 201 202 #define SIO_SET(x) \ 203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 204 205 #define SIO_CLR(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 207 208 /* 209 * Read a word of data stored in the EEPROM at address 'addr.' 210 */ 211 static void 212 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 213 { 214 int i; 215 uint32_t val; 216 217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 218 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 219 220 for (i = 0; i < LGE_TIMEOUT; i++) { 221 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 222 break; 223 } 224 225 if (i == LGE_TIMEOUT) { 226 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 227 return; 228 } 229 230 val = CSR_READ_4(sc, LGE_EEDATA); 231 232 if (addr & 1) 233 *dest = (val >> 16) & 0xFFFF; 234 else 235 *dest = val & 0xFFFF; 236 } 237 238 /* 239 * Read a sequence of words from the EEPROM. 240 */ 241 static void 242 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 243 { 244 int i; 245 uint16_t word = 0, *ptr; 246 247 for (i = 0; i < cnt; i++) { 248 lge_eeprom_getword(sc, off + i, &word); 249 ptr = (uint16_t *)(dest + (i * 2)); 250 *ptr = ntohs(word); 251 } 252 } 253 254 static int 255 lge_miibus_readreg(device_t dev, int phy, int reg) 256 { 257 struct lge_softc *sc = device_get_softc(dev); 258 int i; 259 260 /* 261 * If we have a non-PCS PHY, pretend that the internal 262 * autoneg stuff at PHY address 0 isn't there so that 263 * the miibus code will find only the GMII PHY. 264 */ 265 if (sc->lge_pcs == 0 && phy == 0) 266 return(0); 267 268 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 269 270 for (i = 0; i < LGE_TIMEOUT; i++) { 271 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 272 break; 273 } 274 275 if (i == LGE_TIMEOUT) { 276 printf("lge%d: PHY read timed out\n", sc->lge_unit); 277 return(0); 278 } 279 280 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 281 } 282 283 static int 284 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 285 { 286 struct lge_softc *sc = device_get_softc(dev); 287 int i; 288 289 CSR_WRITE_4(sc, LGE_GMIICTL, 290 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) { 293 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 294 break; 295 } 296 297 if (i == LGE_TIMEOUT) { 298 printf("lge%d: PHY write timed out\n", sc->lge_unit); 299 return(0); 300 } 301 302 return(0); 303 } 304 305 static void 306 lge_miibus_statchg(device_t dev) 307 { 308 struct lge_softc *sc = device_get_softc(dev); 309 struct mii_data *mii = device_get_softc(sc->lge_miibus); 310 311 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 312 switch (IFM_SUBTYPE(mii->mii_media_active)) { 313 case IFM_1000_T: 314 case IFM_1000_SX: 315 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 316 break; 317 case IFM_100_TX: 318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 319 break; 320 case IFM_10_T: 321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 322 break; 323 default: 324 /* 325 * Choose something, even if it's wrong. Clearing 326 * all the bits will hose autoneg on the internal 327 * PHY. 328 */ 329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 330 break; 331 } 332 333 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 334 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 335 else 336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 337 } 338 339 static void 340 lge_setmulti(struct lge_softc *sc) 341 { 342 struct ifnet *ifp = &sc->arpcom.ac_if; 343 struct ifmultiaddr *ifma; 344 uint32_t h = 0, hashes[2] = { 0, 0 }; 345 346 /* Make sure multicast hash table is enabled. */ 347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 348 349 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 350 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 351 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 352 return; 353 } 354 355 /* first, zot all the existing hash bits */ 356 CSR_WRITE_4(sc, LGE_MAR0, 0); 357 CSR_WRITE_4(sc, LGE_MAR1, 0); 358 359 /* now program new ones */ 360 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 361 if (ifma->ifma_addr->sa_family != AF_LINK) 362 continue; 363 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 364 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 365 if (h < 32) 366 hashes[0] |= (1 << h); 367 else 368 hashes[1] |= (1 << (h - 32)); 369 } 370 371 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 372 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 373 374 return; 375 } 376 377 static void 378 lge_reset(struct lge_softc *sc) 379 { 380 int i; 381 382 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 383 384 for (i = 0; i < LGE_TIMEOUT; i++) { 385 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 386 break; 387 } 388 389 if (i == LGE_TIMEOUT) 390 printf("lge%d: reset never completed\n", sc->lge_unit); 391 392 /* Wait a little while for the chip to get its brains in order. */ 393 DELAY(1000); 394 } 395 396 /* 397 * Probe for a Level 1 chip. Check the PCI vendor and device 398 * IDs against our list and return a device name if we find a match. 399 */ 400 static int 401 lge_probe(device_t dev) 402 { 403 struct lge_type *t; 404 uint16_t vendor, product; 405 406 vendor = pci_get_vendor(dev); 407 product = pci_get_device(dev); 408 409 for (t = lge_devs; t->lge_name != NULL; t++) { 410 if (vendor == t->lge_vid && product == t->lge_did) { 411 device_set_desc(dev, t->lge_name); 412 return(0); 413 } 414 } 415 416 return(ENXIO); 417 } 418 419 /* 420 * Attach the interface. Allocate softc structures, do ifmedia 421 * setup and ethernet/BPF attach. 422 */ 423 static int 424 lge_attach(device_t dev) 425 { 426 uint8_t eaddr[ETHER_ADDR_LEN]; 427 uint32_t command; 428 struct lge_softc *sc; 429 struct ifnet *ifp; 430 int unit, error = 0, rid, s; 431 432 s = splimp(); 433 434 sc = device_get_softc(dev); 435 unit = device_get_unit(dev); 436 callout_init(&sc->lge_stat_timer); 437 438 /* 439 * Handle power management nonsense. 440 */ 441 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF; 442 if (command == 0x01) { 443 444 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4); 445 if (command & LGE_PSTATE_MASK) { 446 uint32_t iobase, membase, irq; 447 448 /* Save important PCI config data. */ 449 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 450 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 451 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 452 453 /* Reset the power state. */ 454 printf("lge%d: chip is in D%d power mode " 455 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK); 456 command &= 0xFFFFFFFC; 457 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4); 458 459 /* Restore PCI config data. */ 460 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 461 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 462 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 463 } 464 } 465 466 /* 467 * Map control/status registers. 468 */ 469 command = pci_read_config(dev, PCIR_COMMAND, 4); 470 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 471 pci_write_config(dev, PCIR_COMMAND, command, 4); 472 command = pci_read_config(dev, PCIR_COMMAND, 4); 473 474 #ifdef LGE_USEIOSPACE 475 if (!(command & PCIM_CMD_PORTEN)) { 476 printf("lge%d: failed to enable I/O ports!\n", unit); 477 error = ENXIO; 478 goto fail; 479 } 480 #else 481 if (!(command & PCIM_CMD_MEMEN)) { 482 printf("lge%d: failed to enable memory mapping!\n", unit); 483 error = ENXIO; 484 goto fail; 485 } 486 #endif 487 488 rid = LGE_RID; 489 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 490 491 if (sc->lge_res == NULL) { 492 printf("lge%d: couldn't map ports/memory\n", unit); 493 error = ENXIO; 494 goto fail; 495 } 496 497 sc->lge_btag = rman_get_bustag(sc->lge_res); 498 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 499 500 /* Allocate interrupt */ 501 rid = 0; 502 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 503 RF_SHAREABLE | RF_ACTIVE); 504 505 if (sc->lge_irq == NULL) { 506 printf("lge%d: couldn't map interrupt\n", unit); 507 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 508 error = ENXIO; 509 goto fail; 510 } 511 512 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 513 lge_intr, sc, &sc->lge_intrhand, NULL); 514 515 if (error) { 516 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 517 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 518 printf("lge%d: couldn't set up irq\n", unit); 519 goto fail; 520 } 521 522 /* Reset the adapter. */ 523 lge_reset(sc); 524 525 /* 526 * Get station address from the EEPROM. 527 */ 528 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 529 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 530 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 531 532 sc->lge_unit = unit; 533 534 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 535 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 536 537 if (sc->lge_ldata == NULL) { 538 printf("lge%d: no memory for list buffers!\n", unit); 539 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 540 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 541 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 542 error = ENXIO; 543 goto fail; 544 } 545 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 546 547 /* Try to allocate memory for jumbo buffers. */ 548 if (lge_alloc_jumbo_mem(sc)) { 549 printf("lge%d: jumbo buffer allocation failed\n", 550 sc->lge_unit); 551 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 552 M_DEVBUF); 553 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 554 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 555 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 556 error = ENXIO; 557 goto fail; 558 } 559 560 ifp = &sc->arpcom.ac_if; 561 ifp->if_softc = sc; 562 if_initname(ifp, "lge", unit); 563 ifp->if_mtu = ETHERMTU; 564 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 565 ifp->if_ioctl = lge_ioctl; 566 ifp->if_start = lge_start; 567 ifp->if_watchdog = lge_watchdog; 568 ifp->if_init = lge_init; 569 ifp->if_baudrate = 1000000000; 570 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 571 ifq_set_ready(&ifp->if_snd); 572 ifp->if_capabilities = IFCAP_RXCSUM; 573 ifp->if_capenable = ifp->if_capabilities; 574 575 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 576 sc->lge_pcs = 1; 577 else 578 sc->lge_pcs = 0; 579 580 /* 581 * Do MII setup. 582 */ 583 if (mii_phy_probe(dev, &sc->lge_miibus, 584 lge_ifmedia_upd, lge_ifmedia_sts)) { 585 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 586 contigfree(sc->lge_ldata, 587 sizeof(struct lge_list_data), M_DEVBUF); 588 lge_free_jumbo_mem(sc); 589 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 592 error = ENXIO; 593 goto fail; 594 } 595 596 /* 597 * Call MI attach routine. 598 */ 599 ether_ifattach(ifp, eaddr); 600 601 fail: 602 splx(s); 603 return(error); 604 } 605 606 static int 607 lge_detach(device_t dev) 608 { 609 struct lge_softc *sc= device_get_softc(dev); 610 struct ifnet *ifp = &sc->arpcom.ac_if; 611 int s; 612 613 s = splimp(); 614 615 lge_reset(sc); 616 lge_stop(sc); 617 ether_ifdetach(ifp); 618 619 bus_generic_detach(dev); 620 device_delete_child(dev, sc->lge_miibus); 621 622 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 623 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 624 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 625 626 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 627 lge_free_jumbo_mem(sc); 628 629 splx(s); 630 631 return(0); 632 } 633 634 /* 635 * Initialize the transmit descriptors. 636 */ 637 static int 638 lge_list_tx_init(struct lge_softc *sc) 639 { 640 struct lge_list_data *ld; 641 struct lge_ring_data *cd; 642 int i; 643 644 cd = &sc->lge_cdata; 645 ld = sc->lge_ldata; 646 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 647 ld->lge_tx_list[i].lge_mbuf = NULL; 648 ld->lge_tx_list[i].lge_ctl = 0; 649 } 650 651 cd->lge_tx_prod = cd->lge_tx_cons = 0; 652 653 return(0); 654 } 655 656 657 /* 658 * Initialize the RX descriptors and allocate mbufs for them. Note that 659 * we arralge the descriptors in a closed ring, so that the last descriptor 660 * points back to the first. 661 */ 662 static int 663 lge_list_rx_init(struct lge_softc *sc) 664 { 665 struct lge_list_data *ld; 666 struct lge_ring_data *cd; 667 int i; 668 669 ld = sc->lge_ldata; 670 cd = &sc->lge_cdata; 671 672 cd->lge_rx_prod = cd->lge_rx_cons = 0; 673 674 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 675 676 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 677 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 678 break; 679 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 680 return(ENOBUFS); 681 } 682 683 /* Clear possible 'rx command queue empty' interrupt. */ 684 CSR_READ_4(sc, LGE_ISR); 685 686 return(0); 687 } 688 689 /* 690 * Initialize an RX descriptor and attach an MBUF cluster. 691 */ 692 static int 693 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 694 { 695 struct mbuf *m_new = NULL; 696 struct lge_jslot *buf; 697 698 if (m == NULL) { 699 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 700 if (m_new == NULL) { 701 printf("lge%d: no memory for rx list " 702 "-- packet dropped!\n", sc->lge_unit); 703 return(ENOBUFS); 704 } 705 706 /* Allocate the jumbo buffer */ 707 buf = lge_jalloc(sc); 708 if (buf == NULL) { 709 #ifdef LGE_VERBOSE 710 printf("lge%d: jumbo allocation failed " 711 "-- packet dropped!\n", sc->lge_unit); 712 #endif 713 m_freem(m_new); 714 return(ENOBUFS); 715 } 716 /* Attach the buffer to the mbuf */ 717 m_new->m_ext.ext_arg = buf; 718 m_new->m_ext.ext_buf = buf->lge_buf; 719 m_new->m_ext.ext_free = lge_jfree; 720 m_new->m_ext.ext_ref = lge_jref; 721 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 722 723 m_new->m_data = m_new->m_ext.ext_buf; 724 m_new->m_flags |= M_EXT; 725 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 726 } else { 727 m_new = m; 728 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 729 m_new->m_data = m_new->m_ext.ext_buf; 730 } 731 732 /* 733 * Adjust alignment so packet payload begins on a 734 * longword boundary. Mandatory for Alpha, useful on 735 * x86 too. 736 */ 737 m_adj(m_new, ETHER_ALIGN); 738 739 c->lge_mbuf = m_new; 740 c->lge_fragptr_hi = 0; 741 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 742 c->lge_fraglen = m_new->m_len; 743 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 744 c->lge_sts = 0; 745 746 /* 747 * Put this buffer in the RX command FIFO. To do this, 748 * we just write the physical address of the descriptor 749 * into the RX descriptor address registers. Note that 750 * there are two registers, one high DWORD and one low 751 * DWORD, which lets us specify a 64-bit address if 752 * desired. We only use a 32-bit address for now. 753 * Writing to the low DWORD register is what actually 754 * causes the command to be issued, so we do that 755 * last. 756 */ 757 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 758 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 759 760 return(0); 761 } 762 763 static int 764 lge_alloc_jumbo_mem(struct lge_softc *sc) 765 { 766 struct lge_jslot *entry; 767 caddr_t ptr; 768 int i; 769 770 /* Grab a big chunk o' storage. */ 771 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 772 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 773 774 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 775 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 776 return(ENOBUFS); 777 } 778 779 SLIST_INIT(&sc->lge_jfree_listhead); 780 781 /* 782 * Now divide it up into 9K pieces and save the addresses 783 * in an array. 784 */ 785 ptr = sc->lge_cdata.lge_jumbo_buf; 786 for (i = 0; i < LGE_JSLOTS; i++) { 787 entry = &sc->lge_cdata.lge_jslots[i]; 788 entry->lge_sc = sc; 789 entry->lge_buf = ptr; 790 entry->lge_inuse = 0; 791 entry->lge_slot = i; 792 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 793 ptr += LGE_JLEN; 794 } 795 796 return(0); 797 } 798 799 static void 800 lge_free_jumbo_mem(struct lge_softc *sc) 801 { 802 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 803 } 804 805 /* 806 * Allocate a jumbo buffer. 807 */ 808 static struct lge_jslot * 809 lge_jalloc(struct lge_softc *sc) 810 { 811 struct lge_jslot *entry; 812 813 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 814 815 if (entry == NULL) { 816 #ifdef LGE_VERBOSE 817 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 818 #endif 819 return(NULL); 820 } 821 822 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 823 entry->lge_inuse = 1; 824 825 return(entry); 826 } 827 828 /* 829 * Adjust usage count on a jumbo buffer. In general this doesn't 830 * get used much because our jumbo buffers don't get passed around 831 * a lot, but it's implemented for correctness. 832 */ 833 static void 834 lge_jref(void *arg) 835 { 836 struct lge_jslot *entry = (struct lge_jslot *)arg; 837 struct lge_softc *sc = entry->lge_sc; 838 839 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 840 panic("lge_jref: asked to reference buffer " 841 "that we don't manage!"); 842 else if (entry->lge_inuse == 0) 843 panic("lge_jref: buffer already free!"); 844 else 845 entry->lge_inuse++; 846 } 847 848 /* 849 * Release a jumbo buffer. 850 */ 851 static void 852 lge_jfree(void *arg) 853 { 854 struct lge_jslot *entry = (struct lge_jslot *)arg; 855 struct lge_softc *sc = entry->lge_sc; 856 857 if (sc == NULL) 858 panic("lge_jfree: can't find softc pointer!"); 859 860 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 861 panic("lge_jfree: asked to free buffer that we don't manage!"); 862 else if (entry->lge_inuse == 0) 863 panic("lge_jfree: buffer already free!"); 864 else if (--entry->lge_inuse == 0) 865 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 866 } 867 868 /* 869 * A frame has been uploaded: pass the resulting mbuf chain up to 870 * the higher level protocols. 871 */ 872 static void 873 lge_rxeof(struct lge_softc *sc, int cnt) 874 { 875 struct ifnet *ifp = &sc->arpcom.ac_if; 876 struct mbuf *m; 877 struct lge_rx_desc *cur_rx; 878 int c, i, total_len = 0; 879 uint32_t rxsts, rxctl; 880 881 882 /* Find out how many frames were processed. */ 883 c = cnt; 884 i = sc->lge_cdata.lge_rx_cons; 885 886 /* Suck them in. */ 887 while(c) { 888 struct mbuf *m0 = NULL; 889 890 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 891 rxctl = cur_rx->lge_ctl; 892 rxsts = cur_rx->lge_sts; 893 m = cur_rx->lge_mbuf; 894 cur_rx->lge_mbuf = NULL; 895 total_len = LGE_RXBYTES(cur_rx); 896 LGE_INC(i, LGE_RX_LIST_CNT); 897 c--; 898 899 /* 900 * If an error occurs, update stats, clear the 901 * status word and leave the mbuf cluster in place: 902 * it should simply get re-used next time this descriptor 903 * comes up in the ring. 904 */ 905 if (rxctl & LGE_RXCTL_ERRMASK) { 906 ifp->if_ierrors++; 907 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 908 continue; 909 } 910 911 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 912 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 913 total_len + ETHER_ALIGN, 0, ifp, NULL); 914 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 915 if (m0 == NULL) { 916 printf("lge%d: no receive buffers " 917 "available -- packet dropped!\n", 918 sc->lge_unit); 919 ifp->if_ierrors++; 920 continue; 921 } 922 m_adj(m0, ETHER_ALIGN); 923 m = m0; 924 } else { 925 m->m_pkthdr.rcvif = ifp; 926 m->m_pkthdr.len = m->m_len = total_len; 927 } 928 929 ifp->if_ipackets++; 930 931 /* Do IP checksum checking. */ 932 if (rxsts & LGE_RXSTS_ISIP) 933 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 934 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 935 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 936 if ((rxsts & LGE_RXSTS_ISTCP && 937 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 938 (rxsts & LGE_RXSTS_ISUDP && 939 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 940 m->m_pkthdr.csum_flags |= 941 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 942 m->m_pkthdr.csum_data = 0xffff; 943 } 944 945 (*ifp->if_input)(ifp, m); 946 } 947 948 sc->lge_cdata.lge_rx_cons = i; 949 } 950 951 static void 952 lge_rxeoc(struct lge_softc *sc) 953 { 954 struct ifnet *ifp = &sc->arpcom.ac_if; 955 956 ifp->if_flags &= ~IFF_RUNNING; 957 lge_init(sc); 958 } 959 960 /* 961 * A frame was downloaded to the chip. It's safe for us to clean up 962 * the list buffers. 963 */ 964 static void 965 lge_txeof(struct lge_softc *sc) 966 { 967 struct ifnet *ifp = &sc->arpcom.ac_if; 968 struct lge_tx_desc *cur_tx = NULL; 969 uint32_t idx, txdone; 970 971 /* Clear the timeout timer. */ 972 ifp->if_timer = 0; 973 974 /* 975 * Go through our tx list and free mbufs for those 976 * frames that have been transmitted. 977 */ 978 idx = sc->lge_cdata.lge_tx_cons; 979 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 980 981 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 982 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 983 984 ifp->if_opackets++; 985 if (cur_tx->lge_mbuf != NULL) { 986 m_freem(cur_tx->lge_mbuf); 987 cur_tx->lge_mbuf = NULL; 988 } 989 cur_tx->lge_ctl = 0; 990 991 txdone--; 992 LGE_INC(idx, LGE_TX_LIST_CNT); 993 ifp->if_timer = 0; 994 } 995 996 sc->lge_cdata.lge_tx_cons = idx; 997 998 if (cur_tx != NULL) 999 ifp->if_flags &= ~IFF_OACTIVE; 1000 } 1001 1002 static void 1003 lge_tick(void *xsc) 1004 { 1005 struct lge_softc *sc = xsc; 1006 struct mii_data *mii; 1007 struct ifnet *ifp = &sc->arpcom.ac_if; 1008 int s; 1009 1010 s = splimp(); 1011 1012 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1013 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1014 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1015 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1016 1017 if (!sc->lge_link) { 1018 mii = device_get_softc(sc->lge_miibus); 1019 mii_tick(mii); 1020 mii_pollstat(mii); 1021 if (mii->mii_media_status & IFM_ACTIVE && 1022 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1023 sc->lge_link++; 1024 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1025 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1026 printf("lge%d: gigabit link up\n", 1027 sc->lge_unit); 1028 if (!ifq_is_empty(&ifp->if_snd)) 1029 (*ifp->if_start)(ifp); 1030 } 1031 } 1032 1033 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1034 1035 splx(s); 1036 } 1037 1038 static void 1039 lge_intr(void *arg) 1040 { 1041 struct lge_softc *sc = arg; 1042 struct ifnet *ifp = &sc->arpcom.ac_if; 1043 uint32_t status; 1044 1045 /* Supress unwanted interrupts */ 1046 if ((ifp->if_flags & IFF_UP) == 0) { 1047 lge_stop(sc); 1048 return; 1049 } 1050 1051 for (;;) { 1052 /* 1053 * Reading the ISR register clears all interrupts, and 1054 * clears the 'interrupts enabled' bit in the IMR 1055 * register. 1056 */ 1057 status = CSR_READ_4(sc, LGE_ISR); 1058 1059 if ((status & LGE_INTRS) == 0) 1060 break; 1061 1062 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1063 lge_txeof(sc); 1064 1065 if (status & LGE_ISR_RXDMA_DONE) 1066 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1067 1068 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1069 lge_rxeoc(sc); 1070 1071 if (status & LGE_ISR_PHY_INTR) { 1072 sc->lge_link = 0; 1073 callout_stop(&sc->lge_stat_timer); 1074 lge_tick(sc); 1075 } 1076 } 1077 1078 /* Re-enable interrupts. */ 1079 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1080 1081 if (!ifq_is_empty(&ifp->if_snd)) 1082 (*ifp->if_start)(ifp); 1083 } 1084 1085 /* 1086 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1087 * pointers to the fragment pointers. 1088 */ 1089 static int 1090 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1091 { 1092 struct lge_frag *f = NULL; 1093 struct lge_tx_desc *cur_tx; 1094 struct mbuf *m; 1095 int frag = 0, tot_len = 0; 1096 1097 /* 1098 * Start packing the mbufs in this chain into 1099 * the fragment pointers. Stop when we run out 1100 * of fragments or hit the end of the mbuf chain. 1101 */ 1102 m = m_head; 1103 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1104 frag = 0; 1105 1106 for (m = m_head; m != NULL; m = m->m_next) { 1107 if (m->m_len != 0) { 1108 tot_len += m->m_len; 1109 f = &cur_tx->lge_frags[frag]; 1110 f->lge_fraglen = m->m_len; 1111 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1112 f->lge_fragptr_hi = 0; 1113 frag++; 1114 } 1115 } 1116 1117 if (m != NULL) 1118 return(ENOBUFS); 1119 1120 cur_tx->lge_mbuf = m_head; 1121 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1122 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1123 1124 /* Queue for transmit */ 1125 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1126 1127 return(0); 1128 } 1129 1130 /* 1131 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1132 * to the mbuf data regions directly in the transmit lists. We also save a 1133 * copy of the pointers since the transmit list fragment pointers are 1134 * physical addresses. 1135 */ 1136 1137 static void 1138 lge_start(struct ifnet *ifp) 1139 { 1140 struct lge_softc *sc = ifp->if_softc; 1141 struct mbuf *m_head = NULL; 1142 uint32_t idx; 1143 1144 if (!sc->lge_link) 1145 return; 1146 1147 idx = sc->lge_cdata.lge_tx_prod; 1148 1149 if (ifp->if_flags & IFF_OACTIVE) 1150 return; 1151 1152 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1153 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1154 break; 1155 1156 m_head = ifq_poll(&ifp->if_snd); 1157 if (m_head == NULL) 1158 break; 1159 1160 if (lge_encap(sc, m_head, &idx)) { 1161 ifp->if_flags |= IFF_OACTIVE; 1162 break; 1163 } 1164 m_head = ifq_dequeue(&ifp->if_snd); 1165 1166 BPF_MTAP(ifp, m_head); 1167 } 1168 1169 sc->lge_cdata.lge_tx_prod = idx; 1170 1171 /* 1172 * Set a timeout in case the chip goes out to lunch. 1173 */ 1174 ifp->if_timer = 5; 1175 } 1176 1177 static void 1178 lge_init(void *xsc) 1179 { 1180 struct lge_softc *sc = xsc; 1181 struct ifnet *ifp = &sc->arpcom.ac_if; 1182 struct mii_data *mii; 1183 int s; 1184 1185 if (ifp->if_flags & IFF_RUNNING) 1186 return; 1187 1188 s = splimp(); 1189 1190 /* 1191 * Cancel pending I/O and free all RX/TX buffers. 1192 */ 1193 lge_stop(sc); 1194 lge_reset(sc); 1195 1196 mii = device_get_softc(sc->lge_miibus); 1197 1198 /* Set MAC address */ 1199 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1200 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1201 1202 /* Init circular RX list. */ 1203 if (lge_list_rx_init(sc) == ENOBUFS) { 1204 printf("lge%d: initialization failed: no " 1205 "memory for rx buffers\n", sc->lge_unit); 1206 lge_stop(sc); 1207 splx(s); 1208 return; 1209 } 1210 1211 /* 1212 * Init tx descriptors. 1213 */ 1214 lge_list_tx_init(sc); 1215 1216 /* Set initial value for MODE1 register. */ 1217 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1218 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1219 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1220 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1221 1222 /* If we want promiscuous mode, set the allframes bit. */ 1223 if (ifp->if_flags & IFF_PROMISC) { 1224 CSR_WRITE_4(sc, LGE_MODE1, 1225 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1226 } else { 1227 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1228 } 1229 1230 /* 1231 * Set the capture broadcast bit to capture broadcast frames. 1232 */ 1233 if (ifp->if_flags & IFF_BROADCAST) { 1234 CSR_WRITE_4(sc, LGE_MODE1, 1235 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1236 } else { 1237 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1238 } 1239 1240 /* Packet padding workaround? */ 1241 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1242 1243 /* No error frames */ 1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1245 1246 /* Receive large frames */ 1247 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1248 1249 /* Workaround: disable RX/TX flow control */ 1250 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1251 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1252 1253 /* Make sure to strip CRC from received frames */ 1254 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1255 1256 /* Turn off magic packet mode */ 1257 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1258 1259 /* Turn off all VLAN stuff */ 1260 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1261 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1262 1263 /* Workarond: FIFO overflow */ 1264 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1265 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1266 1267 /* 1268 * Load the multicast filter. 1269 */ 1270 lge_setmulti(sc); 1271 1272 /* 1273 * Enable hardware checksum validation for all received IPv4 1274 * packets, do not reject packets with bad checksums. 1275 */ 1276 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1277 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1278 LGE_MODE2_RX_ERRCSUM); 1279 1280 /* 1281 * Enable the delivery of PHY interrupts based on 1282 * link/speed/duplex status chalges. 1283 */ 1284 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1285 1286 /* Enable receiver and transmitter. */ 1287 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1288 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1289 1290 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1291 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1292 1293 /* 1294 * Enable interrupts. 1295 */ 1296 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1297 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1298 1299 lge_ifmedia_upd(ifp); 1300 1301 ifp->if_flags |= IFF_RUNNING; 1302 ifp->if_flags &= ~IFF_OACTIVE; 1303 1304 splx(s); 1305 1306 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1307 } 1308 1309 /* 1310 * Set media options. 1311 */ 1312 static int 1313 lge_ifmedia_upd(struct ifnet *ifp) 1314 { 1315 struct lge_softc *sc = ifp->if_softc; 1316 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1317 1318 sc->lge_link = 0; 1319 if (mii->mii_instance) { 1320 struct mii_softc *miisc; 1321 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1322 mii_phy_reset(miisc); 1323 } 1324 mii_mediachg(mii); 1325 1326 return(0); 1327 } 1328 1329 /* 1330 * Report current media status. 1331 */ 1332 static void 1333 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1334 { 1335 struct lge_softc *sc = ifp->if_softc; 1336 struct mii_data *mii; 1337 1338 mii = device_get_softc(sc->lge_miibus); 1339 mii_pollstat(mii); 1340 ifmr->ifm_active = mii->mii_media_active; 1341 ifmr->ifm_status = mii->mii_media_status; 1342 } 1343 1344 static int 1345 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1346 { 1347 struct lge_softc *sc = ifp->if_softc; 1348 struct ifreq *ifr = (struct ifreq *) data; 1349 struct mii_data *mii; 1350 int error = 0, s; 1351 1352 s = splimp(); 1353 1354 switch(command) { 1355 case SIOCSIFMTU: 1356 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1357 error = EINVAL; 1358 else 1359 ifp->if_mtu = ifr->ifr_mtu; 1360 break; 1361 case SIOCSIFFLAGS: 1362 if (ifp->if_flags & IFF_UP) { 1363 if (ifp->if_flags & IFF_RUNNING && 1364 ifp->if_flags & IFF_PROMISC && 1365 !(sc->lge_if_flags & IFF_PROMISC)) { 1366 CSR_WRITE_4(sc, LGE_MODE1, 1367 LGE_MODE1_SETRST_CTL1| 1368 LGE_MODE1_RX_PROMISC); 1369 } else if (ifp->if_flags & IFF_RUNNING && 1370 !(ifp->if_flags & IFF_PROMISC) && 1371 sc->lge_if_flags & IFF_PROMISC) { 1372 CSR_WRITE_4(sc, LGE_MODE1, 1373 LGE_MODE1_RX_PROMISC); 1374 } else { 1375 ifp->if_flags &= ~IFF_RUNNING; 1376 lge_init(sc); 1377 } 1378 } else { 1379 if (ifp->if_flags & IFF_RUNNING) 1380 lge_stop(sc); 1381 } 1382 sc->lge_if_flags = ifp->if_flags; 1383 error = 0; 1384 break; 1385 case SIOCADDMULTI: 1386 case SIOCDELMULTI: 1387 lge_setmulti(sc); 1388 error = 0; 1389 break; 1390 case SIOCGIFMEDIA: 1391 case SIOCSIFMEDIA: 1392 mii = device_get_softc(sc->lge_miibus); 1393 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1394 break; 1395 default: 1396 error = ether_ioctl(ifp, command, data); 1397 break; 1398 } 1399 1400 splx(s); 1401 1402 return(error); 1403 } 1404 1405 static void 1406 lge_watchdog(struct ifnet *ifp) 1407 { 1408 struct lge_softc *sc = ifp->if_softc; 1409 1410 ifp->if_oerrors++; 1411 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1412 1413 lge_stop(sc); 1414 lge_reset(sc); 1415 ifp->if_flags &= ~IFF_RUNNING; 1416 lge_init(sc); 1417 1418 if (!ifq_is_empty(&ifp->if_snd)) 1419 (*ifp->if_start)(ifp); 1420 } 1421 1422 /* 1423 * Stop the adapter and free any mbufs allocated to the 1424 * RX and TX lists. 1425 */ 1426 static void 1427 lge_stop(struct lge_softc *sc) 1428 { 1429 struct ifnet *ifp = &sc->arpcom.ac_if; 1430 int i; 1431 1432 ifp->if_timer = 0; 1433 callout_stop(&sc->lge_stat_timer); 1434 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1435 1436 /* Disable receiver and transmitter. */ 1437 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1438 sc->lge_link = 0; 1439 1440 /* 1441 * Free data in the RX lists. 1442 */ 1443 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1444 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1445 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1446 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1447 } 1448 } 1449 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1450 1451 /* 1452 * Free the TX list buffers. 1453 */ 1454 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1455 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1456 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1457 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1458 } 1459 } 1460 1461 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1462 1463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1464 } 1465 1466 /* 1467 * Stop all chip I/O so that the kernel's probe routines don't 1468 * get confused by errant DMAs when rebooting. 1469 */ 1470 static void 1471 lge_shutdown(device_t dev) 1472 { 1473 struct lge_softc *sc = device_get_softc(dev); 1474 1475 lge_reset(sc); 1476 lge_stop(sc); 1477 } 1478