1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $ 28 */ 29 30 #include "opt_ifpoll.h" 31 #include "opt_jme.h" 32 33 #include <sys/param.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/interrupt.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/serialize.h> 42 #include <sys/serialize2.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/bpf.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_poll.h> 54 #include <net/ifq_var.h> 55 #include <net/toeplitz.h> 56 #include <net/toeplitz2.h> 57 #include <net/vlan/if_vlan_var.h> 58 #include <net/vlan/if_vlan_ether.h> 59 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/netif/mii_layer/miivar.h> 64 #include <dev/netif/mii_layer/jmphyreg.h> 65 66 #include <bus/pci/pcireg.h> 67 #include <bus/pci/pcivar.h> 68 #include <bus/pci/pcidevs.h> 69 70 #include <dev/netif/jme/if_jmereg.h> 71 #include <dev/netif/jme/if_jmevar.h> 72 73 #include "miibus_if.h" 74 75 #define JME_TICK_CPUID 0 /* DO NOT CHANGE THIS */ 76 77 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 78 79 #ifdef JME_RSS_DEBUG 80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \ 81 do { \ 82 if ((sc)->jme_rss_debug >= (lvl)) \ 83 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \ 84 } while (0) 85 #else /* !JME_RSS_DEBUG */ 86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 87 #endif /* JME_RSS_DEBUG */ 88 89 static int jme_probe(device_t); 90 static int jme_attach(device_t); 91 static int jme_detach(device_t); 92 static int jme_shutdown(device_t); 93 static int jme_suspend(device_t); 94 static int jme_resume(device_t); 95 96 static int jme_miibus_readreg(device_t, int, int); 97 static int jme_miibus_writereg(device_t, int, int, int); 98 static void jme_miibus_statchg(device_t); 99 100 static void jme_init(void *); 101 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 102 static void jme_start(struct ifnet *, struct ifaltq_subque *); 103 static void jme_watchdog(struct ifnet *); 104 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 105 static int jme_mediachange(struct ifnet *); 106 #ifdef IFPOLL_ENABLE 107 static void jme_npoll(struct ifnet *, struct ifpoll_info *); 108 static void jme_npoll_status(struct ifnet *); 109 static void jme_npoll_rx(struct ifnet *, void *, int); 110 static void jme_npoll_tx(struct ifnet *, void *, int); 111 #endif 112 static void jme_serialize(struct ifnet *, enum ifnet_serialize); 113 static void jme_deserialize(struct ifnet *, enum ifnet_serialize); 114 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize); 115 #ifdef INVARIANTS 116 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize, 117 boolean_t); 118 #endif 119 120 static void jme_intr(void *); 121 static void jme_msix_tx(void *); 122 static void jme_msix_rx(void *); 123 static void jme_msix_status(void *); 124 static void jme_txeof(struct jme_txdata *); 125 static void jme_rxeof(struct jme_rxdata *, int); 126 static void jme_rx_intr(struct jme_softc *, uint32_t); 127 static void jme_enable_intr(struct jme_softc *); 128 static void jme_disable_intr(struct jme_softc *); 129 static void jme_rx_restart(struct jme_softc *, uint32_t); 130 131 static int jme_msix_setup(device_t); 132 static void jme_msix_teardown(device_t, int); 133 static int jme_intr_setup(device_t); 134 static void jme_intr_teardown(device_t); 135 static void jme_msix_try_alloc(device_t); 136 static void jme_msix_free(device_t); 137 static int jme_intr_alloc(device_t); 138 static void jme_intr_free(device_t); 139 static int jme_dma_alloc(struct jme_softc *); 140 static void jme_dma_free(struct jme_softc *); 141 static int jme_init_rx_ring(struct jme_rxdata *); 142 static void jme_init_tx_ring(struct jme_txdata *); 143 static void jme_init_ssb(struct jme_softc *); 144 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int); 145 static int jme_encap(struct jme_txdata *, struct mbuf **, int *); 146 static void jme_rxpkt(struct jme_rxdata *); 147 static int jme_rxring_dma_alloc(struct jme_rxdata *); 148 static int jme_rxbuf_dma_alloc(struct jme_rxdata *); 149 static int jme_rxbuf_dma_filter(void *, bus_addr_t); 150 151 static void jme_tick(void *); 152 static void jme_stop(struct jme_softc *); 153 static void jme_reset(struct jme_softc *); 154 static void jme_set_msinum(struct jme_softc *); 155 static void jme_set_vlan(struct jme_softc *); 156 static void jme_set_filter(struct jme_softc *); 157 static void jme_stop_tx(struct jme_softc *); 158 static void jme_stop_rx(struct jme_softc *); 159 static void jme_mac_config(struct jme_softc *); 160 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]); 161 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]); 162 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 163 #ifdef notyet 164 static void jme_setwol(struct jme_softc *); 165 static void jme_setlinkspeed(struct jme_softc *); 166 #endif 167 static void jme_set_tx_coal(struct jme_softc *); 168 static void jme_set_rx_coal(struct jme_softc *); 169 static void jme_enable_rss(struct jme_softc *); 170 static void jme_disable_rss(struct jme_softc *); 171 static void jme_serialize_skipmain(struct jme_softc *); 172 static void jme_deserialize_skipmain(struct jme_softc *); 173 174 static void jme_sysctl_node(struct jme_softc *); 175 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS); 176 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 177 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS); 178 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 179 #ifdef IFPOLL_ENABLE 180 static int jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 181 static int jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 182 #endif 183 184 /* 185 * Devices supported by this driver. 186 */ 187 static const struct jme_dev { 188 uint16_t jme_vendorid; 189 uint16_t jme_deviceid; 190 uint32_t jme_caps; 191 const char *jme_name; 192 } jme_devs[] = { 193 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250, 194 JME_CAP_JUMBO, 195 "JMicron Inc, JMC250 Gigabit Ethernet" }, 196 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260, 197 JME_CAP_FASTETH, 198 "JMicron Inc, JMC260 Fast Ethernet" }, 199 { 0, 0, 0, NULL } 200 }; 201 202 static device_method_t jme_methods[] = { 203 /* Device interface. */ 204 DEVMETHOD(device_probe, jme_probe), 205 DEVMETHOD(device_attach, jme_attach), 206 DEVMETHOD(device_detach, jme_detach), 207 DEVMETHOD(device_shutdown, jme_shutdown), 208 DEVMETHOD(device_suspend, jme_suspend), 209 DEVMETHOD(device_resume, jme_resume), 210 211 /* Bus interface. */ 212 DEVMETHOD(bus_print_child, bus_generic_print_child), 213 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 214 215 /* MII interface. */ 216 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 217 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 218 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 219 220 { NULL, NULL } 221 }; 222 223 static driver_t jme_driver = { 224 "jme", 225 jme_methods, 226 sizeof(struct jme_softc) 227 }; 228 229 static devclass_t jme_devclass; 230 231 DECLARE_DUMMY_MODULE(if_jme); 232 MODULE_DEPEND(if_jme, miibus, 1, 1, 1); 233 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL); 234 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL); 235 236 static const struct { 237 uint32_t jme_coal; 238 uint32_t jme_comp; 239 uint32_t jme_empty; 240 } jme_rx_status[JME_NRXRING_MAX] = { 241 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP, 242 INTR_RXQ0_DESC_EMPTY }, 243 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP, 244 INTR_RXQ1_DESC_EMPTY }, 245 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP, 246 INTR_RXQ2_DESC_EMPTY }, 247 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP, 248 INTR_RXQ3_DESC_EMPTY } 249 }; 250 251 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF; 252 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF; 253 static int jme_rx_ring_count = 0; 254 static int jme_msi_enable = 1; 255 static int jme_msix_enable = 1; 256 257 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count); 258 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count); 259 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count); 260 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable); 261 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable); 262 263 static __inline void 264 jme_setup_rxdesc(struct jme_rxdesc *rxd) 265 { 266 struct jme_desc *desc; 267 268 desc = rxd->rx_desc; 269 desc->buflen = htole32(MCLBYTES); 270 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr)); 271 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr)); 272 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 273 } 274 275 /* 276 * Read a PHY register on the MII of the JMC250. 277 */ 278 static int 279 jme_miibus_readreg(device_t dev, int phy, int reg) 280 { 281 struct jme_softc *sc = device_get_softc(dev); 282 uint32_t val; 283 int i; 284 285 /* For FPGA version, PHY address 0 should be ignored. */ 286 if (sc->jme_caps & JME_CAP_FPGA) { 287 if (phy == 0) 288 return (0); 289 } else { 290 if (sc->jme_phyaddr != phy) 291 return (0); 292 } 293 294 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 295 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 296 297 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 298 DELAY(1); 299 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 300 break; 301 } 302 if (i == 0) { 303 device_printf(sc->jme_dev, "phy read timeout: " 304 "phy %d, reg %d\n", phy, reg); 305 return (0); 306 } 307 308 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 309 } 310 311 /* 312 * Write a PHY register on the MII of the JMC250. 313 */ 314 static int 315 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 316 { 317 struct jme_softc *sc = device_get_softc(dev); 318 int i; 319 320 /* For FPGA version, PHY address 0 should be ignored. */ 321 if (sc->jme_caps & JME_CAP_FPGA) { 322 if (phy == 0) 323 return (0); 324 } else { 325 if (sc->jme_phyaddr != phy) 326 return (0); 327 } 328 329 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 330 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 331 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 332 333 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 334 DELAY(1); 335 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 336 break; 337 } 338 if (i == 0) { 339 device_printf(sc->jme_dev, "phy write timeout: " 340 "phy %d, reg %d\n", phy, reg); 341 } 342 343 return (0); 344 } 345 346 /* 347 * Callback from MII layer when media changes. 348 */ 349 static void 350 jme_miibus_statchg(device_t dev) 351 { 352 struct jme_softc *sc = device_get_softc(dev); 353 struct ifnet *ifp = &sc->arpcom.ac_if; 354 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 355 struct mii_data *mii; 356 struct jme_txdesc *txd; 357 bus_addr_t paddr; 358 int i, r; 359 360 if (sc->jme_in_tick) 361 jme_serialize_skipmain(sc); 362 ASSERT_IFNET_SERIALIZED_ALL(ifp); 363 364 if ((ifp->if_flags & IFF_RUNNING) == 0) 365 goto done; 366 367 mii = device_get_softc(sc->jme_miibus); 368 369 sc->jme_has_link = FALSE; 370 if ((mii->mii_media_status & IFM_AVALID) != 0) { 371 switch (IFM_SUBTYPE(mii->mii_media_active)) { 372 case IFM_10_T: 373 case IFM_100_TX: 374 sc->jme_has_link = TRUE; 375 break; 376 case IFM_1000_T: 377 if (sc->jme_caps & JME_CAP_FASTETH) 378 break; 379 sc->jme_has_link = TRUE; 380 break; 381 default: 382 break; 383 } 384 } 385 386 /* 387 * Disabling Rx/Tx MACs have a side-effect of resetting 388 * JME_TXNDA/JME_RXNDA register to the first address of 389 * Tx/Rx descriptor address. So driver should reset its 390 * internal procucer/consumer pointer and reclaim any 391 * allocated resources. Note, just saving the value of 392 * JME_TXNDA and JME_RXNDA registers before stopping MAC 393 * and restoring JME_TXNDA/JME_RXNDA register is not 394 * sufficient to make sure correct MAC state because 395 * stopping MAC operation can take a while and hardware 396 * might have updated JME_TXNDA/JME_RXNDA registers 397 * during the stop operation. 398 */ 399 400 /* Disable interrupts */ 401 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 402 403 /* Stop driver */ 404 ifp->if_flags &= ~IFF_RUNNING; 405 ifq_clr_oactive(&ifp->if_snd); 406 ifp->if_timer = 0; 407 callout_stop(&sc->jme_tick_ch); 408 409 /* Stop receiver/transmitter. */ 410 jme_stop_rx(sc); 411 jme_stop_tx(sc); 412 413 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 414 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 415 416 jme_rxeof(rdata, -1); 417 if (rdata->jme_rxhead != NULL) 418 m_freem(rdata->jme_rxhead); 419 JME_RXCHAIN_RESET(rdata); 420 421 /* 422 * Reuse configured Rx descriptors and reset 423 * procuder/consumer index. 424 */ 425 rdata->jme_rx_cons = 0; 426 } 427 if (JME_ENABLE_HWRSS(sc)) 428 jme_enable_rss(sc); 429 else 430 jme_disable_rss(sc); 431 432 jme_txeof(tdata); 433 if (tdata->jme_tx_cnt != 0) { 434 /* Remove queued packets for transmit. */ 435 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 436 txd = &tdata->jme_txdesc[i]; 437 if (txd->tx_m != NULL) { 438 bus_dmamap_unload( tdata->jme_tx_tag, 439 txd->tx_dmamap); 440 m_freem(txd->tx_m); 441 txd->tx_m = NULL; 442 txd->tx_ndesc = 0; 443 IFNET_STAT_INC(ifp, oerrors, 1); 444 } 445 } 446 } 447 jme_init_tx_ring(tdata); 448 449 /* Initialize shadow status block. */ 450 jme_init_ssb(sc); 451 452 /* Program MAC with resolved speed/duplex/flow-control. */ 453 if (sc->jme_has_link) { 454 jme_mac_config(sc); 455 456 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 457 458 /* Set Tx ring address to the hardware. */ 459 paddr = tdata->jme_tx_ring_paddr; 460 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 461 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 462 463 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 464 CSR_WRITE_4(sc, JME_RXCSR, 465 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 466 467 /* Set Rx ring address to the hardware. */ 468 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr; 469 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 470 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 471 } 472 473 /* Restart receiver/transmitter. */ 474 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 475 RXCSR_RXQ_START); 476 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 477 } 478 479 ifp->if_flags |= IFF_RUNNING; 480 ifq_clr_oactive(&ifp->if_snd); 481 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 482 JME_TICK_CPUID); 483 484 #ifdef IFPOLL_ENABLE 485 if (!(ifp->if_flags & IFF_NPOLLING)) 486 #endif 487 /* Reenable interrupts. */ 488 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 489 490 done: 491 if (sc->jme_in_tick) 492 jme_deserialize_skipmain(sc); 493 } 494 495 /* 496 * Get the current interface media status. 497 */ 498 static void 499 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 500 { 501 struct jme_softc *sc = ifp->if_softc; 502 struct mii_data *mii = device_get_softc(sc->jme_miibus); 503 504 ASSERT_IFNET_SERIALIZED_ALL(ifp); 505 506 mii_pollstat(mii); 507 ifmr->ifm_status = mii->mii_media_status; 508 ifmr->ifm_active = mii->mii_media_active; 509 } 510 511 /* 512 * Set hardware to newly-selected media. 513 */ 514 static int 515 jme_mediachange(struct ifnet *ifp) 516 { 517 struct jme_softc *sc = ifp->if_softc; 518 struct mii_data *mii = device_get_softc(sc->jme_miibus); 519 int error; 520 521 ASSERT_IFNET_SERIALIZED_ALL(ifp); 522 523 if (mii->mii_instance != 0) { 524 struct mii_softc *miisc; 525 526 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 527 mii_phy_reset(miisc); 528 } 529 error = mii_mediachg(mii); 530 531 return (error); 532 } 533 534 static int 535 jme_probe(device_t dev) 536 { 537 const struct jme_dev *sp; 538 uint16_t vid, did; 539 540 vid = pci_get_vendor(dev); 541 did = pci_get_device(dev); 542 for (sp = jme_devs; sp->jme_name != NULL; ++sp) { 543 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) { 544 struct jme_softc *sc = device_get_softc(dev); 545 546 sc->jme_caps = sp->jme_caps; 547 device_set_desc(dev, sp->jme_name); 548 return (0); 549 } 550 } 551 return (ENXIO); 552 } 553 554 static int 555 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 556 { 557 uint32_t reg; 558 int i; 559 560 *val = 0; 561 for (i = JME_TIMEOUT; i > 0; i--) { 562 reg = CSR_READ_4(sc, JME_SMBCSR); 563 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 564 break; 565 DELAY(1); 566 } 567 568 if (i == 0) { 569 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 570 return (ETIMEDOUT); 571 } 572 573 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 574 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 575 for (i = JME_TIMEOUT; i > 0; i--) { 576 DELAY(1); 577 reg = CSR_READ_4(sc, JME_SMBINTF); 578 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 579 break; 580 } 581 582 if (i == 0) { 583 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 584 return (ETIMEDOUT); 585 } 586 587 reg = CSR_READ_4(sc, JME_SMBINTF); 588 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 589 590 return (0); 591 } 592 593 static int 594 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 595 { 596 uint8_t fup, reg, val; 597 uint32_t offset; 598 int match; 599 600 offset = 0; 601 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 602 fup != JME_EEPROM_SIG0) 603 return (ENOENT); 604 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 605 fup != JME_EEPROM_SIG1) 606 return (ENOENT); 607 match = 0; 608 do { 609 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 610 break; 611 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 612 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 613 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 614 break; 615 if (reg >= JME_PAR0 && 616 reg < JME_PAR0 + ETHER_ADDR_LEN) { 617 if (jme_eeprom_read_byte(sc, offset + 2, 618 &val) != 0) 619 break; 620 eaddr[reg - JME_PAR0] = val; 621 match++; 622 } 623 } 624 /* Check for the end of EEPROM descriptor. */ 625 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 626 break; 627 /* Try next eeprom descriptor. */ 628 offset += JME_EEPROM_DESC_BYTES; 629 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 630 631 if (match == ETHER_ADDR_LEN) 632 return (0); 633 634 return (ENOENT); 635 } 636 637 static void 638 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 639 { 640 uint32_t par0, par1; 641 642 /* Read station address. */ 643 par0 = CSR_READ_4(sc, JME_PAR0); 644 par1 = CSR_READ_4(sc, JME_PAR1); 645 par1 &= 0xFFFF; 646 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) { 647 device_printf(sc->jme_dev, 648 "generating fake ethernet address.\n"); 649 par0 = karc4random(); 650 /* Set OUI to JMicron. */ 651 eaddr[0] = 0x00; 652 eaddr[1] = 0x1B; 653 eaddr[2] = 0x8C; 654 eaddr[3] = (par0 >> 16) & 0xff; 655 eaddr[4] = (par0 >> 8) & 0xff; 656 eaddr[5] = par0 & 0xff; 657 } else { 658 eaddr[0] = (par0 >> 0) & 0xFF; 659 eaddr[1] = (par0 >> 8) & 0xFF; 660 eaddr[2] = (par0 >> 16) & 0xFF; 661 eaddr[3] = (par0 >> 24) & 0xFF; 662 eaddr[4] = (par1 >> 0) & 0xFF; 663 eaddr[5] = (par1 >> 8) & 0xFF; 664 } 665 } 666 667 static int 668 jme_attach(device_t dev) 669 { 670 struct jme_softc *sc = device_get_softc(dev); 671 struct ifnet *ifp = &sc->arpcom.ac_if; 672 uint32_t reg; 673 uint16_t did; 674 uint8_t pcie_ptr, rev; 675 int error = 0, i, j, rx_desc_cnt, coal_max; 676 uint8_t eaddr[ETHER_ADDR_LEN]; 677 #ifdef IFPOLL_ENABLE 678 int offset, offset_def; 679 #endif 680 681 /* 682 * Initialize serializers 683 */ 684 lwkt_serialize_init(&sc->jme_serialize); 685 lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize); 686 for (i = 0; i < JME_NRXRING_MAX; ++i) { 687 lwkt_serialize_init( 688 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize); 689 } 690 691 /* 692 * Get # of RX ring descriptors 693 */ 694 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count", 695 jme_rx_desc_count); 696 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN); 697 if (rx_desc_cnt > JME_NDESC_MAX) 698 rx_desc_cnt = JME_NDESC_MAX; 699 700 /* 701 * Get # of TX ring descriptors 702 */ 703 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 704 device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count); 705 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 706 roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN); 707 if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX) 708 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX; 709 710 /* 711 * Get # of RX rings 712 */ 713 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count", 714 jme_rx_ring_count); 715 sc->jme_cdata.jme_rx_ring_cnt = 716 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX); 717 718 /* 719 * Initialize serializer array 720 */ 721 i = 0; 722 723 KKASSERT(i < JME_NSERIALIZE); 724 sc->jme_serialize_arr[i++] = &sc->jme_serialize; 725 726 KKASSERT(i < JME_NSERIALIZE); 727 sc->jme_serialize_arr[i++] = 728 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 729 730 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) { 731 KKASSERT(i < JME_NSERIALIZE); 732 sc->jme_serialize_arr[i++] = 733 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize; 734 } 735 736 KKASSERT(i <= JME_NSERIALIZE); 737 sc->jme_serialize_cnt = i; 738 739 /* 740 * Setup TX ring specific data 741 */ 742 sc->jme_cdata.jme_tx_data.jme_sc = sc; 743 744 /* 745 * Setup RX rings specific data 746 */ 747 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 748 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 749 750 rdata->jme_sc = sc; 751 rdata->jme_rx_coal = jme_rx_status[i].jme_coal; 752 rdata->jme_rx_comp = jme_rx_status[i].jme_comp; 753 rdata->jme_rx_empty = jme_rx_status[i].jme_empty; 754 rdata->jme_rx_idx = i; 755 rdata->jme_rx_desc_cnt = rx_desc_cnt; 756 } 757 758 sc->jme_dev = dev; 759 sc->jme_lowaddr = BUS_SPACE_MAXADDR; 760 761 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 762 763 callout_init(&sc->jme_tick_ch); 764 765 #ifndef BURN_BRIDGES 766 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 767 uint32_t irq, mem; 768 769 irq = pci_read_config(dev, PCIR_INTLINE, 4); 770 mem = pci_read_config(dev, JME_PCIR_BAR, 4); 771 772 device_printf(dev, "chip is in D%d power mode " 773 "-- setting to D0\n", pci_get_powerstate(dev)); 774 775 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 776 777 pci_write_config(dev, PCIR_INTLINE, irq, 4); 778 pci_write_config(dev, JME_PCIR_BAR, mem, 4); 779 } 780 #endif /* !BURN_BRIDGE */ 781 782 /* Enable bus mastering */ 783 pci_enable_busmaster(dev); 784 785 /* 786 * Allocate IO memory 787 * 788 * JMC250 supports both memory mapped and I/O register space 789 * access. Because I/O register access should use different 790 * BARs to access registers it's waste of time to use I/O 791 * register spce access. JMC250 uses 16K to map entire memory 792 * space. 793 */ 794 sc->jme_mem_rid = JME_PCIR_BAR; 795 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 796 &sc->jme_mem_rid, RF_ACTIVE); 797 if (sc->jme_mem_res == NULL) { 798 device_printf(dev, "can't allocate IO memory\n"); 799 return ENXIO; 800 } 801 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res); 802 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res); 803 804 /* 805 * Allocate IRQ 806 */ 807 error = jme_intr_alloc(dev); 808 if (error) 809 goto fail; 810 811 /* 812 * Extract revisions 813 */ 814 reg = CSR_READ_4(sc, JME_CHIPMODE); 815 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 816 CHIPMODE_NOT_FPGA) { 817 sc->jme_caps |= JME_CAP_FPGA; 818 if (bootverbose) { 819 device_printf(dev, "FPGA revision: 0x%04x\n", 820 (reg & CHIPMODE_FPGA_REV_MASK) >> 821 CHIPMODE_FPGA_REV_SHIFT); 822 } 823 } 824 825 /* NOTE: FM revision is put in the upper 4 bits */ 826 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4; 827 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT; 828 if (bootverbose) 829 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev); 830 831 did = pci_get_device(dev); 832 switch (did) { 833 case PCI_PRODUCT_JMICRON_JMC250: 834 if (rev == JME_REV1_A2) 835 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX; 836 break; 837 838 case PCI_PRODUCT_JMICRON_JMC260: 839 if (rev == JME_REV2) 840 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT; 841 break; 842 843 default: 844 panic("unknown device id 0x%04x", did); 845 } 846 if (rev >= JME_REV2) { 847 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC; 848 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 | 849 GHC_TXMAC_CLKSRC_1000; 850 } 851 852 /* Reset the ethernet controller. */ 853 jme_reset(sc); 854 855 /* Map MSI/MSI-X vectors */ 856 jme_set_msinum(sc); 857 858 /* Get station address. */ 859 reg = CSR_READ_4(sc, JME_SMBCSR); 860 if (reg & SMBCSR_EEPROM_PRESENT) 861 error = jme_eeprom_macaddr(sc, eaddr); 862 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 863 if (error != 0 && (bootverbose)) { 864 device_printf(dev, "ethernet hardware address " 865 "not found in EEPROM.\n"); 866 } 867 jme_reg_macaddr(sc, eaddr); 868 } 869 870 /* 871 * Save PHY address. 872 * Integrated JR0211 has fixed PHY address whereas FPGA version 873 * requires PHY probing to get correct PHY address. 874 */ 875 if ((sc->jme_caps & JME_CAP_FPGA) == 0) { 876 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 877 GPREG0_PHY_ADDR_MASK; 878 if (bootverbose) { 879 device_printf(dev, "PHY is at address %d.\n", 880 sc->jme_phyaddr); 881 } 882 } else { 883 sc->jme_phyaddr = 0; 884 } 885 886 /* Set max allowable DMA size. */ 887 pcie_ptr = pci_get_pciecap_ptr(dev); 888 if (pcie_ptr != 0) { 889 uint16_t ctrl; 890 891 sc->jme_caps |= JME_CAP_PCIE; 892 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 893 if (bootverbose) { 894 device_printf(dev, "Read request size : %d bytes.\n", 895 128 << ((ctrl >> 12) & 0x07)); 896 device_printf(dev, "TLP payload size : %d bytes.\n", 897 128 << ((ctrl >> 5) & 0x07)); 898 } 899 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) { 900 case PCIEM_DEVCTL_MAX_READRQ_128: 901 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 902 break; 903 case PCIEM_DEVCTL_MAX_READRQ_256: 904 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 905 break; 906 default: 907 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 908 break; 909 } 910 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 911 } else { 912 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 913 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 914 } 915 916 #ifdef notyet 917 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 918 sc->jme_caps |= JME_CAP_PMCAP; 919 #endif 920 921 #ifdef IFPOLL_ENABLE 922 /* 923 * NPOLLING RX CPU offset 924 */ 925 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 926 offset = 0; 927 } else { 928 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 929 device_get_unit(dev)) % ncpus2; 930 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 931 if (offset >= ncpus2 || 932 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 933 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 934 offset, offset_def); 935 offset = offset_def; 936 } 937 } 938 sc->jme_npoll_rxoff = offset; 939 940 /* 941 * NPOLLING TX CPU offset 942 */ 943 offset_def = sc->jme_npoll_rxoff; 944 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 945 if (offset >= ncpus2) { 946 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 947 offset, offset_def); 948 offset = offset_def; 949 } 950 sc->jme_npoll_txoff = offset; 951 #endif 952 953 /* 954 * Set default coalesce valves 955 */ 956 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 957 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 958 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 959 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 960 961 /* 962 * Adjust coalesce valves, in case that the number of TX/RX 963 * descs are set to small values by users. 964 * 965 * NOTE: coal_max will not be zero, since number of descs 966 * must aligned by JME_NDESC_ALIGN (16 currently) 967 */ 968 coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2; 969 if (coal_max < sc->jme_tx_coal_pkt) 970 sc->jme_tx_coal_pkt = coal_max; 971 972 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2; 973 if (coal_max < sc->jme_rx_coal_pkt) 974 sc->jme_rx_coal_pkt = coal_max; 975 976 sc->jme_cdata.jme_tx_data.jme_tx_wreg = JME_TXWREG_NSEGS; 977 978 /* 979 * Create sysctl tree 980 */ 981 jme_sysctl_node(sc); 982 983 /* Allocate DMA stuffs */ 984 error = jme_dma_alloc(sc); 985 if (error) 986 goto fail; 987 988 ifp->if_softc = sc; 989 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 990 ifp->if_init = jme_init; 991 ifp->if_ioctl = jme_ioctl; 992 ifp->if_start = jme_start; 993 #ifdef IFPOLL_ENABLE 994 ifp->if_npoll = jme_npoll; 995 #endif 996 ifp->if_watchdog = jme_watchdog; 997 ifp->if_serialize = jme_serialize; 998 ifp->if_deserialize = jme_deserialize; 999 ifp->if_tryserialize = jme_tryserialize; 1000 #ifdef INVARIANTS 1001 ifp->if_serialize_assert = jme_serialize_assert; 1002 #endif 1003 ifq_set_maxlen(&ifp->if_snd, 1004 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD); 1005 ifq_set_ready(&ifp->if_snd); 1006 1007 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */ 1008 ifp->if_capabilities = IFCAP_HWCSUM | 1009 IFCAP_TSO | 1010 IFCAP_VLAN_MTU | 1011 IFCAP_VLAN_HWTAGGING; 1012 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN) 1013 ifp->if_capabilities |= IFCAP_RSS; 1014 ifp->if_capenable = ifp->if_capabilities; 1015 1016 /* 1017 * Disable TXCSUM by default to improve bulk data 1018 * transmit performance (+20Mbps improvement). 1019 */ 1020 ifp->if_capenable &= ~IFCAP_TXCSUM; 1021 1022 if (ifp->if_capenable & IFCAP_TXCSUM) 1023 ifp->if_hwassist |= JME_CSUM_FEATURES; 1024 ifp->if_hwassist |= CSUM_TSO; 1025 1026 /* Set up MII bus. */ 1027 error = mii_phy_probe(dev, &sc->jme_miibus, 1028 jme_mediachange, jme_mediastatus); 1029 if (error) { 1030 device_printf(dev, "no PHY found!\n"); 1031 goto fail; 1032 } 1033 1034 /* 1035 * Save PHYADDR for FPGA mode PHY. 1036 */ 1037 if (sc->jme_caps & JME_CAP_FPGA) { 1038 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1039 1040 if (mii->mii_instance != 0) { 1041 struct mii_softc *miisc; 1042 1043 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1044 if (miisc->mii_phy != 0) { 1045 sc->jme_phyaddr = miisc->mii_phy; 1046 break; 1047 } 1048 } 1049 if (sc->jme_phyaddr != 0) { 1050 device_printf(sc->jme_dev, 1051 "FPGA PHY is at %d\n", sc->jme_phyaddr); 1052 /* vendor magic. */ 1053 jme_miibus_writereg(dev, sc->jme_phyaddr, 1054 JMPHY_CONF, JMPHY_CONF_DEFFIFO); 1055 1056 /* XXX should we clear JME_WA_EXTFIFO */ 1057 } 1058 } 1059 } 1060 1061 ether_ifattach(ifp, eaddr, NULL); 1062 1063 /* Tell the upper layer(s) we support long frames. */ 1064 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1065 1066 /* Setup the TX ring's CPUID */ 1067 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 1068 ifsq_set_hw_serialize(ifq_get_subq_default(&ifp->if_snd), 1069 &sc->jme_cdata.jme_tx_data.jme_tx_serialize); 1070 1071 error = jme_intr_setup(dev); 1072 if (error) { 1073 ether_ifdetach(ifp); 1074 goto fail; 1075 } 1076 1077 return 0; 1078 fail: 1079 jme_detach(dev); 1080 return (error); 1081 } 1082 1083 static int 1084 jme_detach(device_t dev) 1085 { 1086 struct jme_softc *sc = device_get_softc(dev); 1087 1088 if (device_is_attached(dev)) { 1089 struct ifnet *ifp = &sc->arpcom.ac_if; 1090 1091 ifnet_serialize_all(ifp); 1092 jme_stop(sc); 1093 jme_intr_teardown(dev); 1094 ifnet_deserialize_all(ifp); 1095 1096 ether_ifdetach(ifp); 1097 } 1098 1099 if (sc->jme_sysctl_tree != NULL) 1100 sysctl_ctx_free(&sc->jme_sysctl_ctx); 1101 1102 if (sc->jme_miibus != NULL) 1103 device_delete_child(dev, sc->jme_miibus); 1104 bus_generic_detach(dev); 1105 1106 jme_intr_free(dev); 1107 1108 if (sc->jme_mem_res != NULL) { 1109 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid, 1110 sc->jme_mem_res); 1111 } 1112 1113 jme_dma_free(sc); 1114 1115 return (0); 1116 } 1117 1118 static void 1119 jme_sysctl_node(struct jme_softc *sc) 1120 { 1121 #ifdef JME_RSS_DEBUG 1122 int r; 1123 #endif 1124 1125 sysctl_ctx_init(&sc->jme_sysctl_ctx); 1126 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx, 1127 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 1128 device_get_nameunit(sc->jme_dev), 1129 CTLFLAG_RD, 0, ""); 1130 if (sc->jme_sysctl_tree == NULL) { 1131 device_printf(sc->jme_dev, "can't add sysctl node\n"); 1132 return; 1133 } 1134 1135 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1136 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1137 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1138 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout"); 1139 1140 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1141 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1142 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1143 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet"); 1144 1145 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1146 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1147 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1148 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout"); 1149 1150 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1151 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1152 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1153 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet"); 1154 1155 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1156 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1157 "rx_desc_count", CTLFLAG_RD, 1158 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt, 1159 0, "RX desc count"); 1160 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1161 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1162 "tx_desc_count", CTLFLAG_RD, 1163 &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, 1164 0, "TX desc count"); 1165 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1166 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1167 "rx_ring_count", CTLFLAG_RD, 1168 &sc->jme_cdata.jme_rx_ring_cnt, 1169 0, "RX ring count"); 1170 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1171 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1172 "tx_wreg", CTLFLAG_RW, 1173 &sc->jme_cdata.jme_tx_data.jme_tx_wreg, 0, 1174 "# of segments before writing to hardware register"); 1175 1176 #ifdef JME_RSS_DEBUG 1177 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1178 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1179 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug, 1180 0, "RSS debug level"); 1181 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1182 char rx_ring_desc[32]; 1183 1184 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1185 "rx_ring%d_pkt", r); 1186 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx, 1187 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1188 rx_ring_desc, CTLFLAG_RW, 1189 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets"); 1190 1191 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1192 "rx_ring%d_emp", r); 1193 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx, 1194 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1195 rx_ring_desc, CTLFLAG_RW, 1196 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp, 1197 "# of time RX ring empty"); 1198 } 1199 #endif 1200 1201 #ifdef IFPOLL_ENABLE 1202 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1203 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1204 "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1205 jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset"); 1206 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1207 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1208 "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1209 jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset"); 1210 #endif 1211 } 1212 1213 static int 1214 jme_dma_alloc(struct jme_softc *sc) 1215 { 1216 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1217 struct jme_txdesc *txd; 1218 bus_dmamem_t dmem; 1219 int error, i, asize; 1220 1221 asize = __VM_CACHELINE_ALIGN( 1222 tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc)); 1223 tdata->jme_txdesc = kmalloc_cachealign(asize, M_DEVBUF, 1224 M_WAITOK | M_ZERO); 1225 1226 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1227 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 1228 1229 asize = __VM_CACHELINE_ALIGN( 1230 rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc)); 1231 rdata->jme_rxdesc = kmalloc_cachealign(asize, M_DEVBUF, 1232 M_WAITOK | M_ZERO); 1233 } 1234 1235 /* Create parent ring tag. */ 1236 error = bus_dma_tag_create(NULL,/* parent */ 1237 1, JME_RING_BOUNDARY, /* algnmnt, boundary */ 1238 sc->jme_lowaddr, /* lowaddr */ 1239 BUS_SPACE_MAXADDR, /* highaddr */ 1240 NULL, NULL, /* filter, filterarg */ 1241 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1242 0, /* nsegments */ 1243 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1244 0, /* flags */ 1245 &sc->jme_cdata.jme_ring_tag); 1246 if (error) { 1247 device_printf(sc->jme_dev, 1248 "could not create parent ring DMA tag.\n"); 1249 return error; 1250 } 1251 1252 /* 1253 * Create DMA stuffs for TX ring 1254 */ 1255 asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN); 1256 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag, 1257 JME_TX_RING_ALIGN, 0, 1258 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1259 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1260 if (error) { 1261 device_printf(sc->jme_dev, "could not allocate Tx ring.\n"); 1262 return error; 1263 } 1264 tdata->jme_tx_ring_tag = dmem.dmem_tag; 1265 tdata->jme_tx_ring_map = dmem.dmem_map; 1266 tdata->jme_tx_ring = dmem.dmem_addr; 1267 tdata->jme_tx_ring_paddr = dmem.dmem_busaddr; 1268 1269 /* 1270 * Create DMA stuffs for RX rings 1271 */ 1272 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1273 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1274 if (error) 1275 return error; 1276 } 1277 1278 /* Create parent buffer tag. */ 1279 error = bus_dma_tag_create(NULL,/* parent */ 1280 1, 0, /* algnmnt, boundary */ 1281 sc->jme_lowaddr, /* lowaddr */ 1282 BUS_SPACE_MAXADDR, /* highaddr */ 1283 NULL, NULL, /* filter, filterarg */ 1284 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1285 0, /* nsegments */ 1286 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1287 0, /* flags */ 1288 &sc->jme_cdata.jme_buffer_tag); 1289 if (error) { 1290 device_printf(sc->jme_dev, 1291 "could not create parent buffer DMA tag.\n"); 1292 return error; 1293 } 1294 1295 /* 1296 * Create DMA stuffs for shadow status block 1297 */ 1298 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN); 1299 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag, 1300 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1301 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1302 if (error) { 1303 device_printf(sc->jme_dev, 1304 "could not create shadow status block.\n"); 1305 return error; 1306 } 1307 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag; 1308 sc->jme_cdata.jme_ssb_map = dmem.dmem_map; 1309 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr; 1310 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr; 1311 1312 /* 1313 * Create DMA stuffs for TX buffers 1314 */ 1315 1316 /* Create tag for Tx buffers. */ 1317 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1318 1, 0, /* algnmnt, boundary */ 1319 BUS_SPACE_MAXADDR, /* lowaddr */ 1320 BUS_SPACE_MAXADDR, /* highaddr */ 1321 NULL, NULL, /* filter, filterarg */ 1322 JME_TSO_MAXSIZE, /* maxsize */ 1323 JME_MAXTXSEGS, /* nsegments */ 1324 JME_MAXSEGSIZE, /* maxsegsize */ 1325 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */ 1326 &tdata->jme_tx_tag); 1327 if (error != 0) { 1328 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1329 return error; 1330 } 1331 1332 /* Create DMA maps for Tx buffers. */ 1333 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1334 txd = &tdata->jme_txdesc[i]; 1335 error = bus_dmamap_create(tdata->jme_tx_tag, 1336 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1337 &txd->tx_dmamap); 1338 if (error) { 1339 int j; 1340 1341 device_printf(sc->jme_dev, 1342 "could not create %dth Tx dmamap.\n", i); 1343 1344 for (j = 0; j < i; ++j) { 1345 txd = &tdata->jme_txdesc[j]; 1346 bus_dmamap_destroy(tdata->jme_tx_tag, 1347 txd->tx_dmamap); 1348 } 1349 bus_dma_tag_destroy(tdata->jme_tx_tag); 1350 tdata->jme_tx_tag = NULL; 1351 return error; 1352 } 1353 } 1354 1355 /* 1356 * Create DMA stuffs for RX buffers 1357 */ 1358 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1359 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1360 if (error) 1361 return error; 1362 } 1363 return 0; 1364 } 1365 1366 static void 1367 jme_dma_free(struct jme_softc *sc) 1368 { 1369 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1370 struct jme_txdesc *txd; 1371 struct jme_rxdesc *rxd; 1372 struct jme_rxdata *rdata; 1373 int i, r; 1374 1375 /* Tx ring */ 1376 if (tdata->jme_tx_ring_tag != NULL) { 1377 bus_dmamap_unload(tdata->jme_tx_ring_tag, 1378 tdata->jme_tx_ring_map); 1379 bus_dmamem_free(tdata->jme_tx_ring_tag, 1380 tdata->jme_tx_ring, tdata->jme_tx_ring_map); 1381 bus_dma_tag_destroy(tdata->jme_tx_ring_tag); 1382 tdata->jme_tx_ring_tag = NULL; 1383 } 1384 1385 /* Rx ring */ 1386 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1387 rdata = &sc->jme_cdata.jme_rx_data[r]; 1388 if (rdata->jme_rx_ring_tag != NULL) { 1389 bus_dmamap_unload(rdata->jme_rx_ring_tag, 1390 rdata->jme_rx_ring_map); 1391 bus_dmamem_free(rdata->jme_rx_ring_tag, 1392 rdata->jme_rx_ring, 1393 rdata->jme_rx_ring_map); 1394 bus_dma_tag_destroy(rdata->jme_rx_ring_tag); 1395 rdata->jme_rx_ring_tag = NULL; 1396 } 1397 } 1398 1399 /* Tx buffers */ 1400 if (tdata->jme_tx_tag != NULL) { 1401 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1402 txd = &tdata->jme_txdesc[i]; 1403 bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap); 1404 } 1405 bus_dma_tag_destroy(tdata->jme_tx_tag); 1406 tdata->jme_tx_tag = NULL; 1407 } 1408 1409 /* Rx buffers */ 1410 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1411 rdata = &sc->jme_cdata.jme_rx_data[r]; 1412 if (rdata->jme_rx_tag != NULL) { 1413 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 1414 rxd = &rdata->jme_rxdesc[i]; 1415 bus_dmamap_destroy(rdata->jme_rx_tag, 1416 rxd->rx_dmamap); 1417 } 1418 bus_dmamap_destroy(rdata->jme_rx_tag, 1419 rdata->jme_rx_sparemap); 1420 bus_dma_tag_destroy(rdata->jme_rx_tag); 1421 rdata->jme_rx_tag = NULL; 1422 } 1423 } 1424 1425 /* Shadow status block. */ 1426 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1427 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1428 sc->jme_cdata.jme_ssb_map); 1429 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1430 sc->jme_cdata.jme_ssb_block, 1431 sc->jme_cdata.jme_ssb_map); 1432 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1433 sc->jme_cdata.jme_ssb_tag = NULL; 1434 } 1435 1436 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1437 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1438 sc->jme_cdata.jme_buffer_tag = NULL; 1439 } 1440 if (sc->jme_cdata.jme_ring_tag != NULL) { 1441 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1442 sc->jme_cdata.jme_ring_tag = NULL; 1443 } 1444 1445 if (tdata->jme_txdesc != NULL) { 1446 kfree(tdata->jme_txdesc, M_DEVBUF); 1447 tdata->jme_txdesc = NULL; 1448 } 1449 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1450 rdata = &sc->jme_cdata.jme_rx_data[r]; 1451 if (rdata->jme_rxdesc != NULL) { 1452 kfree(rdata->jme_rxdesc, M_DEVBUF); 1453 rdata->jme_rxdesc = NULL; 1454 } 1455 } 1456 } 1457 1458 /* 1459 * Make sure the interface is stopped at reboot time. 1460 */ 1461 static int 1462 jme_shutdown(device_t dev) 1463 { 1464 return jme_suspend(dev); 1465 } 1466 1467 #ifdef notyet 1468 /* 1469 * Unlike other ethernet controllers, JMC250 requires 1470 * explicit resetting link speed to 10/100Mbps as gigabit 1471 * link will cunsume more power than 375mA. 1472 * Note, we reset the link speed to 10/100Mbps with 1473 * auto-negotiation but we don't know whether that operation 1474 * would succeed or not as we have no control after powering 1475 * off. If the renegotiation fail WOL may not work. Running 1476 * at 1Gbps draws more power than 375mA at 3.3V which is 1477 * specified in PCI specification and that would result in 1478 * complete shutdowning power to ethernet controller. 1479 * 1480 * TODO 1481 * Save current negotiated media speed/duplex/flow-control 1482 * to softc and restore the same link again after resuming. 1483 * PHY handling such as power down/resetting to 100Mbps 1484 * may be better handled in suspend method in phy driver. 1485 */ 1486 static void 1487 jme_setlinkspeed(struct jme_softc *sc) 1488 { 1489 struct mii_data *mii; 1490 int aneg, i; 1491 1492 JME_LOCK_ASSERT(sc); 1493 1494 mii = device_get_softc(sc->jme_miibus); 1495 mii_pollstat(mii); 1496 aneg = 0; 1497 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1498 switch IFM_SUBTYPE(mii->mii_media_active) { 1499 case IFM_10_T: 1500 case IFM_100_TX: 1501 return; 1502 case IFM_1000_T: 1503 aneg++; 1504 default: 1505 break; 1506 } 1507 } 1508 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1509 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1510 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1511 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1512 BMCR_AUTOEN | BMCR_STARTNEG); 1513 DELAY(1000); 1514 if (aneg != 0) { 1515 /* Poll link state until jme(4) get a 10/100 link. */ 1516 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1517 mii_pollstat(mii); 1518 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1519 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1520 case IFM_10_T: 1521 case IFM_100_TX: 1522 jme_mac_config(sc); 1523 return; 1524 default: 1525 break; 1526 } 1527 } 1528 JME_UNLOCK(sc); 1529 pause("jmelnk", hz); 1530 JME_LOCK(sc); 1531 } 1532 if (i == MII_ANEGTICKS_GIGE) 1533 device_printf(sc->jme_dev, "establishing link failed, " 1534 "WOL may not work!"); 1535 } 1536 /* 1537 * No link, force MAC to have 100Mbps, full-duplex link. 1538 * This is the last resort and may/may not work. 1539 */ 1540 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1541 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1542 jme_mac_config(sc); 1543 } 1544 1545 static void 1546 jme_setwol(struct jme_softc *sc) 1547 { 1548 struct ifnet *ifp = &sc->arpcom.ac_if; 1549 uint32_t gpr, pmcs; 1550 uint16_t pmstat; 1551 int pmc; 1552 1553 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1554 /* No PME capability, PHY power down. */ 1555 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1556 MII_BMCR, BMCR_PDOWN); 1557 return; 1558 } 1559 1560 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1561 pmcs = CSR_READ_4(sc, JME_PMCS); 1562 pmcs &= ~PMCS_WOL_ENB_MASK; 1563 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1564 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1565 /* Enable PME message. */ 1566 gpr |= GPREG0_PME_ENB; 1567 /* For gigabit controllers, reset link speed to 10/100. */ 1568 if ((sc->jme_caps & JME_CAP_FASTETH) == 0) 1569 jme_setlinkspeed(sc); 1570 } 1571 1572 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1573 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1574 1575 /* Request PME. */ 1576 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1577 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1578 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1579 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1580 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1581 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1582 /* No WOL, PHY power down. */ 1583 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1584 MII_BMCR, BMCR_PDOWN); 1585 } 1586 } 1587 #endif 1588 1589 static int 1590 jme_suspend(device_t dev) 1591 { 1592 struct jme_softc *sc = device_get_softc(dev); 1593 struct ifnet *ifp = &sc->arpcom.ac_if; 1594 1595 ifnet_serialize_all(ifp); 1596 jme_stop(sc); 1597 #ifdef notyet 1598 jme_setwol(sc); 1599 #endif 1600 ifnet_deserialize_all(ifp); 1601 1602 return (0); 1603 } 1604 1605 static int 1606 jme_resume(device_t dev) 1607 { 1608 struct jme_softc *sc = device_get_softc(dev); 1609 struct ifnet *ifp = &sc->arpcom.ac_if; 1610 #ifdef notyet 1611 int pmc; 1612 #endif 1613 1614 ifnet_serialize_all(ifp); 1615 1616 #ifdef notyet 1617 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1618 uint16_t pmstat; 1619 1620 pmstat = pci_read_config(sc->jme_dev, 1621 pmc + PCIR_POWER_STATUS, 2); 1622 /* Disable PME clear PME status. */ 1623 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1624 pci_write_config(sc->jme_dev, 1625 pmc + PCIR_POWER_STATUS, pmstat, 2); 1626 } 1627 #endif 1628 1629 if (ifp->if_flags & IFF_UP) 1630 jme_init(sc); 1631 1632 ifnet_deserialize_all(ifp); 1633 1634 return (0); 1635 } 1636 1637 static __inline int 1638 jme_tso_pullup(struct mbuf **mp) 1639 { 1640 int hoff, iphlen, thoff; 1641 struct mbuf *m; 1642 1643 m = *mp; 1644 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 1645 1646 iphlen = m->m_pkthdr.csum_iphlen; 1647 thoff = m->m_pkthdr.csum_thlen; 1648 hoff = m->m_pkthdr.csum_lhlen; 1649 1650 KASSERT(iphlen > 0, ("invalid ip hlen")); 1651 KASSERT(thoff > 0, ("invalid tcp hlen")); 1652 KASSERT(hoff > 0, ("invalid ether hlen")); 1653 1654 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 1655 m = m_pullup(m, hoff + iphlen + thoff); 1656 if (m == NULL) { 1657 *mp = NULL; 1658 return ENOBUFS; 1659 } 1660 *mp = m; 1661 } 1662 return 0; 1663 } 1664 1665 static int 1666 jme_encap(struct jme_txdata *tdata, struct mbuf **m_head, int *segs_used) 1667 { 1668 struct jme_txdesc *txd; 1669 struct jme_desc *desc; 1670 struct mbuf *m; 1671 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1672 int maxsegs, nsegs; 1673 int error, i, prod, symbol_desc; 1674 uint32_t cflags, flag64, mss; 1675 1676 M_ASSERTPKTHDR((*m_head)); 1677 1678 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) { 1679 /* XXX Is this necessary? */ 1680 error = jme_tso_pullup(m_head); 1681 if (error) 1682 return error; 1683 } 1684 1685 prod = tdata->jme_tx_prod; 1686 txd = &tdata->jme_txdesc[prod]; 1687 1688 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) 1689 symbol_desc = 1; 1690 else 1691 symbol_desc = 0; 1692 1693 maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) - 1694 (JME_TXD_RSVD + symbol_desc); 1695 if (maxsegs > JME_MAXTXSEGS) 1696 maxsegs = JME_MAXTXSEGS; 1697 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc), 1698 ("not enough segments %d", maxsegs)); 1699 1700 error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag, 1701 txd->tx_dmamap, m_head, 1702 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1703 if (error) 1704 goto fail; 1705 *segs_used += nsegs; 1706 1707 bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap, 1708 BUS_DMASYNC_PREWRITE); 1709 1710 m = *m_head; 1711 cflags = 0; 1712 mss = 0; 1713 1714 /* Configure checksum offload. */ 1715 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1716 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT; 1717 cflags |= JME_TD_TSO; 1718 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) { 1719 if (m->m_pkthdr.csum_flags & CSUM_IP) 1720 cflags |= JME_TD_IPCSUM; 1721 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1722 cflags |= JME_TD_TCPCSUM; 1723 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1724 cflags |= JME_TD_UDPCSUM; 1725 } 1726 1727 /* Configure VLAN. */ 1728 if (m->m_flags & M_VLANTAG) { 1729 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK); 1730 cflags |= JME_TD_VLAN_TAG; 1731 } 1732 1733 desc = &tdata->jme_tx_ring[prod]; 1734 desc->flags = htole32(cflags); 1735 desc->addr_hi = htole32(m->m_pkthdr.len); 1736 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1737 /* 1738 * Use 64bits TX desc chain format. 1739 * 1740 * The first TX desc of the chain, which is setup here, 1741 * is just a symbol TX desc carrying no payload. 1742 */ 1743 flag64 = JME_TD_64BIT; 1744 desc->buflen = htole32(mss); 1745 desc->addr_lo = 0; 1746 1747 *segs_used += 1; 1748 1749 /* No effective TX desc is consumed */ 1750 i = 0; 1751 } else { 1752 /* 1753 * Use 32bits TX desc chain format. 1754 * 1755 * The first TX desc of the chain, which is setup here, 1756 * is an effective TX desc carrying the first segment of 1757 * the mbuf chain. 1758 */ 1759 flag64 = 0; 1760 desc->buflen = htole32(mss | txsegs[0].ds_len); 1761 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr)); 1762 1763 /* One effective TX desc is consumed */ 1764 i = 1; 1765 } 1766 tdata->jme_tx_cnt++; 1767 KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1768 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1769 1770 txd->tx_ndesc = 1 - i; 1771 for (; i < nsegs; i++) { 1772 desc = &tdata->jme_tx_ring[prod]; 1773 desc->buflen = htole32(txsegs[i].ds_len); 1774 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1775 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1776 desc->flags = htole32(JME_TD_OWN | flag64); 1777 1778 tdata->jme_tx_cnt++; 1779 KKASSERT(tdata->jme_tx_cnt <= 1780 tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1781 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1782 } 1783 1784 /* Update producer index. */ 1785 tdata->jme_tx_prod = prod; 1786 /* 1787 * Finally request interrupt and give the first descriptor 1788 * owenership to hardware. 1789 */ 1790 desc = txd->tx_desc; 1791 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1792 1793 txd->tx_m = m; 1794 txd->tx_ndesc += nsegs; 1795 1796 return 0; 1797 fail: 1798 m_freem(*m_head); 1799 *m_head = NULL; 1800 return error; 1801 } 1802 1803 static void 1804 jme_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1805 { 1806 struct jme_softc *sc = ifp->if_softc; 1807 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1808 struct mbuf *m_head; 1809 int enq = 0; 1810 1811 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1812 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 1813 1814 if (!sc->jme_has_link) { 1815 ifq_purge(&ifp->if_snd); 1816 return; 1817 } 1818 1819 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1820 return; 1821 1822 if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata)) 1823 jme_txeof(tdata); 1824 1825 while (!ifq_is_empty(&ifp->if_snd)) { 1826 /* 1827 * Check number of available TX descs, always 1828 * leave JME_TXD_RSVD free TX descs. 1829 */ 1830 if (tdata->jme_tx_cnt + JME_TXD_SPARE > 1831 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) { 1832 ifq_set_oactive(&ifp->if_snd); 1833 break; 1834 } 1835 1836 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1837 if (m_head == NULL) 1838 break; 1839 1840 /* 1841 * Pack the data into the transmit ring. If we 1842 * don't have room, set the OACTIVE flag and wait 1843 * for the NIC to drain the ring. 1844 */ 1845 if (jme_encap(tdata, &m_head, &enq)) { 1846 KKASSERT(m_head == NULL); 1847 IFNET_STAT_INC(ifp, oerrors, 1); 1848 ifq_set_oactive(&ifp->if_snd); 1849 break; 1850 } 1851 1852 if (enq >= tdata->jme_tx_wreg) { 1853 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | 1854 TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1855 enq = 0; 1856 } 1857 1858 /* 1859 * If there's a BPF listener, bounce a copy of this frame 1860 * to him. 1861 */ 1862 ETHER_BPF_MTAP(ifp, m_head); 1863 1864 /* Set a timeout in case the chip goes out to lunch. */ 1865 ifp->if_timer = JME_TX_TIMEOUT; 1866 } 1867 1868 if (enq > 0) { 1869 /* 1870 * Reading TXCSR takes very long time under heavy load 1871 * so cache TXCSR value and writes the ORed value with 1872 * the kick command to the TXCSR. This saves one register 1873 * access cycle. 1874 */ 1875 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1876 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1877 } 1878 } 1879 1880 static void 1881 jme_watchdog(struct ifnet *ifp) 1882 { 1883 struct jme_softc *sc = ifp->if_softc; 1884 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1885 1886 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1887 1888 if (!sc->jme_has_link) { 1889 if_printf(ifp, "watchdog timeout (missed link)\n"); 1890 IFNET_STAT_INC(ifp, oerrors, 1); 1891 jme_init(sc); 1892 return; 1893 } 1894 1895 jme_txeof(tdata); 1896 if (tdata->jme_tx_cnt == 0) { 1897 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 1898 "-- recovering\n"); 1899 if (!ifq_is_empty(&ifp->if_snd)) 1900 if_devstart(ifp); 1901 return; 1902 } 1903 1904 if_printf(ifp, "watchdog timeout\n"); 1905 IFNET_STAT_INC(ifp, oerrors, 1); 1906 jme_init(sc); 1907 if (!ifq_is_empty(&ifp->if_snd)) 1908 if_devstart(ifp); 1909 } 1910 1911 static int 1912 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1913 { 1914 struct jme_softc *sc = ifp->if_softc; 1915 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1916 struct ifreq *ifr = (struct ifreq *)data; 1917 int error = 0, mask; 1918 1919 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1920 1921 switch (cmd) { 1922 case SIOCSIFMTU: 1923 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1924 (!(sc->jme_caps & JME_CAP_JUMBO) && 1925 ifr->ifr_mtu > JME_MAX_MTU)) { 1926 error = EINVAL; 1927 break; 1928 } 1929 1930 if (ifp->if_mtu != ifr->ifr_mtu) { 1931 /* 1932 * No special configuration is required when interface 1933 * MTU is changed but availability of Tx checksum 1934 * offload should be chcked against new MTU size as 1935 * FIFO size is just 2K. 1936 */ 1937 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1938 ifp->if_capenable &= 1939 ~(IFCAP_TXCSUM | IFCAP_TSO); 1940 ifp->if_hwassist &= 1941 ~(JME_CSUM_FEATURES | CSUM_TSO); 1942 } 1943 ifp->if_mtu = ifr->ifr_mtu; 1944 if (ifp->if_flags & IFF_RUNNING) 1945 jme_init(sc); 1946 } 1947 break; 1948 1949 case SIOCSIFFLAGS: 1950 if (ifp->if_flags & IFF_UP) { 1951 if (ifp->if_flags & IFF_RUNNING) { 1952 if ((ifp->if_flags ^ sc->jme_if_flags) & 1953 (IFF_PROMISC | IFF_ALLMULTI)) 1954 jme_set_filter(sc); 1955 } else { 1956 jme_init(sc); 1957 } 1958 } else { 1959 if (ifp->if_flags & IFF_RUNNING) 1960 jme_stop(sc); 1961 } 1962 sc->jme_if_flags = ifp->if_flags; 1963 break; 1964 1965 case SIOCADDMULTI: 1966 case SIOCDELMULTI: 1967 if (ifp->if_flags & IFF_RUNNING) 1968 jme_set_filter(sc); 1969 break; 1970 1971 case SIOCSIFMEDIA: 1972 case SIOCGIFMEDIA: 1973 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1974 break; 1975 1976 case SIOCSIFCAP: 1977 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1978 1979 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 1980 ifp->if_capenable ^= IFCAP_TXCSUM; 1981 if (ifp->if_capenable & IFCAP_TXCSUM) 1982 ifp->if_hwassist |= JME_CSUM_FEATURES; 1983 else 1984 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1985 } 1986 if (mask & IFCAP_RXCSUM) { 1987 uint32_t reg; 1988 1989 ifp->if_capenable ^= IFCAP_RXCSUM; 1990 reg = CSR_READ_4(sc, JME_RXMAC); 1991 reg &= ~RXMAC_CSUM_ENB; 1992 if (ifp->if_capenable & IFCAP_RXCSUM) 1993 reg |= RXMAC_CSUM_ENB; 1994 CSR_WRITE_4(sc, JME_RXMAC, reg); 1995 } 1996 1997 if (mask & IFCAP_VLAN_HWTAGGING) { 1998 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1999 jme_set_vlan(sc); 2000 } 2001 2002 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 2003 ifp->if_capenable ^= IFCAP_TSO; 2004 if (ifp->if_capenable & IFCAP_TSO) 2005 ifp->if_hwassist |= CSUM_TSO; 2006 else 2007 ifp->if_hwassist &= ~CSUM_TSO; 2008 } 2009 2010 if (mask & IFCAP_RSS) 2011 ifp->if_capenable ^= IFCAP_RSS; 2012 break; 2013 2014 default: 2015 error = ether_ioctl(ifp, cmd, data); 2016 break; 2017 } 2018 return (error); 2019 } 2020 2021 static void 2022 jme_mac_config(struct jme_softc *sc) 2023 { 2024 struct mii_data *mii; 2025 uint32_t ghc, rxmac, txmac, txpause, gp1; 2026 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0; 2027 2028 mii = device_get_softc(sc->jme_miibus); 2029 2030 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2031 DELAY(10); 2032 CSR_WRITE_4(sc, JME_GHC, 0); 2033 ghc = 0; 2034 rxmac = CSR_READ_4(sc, JME_RXMAC); 2035 rxmac &= ~RXMAC_FC_ENB; 2036 txmac = CSR_READ_4(sc, JME_TXMAC); 2037 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2038 txpause = CSR_READ_4(sc, JME_TXPFC); 2039 txpause &= ~TXPFC_PAUSE_ENB; 2040 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2041 ghc |= GHC_FULL_DUPLEX; 2042 rxmac &= ~RXMAC_COLL_DET_ENB; 2043 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2044 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2045 TXMAC_FRAME_BURST); 2046 #ifdef notyet 2047 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2048 txpause |= TXPFC_PAUSE_ENB; 2049 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2050 rxmac |= RXMAC_FC_ENB; 2051 #endif 2052 /* Disable retry transmit timer/retry limit. */ 2053 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2054 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2055 } else { 2056 rxmac |= RXMAC_COLL_DET_ENB; 2057 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2058 /* Enable retry transmit timer/retry limit. */ 2059 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2060 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2061 } 2062 2063 /* 2064 * Reprogram Tx/Rx MACs with resolved speed/duplex. 2065 */ 2066 gp1 = CSR_READ_4(sc, JME_GPREG1); 2067 gp1 &= ~GPREG1_WA_HDX; 2068 2069 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2070 hdx = 1; 2071 2072 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2073 case IFM_10_T: 2074 ghc |= GHC_SPEED_10 | sc->jme_clksrc; 2075 if (hdx) 2076 gp1 |= GPREG1_WA_HDX; 2077 break; 2078 2079 case IFM_100_TX: 2080 ghc |= GHC_SPEED_100 | sc->jme_clksrc; 2081 if (hdx) 2082 gp1 |= GPREG1_WA_HDX; 2083 2084 /* 2085 * Use extended FIFO depth to workaround CRC errors 2086 * emitted by chips before JMC250B 2087 */ 2088 phyconf = JMPHY_CONF_EXTFIFO; 2089 break; 2090 2091 case IFM_1000_T: 2092 if (sc->jme_caps & JME_CAP_FASTETH) 2093 break; 2094 2095 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000; 2096 if (hdx) 2097 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2098 break; 2099 2100 default: 2101 break; 2102 } 2103 CSR_WRITE_4(sc, JME_GHC, ghc); 2104 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2105 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2106 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2107 2108 if (sc->jme_workaround & JME_WA_EXTFIFO) { 2109 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2110 JMPHY_CONF, phyconf); 2111 } 2112 if (sc->jme_workaround & JME_WA_HDX) 2113 CSR_WRITE_4(sc, JME_GPREG1, gp1); 2114 } 2115 2116 static void 2117 jme_intr(void *xsc) 2118 { 2119 struct jme_softc *sc = xsc; 2120 struct ifnet *ifp = &sc->arpcom.ac_if; 2121 uint32_t status; 2122 int r; 2123 2124 ASSERT_SERIALIZED(&sc->jme_serialize); 2125 2126 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2127 if (status == 0 || status == 0xFFFFFFFF) 2128 return; 2129 2130 /* Disable interrupts. */ 2131 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2132 2133 status = CSR_READ_4(sc, JME_INTR_STATUS); 2134 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2135 goto back; 2136 2137 /* Reset PCC counter/timer and Ack interrupts. */ 2138 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2139 2140 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) 2141 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2142 2143 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2144 if (status & jme_rx_status[r].jme_coal) { 2145 status |= jme_rx_status[r].jme_coal | 2146 jme_rx_status[r].jme_comp; 2147 } 2148 } 2149 2150 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2151 2152 if (ifp->if_flags & IFF_RUNNING) { 2153 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2154 2155 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) 2156 jme_rx_intr(sc, status); 2157 2158 if (status & INTR_RXQ_DESC_EMPTY) { 2159 /* 2160 * Notify hardware availability of new Rx buffers. 2161 * Reading RXCSR takes very long time under heavy 2162 * load so cache RXCSR value and writes the ORed 2163 * value with the kick command to the RXCSR. This 2164 * saves one register access cycle. 2165 */ 2166 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2167 RXCSR_RX_ENB | RXCSR_RXQ_START); 2168 } 2169 2170 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) { 2171 lwkt_serialize_enter(&tdata->jme_tx_serialize); 2172 jme_txeof(tdata); 2173 if (!ifq_is_empty(&ifp->if_snd)) 2174 if_devstart(ifp); 2175 lwkt_serialize_exit(&tdata->jme_tx_serialize); 2176 } 2177 } 2178 back: 2179 /* Reenable interrupts. */ 2180 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2181 } 2182 2183 static void 2184 jme_txeof(struct jme_txdata *tdata) 2185 { 2186 struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if; 2187 int cons; 2188 2189 cons = tdata->jme_tx_cons; 2190 if (cons == tdata->jme_tx_prod) 2191 return; 2192 2193 /* 2194 * Go through our Tx list and free mbufs for those 2195 * frames which have been transmitted. 2196 */ 2197 while (cons != tdata->jme_tx_prod) { 2198 struct jme_txdesc *txd, *next_txd; 2199 uint32_t status, next_status; 2200 int next_cons, nsegs; 2201 2202 txd = &tdata->jme_txdesc[cons]; 2203 KASSERT(txd->tx_m != NULL, 2204 ("%s: freeing NULL mbuf!", __func__)); 2205 2206 status = le32toh(txd->tx_desc->flags); 2207 if ((status & JME_TD_OWN) == JME_TD_OWN) 2208 break; 2209 2210 /* 2211 * NOTE: 2212 * This chip will always update the TX descriptor's 2213 * buflen field and this updating always happens 2214 * after clearing the OWN bit, so even if the OWN 2215 * bit is cleared by the chip, we still don't sure 2216 * about whether the buflen field has been updated 2217 * by the chip or not. To avoid this race, we wait 2218 * for the next TX descriptor's OWN bit to be cleared 2219 * by the chip before reusing this TX descriptor. 2220 */ 2221 next_cons = cons; 2222 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt); 2223 next_txd = &tdata->jme_txdesc[next_cons]; 2224 if (next_txd->tx_m == NULL) 2225 break; 2226 next_status = le32toh(next_txd->tx_desc->flags); 2227 if ((next_status & JME_TD_OWN) == JME_TD_OWN) 2228 break; 2229 2230 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) { 2231 IFNET_STAT_INC(ifp, oerrors, 1); 2232 } else { 2233 IFNET_STAT_INC(ifp, opackets, 1); 2234 if (status & JME_TD_COLLISION) { 2235 IFNET_STAT_INC(ifp, collisions, 2236 le32toh(txd->tx_desc->buflen) & 2237 JME_TD_BUF_LEN_MASK); 2238 } 2239 } 2240 2241 /* 2242 * Only the first descriptor of multi-descriptor 2243 * transmission is updated so driver have to skip entire 2244 * chained buffers for the transmiited frame. In other 2245 * words, JME_TD_OWN bit is valid only at the first 2246 * descriptor of a multi-descriptor transmission. 2247 */ 2248 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2249 tdata->jme_tx_ring[cons].flags = 0; 2250 JME_DESC_INC(cons, tdata->jme_tx_desc_cnt); 2251 } 2252 2253 /* Reclaim transferred mbufs. */ 2254 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2255 m_freem(txd->tx_m); 2256 txd->tx_m = NULL; 2257 tdata->jme_tx_cnt -= txd->tx_ndesc; 2258 KASSERT(tdata->jme_tx_cnt >= 0, 2259 ("%s: Active Tx desc counter was garbled", __func__)); 2260 txd->tx_ndesc = 0; 2261 } 2262 tdata->jme_tx_cons = cons; 2263 2264 /* 1 for symbol TX descriptor */ 2265 if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1) 2266 ifp->if_timer = 0; 2267 2268 if (tdata->jme_tx_cnt + JME_TXD_SPARE <= 2269 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) 2270 ifq_clr_oactive(&ifp->if_snd); 2271 } 2272 2273 static __inline void 2274 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count) 2275 { 2276 int i; 2277 2278 for (i = 0; i < count; ++i) { 2279 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]); 2280 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2281 } 2282 } 2283 2284 static __inline struct pktinfo * 2285 jme_pktinfo(struct pktinfo *pi, uint32_t flags) 2286 { 2287 if (flags & JME_RD_IPV4) 2288 pi->pi_netisr = NETISR_IP; 2289 else if (flags & JME_RD_IPV6) 2290 pi->pi_netisr = NETISR_IPV6; 2291 else 2292 return NULL; 2293 2294 pi->pi_flags = 0; 2295 pi->pi_l3proto = IPPROTO_UNKNOWN; 2296 2297 if (flags & JME_RD_MORE_FRAG) 2298 pi->pi_flags |= PKTINFO_FLAG_FRAG; 2299 else if (flags & JME_RD_TCP) 2300 pi->pi_l3proto = IPPROTO_TCP; 2301 else if (flags & JME_RD_UDP) 2302 pi->pi_l3proto = IPPROTO_UDP; 2303 else 2304 pi = NULL; 2305 return pi; 2306 } 2307 2308 /* Receive a frame. */ 2309 static void 2310 jme_rxpkt(struct jme_rxdata *rdata) 2311 { 2312 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if; 2313 struct jme_desc *desc; 2314 struct jme_rxdesc *rxd; 2315 struct mbuf *mp, *m; 2316 uint32_t flags, status, hash, hashinfo; 2317 int cons, count, nsegs; 2318 2319 cons = rdata->jme_rx_cons; 2320 desc = &rdata->jme_rx_ring[cons]; 2321 2322 flags = le32toh(desc->flags); 2323 status = le32toh(desc->buflen); 2324 hash = le32toh(desc->addr_hi); 2325 hashinfo = le32toh(desc->addr_lo); 2326 nsegs = JME_RX_NSEGS(status); 2327 2328 if (nsegs > 1) { 2329 /* Skip the first descriptor. */ 2330 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2331 2332 /* 2333 * Clear the OWN bit of the following RX descriptors; 2334 * hardware will not clear the OWN bit except the first 2335 * RX descriptor. 2336 * 2337 * Since the first RX descriptor is setup, i.e. OWN bit 2338 * on, before its followins RX descriptors, leaving the 2339 * OWN bit on the following RX descriptors will trick 2340 * the hardware into thinking that the following RX 2341 * descriptors are ready to be used too. 2342 */ 2343 for (count = 1; count < nsegs; count++, 2344 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) 2345 rdata->jme_rx_ring[cons].flags = 0; 2346 2347 cons = rdata->jme_rx_cons; 2348 } 2349 2350 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, " 2351 "hash 0x%08x, hash info 0x%08x\n", 2352 rdata->jme_rx_idx, flags, hash, hashinfo); 2353 2354 if (status & JME_RX_ERR_STAT) { 2355 IFNET_STAT_INC(ifp, ierrors, 1); 2356 jme_discard_rxbufs(rdata, cons, nsegs); 2357 #ifdef JME_SHOW_ERRORS 2358 if_printf(ifp, "%s : receive error = 0x%b\n", 2359 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2360 #endif 2361 rdata->jme_rx_cons += nsegs; 2362 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2363 return; 2364 } 2365 2366 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2367 for (count = 0; count < nsegs; count++, 2368 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) { 2369 rxd = &rdata->jme_rxdesc[cons]; 2370 mp = rxd->rx_m; 2371 2372 /* Add a new receive buffer to the ring. */ 2373 if (jme_newbuf(rdata, rxd, 0) != 0) { 2374 IFNET_STAT_INC(ifp, iqdrops, 1); 2375 /* Reuse buffer. */ 2376 jme_discard_rxbufs(rdata, cons, nsegs - count); 2377 if (rdata->jme_rxhead != NULL) { 2378 m_freem(rdata->jme_rxhead); 2379 JME_RXCHAIN_RESET(rdata); 2380 } 2381 break; 2382 } 2383 2384 /* 2385 * Assume we've received a full sized frame. 2386 * Actual size is fixed when we encounter the end of 2387 * multi-segmented frame. 2388 */ 2389 mp->m_len = MCLBYTES; 2390 2391 /* Chain received mbufs. */ 2392 if (rdata->jme_rxhead == NULL) { 2393 rdata->jme_rxhead = mp; 2394 rdata->jme_rxtail = mp; 2395 } else { 2396 /* 2397 * Receive processor can receive a maximum frame 2398 * size of 65535 bytes. 2399 */ 2400 rdata->jme_rxtail->m_next = mp; 2401 rdata->jme_rxtail = mp; 2402 } 2403 2404 if (count == nsegs - 1) { 2405 struct pktinfo pi0, *pi; 2406 2407 /* Last desc. for this frame. */ 2408 m = rdata->jme_rxhead; 2409 m->m_pkthdr.len = rdata->jme_rxlen; 2410 if (nsegs > 1) { 2411 /* Set first mbuf size. */ 2412 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2413 /* Set last mbuf size. */ 2414 mp->m_len = rdata->jme_rxlen - 2415 ((MCLBYTES - JME_RX_PAD_BYTES) + 2416 (MCLBYTES * (nsegs - 2))); 2417 } else { 2418 m->m_len = rdata->jme_rxlen; 2419 } 2420 m->m_pkthdr.rcvif = ifp; 2421 2422 /* 2423 * Account for 10bytes auto padding which is used 2424 * to align IP header on 32bit boundary. Also note, 2425 * CRC bytes is automatically removed by the 2426 * hardware. 2427 */ 2428 m->m_data += JME_RX_PAD_BYTES; 2429 2430 /* Set checksum information. */ 2431 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2432 (flags & JME_RD_IPV4)) { 2433 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2434 if (flags & JME_RD_IPCSUM) 2435 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2436 if ((flags & JME_RD_MORE_FRAG) == 0 && 2437 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2438 (JME_RD_TCP | JME_RD_TCPCSUM) || 2439 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2440 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2441 m->m_pkthdr.csum_flags |= 2442 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2443 m->m_pkthdr.csum_data = 0xffff; 2444 } 2445 } 2446 2447 /* Check for VLAN tagged packets. */ 2448 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 2449 (flags & JME_RD_VLAN_TAG)) { 2450 m->m_pkthdr.ether_vlantag = 2451 flags & JME_RD_VLAN_MASK; 2452 m->m_flags |= M_VLANTAG; 2453 } 2454 2455 IFNET_STAT_INC(ifp, ipackets, 1); 2456 2457 if (ifp->if_capenable & IFCAP_RSS) 2458 pi = jme_pktinfo(&pi0, flags); 2459 else 2460 pi = NULL; 2461 2462 if (pi != NULL && 2463 (hashinfo & JME_RD_HASH_FN_MASK) == 2464 JME_RD_HASH_FN_TOEPLITZ) { 2465 m->m_flags |= (M_HASH | M_CKHASH); 2466 m->m_pkthdr.hash = toeplitz_hash(hash); 2467 } 2468 2469 #ifdef JME_RSS_DEBUG 2470 if (pi != NULL) { 2471 JME_RSS_DPRINTF(rdata->jme_sc, 10, 2472 "isr %d flags %08x, l3 %d %s\n", 2473 pi->pi_netisr, pi->pi_flags, 2474 pi->pi_l3proto, 2475 (m->m_flags & M_HASH) ? "hash" : ""); 2476 } 2477 #endif 2478 2479 /* Pass it on. */ 2480 ether_input_pkt(ifp, m, pi); 2481 2482 /* Reset mbuf chains. */ 2483 JME_RXCHAIN_RESET(rdata); 2484 #ifdef JME_RSS_DEBUG 2485 rdata->jme_rx_pkt++; 2486 #endif 2487 } 2488 } 2489 2490 rdata->jme_rx_cons += nsegs; 2491 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2492 } 2493 2494 static void 2495 jme_rxeof(struct jme_rxdata *rdata, int count) 2496 { 2497 struct jme_desc *desc; 2498 int nsegs, pktlen; 2499 2500 for (;;) { 2501 #ifdef IFPOLL_ENABLE 2502 if (count >= 0 && count-- == 0) 2503 break; 2504 #endif 2505 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons]; 2506 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2507 break; 2508 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2509 break; 2510 2511 /* 2512 * Check number of segments against received bytes. 2513 * Non-matching value would indicate that hardware 2514 * is still trying to update Rx descriptors. I'm not 2515 * sure whether this check is needed. 2516 */ 2517 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2518 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2519 if (nsegs != howmany(pktlen, MCLBYTES)) { 2520 if_printf(&rdata->jme_sc->arpcom.ac_if, 2521 "RX fragment count(%d) and " 2522 "packet size(%d) mismach\n", nsegs, pktlen); 2523 break; 2524 } 2525 2526 /* 2527 * NOTE: 2528 * RSS hash and hash information may _not_ be set by the 2529 * hardware even if the OWN bit is cleared and VALID bit 2530 * is set. 2531 * 2532 * If the RSS information is not delivered by the hardware 2533 * yet, we MUST NOT accept this packet, let alone reusing 2534 * its RX descriptor. If this packet was accepted and its 2535 * RX descriptor was reused before hardware delivering the 2536 * RSS information, the RX buffer's address would be trashed 2537 * by the RSS information delivered by the hardware. 2538 */ 2539 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 2540 struct jme_rxdesc *rxd; 2541 uint32_t hashinfo; 2542 2543 hashinfo = le32toh(desc->addr_lo); 2544 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons]; 2545 2546 /* 2547 * This test should be enough to detect the pending 2548 * RSS information delivery, given: 2549 * - If RSS hash is not calculated, the hashinfo 2550 * will be 0. Howvever, the lower 32bits of RX 2551 * buffers' physical address will never be 0. 2552 * (see jme_rxbuf_dma_filter) 2553 * - If RSS hash is calculated, the lowest 4 bits 2554 * of hashinfo will be set, while the RX buffers 2555 * are at least 2K aligned. 2556 */ 2557 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) { 2558 #ifdef JME_SHOW_RSSWB 2559 if_printf(&rdata->jme_sc->arpcom.ac_if, 2560 "RSS is not written back yet\n"); 2561 #endif 2562 break; 2563 } 2564 } 2565 2566 /* Received a frame. */ 2567 jme_rxpkt(rdata); 2568 } 2569 } 2570 2571 static void 2572 jme_tick(void *xsc) 2573 { 2574 struct jme_softc *sc = xsc; 2575 struct mii_data *mii = device_get_softc(sc->jme_miibus); 2576 2577 lwkt_serialize_enter(&sc->jme_serialize); 2578 2579 KKASSERT(mycpuid == JME_TICK_CPUID); 2580 2581 sc->jme_in_tick = TRUE; 2582 mii_tick(mii); 2583 sc->jme_in_tick = FALSE; 2584 2585 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2586 2587 lwkt_serialize_exit(&sc->jme_serialize); 2588 } 2589 2590 static void 2591 jme_reset(struct jme_softc *sc) 2592 { 2593 uint32_t val; 2594 2595 /* Make sure that TX and RX are stopped */ 2596 jme_stop_tx(sc); 2597 jme_stop_rx(sc); 2598 2599 /* Start reset */ 2600 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2601 DELAY(20); 2602 2603 /* 2604 * Hold reset bit before stop reset 2605 */ 2606 2607 /* Disable TXMAC and TXOFL clock sources */ 2608 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2609 /* Disable RXMAC clock source */ 2610 val = CSR_READ_4(sc, JME_GPREG1); 2611 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2612 /* Flush */ 2613 CSR_READ_4(sc, JME_GHC); 2614 2615 /* Stop reset */ 2616 CSR_WRITE_4(sc, JME_GHC, 0); 2617 /* Flush */ 2618 CSR_READ_4(sc, JME_GHC); 2619 2620 /* 2621 * Clear reset bit after stop reset 2622 */ 2623 2624 /* Enable TXMAC and TXOFL clock sources */ 2625 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2626 /* Enable RXMAC clock source */ 2627 val = CSR_READ_4(sc, JME_GPREG1); 2628 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2629 /* Flush */ 2630 CSR_READ_4(sc, JME_GHC); 2631 2632 /* Disable TXMAC and TXOFL clock sources */ 2633 CSR_WRITE_4(sc, JME_GHC, 0); 2634 /* Disable RXMAC clock source */ 2635 val = CSR_READ_4(sc, JME_GPREG1); 2636 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2637 /* Flush */ 2638 CSR_READ_4(sc, JME_GHC); 2639 2640 /* Enable TX and RX */ 2641 val = CSR_READ_4(sc, JME_TXCSR); 2642 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB); 2643 val = CSR_READ_4(sc, JME_RXCSR); 2644 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB); 2645 /* Flush */ 2646 CSR_READ_4(sc, JME_TXCSR); 2647 CSR_READ_4(sc, JME_RXCSR); 2648 2649 /* Enable TXMAC and TXOFL clock sources */ 2650 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2651 /* Eisable RXMAC clock source */ 2652 val = CSR_READ_4(sc, JME_GPREG1); 2653 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2654 /* Flush */ 2655 CSR_READ_4(sc, JME_GHC); 2656 2657 /* Stop TX and RX */ 2658 jme_stop_tx(sc); 2659 jme_stop_rx(sc); 2660 } 2661 2662 static void 2663 jme_init(void *xsc) 2664 { 2665 struct jme_softc *sc = xsc; 2666 struct ifnet *ifp = &sc->arpcom.ac_if; 2667 struct mii_data *mii; 2668 uint8_t eaddr[ETHER_ADDR_LEN]; 2669 bus_addr_t paddr; 2670 uint32_t reg; 2671 int error, r; 2672 2673 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2674 2675 /* 2676 * Cancel any pending I/O. 2677 */ 2678 jme_stop(sc); 2679 2680 /* 2681 * Reset the chip to a known state. 2682 */ 2683 jme_reset(sc); 2684 2685 /* 2686 * Setup MSI/MSI-X vectors to interrupts mapping 2687 */ 2688 jme_set_msinum(sc); 2689 2690 if (JME_ENABLE_HWRSS(sc)) 2691 jme_enable_rss(sc); 2692 else 2693 jme_disable_rss(sc); 2694 2695 /* Init RX descriptors */ 2696 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2697 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]); 2698 if (error) { 2699 if_printf(ifp, "initialization failed: " 2700 "no memory for %dth RX ring.\n", r); 2701 jme_stop(sc); 2702 return; 2703 } 2704 } 2705 2706 /* Init TX descriptors */ 2707 jme_init_tx_ring(&sc->jme_cdata.jme_tx_data); 2708 2709 /* Initialize shadow status block. */ 2710 jme_init_ssb(sc); 2711 2712 /* Reprogram the station address. */ 2713 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2714 CSR_WRITE_4(sc, JME_PAR0, 2715 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2716 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2717 2718 /* 2719 * Configure Tx queue. 2720 * Tx priority queue weight value : 0 2721 * Tx FIFO threshold for processing next packet : 16QW 2722 * Maximum Tx DMA length : 512 2723 * Allow Tx DMA burst. 2724 */ 2725 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2726 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2727 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2728 sc->jme_txcsr |= sc->jme_tx_dma_size; 2729 sc->jme_txcsr |= TXCSR_DMA_BURST; 2730 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2731 2732 /* Set Tx descriptor counter. */ 2733 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt); 2734 2735 /* Set Tx ring address to the hardware. */ 2736 paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr; 2737 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2738 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2739 2740 /* Configure TxMAC parameters. */ 2741 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2742 reg |= TXMAC_THRESH_1_PKT; 2743 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2744 CSR_WRITE_4(sc, JME_TXMAC, reg); 2745 2746 /* 2747 * Configure Rx queue. 2748 * FIFO full threshold for transmitting Tx pause packet : 128T 2749 * FIFO threshold for processing next packet : 128QW 2750 * Rx queue 0 select 2751 * Max Rx DMA length : 128 2752 * Rx descriptor retry : 32 2753 * Rx descriptor retry time gap : 256ns 2754 * Don't receive runt/bad frame. 2755 */ 2756 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2757 #if 0 2758 /* 2759 * Since Rx FIFO size is 4K bytes, receiving frames larger 2760 * than 4K bytes will suffer from Rx FIFO overruns. So 2761 * decrease FIFO threshold to reduce the FIFO overruns for 2762 * frames larger than 4000 bytes. 2763 * For best performance of standard MTU sized frames use 2764 * maximum allowable FIFO threshold, 128QW. 2765 */ 2766 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) > 2767 JME_RX_FIFO_SIZE) 2768 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2769 else 2770 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2771 #else 2772 /* Improve PCI Express compatibility */ 2773 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2774 #endif 2775 sc->jme_rxcsr |= sc->jme_rx_dma_size; 2776 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2777 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2778 /* XXX TODO DROP_BAD */ 2779 2780 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2781 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 2782 2783 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 2784 2785 /* Set Rx descriptor counter. */ 2786 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt); 2787 2788 /* Set Rx ring address to the hardware. */ 2789 paddr = rdata->jme_rx_ring_paddr; 2790 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2791 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2792 } 2793 2794 /* Clear receive filter. */ 2795 CSR_WRITE_4(sc, JME_RXMAC, 0); 2796 2797 /* Set up the receive filter. */ 2798 jme_set_filter(sc); 2799 jme_set_vlan(sc); 2800 2801 /* 2802 * Disable all WOL bits as WOL can interfere normal Rx 2803 * operation. Also clear WOL detection status bits. 2804 */ 2805 reg = CSR_READ_4(sc, JME_PMCS); 2806 reg &= ~PMCS_WOL_ENB_MASK; 2807 CSR_WRITE_4(sc, JME_PMCS, reg); 2808 2809 /* 2810 * Pad 10bytes right before received frame. This will greatly 2811 * help Rx performance on strict-alignment architectures as 2812 * it does not need to copy the frame to align the payload. 2813 */ 2814 reg = CSR_READ_4(sc, JME_RXMAC); 2815 reg |= RXMAC_PAD_10BYTES; 2816 2817 if (ifp->if_capenable & IFCAP_RXCSUM) 2818 reg |= RXMAC_CSUM_ENB; 2819 CSR_WRITE_4(sc, JME_RXMAC, reg); 2820 2821 /* Configure general purpose reg0 */ 2822 reg = CSR_READ_4(sc, JME_GPREG0); 2823 reg &= ~GPREG0_PCC_UNIT_MASK; 2824 /* Set PCC timer resolution to micro-seconds unit. */ 2825 reg |= GPREG0_PCC_UNIT_US; 2826 /* 2827 * Disable all shadow register posting as we have to read 2828 * JME_INTR_STATUS register in jme_intr. Also it seems 2829 * that it's hard to synchronize interrupt status between 2830 * hardware and software with shadow posting due to 2831 * requirements of bus_dmamap_sync(9). 2832 */ 2833 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2834 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2835 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2836 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2837 /* Disable posting of DW0. */ 2838 reg &= ~GPREG0_POST_DW0_ENB; 2839 /* Clear PME message. */ 2840 reg &= ~GPREG0_PME_ENB; 2841 /* Set PHY address. */ 2842 reg &= ~GPREG0_PHY_ADDR_MASK; 2843 reg |= sc->jme_phyaddr; 2844 CSR_WRITE_4(sc, JME_GPREG0, reg); 2845 2846 /* Configure Tx queue 0 packet completion coalescing. */ 2847 jme_set_tx_coal(sc); 2848 2849 /* Configure Rx queues packet completion coalescing. */ 2850 jme_set_rx_coal(sc); 2851 2852 /* Configure shadow status block but don't enable posting. */ 2853 paddr = sc->jme_cdata.jme_ssb_block_paddr; 2854 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2855 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2856 2857 /* Disable Timer 1 and Timer 2. */ 2858 CSR_WRITE_4(sc, JME_TIMER1, 0); 2859 CSR_WRITE_4(sc, JME_TIMER2, 0); 2860 2861 /* Configure retry transmit period, retry limit value. */ 2862 CSR_WRITE_4(sc, JME_TXTRHD, 2863 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2864 TXTRHD_RT_PERIOD_MASK) | 2865 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2866 TXTRHD_RT_LIMIT_SHIFT)); 2867 2868 #ifdef IFPOLL_ENABLE 2869 if (!(ifp->if_flags & IFF_NPOLLING)) 2870 #endif 2871 /* Initialize the interrupt mask. */ 2872 jme_enable_intr(sc); 2873 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2874 2875 /* 2876 * Enabling Tx/Rx DMA engines and Rx queue processing is 2877 * done after detection of valid link in jme_miibus_statchg. 2878 */ 2879 sc->jme_has_link = FALSE; 2880 2881 /* Set the current media. */ 2882 mii = device_get_softc(sc->jme_miibus); 2883 mii_mediachg(mii); 2884 2885 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 2886 JME_TICK_CPUID); 2887 2888 ifp->if_flags |= IFF_RUNNING; 2889 ifq_clr_oactive(&ifp->if_snd); 2890 } 2891 2892 static void 2893 jme_stop(struct jme_softc *sc) 2894 { 2895 struct ifnet *ifp = &sc->arpcom.ac_if; 2896 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2897 struct jme_txdesc *txd; 2898 struct jme_rxdesc *rxd; 2899 struct jme_rxdata *rdata; 2900 int i, r; 2901 2902 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2903 2904 /* 2905 * Mark the interface down and cancel the watchdog timer. 2906 */ 2907 ifp->if_flags &= ~IFF_RUNNING; 2908 ifq_clr_oactive(&ifp->if_snd); 2909 ifp->if_timer = 0; 2910 2911 callout_stop(&sc->jme_tick_ch); 2912 sc->jme_has_link = FALSE; 2913 2914 /* 2915 * Disable interrupts. 2916 */ 2917 jme_disable_intr(sc); 2918 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2919 2920 /* Disable updating shadow status block. */ 2921 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2922 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2923 2924 /* Stop receiver, transmitter. */ 2925 jme_stop_rx(sc); 2926 jme_stop_tx(sc); 2927 2928 /* 2929 * Free partial finished RX segments 2930 */ 2931 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2932 rdata = &sc->jme_cdata.jme_rx_data[r]; 2933 if (rdata->jme_rxhead != NULL) 2934 m_freem(rdata->jme_rxhead); 2935 JME_RXCHAIN_RESET(rdata); 2936 } 2937 2938 /* 2939 * Free RX and TX mbufs still in the queues. 2940 */ 2941 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2942 rdata = &sc->jme_cdata.jme_rx_data[r]; 2943 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 2944 rxd = &rdata->jme_rxdesc[i]; 2945 if (rxd->rx_m != NULL) { 2946 bus_dmamap_unload(rdata->jme_rx_tag, 2947 rxd->rx_dmamap); 2948 m_freem(rxd->rx_m); 2949 rxd->rx_m = NULL; 2950 } 2951 } 2952 } 2953 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 2954 txd = &tdata->jme_txdesc[i]; 2955 if (txd->tx_m != NULL) { 2956 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2957 m_freem(txd->tx_m); 2958 txd->tx_m = NULL; 2959 txd->tx_ndesc = 0; 2960 } 2961 } 2962 } 2963 2964 static void 2965 jme_stop_tx(struct jme_softc *sc) 2966 { 2967 uint32_t reg; 2968 int i; 2969 2970 reg = CSR_READ_4(sc, JME_TXCSR); 2971 if ((reg & TXCSR_TX_ENB) == 0) 2972 return; 2973 reg &= ~TXCSR_TX_ENB; 2974 CSR_WRITE_4(sc, JME_TXCSR, reg); 2975 for (i = JME_TIMEOUT; i > 0; i--) { 2976 DELAY(1); 2977 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2978 break; 2979 } 2980 if (i == 0) 2981 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2982 } 2983 2984 static void 2985 jme_stop_rx(struct jme_softc *sc) 2986 { 2987 uint32_t reg; 2988 int i; 2989 2990 reg = CSR_READ_4(sc, JME_RXCSR); 2991 if ((reg & RXCSR_RX_ENB) == 0) 2992 return; 2993 reg &= ~RXCSR_RX_ENB; 2994 CSR_WRITE_4(sc, JME_RXCSR, reg); 2995 for (i = JME_TIMEOUT; i > 0; i--) { 2996 DELAY(1); 2997 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2998 break; 2999 } 3000 if (i == 0) 3001 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3002 } 3003 3004 static void 3005 jme_init_tx_ring(struct jme_txdata *tdata) 3006 { 3007 struct jme_txdesc *txd; 3008 int i; 3009 3010 tdata->jme_tx_prod = 0; 3011 tdata->jme_tx_cons = 0; 3012 tdata->jme_tx_cnt = 0; 3013 3014 bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata)); 3015 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 3016 txd = &tdata->jme_txdesc[i]; 3017 txd->tx_m = NULL; 3018 txd->tx_desc = &tdata->jme_tx_ring[i]; 3019 txd->tx_ndesc = 0; 3020 } 3021 } 3022 3023 static void 3024 jme_init_ssb(struct jme_softc *sc) 3025 { 3026 struct jme_chain_data *cd; 3027 3028 cd = &sc->jme_cdata; 3029 bzero(cd->jme_ssb_block, JME_SSB_SIZE); 3030 } 3031 3032 static int 3033 jme_init_rx_ring(struct jme_rxdata *rdata) 3034 { 3035 struct jme_rxdesc *rxd; 3036 int i; 3037 3038 KKASSERT(rdata->jme_rxhead == NULL && 3039 rdata->jme_rxtail == NULL && 3040 rdata->jme_rxlen == 0); 3041 rdata->jme_rx_cons = 0; 3042 3043 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata)); 3044 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3045 int error; 3046 3047 rxd = &rdata->jme_rxdesc[i]; 3048 rxd->rx_m = NULL; 3049 rxd->rx_desc = &rdata->jme_rx_ring[i]; 3050 error = jme_newbuf(rdata, rxd, 1); 3051 if (error) 3052 return error; 3053 } 3054 return 0; 3055 } 3056 3057 static int 3058 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init) 3059 { 3060 struct mbuf *m; 3061 bus_dma_segment_t segs; 3062 bus_dmamap_t map; 3063 int error, nsegs; 3064 3065 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3066 if (m == NULL) 3067 return ENOBUFS; 3068 /* 3069 * JMC250 has 64bit boundary alignment limitation so jme(4) 3070 * takes advantage of 10 bytes padding feature of hardware 3071 * in order not to copy entire frame to align IP header on 3072 * 32bit boundary. 3073 */ 3074 m->m_len = m->m_pkthdr.len = MCLBYTES; 3075 3076 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag, 3077 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs, 3078 BUS_DMA_NOWAIT); 3079 if (error) { 3080 m_freem(m); 3081 if (init) { 3082 if_printf(&rdata->jme_sc->arpcom.ac_if, 3083 "can't load RX mbuf\n"); 3084 } 3085 return error; 3086 } 3087 3088 if (rxd->rx_m != NULL) { 3089 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap, 3090 BUS_DMASYNC_POSTREAD); 3091 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap); 3092 } 3093 map = rxd->rx_dmamap; 3094 rxd->rx_dmamap = rdata->jme_rx_sparemap; 3095 rdata->jme_rx_sparemap = map; 3096 rxd->rx_m = m; 3097 rxd->rx_paddr = segs.ds_addr; 3098 3099 jme_setup_rxdesc(rxd); 3100 return 0; 3101 } 3102 3103 static void 3104 jme_set_vlan(struct jme_softc *sc) 3105 { 3106 struct ifnet *ifp = &sc->arpcom.ac_if; 3107 uint32_t reg; 3108 3109 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3110 3111 reg = CSR_READ_4(sc, JME_RXMAC); 3112 reg &= ~RXMAC_VLAN_ENB; 3113 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 3114 reg |= RXMAC_VLAN_ENB; 3115 CSR_WRITE_4(sc, JME_RXMAC, reg); 3116 } 3117 3118 static void 3119 jme_set_filter(struct jme_softc *sc) 3120 { 3121 struct ifnet *ifp = &sc->arpcom.ac_if; 3122 struct ifmultiaddr *ifma; 3123 uint32_t crc; 3124 uint32_t mchash[2]; 3125 uint32_t rxcfg; 3126 3127 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3128 3129 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3130 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3131 RXMAC_ALLMULTI); 3132 3133 /* 3134 * Always accept frames destined to our station address. 3135 * Always accept broadcast frames. 3136 */ 3137 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST; 3138 3139 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 3140 if (ifp->if_flags & IFF_PROMISC) 3141 rxcfg |= RXMAC_PROMISC; 3142 if (ifp->if_flags & IFF_ALLMULTI) 3143 rxcfg |= RXMAC_ALLMULTI; 3144 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3145 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3146 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3147 return; 3148 } 3149 3150 /* 3151 * Set up the multicast address filter by passing all multicast 3152 * addresses through a CRC generator, and then using the low-order 3153 * 6 bits as an index into the 64 bit multicast hash table. The 3154 * high order bits select the register, while the rest of the bits 3155 * select the bit within the register. 3156 */ 3157 rxcfg |= RXMAC_MULTICAST; 3158 bzero(mchash, sizeof(mchash)); 3159 3160 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3161 if (ifma->ifma_addr->sa_family != AF_LINK) 3162 continue; 3163 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3164 ifma->ifma_addr), ETHER_ADDR_LEN); 3165 3166 /* Just want the 6 least significant bits. */ 3167 crc &= 0x3f; 3168 3169 /* Set the corresponding bit in the hash table. */ 3170 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3171 } 3172 3173 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3174 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3175 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3176 } 3177 3178 static int 3179 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS) 3180 { 3181 struct jme_softc *sc = arg1; 3182 struct ifnet *ifp = &sc->arpcom.ac_if; 3183 int error, v; 3184 3185 ifnet_serialize_all(ifp); 3186 3187 v = sc->jme_tx_coal_to; 3188 error = sysctl_handle_int(oidp, &v, 0, req); 3189 if (error || req->newptr == NULL) 3190 goto back; 3191 3192 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) { 3193 error = EINVAL; 3194 goto back; 3195 } 3196 3197 if (v != sc->jme_tx_coal_to) { 3198 sc->jme_tx_coal_to = v; 3199 if (ifp->if_flags & IFF_RUNNING) 3200 jme_set_tx_coal(sc); 3201 } 3202 back: 3203 ifnet_deserialize_all(ifp); 3204 return error; 3205 } 3206 3207 static int 3208 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3209 { 3210 struct jme_softc *sc = arg1; 3211 struct ifnet *ifp = &sc->arpcom.ac_if; 3212 int error, v; 3213 3214 ifnet_serialize_all(ifp); 3215 3216 v = sc->jme_tx_coal_pkt; 3217 error = sysctl_handle_int(oidp, &v, 0, req); 3218 if (error || req->newptr == NULL) 3219 goto back; 3220 3221 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) { 3222 error = EINVAL; 3223 goto back; 3224 } 3225 3226 if (v != sc->jme_tx_coal_pkt) { 3227 sc->jme_tx_coal_pkt = v; 3228 if (ifp->if_flags & IFF_RUNNING) 3229 jme_set_tx_coal(sc); 3230 } 3231 back: 3232 ifnet_deserialize_all(ifp); 3233 return error; 3234 } 3235 3236 static int 3237 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS) 3238 { 3239 struct jme_softc *sc = arg1; 3240 struct ifnet *ifp = &sc->arpcom.ac_if; 3241 int error, v; 3242 3243 ifnet_serialize_all(ifp); 3244 3245 v = sc->jme_rx_coal_to; 3246 error = sysctl_handle_int(oidp, &v, 0, req); 3247 if (error || req->newptr == NULL) 3248 goto back; 3249 3250 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) { 3251 error = EINVAL; 3252 goto back; 3253 } 3254 3255 if (v != sc->jme_rx_coal_to) { 3256 sc->jme_rx_coal_to = v; 3257 if (ifp->if_flags & IFF_RUNNING) 3258 jme_set_rx_coal(sc); 3259 } 3260 back: 3261 ifnet_deserialize_all(ifp); 3262 return error; 3263 } 3264 3265 static int 3266 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3267 { 3268 struct jme_softc *sc = arg1; 3269 struct ifnet *ifp = &sc->arpcom.ac_if; 3270 int error, v; 3271 3272 ifnet_serialize_all(ifp); 3273 3274 v = sc->jme_rx_coal_pkt; 3275 error = sysctl_handle_int(oidp, &v, 0, req); 3276 if (error || req->newptr == NULL) 3277 goto back; 3278 3279 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) { 3280 error = EINVAL; 3281 goto back; 3282 } 3283 3284 if (v != sc->jme_rx_coal_pkt) { 3285 sc->jme_rx_coal_pkt = v; 3286 if (ifp->if_flags & IFF_RUNNING) 3287 jme_set_rx_coal(sc); 3288 } 3289 back: 3290 ifnet_deserialize_all(ifp); 3291 return error; 3292 } 3293 3294 static void 3295 jme_set_tx_coal(struct jme_softc *sc) 3296 { 3297 uint32_t reg; 3298 3299 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 3300 PCCTX_COAL_TO_MASK; 3301 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 3302 PCCTX_COAL_PKT_MASK; 3303 reg |= PCCTX_COAL_TXQ0; 3304 CSR_WRITE_4(sc, JME_PCCTX, reg); 3305 } 3306 3307 static void 3308 jme_set_rx_coal(struct jme_softc *sc) 3309 { 3310 uint32_t reg; 3311 int r; 3312 3313 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 3314 PCCRX_COAL_TO_MASK; 3315 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 3316 PCCRX_COAL_PKT_MASK; 3317 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) 3318 CSR_WRITE_4(sc, JME_PCCRX(r), reg); 3319 } 3320 3321 #ifdef IFPOLL_ENABLE 3322 3323 static void 3324 jme_npoll_status(struct ifnet *ifp) 3325 { 3326 struct jme_softc *sc = ifp->if_softc; 3327 uint32_t status; 3328 3329 ASSERT_SERIALIZED(&sc->jme_serialize); 3330 3331 status = CSR_READ_4(sc, JME_INTR_STATUS); 3332 if (status & INTR_RXQ_DESC_EMPTY) { 3333 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3334 jme_rx_restart(sc, status); 3335 } 3336 } 3337 3338 static void 3339 jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3340 { 3341 struct jme_rxdata *rdata = arg; 3342 3343 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3344 3345 jme_rxeof(rdata, cycle); 3346 } 3347 3348 static void 3349 jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3350 { 3351 struct jme_txdata *tdata = arg; 3352 3353 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3354 3355 jme_txeof(tdata); 3356 if (!ifq_is_empty(&ifp->if_snd)) 3357 if_devstart(ifp); 3358 } 3359 3360 static void 3361 jme_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3362 { 3363 struct jme_softc *sc = ifp->if_softc; 3364 3365 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3366 3367 if (info) { 3368 int i, off; 3369 3370 info->ifpi_status.status_func = jme_npoll_status; 3371 info->ifpi_status.serializer = &sc->jme_serialize; 3372 3373 off = sc->jme_npoll_txoff; 3374 KKASSERT(off <= ncpus2); 3375 info->ifpi_tx[off].poll_func = jme_npoll_tx; 3376 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data; 3377 info->ifpi_tx[off].serializer = 3378 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3379 ifq_set_cpuid(&ifp->if_snd, sc->jme_npoll_txoff); 3380 3381 off = sc->jme_npoll_rxoff; 3382 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3383 struct jme_rxdata *rdata = 3384 &sc->jme_cdata.jme_rx_data[i]; 3385 int idx = i + off; 3386 3387 info->ifpi_rx[idx].poll_func = jme_npoll_rx; 3388 info->ifpi_rx[idx].arg = rdata; 3389 info->ifpi_rx[idx].serializer = 3390 &rdata->jme_rx_serialize; 3391 } 3392 3393 if (ifp->if_flags & IFF_RUNNING) 3394 jme_disable_intr(sc); 3395 } else { 3396 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 3397 if (ifp->if_flags & IFF_RUNNING) 3398 jme_enable_intr(sc); 3399 } 3400 } 3401 3402 static int 3403 jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3404 { 3405 struct jme_softc *sc = (void *)arg1; 3406 struct ifnet *ifp = &sc->arpcom.ac_if; 3407 int error, off; 3408 3409 off = sc->jme_npoll_rxoff; 3410 error = sysctl_handle_int(oidp, &off, 0, req); 3411 if (error || req->newptr == NULL) 3412 return error; 3413 if (off < 0) 3414 return EINVAL; 3415 3416 ifnet_serialize_all(ifp); 3417 if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3418 error = EINVAL; 3419 } else { 3420 error = 0; 3421 sc->jme_npoll_rxoff = off; 3422 } 3423 ifnet_deserialize_all(ifp); 3424 3425 return error; 3426 } 3427 3428 static int 3429 jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3430 { 3431 struct jme_softc *sc = (void *)arg1; 3432 struct ifnet *ifp = &sc->arpcom.ac_if; 3433 int error, off; 3434 3435 off = sc->jme_npoll_txoff; 3436 error = sysctl_handle_int(oidp, &off, 0, req); 3437 if (error || req->newptr == NULL) 3438 return error; 3439 if (off < 0) 3440 return EINVAL; 3441 3442 ifnet_serialize_all(ifp); 3443 if (off >= ncpus2) { 3444 error = EINVAL; 3445 } else { 3446 error = 0; 3447 sc->jme_npoll_txoff = off; 3448 } 3449 ifnet_deserialize_all(ifp); 3450 3451 return error; 3452 } 3453 3454 #endif /* IFPOLL_ENABLE */ 3455 3456 static int 3457 jme_rxring_dma_alloc(struct jme_rxdata *rdata) 3458 { 3459 bus_dmamem_t dmem; 3460 int error, asize; 3461 3462 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN); 3463 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag, 3464 JME_RX_RING_ALIGN, 0, 3465 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3466 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3467 if (error) { 3468 device_printf(rdata->jme_sc->jme_dev, 3469 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx); 3470 return error; 3471 } 3472 rdata->jme_rx_ring_tag = dmem.dmem_tag; 3473 rdata->jme_rx_ring_map = dmem.dmem_map; 3474 rdata->jme_rx_ring = dmem.dmem_addr; 3475 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr; 3476 3477 return 0; 3478 } 3479 3480 static int 3481 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr) 3482 { 3483 if ((paddr & 0xffffffff) == 0) { 3484 /* 3485 * Don't allow lower 32bits of the RX buffer's 3486 * physical address to be 0, else it will break 3487 * hardware pending RSS information delivery 3488 * detection on RX path. 3489 */ 3490 return 1; 3491 } 3492 return 0; 3493 } 3494 3495 static int 3496 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata) 3497 { 3498 bus_addr_t lowaddr; 3499 int i, error; 3500 3501 lowaddr = BUS_SPACE_MAXADDR; 3502 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 3503 /* jme_rxbuf_dma_filter will be called */ 3504 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3505 } 3506 3507 /* Create tag for Rx buffers. */ 3508 error = bus_dma_tag_create( 3509 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */ 3510 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 3511 lowaddr, /* lowaddr */ 3512 BUS_SPACE_MAXADDR, /* highaddr */ 3513 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */ 3514 MCLBYTES, /* maxsize */ 3515 1, /* nsegments */ 3516 MCLBYTES, /* maxsegsize */ 3517 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */ 3518 &rdata->jme_rx_tag); 3519 if (error) { 3520 device_printf(rdata->jme_sc->jme_dev, 3521 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx); 3522 return error; 3523 } 3524 3525 /* Create DMA maps for Rx buffers. */ 3526 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3527 &rdata->jme_rx_sparemap); 3528 if (error) { 3529 device_printf(rdata->jme_sc->jme_dev, 3530 "could not create %dth spare Rx dmamap.\n", 3531 rdata->jme_rx_idx); 3532 bus_dma_tag_destroy(rdata->jme_rx_tag); 3533 rdata->jme_rx_tag = NULL; 3534 return error; 3535 } 3536 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3537 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i]; 3538 3539 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3540 &rxd->rx_dmamap); 3541 if (error) { 3542 int j; 3543 3544 device_printf(rdata->jme_sc->jme_dev, 3545 "could not create %dth Rx dmamap " 3546 "for %dth RX ring.\n", i, rdata->jme_rx_idx); 3547 3548 for (j = 0; j < i; ++j) { 3549 rxd = &rdata->jme_rxdesc[j]; 3550 bus_dmamap_destroy(rdata->jme_rx_tag, 3551 rxd->rx_dmamap); 3552 } 3553 bus_dmamap_destroy(rdata->jme_rx_tag, 3554 rdata->jme_rx_sparemap); 3555 bus_dma_tag_destroy(rdata->jme_rx_tag); 3556 rdata->jme_rx_tag = NULL; 3557 return error; 3558 } 3559 } 3560 return 0; 3561 } 3562 3563 static void 3564 jme_rx_intr(struct jme_softc *sc, uint32_t status) 3565 { 3566 int r; 3567 3568 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3569 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3570 3571 if (status & rdata->jme_rx_coal) { 3572 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3573 jme_rxeof(rdata, -1); 3574 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3575 } 3576 } 3577 } 3578 3579 static void 3580 jme_enable_rss(struct jme_softc *sc) 3581 { 3582 uint32_t rssc, ind; 3583 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE]; 3584 int i; 3585 3586 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 || 3587 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4, 3588 ("%s: invalid # of RX rings (%d)", 3589 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt)); 3590 3591 rssc = RSSC_HASH_64_ENTRY; 3592 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP; 3593 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1; 3594 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc); 3595 CSR_WRITE_4(sc, JME_RSSC, rssc); 3596 3597 toeplitz_get_key(key, sizeof(key)); 3598 for (i = 0; i < RSSKEY_NREGS; ++i) { 3599 uint32_t keyreg; 3600 3601 keyreg = RSSKEY_REGVAL(key, i); 3602 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x, reg 0x%08x\n", 3603 i, keyreg, RSSKEY_REG(RSSKEY_NREGS - 1 - i)); 3604 3605 CSR_WRITE_4(sc, RSSKEY_REG(RSSKEY_NREGS - 1 - i), keyreg); 3606 } 3607 3608 /* 3609 * Create redirect table in following fashion: 3610 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3611 */ 3612 ind = 0; 3613 for (i = 0; i < RSSTBL_REGSIZE; ++i) { 3614 int q; 3615 3616 q = i % sc->jme_cdata.jme_rx_ring_cnt; 3617 ind |= q << (i * 8); 3618 } 3619 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind); 3620 3621 for (i = 0; i < RSSTBL_NREGS; ++i) 3622 CSR_WRITE_4(sc, RSSTBL_REG(i), ind); 3623 } 3624 3625 static void 3626 jme_disable_rss(struct jme_softc *sc) 3627 { 3628 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 3629 } 3630 3631 static void 3632 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3633 { 3634 struct jme_softc *sc = ifp->if_softc; 3635 3636 ifnet_serialize_array_enter(sc->jme_serialize_arr, 3637 sc->jme_serialize_cnt, slz); 3638 } 3639 3640 static void 3641 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3642 { 3643 struct jme_softc *sc = ifp->if_softc; 3644 3645 ifnet_serialize_array_exit(sc->jme_serialize_arr, 3646 sc->jme_serialize_cnt, slz); 3647 } 3648 3649 static int 3650 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3651 { 3652 struct jme_softc *sc = ifp->if_softc; 3653 3654 return ifnet_serialize_array_try(sc->jme_serialize_arr, 3655 sc->jme_serialize_cnt, slz); 3656 } 3657 3658 #ifdef INVARIANTS 3659 3660 static void 3661 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3662 boolean_t serialized) 3663 { 3664 struct jme_softc *sc = ifp->if_softc; 3665 3666 ifnet_serialize_array_assert(sc->jme_serialize_arr, 3667 sc->jme_serialize_cnt, slz, serialized); 3668 } 3669 3670 #endif /* INVARIANTS */ 3671 3672 static void 3673 jme_msix_try_alloc(device_t dev) 3674 { 3675 struct jme_softc *sc = device_get_softc(dev); 3676 struct jme_msix_data *msix; 3677 int error, i, r, msix_enable, msix_count; 3678 int offset, offset_def; 3679 3680 msix_count = JME_MSIXCNT(sc->jme_cdata.jme_rx_ring_cnt); 3681 KKASSERT(msix_count <= JME_NMSIX); 3682 3683 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable); 3684 3685 /* 3686 * We leave the 1st MSI-X vector unused, so we 3687 * actually need msix_count + 1 MSI-X vectors. 3688 */ 3689 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1)) 3690 return; 3691 3692 for (i = 0; i < msix_count; ++i) 3693 sc->jme_msix[i].jme_msix_rid = -1; 3694 3695 i = 0; 3696 3697 /* 3698 * Setup status MSI-X 3699 */ 3700 3701 msix = &sc->jme_msix[i++]; 3702 msix->jme_msix_cpuid = 0; 3703 msix->jme_msix_arg = sc; 3704 msix->jme_msix_func = jme_msix_status; 3705 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3706 msix->jme_msix_intrs |= 3707 sc->jme_cdata.jme_rx_data[r].jme_rx_empty; 3708 } 3709 msix->jme_msix_serialize = &sc->jme_serialize; 3710 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s sts", 3711 device_get_nameunit(dev)); 3712 3713 /* 3714 * Setup TX MSI-X 3715 */ 3716 3717 offset_def = device_get_unit(dev) % ncpus2; 3718 offset = device_getenv_int(dev, "msix.txoff", offset_def); 3719 if (offset >= ncpus2) { 3720 device_printf(dev, "invalid msix.txoff %d, use %d\n", 3721 offset, offset_def); 3722 offset = offset_def; 3723 } 3724 3725 msix = &sc->jme_msix[i++]; 3726 msix->jme_msix_cpuid = offset; 3727 sc->jme_tx_cpuid = msix->jme_msix_cpuid; 3728 msix->jme_msix_arg = &sc->jme_cdata.jme_tx_data; 3729 msix->jme_msix_func = jme_msix_tx; 3730 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO; 3731 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3732 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx", 3733 device_get_nameunit(dev)); 3734 3735 /* 3736 * Setup RX MSI-X 3737 */ 3738 3739 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 3740 offset = 0; 3741 } else { 3742 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 3743 device_get_unit(dev)) % ncpus2; 3744 3745 offset = device_getenv_int(dev, "msix.rxoff", offset_def); 3746 if (offset >= ncpus2 || 3747 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3748 device_printf(dev, "invalid msix.rxoff %d, use %d\n", 3749 offset, offset_def); 3750 offset = offset_def; 3751 } 3752 } 3753 3754 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3755 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3756 3757 msix = &sc->jme_msix[i++]; 3758 msix->jme_msix_cpuid = r + offset; 3759 KKASSERT(msix->jme_msix_cpuid < ncpus2); 3760 msix->jme_msix_arg = rdata; 3761 msix->jme_msix_func = jme_msix_rx; 3762 msix->jme_msix_intrs = rdata->jme_rx_coal; 3763 msix->jme_msix_serialize = &rdata->jme_rx_serialize; 3764 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), 3765 "%s rx%d", device_get_nameunit(dev), r); 3766 } 3767 3768 KKASSERT(i == msix_count); 3769 3770 error = pci_setup_msix(dev); 3771 if (error) 3772 return; 3773 3774 /* Setup jme_msix_cnt early, so we could cleanup */ 3775 sc->jme_msix_cnt = msix_count; 3776 3777 for (i = 0; i < msix_count; ++i) { 3778 msix = &sc->jme_msix[i]; 3779 3780 msix->jme_msix_vector = i + 1; 3781 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector, 3782 &msix->jme_msix_rid, msix->jme_msix_cpuid); 3783 if (error) 3784 goto back; 3785 3786 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3787 &msix->jme_msix_rid, RF_ACTIVE); 3788 if (msix->jme_msix_res == NULL) { 3789 error = ENOMEM; 3790 goto back; 3791 } 3792 } 3793 3794 for (i = 0; i < JME_INTR_CNT; ++i) { 3795 uint32_t intr_mask = (1 << i); 3796 int x; 3797 3798 if ((JME_INTRS & intr_mask) == 0) 3799 continue; 3800 3801 for (x = 0; x < msix_count; ++x) { 3802 msix = &sc->jme_msix[x]; 3803 if (msix->jme_msix_intrs & intr_mask) { 3804 int reg, shift; 3805 3806 reg = i / JME_MSINUM_FACTOR; 3807 KKASSERT(reg < JME_MSINUM_CNT); 3808 3809 shift = (i % JME_MSINUM_FACTOR) * 4; 3810 3811 sc->jme_msinum[reg] |= 3812 (msix->jme_msix_vector << shift); 3813 3814 break; 3815 } 3816 } 3817 } 3818 3819 if (bootverbose) { 3820 for (i = 0; i < JME_MSINUM_CNT; ++i) { 3821 device_printf(dev, "MSINUM%d: %#x\n", i, 3822 sc->jme_msinum[i]); 3823 } 3824 } 3825 3826 pci_enable_msix(dev); 3827 sc->jme_irq_type = PCI_INTR_TYPE_MSIX; 3828 3829 back: 3830 if (error) 3831 jme_msix_free(dev); 3832 } 3833 3834 static int 3835 jme_intr_alloc(device_t dev) 3836 { 3837 struct jme_softc *sc = device_get_softc(dev); 3838 u_int irq_flags; 3839 3840 jme_msix_try_alloc(dev); 3841 3842 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3843 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable, 3844 &sc->jme_irq_rid, &irq_flags); 3845 3846 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3847 &sc->jme_irq_rid, irq_flags); 3848 if (sc->jme_irq_res == NULL) { 3849 device_printf(dev, "can't allocate irq\n"); 3850 return ENXIO; 3851 } 3852 sc->jme_tx_cpuid = rman_get_cpuid(sc->jme_irq_res); 3853 } 3854 return 0; 3855 } 3856 3857 static void 3858 jme_msix_free(device_t dev) 3859 { 3860 struct jme_softc *sc = device_get_softc(dev); 3861 int i; 3862 3863 KKASSERT(sc->jme_msix_cnt > 1); 3864 3865 for (i = 0; i < sc->jme_msix_cnt; ++i) { 3866 struct jme_msix_data *msix = &sc->jme_msix[i]; 3867 3868 if (msix->jme_msix_res != NULL) { 3869 bus_release_resource(dev, SYS_RES_IRQ, 3870 msix->jme_msix_rid, msix->jme_msix_res); 3871 msix->jme_msix_res = NULL; 3872 } 3873 if (msix->jme_msix_rid >= 0) { 3874 pci_release_msix_vector(dev, msix->jme_msix_rid); 3875 msix->jme_msix_rid = -1; 3876 } 3877 } 3878 pci_teardown_msix(dev); 3879 } 3880 3881 static void 3882 jme_intr_free(device_t dev) 3883 { 3884 struct jme_softc *sc = device_get_softc(dev); 3885 3886 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3887 if (sc->jme_irq_res != NULL) { 3888 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid, 3889 sc->jme_irq_res); 3890 } 3891 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI) 3892 pci_release_msi(dev); 3893 } else { 3894 jme_msix_free(dev); 3895 } 3896 } 3897 3898 static void 3899 jme_msix_tx(void *xtdata) 3900 { 3901 struct jme_txdata *tdata = xtdata; 3902 struct jme_softc *sc = tdata->jme_sc; 3903 struct ifnet *ifp = &sc->arpcom.ac_if; 3904 3905 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3906 3907 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3908 3909 CSR_WRITE_4(sc, JME_INTR_STATUS, 3910 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP); 3911 3912 if (ifp->if_flags & IFF_RUNNING) { 3913 jme_txeof(tdata); 3914 if (!ifq_is_empty(&ifp->if_snd)) 3915 if_devstart(ifp); 3916 } 3917 3918 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3919 } 3920 3921 static void 3922 jme_msix_rx(void *xrdata) 3923 { 3924 struct jme_rxdata *rdata = xrdata; 3925 struct jme_softc *sc = rdata->jme_sc; 3926 struct ifnet *ifp = &sc->arpcom.ac_if; 3927 3928 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3929 3930 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, rdata->jme_rx_coal); 3931 3932 CSR_WRITE_4(sc, JME_INTR_STATUS, 3933 rdata->jme_rx_coal | rdata->jme_rx_comp); 3934 3935 if (ifp->if_flags & IFF_RUNNING) 3936 jme_rxeof(rdata, -1); 3937 3938 CSR_WRITE_4(sc, JME_INTR_MASK_SET, rdata->jme_rx_coal); 3939 } 3940 3941 static void 3942 jme_msix_status(void *xsc) 3943 { 3944 struct jme_softc *sc = xsc; 3945 struct ifnet *ifp = &sc->arpcom.ac_if; 3946 uint32_t status; 3947 3948 ASSERT_SERIALIZED(&sc->jme_serialize); 3949 3950 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_RXQ_DESC_EMPTY); 3951 3952 status = CSR_READ_4(sc, JME_INTR_STATUS); 3953 3954 if (status & INTR_RXQ_DESC_EMPTY) { 3955 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3956 if (ifp->if_flags & IFF_RUNNING) 3957 jme_rx_restart(sc, status); 3958 } 3959 3960 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_RXQ_DESC_EMPTY); 3961 } 3962 3963 static void 3964 jme_rx_restart(struct jme_softc *sc, uint32_t status) 3965 { 3966 int i; 3967 3968 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3969 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 3970 3971 if (status & rdata->jme_rx_empty) { 3972 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3973 jme_rxeof(rdata, -1); 3974 #ifdef JME_RSS_DEBUG 3975 rdata->jme_rx_emp++; 3976 #endif 3977 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3978 } 3979 } 3980 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 3981 RXCSR_RXQ_START); 3982 } 3983 3984 static void 3985 jme_set_msinum(struct jme_softc *sc) 3986 { 3987 int i; 3988 3989 for (i = 0; i < JME_MSINUM_CNT; ++i) 3990 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]); 3991 } 3992 3993 static int 3994 jme_intr_setup(device_t dev) 3995 { 3996 struct jme_softc *sc = device_get_softc(dev); 3997 int error; 3998 3999 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 4000 return jme_msix_setup(dev); 4001 4002 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, 4003 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize); 4004 if (error) { 4005 device_printf(dev, "could not set up interrupt handler.\n"); 4006 return error; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static void 4013 jme_intr_teardown(device_t dev) 4014 { 4015 struct jme_softc *sc = device_get_softc(dev); 4016 4017 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 4018 jme_msix_teardown(dev, sc->jme_msix_cnt); 4019 else 4020 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle); 4021 } 4022 4023 static int 4024 jme_msix_setup(device_t dev) 4025 { 4026 struct jme_softc *sc = device_get_softc(dev); 4027 int x; 4028 4029 for (x = 0; x < sc->jme_msix_cnt; ++x) { 4030 struct jme_msix_data *msix = &sc->jme_msix[x]; 4031 int error; 4032 4033 error = bus_setup_intr_descr(dev, msix->jme_msix_res, 4034 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg, 4035 &msix->jme_msix_handle, msix->jme_msix_serialize, 4036 msix->jme_msix_desc); 4037 if (error) { 4038 device_printf(dev, "could not set up %s " 4039 "interrupt handler.\n", msix->jme_msix_desc); 4040 jme_msix_teardown(dev, x); 4041 return error; 4042 } 4043 } 4044 return 0; 4045 } 4046 4047 static void 4048 jme_msix_teardown(device_t dev, int msix_count) 4049 { 4050 struct jme_softc *sc = device_get_softc(dev); 4051 int x; 4052 4053 for (x = 0; x < msix_count; ++x) { 4054 struct jme_msix_data *msix = &sc->jme_msix[x]; 4055 4056 bus_teardown_intr(dev, msix->jme_msix_res, 4057 msix->jme_msix_handle); 4058 } 4059 } 4060 4061 static void 4062 jme_serialize_skipmain(struct jme_softc *sc) 4063 { 4064 lwkt_serialize_array_enter(sc->jme_serialize_arr, 4065 sc->jme_serialize_cnt, 1); 4066 } 4067 4068 static void 4069 jme_deserialize_skipmain(struct jme_softc *sc) 4070 { 4071 lwkt_serialize_array_exit(sc->jme_serialize_arr, 4072 sc->jme_serialize_cnt, 1); 4073 } 4074 4075 static void 4076 jme_enable_intr(struct jme_softc *sc) 4077 { 4078 int i; 4079 4080 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4081 lwkt_serialize_handler_enable(sc->jme_serialize_arr[i]); 4082 4083 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 4084 } 4085 4086 static void 4087 jme_disable_intr(struct jme_softc *sc) 4088 { 4089 int i; 4090 4091 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 4092 4093 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4094 lwkt_serialize_handler_disable(sc->jme_serialize_arr[i]); 4095 } 4096