1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $ 28 */ 29 30 #include "opt_ifpoll.h" 31 #include "opt_jme.h" 32 33 #include <sys/param.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/interrupt.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/serialize.h> 42 #include <sys/serialize2.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/bpf.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_poll.h> 54 #include <net/ifq_var.h> 55 #include <net/toeplitz.h> 56 #include <net/toeplitz2.h> 57 #include <net/vlan/if_vlan_var.h> 58 #include <net/vlan/if_vlan_ether.h> 59 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/netif/mii_layer/miivar.h> 64 #include <dev/netif/mii_layer/jmphyreg.h> 65 66 #include <bus/pci/pcireg.h> 67 #include <bus/pci/pcivar.h> 68 #include <bus/pci/pcidevs.h> 69 70 #include <dev/netif/jme/if_jmereg.h> 71 #include <dev/netif/jme/if_jmevar.h> 72 73 #include "miibus_if.h" 74 75 #define JME_TICK_CPUID 0 /* DO NOT CHANGE THIS */ 76 77 #define JME_TX_SERIALIZE 1 78 #define JME_RX_SERIALIZE 2 79 80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 81 82 #ifdef JME_RSS_DEBUG 83 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \ 84 do { \ 85 if ((sc)->jme_rss_debug >= (lvl)) \ 86 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \ 87 } while (0) 88 #else /* !JME_RSS_DEBUG */ 89 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 90 #endif /* JME_RSS_DEBUG */ 91 92 static int jme_probe(device_t); 93 static int jme_attach(device_t); 94 static int jme_detach(device_t); 95 static int jme_shutdown(device_t); 96 static int jme_suspend(device_t); 97 static int jme_resume(device_t); 98 99 static int jme_miibus_readreg(device_t, int, int); 100 static int jme_miibus_writereg(device_t, int, int, int); 101 static void jme_miibus_statchg(device_t); 102 103 static void jme_init(void *); 104 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 105 static void jme_start(struct ifnet *, struct ifaltq_subque *); 106 static void jme_watchdog(struct ifnet *); 107 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 108 static int jme_mediachange(struct ifnet *); 109 #ifdef IFPOLL_ENABLE 110 static void jme_npoll(struct ifnet *, struct ifpoll_info *); 111 static void jme_npoll_status(struct ifnet *); 112 static void jme_npoll_rx(struct ifnet *, void *, int); 113 static void jme_npoll_tx(struct ifnet *, void *, int); 114 #endif 115 static void jme_serialize(struct ifnet *, enum ifnet_serialize); 116 static void jme_deserialize(struct ifnet *, enum ifnet_serialize); 117 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize); 118 #ifdef INVARIANTS 119 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize, 120 boolean_t); 121 #endif 122 123 static void jme_intr(void *); 124 static void jme_msix_tx(void *); 125 static void jme_msix_rx(void *); 126 static void jme_msix_status(void *); 127 static void jme_txeof(struct jme_txdata *); 128 static void jme_rxeof(struct jme_rxdata *, int); 129 static void jme_rx_intr(struct jme_softc *, uint32_t); 130 static void jme_enable_intr(struct jme_softc *); 131 static void jme_disable_intr(struct jme_softc *); 132 static void jme_rx_restart(struct jme_softc *, uint32_t); 133 134 static int jme_msix_setup(device_t); 135 static void jme_msix_teardown(device_t, int); 136 static int jme_intr_setup(device_t); 137 static void jme_intr_teardown(device_t); 138 static void jme_msix_try_alloc(device_t); 139 static void jme_msix_free(device_t); 140 static int jme_intr_alloc(device_t); 141 static void jme_intr_free(device_t); 142 static int jme_dma_alloc(struct jme_softc *); 143 static void jme_dma_free(struct jme_softc *); 144 static int jme_init_rx_ring(struct jme_rxdata *); 145 static void jme_init_tx_ring(struct jme_txdata *); 146 static void jme_init_ssb(struct jme_softc *); 147 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int); 148 static int jme_encap(struct jme_txdata *, struct mbuf **, int *); 149 static void jme_rxpkt(struct jme_rxdata *); 150 static int jme_rxring_dma_alloc(struct jme_rxdata *); 151 static int jme_rxbuf_dma_alloc(struct jme_rxdata *); 152 static int jme_rxbuf_dma_filter(void *, bus_addr_t); 153 154 static void jme_tick(void *); 155 static void jme_stop(struct jme_softc *); 156 static void jme_reset(struct jme_softc *); 157 static void jme_set_msinum(struct jme_softc *); 158 static void jme_set_vlan(struct jme_softc *); 159 static void jme_set_filter(struct jme_softc *); 160 static void jme_stop_tx(struct jme_softc *); 161 static void jme_stop_rx(struct jme_softc *); 162 static void jme_mac_config(struct jme_softc *); 163 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]); 164 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]); 165 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 166 #ifdef notyet 167 static void jme_setwol(struct jme_softc *); 168 static void jme_setlinkspeed(struct jme_softc *); 169 #endif 170 static void jme_set_tx_coal(struct jme_softc *); 171 static void jme_set_rx_coal(struct jme_softc *); 172 static void jme_enable_rss(struct jme_softc *); 173 static void jme_disable_rss(struct jme_softc *); 174 static void jme_serialize_skipmain(struct jme_softc *); 175 static void jme_deserialize_skipmain(struct jme_softc *); 176 177 static void jme_sysctl_node(struct jme_softc *); 178 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS); 179 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 180 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS); 181 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 182 #ifdef IFPOLL_ENABLE 183 static int jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 184 static int jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 185 #endif 186 187 /* 188 * Devices supported by this driver. 189 */ 190 static const struct jme_dev { 191 uint16_t jme_vendorid; 192 uint16_t jme_deviceid; 193 uint32_t jme_caps; 194 const char *jme_name; 195 } jme_devs[] = { 196 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250, 197 JME_CAP_JUMBO, 198 "JMicron Inc, JMC250 Gigabit Ethernet" }, 199 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260, 200 JME_CAP_FASTETH, 201 "JMicron Inc, JMC260 Fast Ethernet" }, 202 { 0, 0, 0, NULL } 203 }; 204 205 static device_method_t jme_methods[] = { 206 /* Device interface. */ 207 DEVMETHOD(device_probe, jme_probe), 208 DEVMETHOD(device_attach, jme_attach), 209 DEVMETHOD(device_detach, jme_detach), 210 DEVMETHOD(device_shutdown, jme_shutdown), 211 DEVMETHOD(device_suspend, jme_suspend), 212 DEVMETHOD(device_resume, jme_resume), 213 214 /* Bus interface. */ 215 DEVMETHOD(bus_print_child, bus_generic_print_child), 216 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 217 218 /* MII interface. */ 219 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 220 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 221 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 222 223 { NULL, NULL } 224 }; 225 226 static driver_t jme_driver = { 227 "jme", 228 jme_methods, 229 sizeof(struct jme_softc) 230 }; 231 232 static devclass_t jme_devclass; 233 234 DECLARE_DUMMY_MODULE(if_jme); 235 MODULE_DEPEND(if_jme, miibus, 1, 1, 1); 236 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL); 237 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL); 238 239 static const struct { 240 uint32_t jme_coal; 241 uint32_t jme_comp; 242 uint32_t jme_empty; 243 } jme_rx_status[JME_NRXRING_MAX] = { 244 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP, 245 INTR_RXQ0_DESC_EMPTY }, 246 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP, 247 INTR_RXQ1_DESC_EMPTY }, 248 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP, 249 INTR_RXQ2_DESC_EMPTY }, 250 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP, 251 INTR_RXQ3_DESC_EMPTY } 252 }; 253 254 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF; 255 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF; 256 static int jme_rx_ring_count = 0; 257 static int jme_msi_enable = 1; 258 static int jme_msix_enable = 1; 259 260 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count); 261 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count); 262 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count); 263 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable); 264 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable); 265 266 static __inline void 267 jme_setup_rxdesc(struct jme_rxdesc *rxd) 268 { 269 struct jme_desc *desc; 270 271 desc = rxd->rx_desc; 272 desc->buflen = htole32(MCLBYTES); 273 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr)); 274 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr)); 275 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 276 } 277 278 /* 279 * Read a PHY register on the MII of the JMC250. 280 */ 281 static int 282 jme_miibus_readreg(device_t dev, int phy, int reg) 283 { 284 struct jme_softc *sc = device_get_softc(dev); 285 uint32_t val; 286 int i; 287 288 /* For FPGA version, PHY address 0 should be ignored. */ 289 if (sc->jme_caps & JME_CAP_FPGA) { 290 if (phy == 0) 291 return (0); 292 } else { 293 if (sc->jme_phyaddr != phy) 294 return (0); 295 } 296 297 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 298 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 299 300 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 301 DELAY(1); 302 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 303 break; 304 } 305 if (i == 0) { 306 device_printf(sc->jme_dev, "phy read timeout: " 307 "phy %d, reg %d\n", phy, reg); 308 return (0); 309 } 310 311 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 312 } 313 314 /* 315 * Write a PHY register on the MII of the JMC250. 316 */ 317 static int 318 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 319 { 320 struct jme_softc *sc = device_get_softc(dev); 321 int i; 322 323 /* For FPGA version, PHY address 0 should be ignored. */ 324 if (sc->jme_caps & JME_CAP_FPGA) { 325 if (phy == 0) 326 return (0); 327 } else { 328 if (sc->jme_phyaddr != phy) 329 return (0); 330 } 331 332 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 333 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 334 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 335 336 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 337 DELAY(1); 338 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 339 break; 340 } 341 if (i == 0) { 342 device_printf(sc->jme_dev, "phy write timeout: " 343 "phy %d, reg %d\n", phy, reg); 344 } 345 346 return (0); 347 } 348 349 /* 350 * Callback from MII layer when media changes. 351 */ 352 static void 353 jme_miibus_statchg(device_t dev) 354 { 355 struct jme_softc *sc = device_get_softc(dev); 356 struct ifnet *ifp = &sc->arpcom.ac_if; 357 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 358 struct mii_data *mii; 359 struct jme_txdesc *txd; 360 bus_addr_t paddr; 361 int i, r; 362 363 if (sc->jme_in_tick) 364 jme_serialize_skipmain(sc); 365 ASSERT_IFNET_SERIALIZED_ALL(ifp); 366 367 if ((ifp->if_flags & IFF_RUNNING) == 0) 368 goto done; 369 370 mii = device_get_softc(sc->jme_miibus); 371 372 sc->jme_has_link = FALSE; 373 if ((mii->mii_media_status & IFM_AVALID) != 0) { 374 switch (IFM_SUBTYPE(mii->mii_media_active)) { 375 case IFM_10_T: 376 case IFM_100_TX: 377 sc->jme_has_link = TRUE; 378 break; 379 case IFM_1000_T: 380 if (sc->jme_caps & JME_CAP_FASTETH) 381 break; 382 sc->jme_has_link = TRUE; 383 break; 384 default: 385 break; 386 } 387 } 388 389 /* 390 * Disabling Rx/Tx MACs have a side-effect of resetting 391 * JME_TXNDA/JME_RXNDA register to the first address of 392 * Tx/Rx descriptor address. So driver should reset its 393 * internal procucer/consumer pointer and reclaim any 394 * allocated resources. Note, just saving the value of 395 * JME_TXNDA and JME_RXNDA registers before stopping MAC 396 * and restoring JME_TXNDA/JME_RXNDA register is not 397 * sufficient to make sure correct MAC state because 398 * stopping MAC operation can take a while and hardware 399 * might have updated JME_TXNDA/JME_RXNDA registers 400 * during the stop operation. 401 */ 402 403 /* Disable interrupts */ 404 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 405 406 /* Stop driver */ 407 ifp->if_flags &= ~IFF_RUNNING; 408 ifq_clr_oactive(&ifp->if_snd); 409 ifp->if_timer = 0; 410 callout_stop(&sc->jme_tick_ch); 411 412 /* Stop receiver/transmitter. */ 413 jme_stop_rx(sc); 414 jme_stop_tx(sc); 415 416 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 417 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 418 419 jme_rxeof(rdata, -1); 420 if (rdata->jme_rxhead != NULL) 421 m_freem(rdata->jme_rxhead); 422 JME_RXCHAIN_RESET(rdata); 423 424 /* 425 * Reuse configured Rx descriptors and reset 426 * procuder/consumer index. 427 */ 428 rdata->jme_rx_cons = 0; 429 } 430 if (JME_ENABLE_HWRSS(sc)) 431 jme_enable_rss(sc); 432 else 433 jme_disable_rss(sc); 434 435 jme_txeof(tdata); 436 if (tdata->jme_tx_cnt != 0) { 437 /* Remove queued packets for transmit. */ 438 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 439 txd = &tdata->jme_txdesc[i]; 440 if (txd->tx_m != NULL) { 441 bus_dmamap_unload( tdata->jme_tx_tag, 442 txd->tx_dmamap); 443 m_freem(txd->tx_m); 444 txd->tx_m = NULL; 445 txd->tx_ndesc = 0; 446 IFNET_STAT_INC(ifp, oerrors, 1); 447 } 448 } 449 } 450 jme_init_tx_ring(tdata); 451 452 /* Initialize shadow status block. */ 453 jme_init_ssb(sc); 454 455 /* Program MAC with resolved speed/duplex/flow-control. */ 456 if (sc->jme_has_link) { 457 jme_mac_config(sc); 458 459 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 460 461 /* Set Tx ring address to the hardware. */ 462 paddr = tdata->jme_tx_ring_paddr; 463 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 464 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 465 466 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 467 CSR_WRITE_4(sc, JME_RXCSR, 468 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 469 470 /* Set Rx ring address to the hardware. */ 471 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr; 472 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 473 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 474 } 475 476 /* Restart receiver/transmitter. */ 477 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 478 RXCSR_RXQ_START); 479 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 480 } 481 482 ifp->if_flags |= IFF_RUNNING; 483 ifq_clr_oactive(&ifp->if_snd); 484 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 485 JME_TICK_CPUID); 486 487 #ifdef IFPOLL_ENABLE 488 if (!(ifp->if_flags & IFF_NPOLLING)) 489 #endif 490 /* Reenable interrupts. */ 491 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 492 493 done: 494 if (sc->jme_in_tick) 495 jme_deserialize_skipmain(sc); 496 } 497 498 /* 499 * Get the current interface media status. 500 */ 501 static void 502 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 503 { 504 struct jme_softc *sc = ifp->if_softc; 505 struct mii_data *mii = device_get_softc(sc->jme_miibus); 506 507 ASSERT_IFNET_SERIALIZED_ALL(ifp); 508 509 mii_pollstat(mii); 510 ifmr->ifm_status = mii->mii_media_status; 511 ifmr->ifm_active = mii->mii_media_active; 512 } 513 514 /* 515 * Set hardware to newly-selected media. 516 */ 517 static int 518 jme_mediachange(struct ifnet *ifp) 519 { 520 struct jme_softc *sc = ifp->if_softc; 521 struct mii_data *mii = device_get_softc(sc->jme_miibus); 522 int error; 523 524 ASSERT_IFNET_SERIALIZED_ALL(ifp); 525 526 if (mii->mii_instance != 0) { 527 struct mii_softc *miisc; 528 529 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 530 mii_phy_reset(miisc); 531 } 532 error = mii_mediachg(mii); 533 534 return (error); 535 } 536 537 static int 538 jme_probe(device_t dev) 539 { 540 const struct jme_dev *sp; 541 uint16_t vid, did; 542 543 vid = pci_get_vendor(dev); 544 did = pci_get_device(dev); 545 for (sp = jme_devs; sp->jme_name != NULL; ++sp) { 546 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) { 547 struct jme_softc *sc = device_get_softc(dev); 548 549 sc->jme_caps = sp->jme_caps; 550 device_set_desc(dev, sp->jme_name); 551 return (0); 552 } 553 } 554 return (ENXIO); 555 } 556 557 static int 558 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 559 { 560 uint32_t reg; 561 int i; 562 563 *val = 0; 564 for (i = JME_TIMEOUT; i > 0; i--) { 565 reg = CSR_READ_4(sc, JME_SMBCSR); 566 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 567 break; 568 DELAY(1); 569 } 570 571 if (i == 0) { 572 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 573 return (ETIMEDOUT); 574 } 575 576 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 577 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 578 for (i = JME_TIMEOUT; i > 0; i--) { 579 DELAY(1); 580 reg = CSR_READ_4(sc, JME_SMBINTF); 581 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 582 break; 583 } 584 585 if (i == 0) { 586 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 587 return (ETIMEDOUT); 588 } 589 590 reg = CSR_READ_4(sc, JME_SMBINTF); 591 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 592 593 return (0); 594 } 595 596 static int 597 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 598 { 599 uint8_t fup, reg, val; 600 uint32_t offset; 601 int match; 602 603 offset = 0; 604 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 605 fup != JME_EEPROM_SIG0) 606 return (ENOENT); 607 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 608 fup != JME_EEPROM_SIG1) 609 return (ENOENT); 610 match = 0; 611 do { 612 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 613 break; 614 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 615 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 616 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 617 break; 618 if (reg >= JME_PAR0 && 619 reg < JME_PAR0 + ETHER_ADDR_LEN) { 620 if (jme_eeprom_read_byte(sc, offset + 2, 621 &val) != 0) 622 break; 623 eaddr[reg - JME_PAR0] = val; 624 match++; 625 } 626 } 627 /* Check for the end of EEPROM descriptor. */ 628 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 629 break; 630 /* Try next eeprom descriptor. */ 631 offset += JME_EEPROM_DESC_BYTES; 632 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 633 634 if (match == ETHER_ADDR_LEN) 635 return (0); 636 637 return (ENOENT); 638 } 639 640 static void 641 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 642 { 643 uint32_t par0, par1; 644 645 /* Read station address. */ 646 par0 = CSR_READ_4(sc, JME_PAR0); 647 par1 = CSR_READ_4(sc, JME_PAR1); 648 par1 &= 0xFFFF; 649 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) { 650 device_printf(sc->jme_dev, 651 "generating fake ethernet address.\n"); 652 par0 = karc4random(); 653 /* Set OUI to JMicron. */ 654 eaddr[0] = 0x00; 655 eaddr[1] = 0x1B; 656 eaddr[2] = 0x8C; 657 eaddr[3] = (par0 >> 16) & 0xff; 658 eaddr[4] = (par0 >> 8) & 0xff; 659 eaddr[5] = par0 & 0xff; 660 } else { 661 eaddr[0] = (par0 >> 0) & 0xFF; 662 eaddr[1] = (par0 >> 8) & 0xFF; 663 eaddr[2] = (par0 >> 16) & 0xFF; 664 eaddr[3] = (par0 >> 24) & 0xFF; 665 eaddr[4] = (par1 >> 0) & 0xFF; 666 eaddr[5] = (par1 >> 8) & 0xFF; 667 } 668 } 669 670 static int 671 jme_attach(device_t dev) 672 { 673 struct jme_softc *sc = device_get_softc(dev); 674 struct ifnet *ifp = &sc->arpcom.ac_if; 675 uint32_t reg; 676 uint16_t did; 677 uint8_t pcie_ptr, rev; 678 int error = 0, i, j, rx_desc_cnt, coal_max; 679 uint8_t eaddr[ETHER_ADDR_LEN]; 680 #ifdef IFPOLL_ENABLE 681 int offset, offset_def; 682 #endif 683 684 /* 685 * Initialize serializers 686 */ 687 lwkt_serialize_init(&sc->jme_serialize); 688 lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize); 689 for (i = 0; i < JME_NRXRING_MAX; ++i) { 690 lwkt_serialize_init( 691 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize); 692 } 693 694 /* 695 * Get # of RX ring descriptors 696 */ 697 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count", 698 jme_rx_desc_count); 699 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN); 700 if (rx_desc_cnt > JME_NDESC_MAX) 701 rx_desc_cnt = JME_NDESC_MAX; 702 703 /* 704 * Get # of TX ring descriptors 705 */ 706 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 707 device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count); 708 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 709 roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN); 710 if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX) 711 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX; 712 713 /* 714 * Get # of RX rings 715 */ 716 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count", 717 jme_rx_ring_count); 718 sc->jme_cdata.jme_rx_ring_cnt = 719 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX); 720 721 /* 722 * Initialize serializer array 723 */ 724 i = 0; 725 sc->jme_serialize_arr[i++] = &sc->jme_serialize; 726 727 KKASSERT(i == JME_TX_SERIALIZE); 728 sc->jme_serialize_arr[i++] = 729 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 730 731 KKASSERT(i == JME_RX_SERIALIZE); 732 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) { 733 sc->jme_serialize_arr[i++] = 734 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize; 735 } 736 KKASSERT(i <= JME_NSERIALIZE); 737 sc->jme_serialize_cnt = i; 738 739 /* 740 * Setup TX ring specific data 741 */ 742 sc->jme_cdata.jme_tx_data.jme_sc = sc; 743 744 /* 745 * Setup RX rings specific data 746 */ 747 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 748 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 749 750 rdata->jme_sc = sc; 751 rdata->jme_rx_coal = jme_rx_status[i].jme_coal; 752 rdata->jme_rx_comp = jme_rx_status[i].jme_comp; 753 rdata->jme_rx_empty = jme_rx_status[i].jme_empty; 754 rdata->jme_rx_idx = i; 755 rdata->jme_rx_desc_cnt = rx_desc_cnt; 756 } 757 758 sc->jme_dev = dev; 759 sc->jme_lowaddr = BUS_SPACE_MAXADDR; 760 761 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 762 763 callout_init(&sc->jme_tick_ch); 764 765 #ifndef BURN_BRIDGES 766 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 767 uint32_t irq, mem; 768 769 irq = pci_read_config(dev, PCIR_INTLINE, 4); 770 mem = pci_read_config(dev, JME_PCIR_BAR, 4); 771 772 device_printf(dev, "chip is in D%d power mode " 773 "-- setting to D0\n", pci_get_powerstate(dev)); 774 775 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 776 777 pci_write_config(dev, PCIR_INTLINE, irq, 4); 778 pci_write_config(dev, JME_PCIR_BAR, mem, 4); 779 } 780 #endif /* !BURN_BRIDGE */ 781 782 /* Enable bus mastering */ 783 pci_enable_busmaster(dev); 784 785 /* 786 * Allocate IO memory 787 * 788 * JMC250 supports both memory mapped and I/O register space 789 * access. Because I/O register access should use different 790 * BARs to access registers it's waste of time to use I/O 791 * register spce access. JMC250 uses 16K to map entire memory 792 * space. 793 */ 794 sc->jme_mem_rid = JME_PCIR_BAR; 795 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 796 &sc->jme_mem_rid, RF_ACTIVE); 797 if (sc->jme_mem_res == NULL) { 798 device_printf(dev, "can't allocate IO memory\n"); 799 return ENXIO; 800 } 801 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res); 802 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res); 803 804 /* 805 * Allocate IRQ 806 */ 807 error = jme_intr_alloc(dev); 808 if (error) 809 goto fail; 810 811 /* 812 * Extract revisions 813 */ 814 reg = CSR_READ_4(sc, JME_CHIPMODE); 815 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 816 CHIPMODE_NOT_FPGA) { 817 sc->jme_caps |= JME_CAP_FPGA; 818 if (bootverbose) { 819 device_printf(dev, "FPGA revision: 0x%04x\n", 820 (reg & CHIPMODE_FPGA_REV_MASK) >> 821 CHIPMODE_FPGA_REV_SHIFT); 822 } 823 } 824 825 /* NOTE: FM revision is put in the upper 4 bits */ 826 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4; 827 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT; 828 if (bootverbose) 829 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev); 830 831 did = pci_get_device(dev); 832 switch (did) { 833 case PCI_PRODUCT_JMICRON_JMC250: 834 if (rev == JME_REV1_A2) 835 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX; 836 break; 837 838 case PCI_PRODUCT_JMICRON_JMC260: 839 if (rev == JME_REV2) 840 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT; 841 break; 842 843 default: 844 panic("unknown device id 0x%04x", did); 845 } 846 if (rev >= JME_REV2) { 847 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC; 848 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 | 849 GHC_TXMAC_CLKSRC_1000; 850 } 851 852 /* Reset the ethernet controller. */ 853 jme_reset(sc); 854 855 /* Map MSI/MSI-X vectors */ 856 jme_set_msinum(sc); 857 858 /* Get station address. */ 859 reg = CSR_READ_4(sc, JME_SMBCSR); 860 if (reg & SMBCSR_EEPROM_PRESENT) 861 error = jme_eeprom_macaddr(sc, eaddr); 862 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 863 if (error != 0 && (bootverbose)) { 864 device_printf(dev, "ethernet hardware address " 865 "not found in EEPROM.\n"); 866 } 867 jme_reg_macaddr(sc, eaddr); 868 } 869 870 /* 871 * Save PHY address. 872 * Integrated JR0211 has fixed PHY address whereas FPGA version 873 * requires PHY probing to get correct PHY address. 874 */ 875 if ((sc->jme_caps & JME_CAP_FPGA) == 0) { 876 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 877 GPREG0_PHY_ADDR_MASK; 878 if (bootverbose) { 879 device_printf(dev, "PHY is at address %d.\n", 880 sc->jme_phyaddr); 881 } 882 } else { 883 sc->jme_phyaddr = 0; 884 } 885 886 /* Set max allowable DMA size. */ 887 pcie_ptr = pci_get_pciecap_ptr(dev); 888 if (pcie_ptr != 0) { 889 uint16_t ctrl; 890 891 sc->jme_caps |= JME_CAP_PCIE; 892 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 893 if (bootverbose) { 894 device_printf(dev, "Read request size : %d bytes.\n", 895 128 << ((ctrl >> 12) & 0x07)); 896 device_printf(dev, "TLP payload size : %d bytes.\n", 897 128 << ((ctrl >> 5) & 0x07)); 898 } 899 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) { 900 case PCIEM_DEVCTL_MAX_READRQ_128: 901 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 902 break; 903 case PCIEM_DEVCTL_MAX_READRQ_256: 904 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 905 break; 906 default: 907 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 908 break; 909 } 910 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 911 } else { 912 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 913 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 914 } 915 916 #ifdef notyet 917 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 918 sc->jme_caps |= JME_CAP_PMCAP; 919 #endif 920 921 #ifdef IFPOLL_ENABLE 922 /* 923 * NPOLLING RX CPU offset 924 */ 925 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 926 offset = 0; 927 } else { 928 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 929 device_get_unit(dev)) % ncpus2; 930 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 931 if (offset >= ncpus2 || 932 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 933 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 934 offset, offset_def); 935 offset = offset_def; 936 } 937 } 938 sc->jme_npoll_rxoff = offset; 939 940 /* 941 * NPOLLING TX CPU offset 942 */ 943 offset_def = sc->jme_npoll_rxoff; 944 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 945 if (offset >= ncpus2) { 946 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 947 offset, offset_def); 948 offset = offset_def; 949 } 950 sc->jme_npoll_txoff = offset; 951 #endif 952 953 /* 954 * Set default coalesce valves 955 */ 956 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 957 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 958 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 959 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 960 961 /* 962 * Adjust coalesce valves, in case that the number of TX/RX 963 * descs are set to small values by users. 964 * 965 * NOTE: coal_max will not be zero, since number of descs 966 * must aligned by JME_NDESC_ALIGN (16 currently) 967 */ 968 coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2; 969 if (coal_max < sc->jme_tx_coal_pkt) 970 sc->jme_tx_coal_pkt = coal_max; 971 972 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2; 973 if (coal_max < sc->jme_rx_coal_pkt) 974 sc->jme_rx_coal_pkt = coal_max; 975 976 sc->jme_cdata.jme_tx_data.jme_tx_wreg = JME_TXWREG_NSEGS; 977 978 /* 979 * Create sysctl tree 980 */ 981 jme_sysctl_node(sc); 982 983 /* Allocate DMA stuffs */ 984 error = jme_dma_alloc(sc); 985 if (error) 986 goto fail; 987 988 ifp->if_softc = sc; 989 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 990 ifp->if_init = jme_init; 991 ifp->if_ioctl = jme_ioctl; 992 ifp->if_start = jme_start; 993 #ifdef IFPOLL_ENABLE 994 ifp->if_npoll = jme_npoll; 995 #endif 996 ifp->if_watchdog = jme_watchdog; 997 ifp->if_serialize = jme_serialize; 998 ifp->if_deserialize = jme_deserialize; 999 ifp->if_tryserialize = jme_tryserialize; 1000 #ifdef INVARIANTS 1001 ifp->if_serialize_assert = jme_serialize_assert; 1002 #endif 1003 ifq_set_maxlen(&ifp->if_snd, 1004 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD); 1005 ifq_set_ready(&ifp->if_snd); 1006 1007 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */ 1008 ifp->if_capabilities = IFCAP_HWCSUM | 1009 IFCAP_TSO | 1010 IFCAP_VLAN_MTU | 1011 IFCAP_VLAN_HWTAGGING; 1012 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN) 1013 ifp->if_capabilities |= IFCAP_RSS; 1014 ifp->if_capenable = ifp->if_capabilities; 1015 1016 /* 1017 * Disable TXCSUM by default to improve bulk data 1018 * transmit performance (+20Mbps improvement). 1019 */ 1020 ifp->if_capenable &= ~IFCAP_TXCSUM; 1021 1022 if (ifp->if_capenable & IFCAP_TXCSUM) 1023 ifp->if_hwassist |= JME_CSUM_FEATURES; 1024 ifp->if_hwassist |= CSUM_TSO; 1025 1026 /* Set up MII bus. */ 1027 error = mii_phy_probe(dev, &sc->jme_miibus, 1028 jme_mediachange, jme_mediastatus); 1029 if (error) { 1030 device_printf(dev, "no PHY found!\n"); 1031 goto fail; 1032 } 1033 1034 /* 1035 * Save PHYADDR for FPGA mode PHY. 1036 */ 1037 if (sc->jme_caps & JME_CAP_FPGA) { 1038 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1039 1040 if (mii->mii_instance != 0) { 1041 struct mii_softc *miisc; 1042 1043 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1044 if (miisc->mii_phy != 0) { 1045 sc->jme_phyaddr = miisc->mii_phy; 1046 break; 1047 } 1048 } 1049 if (sc->jme_phyaddr != 0) { 1050 device_printf(sc->jme_dev, 1051 "FPGA PHY is at %d\n", sc->jme_phyaddr); 1052 /* vendor magic. */ 1053 jme_miibus_writereg(dev, sc->jme_phyaddr, 1054 JMPHY_CONF, JMPHY_CONF_DEFFIFO); 1055 1056 /* XXX should we clear JME_WA_EXTFIFO */ 1057 } 1058 } 1059 } 1060 1061 ether_ifattach(ifp, eaddr, NULL); 1062 1063 /* Tell the upper layer(s) we support long frames. */ 1064 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1065 1066 /* Setup the TX ring's CPUID */ 1067 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 1068 1069 error = jme_intr_setup(dev); 1070 if (error) { 1071 ether_ifdetach(ifp); 1072 goto fail; 1073 } 1074 1075 return 0; 1076 fail: 1077 jme_detach(dev); 1078 return (error); 1079 } 1080 1081 static int 1082 jme_detach(device_t dev) 1083 { 1084 struct jme_softc *sc = device_get_softc(dev); 1085 1086 if (device_is_attached(dev)) { 1087 struct ifnet *ifp = &sc->arpcom.ac_if; 1088 1089 ifnet_serialize_all(ifp); 1090 jme_stop(sc); 1091 jme_intr_teardown(dev); 1092 ifnet_deserialize_all(ifp); 1093 1094 ether_ifdetach(ifp); 1095 } 1096 1097 if (sc->jme_sysctl_tree != NULL) 1098 sysctl_ctx_free(&sc->jme_sysctl_ctx); 1099 1100 if (sc->jme_miibus != NULL) 1101 device_delete_child(dev, sc->jme_miibus); 1102 bus_generic_detach(dev); 1103 1104 jme_intr_free(dev); 1105 1106 if (sc->jme_mem_res != NULL) { 1107 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid, 1108 sc->jme_mem_res); 1109 } 1110 1111 jme_dma_free(sc); 1112 1113 return (0); 1114 } 1115 1116 static void 1117 jme_sysctl_node(struct jme_softc *sc) 1118 { 1119 #ifdef JME_RSS_DEBUG 1120 int r; 1121 #endif 1122 1123 sysctl_ctx_init(&sc->jme_sysctl_ctx); 1124 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx, 1125 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 1126 device_get_nameunit(sc->jme_dev), 1127 CTLFLAG_RD, 0, ""); 1128 if (sc->jme_sysctl_tree == NULL) { 1129 device_printf(sc->jme_dev, "can't add sysctl node\n"); 1130 return; 1131 } 1132 1133 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1134 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1135 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1136 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout"); 1137 1138 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1139 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1140 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1141 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet"); 1142 1143 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1144 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1145 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1146 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout"); 1147 1148 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1149 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1150 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1151 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet"); 1152 1153 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1154 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1155 "rx_desc_count", CTLFLAG_RD, 1156 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt, 1157 0, "RX desc count"); 1158 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1159 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1160 "tx_desc_count", CTLFLAG_RD, 1161 &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, 1162 0, "TX desc count"); 1163 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1164 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1165 "rx_ring_count", CTLFLAG_RD, 1166 &sc->jme_cdata.jme_rx_ring_cnt, 1167 0, "RX ring count"); 1168 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1169 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1170 "tx_wreg", CTLFLAG_RW, 1171 &sc->jme_cdata.jme_tx_data.jme_tx_wreg, 0, 1172 "# of segments before writing to hardware register"); 1173 1174 #ifdef JME_RSS_DEBUG 1175 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1176 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1177 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug, 1178 0, "RSS debug level"); 1179 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1180 char rx_ring_desc[32]; 1181 1182 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1183 "rx_ring%d_pkt", r); 1184 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx, 1185 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1186 rx_ring_desc, CTLFLAG_RW, 1187 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets"); 1188 1189 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1190 "rx_ring%d_emp", r); 1191 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx, 1192 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1193 rx_ring_desc, CTLFLAG_RW, 1194 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp, 1195 "# of time RX ring empty"); 1196 } 1197 #endif 1198 1199 #ifdef IFPOLL_ENABLE 1200 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1201 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1202 "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1203 jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset"); 1204 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1205 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1206 "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1207 jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset"); 1208 #endif 1209 } 1210 1211 static int 1212 jme_dma_alloc(struct jme_softc *sc) 1213 { 1214 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1215 struct jme_txdesc *txd; 1216 bus_dmamem_t dmem; 1217 int error, i, asize; 1218 1219 asize = __VM_CACHELINE_ALIGN( 1220 tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc)); 1221 tdata->jme_txdesc = kmalloc_cachealign(asize, M_DEVBUF, 1222 M_WAITOK | M_ZERO); 1223 1224 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1225 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 1226 1227 asize = __VM_CACHELINE_ALIGN( 1228 rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc)); 1229 rdata->jme_rxdesc = kmalloc_cachealign(asize, M_DEVBUF, 1230 M_WAITOK | M_ZERO); 1231 } 1232 1233 /* Create parent ring tag. */ 1234 error = bus_dma_tag_create(NULL,/* parent */ 1235 1, JME_RING_BOUNDARY, /* algnmnt, boundary */ 1236 sc->jme_lowaddr, /* lowaddr */ 1237 BUS_SPACE_MAXADDR, /* highaddr */ 1238 NULL, NULL, /* filter, filterarg */ 1239 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1240 0, /* nsegments */ 1241 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1242 0, /* flags */ 1243 &sc->jme_cdata.jme_ring_tag); 1244 if (error) { 1245 device_printf(sc->jme_dev, 1246 "could not create parent ring DMA tag.\n"); 1247 return error; 1248 } 1249 1250 /* 1251 * Create DMA stuffs for TX ring 1252 */ 1253 asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN); 1254 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag, 1255 JME_TX_RING_ALIGN, 0, 1256 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1257 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1258 if (error) { 1259 device_printf(sc->jme_dev, "could not allocate Tx ring.\n"); 1260 return error; 1261 } 1262 tdata->jme_tx_ring_tag = dmem.dmem_tag; 1263 tdata->jme_tx_ring_map = dmem.dmem_map; 1264 tdata->jme_tx_ring = dmem.dmem_addr; 1265 tdata->jme_tx_ring_paddr = dmem.dmem_busaddr; 1266 1267 /* 1268 * Create DMA stuffs for RX rings 1269 */ 1270 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1271 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1272 if (error) 1273 return error; 1274 } 1275 1276 /* Create parent buffer tag. */ 1277 error = bus_dma_tag_create(NULL,/* parent */ 1278 1, 0, /* algnmnt, boundary */ 1279 sc->jme_lowaddr, /* lowaddr */ 1280 BUS_SPACE_MAXADDR, /* highaddr */ 1281 NULL, NULL, /* filter, filterarg */ 1282 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1283 0, /* nsegments */ 1284 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1285 0, /* flags */ 1286 &sc->jme_cdata.jme_buffer_tag); 1287 if (error) { 1288 device_printf(sc->jme_dev, 1289 "could not create parent buffer DMA tag.\n"); 1290 return error; 1291 } 1292 1293 /* 1294 * Create DMA stuffs for shadow status block 1295 */ 1296 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN); 1297 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag, 1298 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1299 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1300 if (error) { 1301 device_printf(sc->jme_dev, 1302 "could not create shadow status block.\n"); 1303 return error; 1304 } 1305 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag; 1306 sc->jme_cdata.jme_ssb_map = dmem.dmem_map; 1307 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr; 1308 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr; 1309 1310 /* 1311 * Create DMA stuffs for TX buffers 1312 */ 1313 1314 /* Create tag for Tx buffers. */ 1315 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1316 1, 0, /* algnmnt, boundary */ 1317 BUS_SPACE_MAXADDR, /* lowaddr */ 1318 BUS_SPACE_MAXADDR, /* highaddr */ 1319 NULL, NULL, /* filter, filterarg */ 1320 JME_TSO_MAXSIZE, /* maxsize */ 1321 JME_MAXTXSEGS, /* nsegments */ 1322 JME_MAXSEGSIZE, /* maxsegsize */ 1323 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */ 1324 &tdata->jme_tx_tag); 1325 if (error != 0) { 1326 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1327 return error; 1328 } 1329 1330 /* Create DMA maps for Tx buffers. */ 1331 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1332 txd = &tdata->jme_txdesc[i]; 1333 error = bus_dmamap_create(tdata->jme_tx_tag, 1334 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1335 &txd->tx_dmamap); 1336 if (error) { 1337 int j; 1338 1339 device_printf(sc->jme_dev, 1340 "could not create %dth Tx dmamap.\n", i); 1341 1342 for (j = 0; j < i; ++j) { 1343 txd = &tdata->jme_txdesc[j]; 1344 bus_dmamap_destroy(tdata->jme_tx_tag, 1345 txd->tx_dmamap); 1346 } 1347 bus_dma_tag_destroy(tdata->jme_tx_tag); 1348 tdata->jme_tx_tag = NULL; 1349 return error; 1350 } 1351 } 1352 1353 /* 1354 * Create DMA stuffs for RX buffers 1355 */ 1356 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1357 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1358 if (error) 1359 return error; 1360 } 1361 return 0; 1362 } 1363 1364 static void 1365 jme_dma_free(struct jme_softc *sc) 1366 { 1367 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1368 struct jme_txdesc *txd; 1369 struct jme_rxdesc *rxd; 1370 struct jme_rxdata *rdata; 1371 int i, r; 1372 1373 /* Tx ring */ 1374 if (tdata->jme_tx_ring_tag != NULL) { 1375 bus_dmamap_unload(tdata->jme_tx_ring_tag, 1376 tdata->jme_tx_ring_map); 1377 bus_dmamem_free(tdata->jme_tx_ring_tag, 1378 tdata->jme_tx_ring, tdata->jme_tx_ring_map); 1379 bus_dma_tag_destroy(tdata->jme_tx_ring_tag); 1380 tdata->jme_tx_ring_tag = NULL; 1381 } 1382 1383 /* Rx ring */ 1384 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1385 rdata = &sc->jme_cdata.jme_rx_data[r]; 1386 if (rdata->jme_rx_ring_tag != NULL) { 1387 bus_dmamap_unload(rdata->jme_rx_ring_tag, 1388 rdata->jme_rx_ring_map); 1389 bus_dmamem_free(rdata->jme_rx_ring_tag, 1390 rdata->jme_rx_ring, 1391 rdata->jme_rx_ring_map); 1392 bus_dma_tag_destroy(rdata->jme_rx_ring_tag); 1393 rdata->jme_rx_ring_tag = NULL; 1394 } 1395 } 1396 1397 /* Tx buffers */ 1398 if (tdata->jme_tx_tag != NULL) { 1399 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1400 txd = &tdata->jme_txdesc[i]; 1401 bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap); 1402 } 1403 bus_dma_tag_destroy(tdata->jme_tx_tag); 1404 tdata->jme_tx_tag = NULL; 1405 } 1406 1407 /* Rx buffers */ 1408 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1409 rdata = &sc->jme_cdata.jme_rx_data[r]; 1410 if (rdata->jme_rx_tag != NULL) { 1411 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 1412 rxd = &rdata->jme_rxdesc[i]; 1413 bus_dmamap_destroy(rdata->jme_rx_tag, 1414 rxd->rx_dmamap); 1415 } 1416 bus_dmamap_destroy(rdata->jme_rx_tag, 1417 rdata->jme_rx_sparemap); 1418 bus_dma_tag_destroy(rdata->jme_rx_tag); 1419 rdata->jme_rx_tag = NULL; 1420 } 1421 } 1422 1423 /* Shadow status block. */ 1424 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1425 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1426 sc->jme_cdata.jme_ssb_map); 1427 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1428 sc->jme_cdata.jme_ssb_block, 1429 sc->jme_cdata.jme_ssb_map); 1430 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1431 sc->jme_cdata.jme_ssb_tag = NULL; 1432 } 1433 1434 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1435 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1436 sc->jme_cdata.jme_buffer_tag = NULL; 1437 } 1438 if (sc->jme_cdata.jme_ring_tag != NULL) { 1439 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1440 sc->jme_cdata.jme_ring_tag = NULL; 1441 } 1442 1443 if (tdata->jme_txdesc != NULL) { 1444 kfree(tdata->jme_txdesc, M_DEVBUF); 1445 tdata->jme_txdesc = NULL; 1446 } 1447 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1448 rdata = &sc->jme_cdata.jme_rx_data[r]; 1449 if (rdata->jme_rxdesc != NULL) { 1450 kfree(rdata->jme_rxdesc, M_DEVBUF); 1451 rdata->jme_rxdesc = NULL; 1452 } 1453 } 1454 } 1455 1456 /* 1457 * Make sure the interface is stopped at reboot time. 1458 */ 1459 static int 1460 jme_shutdown(device_t dev) 1461 { 1462 return jme_suspend(dev); 1463 } 1464 1465 #ifdef notyet 1466 /* 1467 * Unlike other ethernet controllers, JMC250 requires 1468 * explicit resetting link speed to 10/100Mbps as gigabit 1469 * link will cunsume more power than 375mA. 1470 * Note, we reset the link speed to 10/100Mbps with 1471 * auto-negotiation but we don't know whether that operation 1472 * would succeed or not as we have no control after powering 1473 * off. If the renegotiation fail WOL may not work. Running 1474 * at 1Gbps draws more power than 375mA at 3.3V which is 1475 * specified in PCI specification and that would result in 1476 * complete shutdowning power to ethernet controller. 1477 * 1478 * TODO 1479 * Save current negotiated media speed/duplex/flow-control 1480 * to softc and restore the same link again after resuming. 1481 * PHY handling such as power down/resetting to 100Mbps 1482 * may be better handled in suspend method in phy driver. 1483 */ 1484 static void 1485 jme_setlinkspeed(struct jme_softc *sc) 1486 { 1487 struct mii_data *mii; 1488 int aneg, i; 1489 1490 JME_LOCK_ASSERT(sc); 1491 1492 mii = device_get_softc(sc->jme_miibus); 1493 mii_pollstat(mii); 1494 aneg = 0; 1495 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1496 switch IFM_SUBTYPE(mii->mii_media_active) { 1497 case IFM_10_T: 1498 case IFM_100_TX: 1499 return; 1500 case IFM_1000_T: 1501 aneg++; 1502 default: 1503 break; 1504 } 1505 } 1506 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1507 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1508 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1509 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1510 BMCR_AUTOEN | BMCR_STARTNEG); 1511 DELAY(1000); 1512 if (aneg != 0) { 1513 /* Poll link state until jme(4) get a 10/100 link. */ 1514 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1515 mii_pollstat(mii); 1516 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1517 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1518 case IFM_10_T: 1519 case IFM_100_TX: 1520 jme_mac_config(sc); 1521 return; 1522 default: 1523 break; 1524 } 1525 } 1526 JME_UNLOCK(sc); 1527 pause("jmelnk", hz); 1528 JME_LOCK(sc); 1529 } 1530 if (i == MII_ANEGTICKS_GIGE) 1531 device_printf(sc->jme_dev, "establishing link failed, " 1532 "WOL may not work!"); 1533 } 1534 /* 1535 * No link, force MAC to have 100Mbps, full-duplex link. 1536 * This is the last resort and may/may not work. 1537 */ 1538 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1539 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1540 jme_mac_config(sc); 1541 } 1542 1543 static void 1544 jme_setwol(struct jme_softc *sc) 1545 { 1546 struct ifnet *ifp = &sc->arpcom.ac_if; 1547 uint32_t gpr, pmcs; 1548 uint16_t pmstat; 1549 int pmc; 1550 1551 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1552 /* No PME capability, PHY power down. */ 1553 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1554 MII_BMCR, BMCR_PDOWN); 1555 return; 1556 } 1557 1558 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1559 pmcs = CSR_READ_4(sc, JME_PMCS); 1560 pmcs &= ~PMCS_WOL_ENB_MASK; 1561 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1562 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1563 /* Enable PME message. */ 1564 gpr |= GPREG0_PME_ENB; 1565 /* For gigabit controllers, reset link speed to 10/100. */ 1566 if ((sc->jme_caps & JME_CAP_FASTETH) == 0) 1567 jme_setlinkspeed(sc); 1568 } 1569 1570 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1571 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1572 1573 /* Request PME. */ 1574 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1575 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1576 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1577 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1578 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1579 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1580 /* No WOL, PHY power down. */ 1581 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1582 MII_BMCR, BMCR_PDOWN); 1583 } 1584 } 1585 #endif 1586 1587 static int 1588 jme_suspend(device_t dev) 1589 { 1590 struct jme_softc *sc = device_get_softc(dev); 1591 struct ifnet *ifp = &sc->arpcom.ac_if; 1592 1593 ifnet_serialize_all(ifp); 1594 jme_stop(sc); 1595 #ifdef notyet 1596 jme_setwol(sc); 1597 #endif 1598 ifnet_deserialize_all(ifp); 1599 1600 return (0); 1601 } 1602 1603 static int 1604 jme_resume(device_t dev) 1605 { 1606 struct jme_softc *sc = device_get_softc(dev); 1607 struct ifnet *ifp = &sc->arpcom.ac_if; 1608 #ifdef notyet 1609 int pmc; 1610 #endif 1611 1612 ifnet_serialize_all(ifp); 1613 1614 #ifdef notyet 1615 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1616 uint16_t pmstat; 1617 1618 pmstat = pci_read_config(sc->jme_dev, 1619 pmc + PCIR_POWER_STATUS, 2); 1620 /* Disable PME clear PME status. */ 1621 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1622 pci_write_config(sc->jme_dev, 1623 pmc + PCIR_POWER_STATUS, pmstat, 2); 1624 } 1625 #endif 1626 1627 if (ifp->if_flags & IFF_UP) 1628 jme_init(sc); 1629 1630 ifnet_deserialize_all(ifp); 1631 1632 return (0); 1633 } 1634 1635 static __inline int 1636 jme_tso_pullup(struct mbuf **mp) 1637 { 1638 int hoff, iphlen, thoff; 1639 struct mbuf *m; 1640 1641 m = *mp; 1642 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 1643 1644 iphlen = m->m_pkthdr.csum_iphlen; 1645 thoff = m->m_pkthdr.csum_thlen; 1646 hoff = m->m_pkthdr.csum_lhlen; 1647 1648 KASSERT(iphlen > 0, ("invalid ip hlen")); 1649 KASSERT(thoff > 0, ("invalid tcp hlen")); 1650 KASSERT(hoff > 0, ("invalid ether hlen")); 1651 1652 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 1653 m = m_pullup(m, hoff + iphlen + thoff); 1654 if (m == NULL) { 1655 *mp = NULL; 1656 return ENOBUFS; 1657 } 1658 *mp = m; 1659 } 1660 return 0; 1661 } 1662 1663 static int 1664 jme_encap(struct jme_txdata *tdata, struct mbuf **m_head, int *segs_used) 1665 { 1666 struct jme_txdesc *txd; 1667 struct jme_desc *desc; 1668 struct mbuf *m; 1669 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1670 int maxsegs, nsegs; 1671 int error, i, prod, symbol_desc; 1672 uint32_t cflags, flag64, mss; 1673 1674 M_ASSERTPKTHDR((*m_head)); 1675 1676 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) { 1677 /* XXX Is this necessary? */ 1678 error = jme_tso_pullup(m_head); 1679 if (error) 1680 return error; 1681 } 1682 1683 prod = tdata->jme_tx_prod; 1684 txd = &tdata->jme_txdesc[prod]; 1685 1686 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) 1687 symbol_desc = 1; 1688 else 1689 symbol_desc = 0; 1690 1691 maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) - 1692 (JME_TXD_RSVD + symbol_desc); 1693 if (maxsegs > JME_MAXTXSEGS) 1694 maxsegs = JME_MAXTXSEGS; 1695 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc), 1696 ("not enough segments %d", maxsegs)); 1697 1698 error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag, 1699 txd->tx_dmamap, m_head, 1700 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1701 if (error) 1702 goto fail; 1703 *segs_used += nsegs; 1704 1705 bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap, 1706 BUS_DMASYNC_PREWRITE); 1707 1708 m = *m_head; 1709 cflags = 0; 1710 mss = 0; 1711 1712 /* Configure checksum offload. */ 1713 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1714 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT; 1715 cflags |= JME_TD_TSO; 1716 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) { 1717 if (m->m_pkthdr.csum_flags & CSUM_IP) 1718 cflags |= JME_TD_IPCSUM; 1719 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1720 cflags |= JME_TD_TCPCSUM; 1721 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1722 cflags |= JME_TD_UDPCSUM; 1723 } 1724 1725 /* Configure VLAN. */ 1726 if (m->m_flags & M_VLANTAG) { 1727 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK); 1728 cflags |= JME_TD_VLAN_TAG; 1729 } 1730 1731 desc = &tdata->jme_tx_ring[prod]; 1732 desc->flags = htole32(cflags); 1733 desc->addr_hi = htole32(m->m_pkthdr.len); 1734 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1735 /* 1736 * Use 64bits TX desc chain format. 1737 * 1738 * The first TX desc of the chain, which is setup here, 1739 * is just a symbol TX desc carrying no payload. 1740 */ 1741 flag64 = JME_TD_64BIT; 1742 desc->buflen = htole32(mss); 1743 desc->addr_lo = 0; 1744 1745 *segs_used += 1; 1746 1747 /* No effective TX desc is consumed */ 1748 i = 0; 1749 } else { 1750 /* 1751 * Use 32bits TX desc chain format. 1752 * 1753 * The first TX desc of the chain, which is setup here, 1754 * is an effective TX desc carrying the first segment of 1755 * the mbuf chain. 1756 */ 1757 flag64 = 0; 1758 desc->buflen = htole32(mss | txsegs[0].ds_len); 1759 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr)); 1760 1761 /* One effective TX desc is consumed */ 1762 i = 1; 1763 } 1764 tdata->jme_tx_cnt++; 1765 KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1766 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1767 1768 txd->tx_ndesc = 1 - i; 1769 for (; i < nsegs; i++) { 1770 desc = &tdata->jme_tx_ring[prod]; 1771 desc->buflen = htole32(txsegs[i].ds_len); 1772 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1773 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1774 desc->flags = htole32(JME_TD_OWN | flag64); 1775 1776 tdata->jme_tx_cnt++; 1777 KKASSERT(tdata->jme_tx_cnt <= 1778 tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1779 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1780 } 1781 1782 /* Update producer index. */ 1783 tdata->jme_tx_prod = prod; 1784 /* 1785 * Finally request interrupt and give the first descriptor 1786 * owenership to hardware. 1787 */ 1788 desc = txd->tx_desc; 1789 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1790 1791 txd->tx_m = m; 1792 txd->tx_ndesc += nsegs; 1793 1794 return 0; 1795 fail: 1796 m_freem(*m_head); 1797 *m_head = NULL; 1798 return error; 1799 } 1800 1801 static void 1802 jme_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1803 { 1804 struct jme_softc *sc = ifp->if_softc; 1805 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1806 struct mbuf *m_head; 1807 int enq = 0; 1808 1809 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1810 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 1811 1812 if (!sc->jme_has_link) { 1813 ifq_purge(&ifp->if_snd); 1814 return; 1815 } 1816 1817 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1818 return; 1819 1820 if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata)) 1821 jme_txeof(tdata); 1822 1823 while (!ifq_is_empty(&ifp->if_snd)) { 1824 /* 1825 * Check number of available TX descs, always 1826 * leave JME_TXD_RSVD free TX descs. 1827 */ 1828 if (tdata->jme_tx_cnt + JME_TXD_SPARE > 1829 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) { 1830 ifq_set_oactive(&ifp->if_snd); 1831 break; 1832 } 1833 1834 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1835 if (m_head == NULL) 1836 break; 1837 1838 /* 1839 * Pack the data into the transmit ring. If we 1840 * don't have room, set the OACTIVE flag and wait 1841 * for the NIC to drain the ring. 1842 */ 1843 if (jme_encap(tdata, &m_head, &enq)) { 1844 KKASSERT(m_head == NULL); 1845 IFNET_STAT_INC(ifp, oerrors, 1); 1846 ifq_set_oactive(&ifp->if_snd); 1847 break; 1848 } 1849 1850 if (enq >= tdata->jme_tx_wreg) { 1851 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | 1852 TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1853 enq = 0; 1854 } 1855 1856 /* 1857 * If there's a BPF listener, bounce a copy of this frame 1858 * to him. 1859 */ 1860 ETHER_BPF_MTAP(ifp, m_head); 1861 1862 /* Set a timeout in case the chip goes out to lunch. */ 1863 ifp->if_timer = JME_TX_TIMEOUT; 1864 } 1865 1866 if (enq > 0) { 1867 /* 1868 * Reading TXCSR takes very long time under heavy load 1869 * so cache TXCSR value and writes the ORed value with 1870 * the kick command to the TXCSR. This saves one register 1871 * access cycle. 1872 */ 1873 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1874 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1875 } 1876 } 1877 1878 static void 1879 jme_watchdog(struct ifnet *ifp) 1880 { 1881 struct jme_softc *sc = ifp->if_softc; 1882 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1883 1884 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1885 1886 if (!sc->jme_has_link) { 1887 if_printf(ifp, "watchdog timeout (missed link)\n"); 1888 IFNET_STAT_INC(ifp, oerrors, 1); 1889 jme_init(sc); 1890 return; 1891 } 1892 1893 jme_txeof(tdata); 1894 if (tdata->jme_tx_cnt == 0) { 1895 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 1896 "-- recovering\n"); 1897 if (!ifq_is_empty(&ifp->if_snd)) 1898 if_devstart(ifp); 1899 return; 1900 } 1901 1902 if_printf(ifp, "watchdog timeout\n"); 1903 IFNET_STAT_INC(ifp, oerrors, 1); 1904 jme_init(sc); 1905 if (!ifq_is_empty(&ifp->if_snd)) 1906 if_devstart(ifp); 1907 } 1908 1909 static int 1910 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1911 { 1912 struct jme_softc *sc = ifp->if_softc; 1913 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1914 struct ifreq *ifr = (struct ifreq *)data; 1915 int error = 0, mask; 1916 1917 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1918 1919 switch (cmd) { 1920 case SIOCSIFMTU: 1921 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1922 (!(sc->jme_caps & JME_CAP_JUMBO) && 1923 ifr->ifr_mtu > JME_MAX_MTU)) { 1924 error = EINVAL; 1925 break; 1926 } 1927 1928 if (ifp->if_mtu != ifr->ifr_mtu) { 1929 /* 1930 * No special configuration is required when interface 1931 * MTU is changed but availability of Tx checksum 1932 * offload should be chcked against new MTU size as 1933 * FIFO size is just 2K. 1934 */ 1935 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1936 ifp->if_capenable &= 1937 ~(IFCAP_TXCSUM | IFCAP_TSO); 1938 ifp->if_hwassist &= 1939 ~(JME_CSUM_FEATURES | CSUM_TSO); 1940 } 1941 ifp->if_mtu = ifr->ifr_mtu; 1942 if (ifp->if_flags & IFF_RUNNING) 1943 jme_init(sc); 1944 } 1945 break; 1946 1947 case SIOCSIFFLAGS: 1948 if (ifp->if_flags & IFF_UP) { 1949 if (ifp->if_flags & IFF_RUNNING) { 1950 if ((ifp->if_flags ^ sc->jme_if_flags) & 1951 (IFF_PROMISC | IFF_ALLMULTI)) 1952 jme_set_filter(sc); 1953 } else { 1954 jme_init(sc); 1955 } 1956 } else { 1957 if (ifp->if_flags & IFF_RUNNING) 1958 jme_stop(sc); 1959 } 1960 sc->jme_if_flags = ifp->if_flags; 1961 break; 1962 1963 case SIOCADDMULTI: 1964 case SIOCDELMULTI: 1965 if (ifp->if_flags & IFF_RUNNING) 1966 jme_set_filter(sc); 1967 break; 1968 1969 case SIOCSIFMEDIA: 1970 case SIOCGIFMEDIA: 1971 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1972 break; 1973 1974 case SIOCSIFCAP: 1975 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1976 1977 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 1978 ifp->if_capenable ^= IFCAP_TXCSUM; 1979 if (ifp->if_capenable & IFCAP_TXCSUM) 1980 ifp->if_hwassist |= JME_CSUM_FEATURES; 1981 else 1982 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1983 } 1984 if (mask & IFCAP_RXCSUM) { 1985 uint32_t reg; 1986 1987 ifp->if_capenable ^= IFCAP_RXCSUM; 1988 reg = CSR_READ_4(sc, JME_RXMAC); 1989 reg &= ~RXMAC_CSUM_ENB; 1990 if (ifp->if_capenable & IFCAP_RXCSUM) 1991 reg |= RXMAC_CSUM_ENB; 1992 CSR_WRITE_4(sc, JME_RXMAC, reg); 1993 } 1994 1995 if (mask & IFCAP_VLAN_HWTAGGING) { 1996 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1997 jme_set_vlan(sc); 1998 } 1999 2000 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 2001 ifp->if_capenable ^= IFCAP_TSO; 2002 if (ifp->if_capenable & IFCAP_TSO) 2003 ifp->if_hwassist |= CSUM_TSO; 2004 else 2005 ifp->if_hwassist &= ~CSUM_TSO; 2006 } 2007 2008 if (mask & IFCAP_RSS) 2009 ifp->if_capenable ^= IFCAP_RSS; 2010 break; 2011 2012 default: 2013 error = ether_ioctl(ifp, cmd, data); 2014 break; 2015 } 2016 return (error); 2017 } 2018 2019 static void 2020 jme_mac_config(struct jme_softc *sc) 2021 { 2022 struct mii_data *mii; 2023 uint32_t ghc, rxmac, txmac, txpause, gp1; 2024 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0; 2025 2026 mii = device_get_softc(sc->jme_miibus); 2027 2028 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2029 DELAY(10); 2030 CSR_WRITE_4(sc, JME_GHC, 0); 2031 ghc = 0; 2032 rxmac = CSR_READ_4(sc, JME_RXMAC); 2033 rxmac &= ~RXMAC_FC_ENB; 2034 txmac = CSR_READ_4(sc, JME_TXMAC); 2035 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2036 txpause = CSR_READ_4(sc, JME_TXPFC); 2037 txpause &= ~TXPFC_PAUSE_ENB; 2038 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2039 ghc |= GHC_FULL_DUPLEX; 2040 rxmac &= ~RXMAC_COLL_DET_ENB; 2041 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2042 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2043 TXMAC_FRAME_BURST); 2044 #ifdef notyet 2045 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2046 txpause |= TXPFC_PAUSE_ENB; 2047 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2048 rxmac |= RXMAC_FC_ENB; 2049 #endif 2050 /* Disable retry transmit timer/retry limit. */ 2051 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2052 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2053 } else { 2054 rxmac |= RXMAC_COLL_DET_ENB; 2055 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2056 /* Enable retry transmit timer/retry limit. */ 2057 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2058 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2059 } 2060 2061 /* 2062 * Reprogram Tx/Rx MACs with resolved speed/duplex. 2063 */ 2064 gp1 = CSR_READ_4(sc, JME_GPREG1); 2065 gp1 &= ~GPREG1_WA_HDX; 2066 2067 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2068 hdx = 1; 2069 2070 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2071 case IFM_10_T: 2072 ghc |= GHC_SPEED_10 | sc->jme_clksrc; 2073 if (hdx) 2074 gp1 |= GPREG1_WA_HDX; 2075 break; 2076 2077 case IFM_100_TX: 2078 ghc |= GHC_SPEED_100 | sc->jme_clksrc; 2079 if (hdx) 2080 gp1 |= GPREG1_WA_HDX; 2081 2082 /* 2083 * Use extended FIFO depth to workaround CRC errors 2084 * emitted by chips before JMC250B 2085 */ 2086 phyconf = JMPHY_CONF_EXTFIFO; 2087 break; 2088 2089 case IFM_1000_T: 2090 if (sc->jme_caps & JME_CAP_FASTETH) 2091 break; 2092 2093 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000; 2094 if (hdx) 2095 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2096 break; 2097 2098 default: 2099 break; 2100 } 2101 CSR_WRITE_4(sc, JME_GHC, ghc); 2102 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2103 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2104 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2105 2106 if (sc->jme_workaround & JME_WA_EXTFIFO) { 2107 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2108 JMPHY_CONF, phyconf); 2109 } 2110 if (sc->jme_workaround & JME_WA_HDX) 2111 CSR_WRITE_4(sc, JME_GPREG1, gp1); 2112 } 2113 2114 static void 2115 jme_intr(void *xsc) 2116 { 2117 struct jme_softc *sc = xsc; 2118 struct ifnet *ifp = &sc->arpcom.ac_if; 2119 uint32_t status; 2120 int r; 2121 2122 ASSERT_SERIALIZED(&sc->jme_serialize); 2123 2124 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2125 if (status == 0 || status == 0xFFFFFFFF) 2126 return; 2127 2128 /* Disable interrupts. */ 2129 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2130 2131 status = CSR_READ_4(sc, JME_INTR_STATUS); 2132 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2133 goto back; 2134 2135 /* Reset PCC counter/timer and Ack interrupts. */ 2136 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2137 2138 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) 2139 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2140 2141 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2142 if (status & jme_rx_status[r].jme_coal) { 2143 status |= jme_rx_status[r].jme_coal | 2144 jme_rx_status[r].jme_comp; 2145 } 2146 } 2147 2148 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2149 2150 if (ifp->if_flags & IFF_RUNNING) { 2151 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2152 2153 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) 2154 jme_rx_intr(sc, status); 2155 2156 if (status & INTR_RXQ_DESC_EMPTY) { 2157 /* 2158 * Notify hardware availability of new Rx buffers. 2159 * Reading RXCSR takes very long time under heavy 2160 * load so cache RXCSR value and writes the ORed 2161 * value with the kick command to the RXCSR. This 2162 * saves one register access cycle. 2163 */ 2164 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2165 RXCSR_RX_ENB | RXCSR_RXQ_START); 2166 } 2167 2168 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) { 2169 lwkt_serialize_enter(&tdata->jme_tx_serialize); 2170 jme_txeof(tdata); 2171 if (!ifq_is_empty(&ifp->if_snd)) 2172 if_devstart(ifp); 2173 lwkt_serialize_exit(&tdata->jme_tx_serialize); 2174 } 2175 } 2176 back: 2177 /* Reenable interrupts. */ 2178 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2179 } 2180 2181 static void 2182 jme_txeof(struct jme_txdata *tdata) 2183 { 2184 struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if; 2185 int cons; 2186 2187 cons = tdata->jme_tx_cons; 2188 if (cons == tdata->jme_tx_prod) 2189 return; 2190 2191 /* 2192 * Go through our Tx list and free mbufs for those 2193 * frames which have been transmitted. 2194 */ 2195 while (cons != tdata->jme_tx_prod) { 2196 struct jme_txdesc *txd, *next_txd; 2197 uint32_t status, next_status; 2198 int next_cons, nsegs; 2199 2200 txd = &tdata->jme_txdesc[cons]; 2201 KASSERT(txd->tx_m != NULL, 2202 ("%s: freeing NULL mbuf!", __func__)); 2203 2204 status = le32toh(txd->tx_desc->flags); 2205 if ((status & JME_TD_OWN) == JME_TD_OWN) 2206 break; 2207 2208 /* 2209 * NOTE: 2210 * This chip will always update the TX descriptor's 2211 * buflen field and this updating always happens 2212 * after clearing the OWN bit, so even if the OWN 2213 * bit is cleared by the chip, we still don't sure 2214 * about whether the buflen field has been updated 2215 * by the chip or not. To avoid this race, we wait 2216 * for the next TX descriptor's OWN bit to be cleared 2217 * by the chip before reusing this TX descriptor. 2218 */ 2219 next_cons = cons; 2220 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt); 2221 next_txd = &tdata->jme_txdesc[next_cons]; 2222 if (next_txd->tx_m == NULL) 2223 break; 2224 next_status = le32toh(next_txd->tx_desc->flags); 2225 if ((next_status & JME_TD_OWN) == JME_TD_OWN) 2226 break; 2227 2228 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) { 2229 IFNET_STAT_INC(ifp, oerrors, 1); 2230 } else { 2231 IFNET_STAT_INC(ifp, opackets, 1); 2232 if (status & JME_TD_COLLISION) { 2233 IFNET_STAT_INC(ifp, collisions, 2234 le32toh(txd->tx_desc->buflen) & 2235 JME_TD_BUF_LEN_MASK); 2236 } 2237 } 2238 2239 /* 2240 * Only the first descriptor of multi-descriptor 2241 * transmission is updated so driver have to skip entire 2242 * chained buffers for the transmiited frame. In other 2243 * words, JME_TD_OWN bit is valid only at the first 2244 * descriptor of a multi-descriptor transmission. 2245 */ 2246 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2247 tdata->jme_tx_ring[cons].flags = 0; 2248 JME_DESC_INC(cons, tdata->jme_tx_desc_cnt); 2249 } 2250 2251 /* Reclaim transferred mbufs. */ 2252 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2253 m_freem(txd->tx_m); 2254 txd->tx_m = NULL; 2255 tdata->jme_tx_cnt -= txd->tx_ndesc; 2256 KASSERT(tdata->jme_tx_cnt >= 0, 2257 ("%s: Active Tx desc counter was garbled", __func__)); 2258 txd->tx_ndesc = 0; 2259 } 2260 tdata->jme_tx_cons = cons; 2261 2262 /* 1 for symbol TX descriptor */ 2263 if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1) 2264 ifp->if_timer = 0; 2265 2266 if (tdata->jme_tx_cnt + JME_TXD_SPARE <= 2267 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) 2268 ifq_clr_oactive(&ifp->if_snd); 2269 } 2270 2271 static __inline void 2272 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count) 2273 { 2274 int i; 2275 2276 for (i = 0; i < count; ++i) { 2277 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]); 2278 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2279 } 2280 } 2281 2282 static __inline struct pktinfo * 2283 jme_pktinfo(struct pktinfo *pi, uint32_t flags) 2284 { 2285 if (flags & JME_RD_IPV4) 2286 pi->pi_netisr = NETISR_IP; 2287 else if (flags & JME_RD_IPV6) 2288 pi->pi_netisr = NETISR_IPV6; 2289 else 2290 return NULL; 2291 2292 pi->pi_flags = 0; 2293 pi->pi_l3proto = IPPROTO_UNKNOWN; 2294 2295 if (flags & JME_RD_MORE_FRAG) 2296 pi->pi_flags |= PKTINFO_FLAG_FRAG; 2297 else if (flags & JME_RD_TCP) 2298 pi->pi_l3proto = IPPROTO_TCP; 2299 else if (flags & JME_RD_UDP) 2300 pi->pi_l3proto = IPPROTO_UDP; 2301 else 2302 pi = NULL; 2303 return pi; 2304 } 2305 2306 /* Receive a frame. */ 2307 static void 2308 jme_rxpkt(struct jme_rxdata *rdata) 2309 { 2310 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if; 2311 struct jme_desc *desc; 2312 struct jme_rxdesc *rxd; 2313 struct mbuf *mp, *m; 2314 uint32_t flags, status, hash, hashinfo; 2315 int cons, count, nsegs; 2316 2317 cons = rdata->jme_rx_cons; 2318 desc = &rdata->jme_rx_ring[cons]; 2319 2320 flags = le32toh(desc->flags); 2321 status = le32toh(desc->buflen); 2322 hash = le32toh(desc->addr_hi); 2323 hashinfo = le32toh(desc->addr_lo); 2324 nsegs = JME_RX_NSEGS(status); 2325 2326 if (nsegs > 1) { 2327 /* Skip the first descriptor. */ 2328 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2329 2330 /* 2331 * Clear the OWN bit of the following RX descriptors; 2332 * hardware will not clear the OWN bit except the first 2333 * RX descriptor. 2334 * 2335 * Since the first RX descriptor is setup, i.e. OWN bit 2336 * on, before its followins RX descriptors, leaving the 2337 * OWN bit on the following RX descriptors will trick 2338 * the hardware into thinking that the following RX 2339 * descriptors are ready to be used too. 2340 */ 2341 for (count = 1; count < nsegs; count++, 2342 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) 2343 rdata->jme_rx_ring[cons].flags = 0; 2344 2345 cons = rdata->jme_rx_cons; 2346 } 2347 2348 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, " 2349 "hash 0x%08x, hash info 0x%08x\n", 2350 rdata->jme_rx_idx, flags, hash, hashinfo); 2351 2352 if (status & JME_RX_ERR_STAT) { 2353 IFNET_STAT_INC(ifp, ierrors, 1); 2354 jme_discard_rxbufs(rdata, cons, nsegs); 2355 #ifdef JME_SHOW_ERRORS 2356 if_printf(ifp, "%s : receive error = 0x%b\n", 2357 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2358 #endif 2359 rdata->jme_rx_cons += nsegs; 2360 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2361 return; 2362 } 2363 2364 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2365 for (count = 0; count < nsegs; count++, 2366 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) { 2367 rxd = &rdata->jme_rxdesc[cons]; 2368 mp = rxd->rx_m; 2369 2370 /* Add a new receive buffer to the ring. */ 2371 if (jme_newbuf(rdata, rxd, 0) != 0) { 2372 IFNET_STAT_INC(ifp, iqdrops, 1); 2373 /* Reuse buffer. */ 2374 jme_discard_rxbufs(rdata, cons, nsegs - count); 2375 if (rdata->jme_rxhead != NULL) { 2376 m_freem(rdata->jme_rxhead); 2377 JME_RXCHAIN_RESET(rdata); 2378 } 2379 break; 2380 } 2381 2382 /* 2383 * Assume we've received a full sized frame. 2384 * Actual size is fixed when we encounter the end of 2385 * multi-segmented frame. 2386 */ 2387 mp->m_len = MCLBYTES; 2388 2389 /* Chain received mbufs. */ 2390 if (rdata->jme_rxhead == NULL) { 2391 rdata->jme_rxhead = mp; 2392 rdata->jme_rxtail = mp; 2393 } else { 2394 /* 2395 * Receive processor can receive a maximum frame 2396 * size of 65535 bytes. 2397 */ 2398 rdata->jme_rxtail->m_next = mp; 2399 rdata->jme_rxtail = mp; 2400 } 2401 2402 if (count == nsegs - 1) { 2403 struct pktinfo pi0, *pi; 2404 2405 /* Last desc. for this frame. */ 2406 m = rdata->jme_rxhead; 2407 m->m_pkthdr.len = rdata->jme_rxlen; 2408 if (nsegs > 1) { 2409 /* Set first mbuf size. */ 2410 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2411 /* Set last mbuf size. */ 2412 mp->m_len = rdata->jme_rxlen - 2413 ((MCLBYTES - JME_RX_PAD_BYTES) + 2414 (MCLBYTES * (nsegs - 2))); 2415 } else { 2416 m->m_len = rdata->jme_rxlen; 2417 } 2418 m->m_pkthdr.rcvif = ifp; 2419 2420 /* 2421 * Account for 10bytes auto padding which is used 2422 * to align IP header on 32bit boundary. Also note, 2423 * CRC bytes is automatically removed by the 2424 * hardware. 2425 */ 2426 m->m_data += JME_RX_PAD_BYTES; 2427 2428 /* Set checksum information. */ 2429 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2430 (flags & JME_RD_IPV4)) { 2431 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2432 if (flags & JME_RD_IPCSUM) 2433 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2434 if ((flags & JME_RD_MORE_FRAG) == 0 && 2435 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2436 (JME_RD_TCP | JME_RD_TCPCSUM) || 2437 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2438 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2439 m->m_pkthdr.csum_flags |= 2440 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2441 m->m_pkthdr.csum_data = 0xffff; 2442 } 2443 } 2444 2445 /* Check for VLAN tagged packets. */ 2446 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 2447 (flags & JME_RD_VLAN_TAG)) { 2448 m->m_pkthdr.ether_vlantag = 2449 flags & JME_RD_VLAN_MASK; 2450 m->m_flags |= M_VLANTAG; 2451 } 2452 2453 IFNET_STAT_INC(ifp, ipackets, 1); 2454 2455 if (ifp->if_capenable & IFCAP_RSS) 2456 pi = jme_pktinfo(&pi0, flags); 2457 else 2458 pi = NULL; 2459 2460 if (pi != NULL && 2461 (hashinfo & JME_RD_HASH_FN_MASK) == 2462 JME_RD_HASH_FN_TOEPLITZ) { 2463 m->m_flags |= (M_HASH | M_CKHASH); 2464 m->m_pkthdr.hash = toeplitz_hash(hash); 2465 } 2466 2467 #ifdef JME_RSS_DEBUG 2468 if (pi != NULL) { 2469 JME_RSS_DPRINTF(rdata->jme_sc, 10, 2470 "isr %d flags %08x, l3 %d %s\n", 2471 pi->pi_netisr, pi->pi_flags, 2472 pi->pi_l3proto, 2473 (m->m_flags & M_HASH) ? "hash" : ""); 2474 } 2475 #endif 2476 2477 /* Pass it on. */ 2478 ether_input_pkt(ifp, m, pi); 2479 2480 /* Reset mbuf chains. */ 2481 JME_RXCHAIN_RESET(rdata); 2482 #ifdef JME_RSS_DEBUG 2483 rdata->jme_rx_pkt++; 2484 #endif 2485 } 2486 } 2487 2488 rdata->jme_rx_cons += nsegs; 2489 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2490 } 2491 2492 static void 2493 jme_rxeof(struct jme_rxdata *rdata, int count) 2494 { 2495 struct jme_desc *desc; 2496 int nsegs, pktlen; 2497 2498 for (;;) { 2499 #ifdef IFPOLL_ENABLE 2500 if (count >= 0 && count-- == 0) 2501 break; 2502 #endif 2503 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons]; 2504 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2505 break; 2506 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2507 break; 2508 2509 /* 2510 * Check number of segments against received bytes. 2511 * Non-matching value would indicate that hardware 2512 * is still trying to update Rx descriptors. I'm not 2513 * sure whether this check is needed. 2514 */ 2515 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2516 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2517 if (nsegs != howmany(pktlen, MCLBYTES)) { 2518 if_printf(&rdata->jme_sc->arpcom.ac_if, 2519 "RX fragment count(%d) and " 2520 "packet size(%d) mismach\n", nsegs, pktlen); 2521 break; 2522 } 2523 2524 /* 2525 * NOTE: 2526 * RSS hash and hash information may _not_ be set by the 2527 * hardware even if the OWN bit is cleared and VALID bit 2528 * is set. 2529 * 2530 * If the RSS information is not delivered by the hardware 2531 * yet, we MUST NOT accept this packet, let alone reusing 2532 * its RX descriptor. If this packet was accepted and its 2533 * RX descriptor was reused before hardware delivering the 2534 * RSS information, the RX buffer's address would be trashed 2535 * by the RSS information delivered by the hardware. 2536 */ 2537 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 2538 struct jme_rxdesc *rxd; 2539 uint32_t hashinfo; 2540 2541 hashinfo = le32toh(desc->addr_lo); 2542 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons]; 2543 2544 /* 2545 * This test should be enough to detect the pending 2546 * RSS information delivery, given: 2547 * - If RSS hash is not calculated, the hashinfo 2548 * will be 0. Howvever, the lower 32bits of RX 2549 * buffers' physical address will never be 0. 2550 * (see jme_rxbuf_dma_filter) 2551 * - If RSS hash is calculated, the lowest 4 bits 2552 * of hashinfo will be set, while the RX buffers 2553 * are at least 2K aligned. 2554 */ 2555 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) { 2556 #ifdef JME_SHOW_RSSWB 2557 if_printf(&rdata->jme_sc->arpcom.ac_if, 2558 "RSS is not written back yet\n"); 2559 #endif 2560 break; 2561 } 2562 } 2563 2564 /* Received a frame. */ 2565 jme_rxpkt(rdata); 2566 } 2567 } 2568 2569 static void 2570 jme_tick(void *xsc) 2571 { 2572 struct jme_softc *sc = xsc; 2573 struct mii_data *mii = device_get_softc(sc->jme_miibus); 2574 2575 lwkt_serialize_enter(&sc->jme_serialize); 2576 2577 KKASSERT(mycpuid == JME_TICK_CPUID); 2578 2579 sc->jme_in_tick = TRUE; 2580 mii_tick(mii); 2581 sc->jme_in_tick = FALSE; 2582 2583 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2584 2585 lwkt_serialize_exit(&sc->jme_serialize); 2586 } 2587 2588 static void 2589 jme_reset(struct jme_softc *sc) 2590 { 2591 uint32_t val; 2592 2593 /* Make sure that TX and RX are stopped */ 2594 jme_stop_tx(sc); 2595 jme_stop_rx(sc); 2596 2597 /* Start reset */ 2598 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2599 DELAY(20); 2600 2601 /* 2602 * Hold reset bit before stop reset 2603 */ 2604 2605 /* Disable TXMAC and TXOFL clock sources */ 2606 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2607 /* Disable RXMAC clock source */ 2608 val = CSR_READ_4(sc, JME_GPREG1); 2609 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2610 /* Flush */ 2611 CSR_READ_4(sc, JME_GHC); 2612 2613 /* Stop reset */ 2614 CSR_WRITE_4(sc, JME_GHC, 0); 2615 /* Flush */ 2616 CSR_READ_4(sc, JME_GHC); 2617 2618 /* 2619 * Clear reset bit after stop reset 2620 */ 2621 2622 /* Enable TXMAC and TXOFL clock sources */ 2623 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2624 /* Enable RXMAC clock source */ 2625 val = CSR_READ_4(sc, JME_GPREG1); 2626 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2627 /* Flush */ 2628 CSR_READ_4(sc, JME_GHC); 2629 2630 /* Disable TXMAC and TXOFL clock sources */ 2631 CSR_WRITE_4(sc, JME_GHC, 0); 2632 /* Disable RXMAC clock source */ 2633 val = CSR_READ_4(sc, JME_GPREG1); 2634 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2635 /* Flush */ 2636 CSR_READ_4(sc, JME_GHC); 2637 2638 /* Enable TX and RX */ 2639 val = CSR_READ_4(sc, JME_TXCSR); 2640 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB); 2641 val = CSR_READ_4(sc, JME_RXCSR); 2642 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB); 2643 /* Flush */ 2644 CSR_READ_4(sc, JME_TXCSR); 2645 CSR_READ_4(sc, JME_RXCSR); 2646 2647 /* Enable TXMAC and TXOFL clock sources */ 2648 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2649 /* Eisable RXMAC clock source */ 2650 val = CSR_READ_4(sc, JME_GPREG1); 2651 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2652 /* Flush */ 2653 CSR_READ_4(sc, JME_GHC); 2654 2655 /* Stop TX and RX */ 2656 jme_stop_tx(sc); 2657 jme_stop_rx(sc); 2658 } 2659 2660 static void 2661 jme_init(void *xsc) 2662 { 2663 struct jme_softc *sc = xsc; 2664 struct ifnet *ifp = &sc->arpcom.ac_if; 2665 struct mii_data *mii; 2666 uint8_t eaddr[ETHER_ADDR_LEN]; 2667 bus_addr_t paddr; 2668 uint32_t reg; 2669 int error, r; 2670 2671 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2672 2673 /* 2674 * Cancel any pending I/O. 2675 */ 2676 jme_stop(sc); 2677 2678 /* 2679 * Reset the chip to a known state. 2680 */ 2681 jme_reset(sc); 2682 2683 /* 2684 * Setup MSI/MSI-X vectors to interrupts mapping 2685 */ 2686 jme_set_msinum(sc); 2687 2688 if (JME_ENABLE_HWRSS(sc)) 2689 jme_enable_rss(sc); 2690 else 2691 jme_disable_rss(sc); 2692 2693 /* Init RX descriptors */ 2694 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2695 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]); 2696 if (error) { 2697 if_printf(ifp, "initialization failed: " 2698 "no memory for %dth RX ring.\n", r); 2699 jme_stop(sc); 2700 return; 2701 } 2702 } 2703 2704 /* Init TX descriptors */ 2705 jme_init_tx_ring(&sc->jme_cdata.jme_tx_data); 2706 2707 /* Initialize shadow status block. */ 2708 jme_init_ssb(sc); 2709 2710 /* Reprogram the station address. */ 2711 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2712 CSR_WRITE_4(sc, JME_PAR0, 2713 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2714 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2715 2716 /* 2717 * Configure Tx queue. 2718 * Tx priority queue weight value : 0 2719 * Tx FIFO threshold for processing next packet : 16QW 2720 * Maximum Tx DMA length : 512 2721 * Allow Tx DMA burst. 2722 */ 2723 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2724 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2725 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2726 sc->jme_txcsr |= sc->jme_tx_dma_size; 2727 sc->jme_txcsr |= TXCSR_DMA_BURST; 2728 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2729 2730 /* Set Tx descriptor counter. */ 2731 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt); 2732 2733 /* Set Tx ring address to the hardware. */ 2734 paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr; 2735 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2736 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2737 2738 /* Configure TxMAC parameters. */ 2739 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2740 reg |= TXMAC_THRESH_1_PKT; 2741 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2742 CSR_WRITE_4(sc, JME_TXMAC, reg); 2743 2744 /* 2745 * Configure Rx queue. 2746 * FIFO full threshold for transmitting Tx pause packet : 128T 2747 * FIFO threshold for processing next packet : 128QW 2748 * Rx queue 0 select 2749 * Max Rx DMA length : 128 2750 * Rx descriptor retry : 32 2751 * Rx descriptor retry time gap : 256ns 2752 * Don't receive runt/bad frame. 2753 */ 2754 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2755 #if 0 2756 /* 2757 * Since Rx FIFO size is 4K bytes, receiving frames larger 2758 * than 4K bytes will suffer from Rx FIFO overruns. So 2759 * decrease FIFO threshold to reduce the FIFO overruns for 2760 * frames larger than 4000 bytes. 2761 * For best performance of standard MTU sized frames use 2762 * maximum allowable FIFO threshold, 128QW. 2763 */ 2764 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) > 2765 JME_RX_FIFO_SIZE) 2766 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2767 else 2768 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2769 #else 2770 /* Improve PCI Express compatibility */ 2771 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2772 #endif 2773 sc->jme_rxcsr |= sc->jme_rx_dma_size; 2774 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2775 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2776 /* XXX TODO DROP_BAD */ 2777 2778 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2779 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 2780 2781 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 2782 2783 /* Set Rx descriptor counter. */ 2784 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt); 2785 2786 /* Set Rx ring address to the hardware. */ 2787 paddr = rdata->jme_rx_ring_paddr; 2788 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2789 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2790 } 2791 2792 /* Clear receive filter. */ 2793 CSR_WRITE_4(sc, JME_RXMAC, 0); 2794 2795 /* Set up the receive filter. */ 2796 jme_set_filter(sc); 2797 jme_set_vlan(sc); 2798 2799 /* 2800 * Disable all WOL bits as WOL can interfere normal Rx 2801 * operation. Also clear WOL detection status bits. 2802 */ 2803 reg = CSR_READ_4(sc, JME_PMCS); 2804 reg &= ~PMCS_WOL_ENB_MASK; 2805 CSR_WRITE_4(sc, JME_PMCS, reg); 2806 2807 /* 2808 * Pad 10bytes right before received frame. This will greatly 2809 * help Rx performance on strict-alignment architectures as 2810 * it does not need to copy the frame to align the payload. 2811 */ 2812 reg = CSR_READ_4(sc, JME_RXMAC); 2813 reg |= RXMAC_PAD_10BYTES; 2814 2815 if (ifp->if_capenable & IFCAP_RXCSUM) 2816 reg |= RXMAC_CSUM_ENB; 2817 CSR_WRITE_4(sc, JME_RXMAC, reg); 2818 2819 /* Configure general purpose reg0 */ 2820 reg = CSR_READ_4(sc, JME_GPREG0); 2821 reg &= ~GPREG0_PCC_UNIT_MASK; 2822 /* Set PCC timer resolution to micro-seconds unit. */ 2823 reg |= GPREG0_PCC_UNIT_US; 2824 /* 2825 * Disable all shadow register posting as we have to read 2826 * JME_INTR_STATUS register in jme_intr. Also it seems 2827 * that it's hard to synchronize interrupt status between 2828 * hardware and software with shadow posting due to 2829 * requirements of bus_dmamap_sync(9). 2830 */ 2831 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2832 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2833 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2834 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2835 /* Disable posting of DW0. */ 2836 reg &= ~GPREG0_POST_DW0_ENB; 2837 /* Clear PME message. */ 2838 reg &= ~GPREG0_PME_ENB; 2839 /* Set PHY address. */ 2840 reg &= ~GPREG0_PHY_ADDR_MASK; 2841 reg |= sc->jme_phyaddr; 2842 CSR_WRITE_4(sc, JME_GPREG0, reg); 2843 2844 /* Configure Tx queue 0 packet completion coalescing. */ 2845 jme_set_tx_coal(sc); 2846 2847 /* Configure Rx queues packet completion coalescing. */ 2848 jme_set_rx_coal(sc); 2849 2850 /* Configure shadow status block but don't enable posting. */ 2851 paddr = sc->jme_cdata.jme_ssb_block_paddr; 2852 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2853 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2854 2855 /* Disable Timer 1 and Timer 2. */ 2856 CSR_WRITE_4(sc, JME_TIMER1, 0); 2857 CSR_WRITE_4(sc, JME_TIMER2, 0); 2858 2859 /* Configure retry transmit period, retry limit value. */ 2860 CSR_WRITE_4(sc, JME_TXTRHD, 2861 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2862 TXTRHD_RT_PERIOD_MASK) | 2863 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2864 TXTRHD_RT_LIMIT_SHIFT)); 2865 2866 #ifdef IFPOLL_ENABLE 2867 if (!(ifp->if_flags & IFF_NPOLLING)) 2868 #endif 2869 /* Initialize the interrupt mask. */ 2870 jme_enable_intr(sc); 2871 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2872 2873 /* 2874 * Enabling Tx/Rx DMA engines and Rx queue processing is 2875 * done after detection of valid link in jme_miibus_statchg. 2876 */ 2877 sc->jme_has_link = FALSE; 2878 2879 /* Set the current media. */ 2880 mii = device_get_softc(sc->jme_miibus); 2881 mii_mediachg(mii); 2882 2883 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 2884 JME_TICK_CPUID); 2885 2886 ifp->if_flags |= IFF_RUNNING; 2887 ifq_clr_oactive(&ifp->if_snd); 2888 } 2889 2890 static void 2891 jme_stop(struct jme_softc *sc) 2892 { 2893 struct ifnet *ifp = &sc->arpcom.ac_if; 2894 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2895 struct jme_txdesc *txd; 2896 struct jme_rxdesc *rxd; 2897 struct jme_rxdata *rdata; 2898 int i, r; 2899 2900 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2901 2902 /* 2903 * Mark the interface down and cancel the watchdog timer. 2904 */ 2905 ifp->if_flags &= ~IFF_RUNNING; 2906 ifq_clr_oactive(&ifp->if_snd); 2907 ifp->if_timer = 0; 2908 2909 callout_stop(&sc->jme_tick_ch); 2910 sc->jme_has_link = FALSE; 2911 2912 /* 2913 * Disable interrupts. 2914 */ 2915 jme_disable_intr(sc); 2916 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2917 2918 /* Disable updating shadow status block. */ 2919 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2920 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2921 2922 /* Stop receiver, transmitter. */ 2923 jme_stop_rx(sc); 2924 jme_stop_tx(sc); 2925 2926 /* 2927 * Free partial finished RX segments 2928 */ 2929 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2930 rdata = &sc->jme_cdata.jme_rx_data[r]; 2931 if (rdata->jme_rxhead != NULL) 2932 m_freem(rdata->jme_rxhead); 2933 JME_RXCHAIN_RESET(rdata); 2934 } 2935 2936 /* 2937 * Free RX and TX mbufs still in the queues. 2938 */ 2939 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2940 rdata = &sc->jme_cdata.jme_rx_data[r]; 2941 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 2942 rxd = &rdata->jme_rxdesc[i]; 2943 if (rxd->rx_m != NULL) { 2944 bus_dmamap_unload(rdata->jme_rx_tag, 2945 rxd->rx_dmamap); 2946 m_freem(rxd->rx_m); 2947 rxd->rx_m = NULL; 2948 } 2949 } 2950 } 2951 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 2952 txd = &tdata->jme_txdesc[i]; 2953 if (txd->tx_m != NULL) { 2954 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2955 m_freem(txd->tx_m); 2956 txd->tx_m = NULL; 2957 txd->tx_ndesc = 0; 2958 } 2959 } 2960 } 2961 2962 static void 2963 jme_stop_tx(struct jme_softc *sc) 2964 { 2965 uint32_t reg; 2966 int i; 2967 2968 reg = CSR_READ_4(sc, JME_TXCSR); 2969 if ((reg & TXCSR_TX_ENB) == 0) 2970 return; 2971 reg &= ~TXCSR_TX_ENB; 2972 CSR_WRITE_4(sc, JME_TXCSR, reg); 2973 for (i = JME_TIMEOUT; i > 0; i--) { 2974 DELAY(1); 2975 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2976 break; 2977 } 2978 if (i == 0) 2979 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2980 } 2981 2982 static void 2983 jme_stop_rx(struct jme_softc *sc) 2984 { 2985 uint32_t reg; 2986 int i; 2987 2988 reg = CSR_READ_4(sc, JME_RXCSR); 2989 if ((reg & RXCSR_RX_ENB) == 0) 2990 return; 2991 reg &= ~RXCSR_RX_ENB; 2992 CSR_WRITE_4(sc, JME_RXCSR, reg); 2993 for (i = JME_TIMEOUT; i > 0; i--) { 2994 DELAY(1); 2995 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2996 break; 2997 } 2998 if (i == 0) 2999 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3000 } 3001 3002 static void 3003 jme_init_tx_ring(struct jme_txdata *tdata) 3004 { 3005 struct jme_txdesc *txd; 3006 int i; 3007 3008 tdata->jme_tx_prod = 0; 3009 tdata->jme_tx_cons = 0; 3010 tdata->jme_tx_cnt = 0; 3011 3012 bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata)); 3013 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 3014 txd = &tdata->jme_txdesc[i]; 3015 txd->tx_m = NULL; 3016 txd->tx_desc = &tdata->jme_tx_ring[i]; 3017 txd->tx_ndesc = 0; 3018 } 3019 } 3020 3021 static void 3022 jme_init_ssb(struct jme_softc *sc) 3023 { 3024 struct jme_chain_data *cd; 3025 3026 cd = &sc->jme_cdata; 3027 bzero(cd->jme_ssb_block, JME_SSB_SIZE); 3028 } 3029 3030 static int 3031 jme_init_rx_ring(struct jme_rxdata *rdata) 3032 { 3033 struct jme_rxdesc *rxd; 3034 int i; 3035 3036 KKASSERT(rdata->jme_rxhead == NULL && 3037 rdata->jme_rxtail == NULL && 3038 rdata->jme_rxlen == 0); 3039 rdata->jme_rx_cons = 0; 3040 3041 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata)); 3042 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3043 int error; 3044 3045 rxd = &rdata->jme_rxdesc[i]; 3046 rxd->rx_m = NULL; 3047 rxd->rx_desc = &rdata->jme_rx_ring[i]; 3048 error = jme_newbuf(rdata, rxd, 1); 3049 if (error) 3050 return error; 3051 } 3052 return 0; 3053 } 3054 3055 static int 3056 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init) 3057 { 3058 struct mbuf *m; 3059 bus_dma_segment_t segs; 3060 bus_dmamap_t map; 3061 int error, nsegs; 3062 3063 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3064 if (m == NULL) 3065 return ENOBUFS; 3066 /* 3067 * JMC250 has 64bit boundary alignment limitation so jme(4) 3068 * takes advantage of 10 bytes padding feature of hardware 3069 * in order not to copy entire frame to align IP header on 3070 * 32bit boundary. 3071 */ 3072 m->m_len = m->m_pkthdr.len = MCLBYTES; 3073 3074 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag, 3075 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs, 3076 BUS_DMA_NOWAIT); 3077 if (error) { 3078 m_freem(m); 3079 if (init) { 3080 if_printf(&rdata->jme_sc->arpcom.ac_if, 3081 "can't load RX mbuf\n"); 3082 } 3083 return error; 3084 } 3085 3086 if (rxd->rx_m != NULL) { 3087 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap, 3088 BUS_DMASYNC_POSTREAD); 3089 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap); 3090 } 3091 map = rxd->rx_dmamap; 3092 rxd->rx_dmamap = rdata->jme_rx_sparemap; 3093 rdata->jme_rx_sparemap = map; 3094 rxd->rx_m = m; 3095 rxd->rx_paddr = segs.ds_addr; 3096 3097 jme_setup_rxdesc(rxd); 3098 return 0; 3099 } 3100 3101 static void 3102 jme_set_vlan(struct jme_softc *sc) 3103 { 3104 struct ifnet *ifp = &sc->arpcom.ac_if; 3105 uint32_t reg; 3106 3107 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3108 3109 reg = CSR_READ_4(sc, JME_RXMAC); 3110 reg &= ~RXMAC_VLAN_ENB; 3111 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 3112 reg |= RXMAC_VLAN_ENB; 3113 CSR_WRITE_4(sc, JME_RXMAC, reg); 3114 } 3115 3116 static void 3117 jme_set_filter(struct jme_softc *sc) 3118 { 3119 struct ifnet *ifp = &sc->arpcom.ac_if; 3120 struct ifmultiaddr *ifma; 3121 uint32_t crc; 3122 uint32_t mchash[2]; 3123 uint32_t rxcfg; 3124 3125 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3126 3127 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3128 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3129 RXMAC_ALLMULTI); 3130 3131 /* 3132 * Always accept frames destined to our station address. 3133 * Always accept broadcast frames. 3134 */ 3135 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST; 3136 3137 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 3138 if (ifp->if_flags & IFF_PROMISC) 3139 rxcfg |= RXMAC_PROMISC; 3140 if (ifp->if_flags & IFF_ALLMULTI) 3141 rxcfg |= RXMAC_ALLMULTI; 3142 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3143 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3144 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3145 return; 3146 } 3147 3148 /* 3149 * Set up the multicast address filter by passing all multicast 3150 * addresses through a CRC generator, and then using the low-order 3151 * 6 bits as an index into the 64 bit multicast hash table. The 3152 * high order bits select the register, while the rest of the bits 3153 * select the bit within the register. 3154 */ 3155 rxcfg |= RXMAC_MULTICAST; 3156 bzero(mchash, sizeof(mchash)); 3157 3158 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3159 if (ifma->ifma_addr->sa_family != AF_LINK) 3160 continue; 3161 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3162 ifma->ifma_addr), ETHER_ADDR_LEN); 3163 3164 /* Just want the 6 least significant bits. */ 3165 crc &= 0x3f; 3166 3167 /* Set the corresponding bit in the hash table. */ 3168 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3169 } 3170 3171 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3172 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3173 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3174 } 3175 3176 static int 3177 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS) 3178 { 3179 struct jme_softc *sc = arg1; 3180 struct ifnet *ifp = &sc->arpcom.ac_if; 3181 int error, v; 3182 3183 ifnet_serialize_all(ifp); 3184 3185 v = sc->jme_tx_coal_to; 3186 error = sysctl_handle_int(oidp, &v, 0, req); 3187 if (error || req->newptr == NULL) 3188 goto back; 3189 3190 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) { 3191 error = EINVAL; 3192 goto back; 3193 } 3194 3195 if (v != sc->jme_tx_coal_to) { 3196 sc->jme_tx_coal_to = v; 3197 if (ifp->if_flags & IFF_RUNNING) 3198 jme_set_tx_coal(sc); 3199 } 3200 back: 3201 ifnet_deserialize_all(ifp); 3202 return error; 3203 } 3204 3205 static int 3206 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3207 { 3208 struct jme_softc *sc = arg1; 3209 struct ifnet *ifp = &sc->arpcom.ac_if; 3210 int error, v; 3211 3212 ifnet_serialize_all(ifp); 3213 3214 v = sc->jme_tx_coal_pkt; 3215 error = sysctl_handle_int(oidp, &v, 0, req); 3216 if (error || req->newptr == NULL) 3217 goto back; 3218 3219 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) { 3220 error = EINVAL; 3221 goto back; 3222 } 3223 3224 if (v != sc->jme_tx_coal_pkt) { 3225 sc->jme_tx_coal_pkt = v; 3226 if (ifp->if_flags & IFF_RUNNING) 3227 jme_set_tx_coal(sc); 3228 } 3229 back: 3230 ifnet_deserialize_all(ifp); 3231 return error; 3232 } 3233 3234 static int 3235 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS) 3236 { 3237 struct jme_softc *sc = arg1; 3238 struct ifnet *ifp = &sc->arpcom.ac_if; 3239 int error, v; 3240 3241 ifnet_serialize_all(ifp); 3242 3243 v = sc->jme_rx_coal_to; 3244 error = sysctl_handle_int(oidp, &v, 0, req); 3245 if (error || req->newptr == NULL) 3246 goto back; 3247 3248 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) { 3249 error = EINVAL; 3250 goto back; 3251 } 3252 3253 if (v != sc->jme_rx_coal_to) { 3254 sc->jme_rx_coal_to = v; 3255 if (ifp->if_flags & IFF_RUNNING) 3256 jme_set_rx_coal(sc); 3257 } 3258 back: 3259 ifnet_deserialize_all(ifp); 3260 return error; 3261 } 3262 3263 static int 3264 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3265 { 3266 struct jme_softc *sc = arg1; 3267 struct ifnet *ifp = &sc->arpcom.ac_if; 3268 int error, v; 3269 3270 ifnet_serialize_all(ifp); 3271 3272 v = sc->jme_rx_coal_pkt; 3273 error = sysctl_handle_int(oidp, &v, 0, req); 3274 if (error || req->newptr == NULL) 3275 goto back; 3276 3277 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) { 3278 error = EINVAL; 3279 goto back; 3280 } 3281 3282 if (v != sc->jme_rx_coal_pkt) { 3283 sc->jme_rx_coal_pkt = v; 3284 if (ifp->if_flags & IFF_RUNNING) 3285 jme_set_rx_coal(sc); 3286 } 3287 back: 3288 ifnet_deserialize_all(ifp); 3289 return error; 3290 } 3291 3292 static void 3293 jme_set_tx_coal(struct jme_softc *sc) 3294 { 3295 uint32_t reg; 3296 3297 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 3298 PCCTX_COAL_TO_MASK; 3299 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 3300 PCCTX_COAL_PKT_MASK; 3301 reg |= PCCTX_COAL_TXQ0; 3302 CSR_WRITE_4(sc, JME_PCCTX, reg); 3303 } 3304 3305 static void 3306 jme_set_rx_coal(struct jme_softc *sc) 3307 { 3308 uint32_t reg; 3309 int r; 3310 3311 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 3312 PCCRX_COAL_TO_MASK; 3313 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 3314 PCCRX_COAL_PKT_MASK; 3315 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) 3316 CSR_WRITE_4(sc, JME_PCCRX(r), reg); 3317 } 3318 3319 #ifdef IFPOLL_ENABLE 3320 3321 static void 3322 jme_npoll_status(struct ifnet *ifp) 3323 { 3324 struct jme_softc *sc = ifp->if_softc; 3325 uint32_t status; 3326 3327 ASSERT_SERIALIZED(&sc->jme_serialize); 3328 3329 status = CSR_READ_4(sc, JME_INTR_STATUS); 3330 if (status & INTR_RXQ_DESC_EMPTY) { 3331 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3332 jme_rx_restart(sc, status); 3333 } 3334 } 3335 3336 static void 3337 jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3338 { 3339 struct jme_rxdata *rdata = arg; 3340 3341 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3342 3343 jme_rxeof(rdata, cycle); 3344 } 3345 3346 static void 3347 jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3348 { 3349 struct jme_txdata *tdata = arg; 3350 3351 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3352 3353 jme_txeof(tdata); 3354 if (!ifq_is_empty(&ifp->if_snd)) 3355 if_devstart(ifp); 3356 } 3357 3358 static void 3359 jme_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3360 { 3361 struct jme_softc *sc = ifp->if_softc; 3362 3363 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3364 3365 if (info) { 3366 int i, off; 3367 3368 info->ifpi_status.status_func = jme_npoll_status; 3369 info->ifpi_status.serializer = &sc->jme_serialize; 3370 3371 off = sc->jme_npoll_txoff; 3372 KKASSERT(off <= ncpus2); 3373 info->ifpi_tx[off].poll_func = jme_npoll_tx; 3374 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data; 3375 info->ifpi_tx[off].serializer = 3376 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3377 ifq_set_cpuid(&ifp->if_snd, sc->jme_npoll_txoff); 3378 3379 off = sc->jme_npoll_rxoff; 3380 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3381 struct jme_rxdata *rdata = 3382 &sc->jme_cdata.jme_rx_data[i]; 3383 int idx = i + off; 3384 3385 info->ifpi_rx[idx].poll_func = jme_npoll_rx; 3386 info->ifpi_rx[idx].arg = rdata; 3387 info->ifpi_rx[idx].serializer = 3388 &rdata->jme_rx_serialize; 3389 } 3390 3391 if (ifp->if_flags & IFF_RUNNING) 3392 jme_disable_intr(sc); 3393 } else { 3394 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 3395 if (ifp->if_flags & IFF_RUNNING) 3396 jme_enable_intr(sc); 3397 } 3398 } 3399 3400 static int 3401 jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3402 { 3403 struct jme_softc *sc = (void *)arg1; 3404 struct ifnet *ifp = &sc->arpcom.ac_if; 3405 int error, off; 3406 3407 off = sc->jme_npoll_rxoff; 3408 error = sysctl_handle_int(oidp, &off, 0, req); 3409 if (error || req->newptr == NULL) 3410 return error; 3411 if (off < 0) 3412 return EINVAL; 3413 3414 ifnet_serialize_all(ifp); 3415 if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3416 error = EINVAL; 3417 } else { 3418 error = 0; 3419 sc->jme_npoll_rxoff = off; 3420 } 3421 ifnet_deserialize_all(ifp); 3422 3423 return error; 3424 } 3425 3426 static int 3427 jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3428 { 3429 struct jme_softc *sc = (void *)arg1; 3430 struct ifnet *ifp = &sc->arpcom.ac_if; 3431 int error, off; 3432 3433 off = sc->jme_npoll_txoff; 3434 error = sysctl_handle_int(oidp, &off, 0, req); 3435 if (error || req->newptr == NULL) 3436 return error; 3437 if (off < 0) 3438 return EINVAL; 3439 3440 ifnet_serialize_all(ifp); 3441 if (off >= ncpus2) { 3442 error = EINVAL; 3443 } else { 3444 error = 0; 3445 sc->jme_npoll_txoff = off; 3446 } 3447 ifnet_deserialize_all(ifp); 3448 3449 return error; 3450 } 3451 3452 #endif /* IFPOLL_ENABLE */ 3453 3454 static int 3455 jme_rxring_dma_alloc(struct jme_rxdata *rdata) 3456 { 3457 bus_dmamem_t dmem; 3458 int error, asize; 3459 3460 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN); 3461 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag, 3462 JME_RX_RING_ALIGN, 0, 3463 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3464 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3465 if (error) { 3466 device_printf(rdata->jme_sc->jme_dev, 3467 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx); 3468 return error; 3469 } 3470 rdata->jme_rx_ring_tag = dmem.dmem_tag; 3471 rdata->jme_rx_ring_map = dmem.dmem_map; 3472 rdata->jme_rx_ring = dmem.dmem_addr; 3473 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr; 3474 3475 return 0; 3476 } 3477 3478 static int 3479 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr) 3480 { 3481 if ((paddr & 0xffffffff) == 0) { 3482 /* 3483 * Don't allow lower 32bits of the RX buffer's 3484 * physical address to be 0, else it will break 3485 * hardware pending RSS information delivery 3486 * detection on RX path. 3487 */ 3488 return 1; 3489 } 3490 return 0; 3491 } 3492 3493 static int 3494 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata) 3495 { 3496 bus_addr_t lowaddr; 3497 int i, error; 3498 3499 lowaddr = BUS_SPACE_MAXADDR; 3500 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 3501 /* jme_rxbuf_dma_filter will be called */ 3502 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3503 } 3504 3505 /* Create tag for Rx buffers. */ 3506 error = bus_dma_tag_create( 3507 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */ 3508 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 3509 lowaddr, /* lowaddr */ 3510 BUS_SPACE_MAXADDR, /* highaddr */ 3511 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */ 3512 MCLBYTES, /* maxsize */ 3513 1, /* nsegments */ 3514 MCLBYTES, /* maxsegsize */ 3515 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */ 3516 &rdata->jme_rx_tag); 3517 if (error) { 3518 device_printf(rdata->jme_sc->jme_dev, 3519 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx); 3520 return error; 3521 } 3522 3523 /* Create DMA maps for Rx buffers. */ 3524 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3525 &rdata->jme_rx_sparemap); 3526 if (error) { 3527 device_printf(rdata->jme_sc->jme_dev, 3528 "could not create %dth spare Rx dmamap.\n", 3529 rdata->jme_rx_idx); 3530 bus_dma_tag_destroy(rdata->jme_rx_tag); 3531 rdata->jme_rx_tag = NULL; 3532 return error; 3533 } 3534 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3535 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i]; 3536 3537 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3538 &rxd->rx_dmamap); 3539 if (error) { 3540 int j; 3541 3542 device_printf(rdata->jme_sc->jme_dev, 3543 "could not create %dth Rx dmamap " 3544 "for %dth RX ring.\n", i, rdata->jme_rx_idx); 3545 3546 for (j = 0; j < i; ++j) { 3547 rxd = &rdata->jme_rxdesc[j]; 3548 bus_dmamap_destroy(rdata->jme_rx_tag, 3549 rxd->rx_dmamap); 3550 } 3551 bus_dmamap_destroy(rdata->jme_rx_tag, 3552 rdata->jme_rx_sparemap); 3553 bus_dma_tag_destroy(rdata->jme_rx_tag); 3554 rdata->jme_rx_tag = NULL; 3555 return error; 3556 } 3557 } 3558 return 0; 3559 } 3560 3561 static void 3562 jme_rx_intr(struct jme_softc *sc, uint32_t status) 3563 { 3564 int r; 3565 3566 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3567 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3568 3569 if (status & rdata->jme_rx_coal) { 3570 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3571 jme_rxeof(rdata, -1); 3572 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3573 } 3574 } 3575 } 3576 3577 static void 3578 jme_enable_rss(struct jme_softc *sc) 3579 { 3580 uint32_t rssc, ind; 3581 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE]; 3582 int i; 3583 3584 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 || 3585 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4, 3586 ("%s: invalid # of RX rings (%d)", 3587 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt)); 3588 3589 rssc = RSSC_HASH_64_ENTRY; 3590 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP; 3591 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1; 3592 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc); 3593 CSR_WRITE_4(sc, JME_RSSC, rssc); 3594 3595 toeplitz_get_key(key, sizeof(key)); 3596 for (i = 0; i < RSSKEY_NREGS; ++i) { 3597 uint32_t keyreg; 3598 3599 keyreg = RSSKEY_REGVAL(key, i); 3600 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x, reg 0x%08x\n", 3601 i, keyreg, RSSKEY_REG(RSSKEY_NREGS - 1 - i)); 3602 3603 CSR_WRITE_4(sc, RSSKEY_REG(RSSKEY_NREGS - 1 - i), keyreg); 3604 } 3605 3606 /* 3607 * Create redirect table in following fashion: 3608 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3609 */ 3610 ind = 0; 3611 for (i = 0; i < RSSTBL_REGSIZE; ++i) { 3612 int q; 3613 3614 q = i % sc->jme_cdata.jme_rx_ring_cnt; 3615 ind |= q << (i * 8); 3616 } 3617 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind); 3618 3619 for (i = 0; i < RSSTBL_NREGS; ++i) 3620 CSR_WRITE_4(sc, RSSTBL_REG(i), ind); 3621 } 3622 3623 static void 3624 jme_disable_rss(struct jme_softc *sc) 3625 { 3626 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 3627 } 3628 3629 static void 3630 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3631 { 3632 struct jme_softc *sc = ifp->if_softc; 3633 3634 ifnet_serialize_array_enter(sc->jme_serialize_arr, 3635 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3636 } 3637 3638 static void 3639 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3640 { 3641 struct jme_softc *sc = ifp->if_softc; 3642 3643 ifnet_serialize_array_exit(sc->jme_serialize_arr, 3644 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3645 } 3646 3647 static int 3648 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3649 { 3650 struct jme_softc *sc = ifp->if_softc; 3651 3652 return ifnet_serialize_array_try(sc->jme_serialize_arr, 3653 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3654 } 3655 3656 #ifdef INVARIANTS 3657 3658 static void 3659 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3660 boolean_t serialized) 3661 { 3662 struct jme_softc *sc = ifp->if_softc; 3663 3664 ifnet_serialize_array_assert(sc->jme_serialize_arr, 3665 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, 3666 slz, serialized); 3667 } 3668 3669 #endif /* INVARIANTS */ 3670 3671 static void 3672 jme_msix_try_alloc(device_t dev) 3673 { 3674 struct jme_softc *sc = device_get_softc(dev); 3675 struct jme_msix_data *msix; 3676 int error, i, r, msix_enable, msix_count; 3677 int offset, offset_def; 3678 3679 msix_count = JME_MSIXCNT(sc->jme_cdata.jme_rx_ring_cnt); 3680 KKASSERT(msix_count <= JME_NMSIX); 3681 3682 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable); 3683 3684 /* 3685 * We leave the 1st MSI-X vector unused, so we 3686 * actually need msix_count + 1 MSI-X vectors. 3687 */ 3688 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1)) 3689 return; 3690 3691 for (i = 0; i < msix_count; ++i) 3692 sc->jme_msix[i].jme_msix_rid = -1; 3693 3694 i = 0; 3695 3696 /* 3697 * Setup status MSI-X 3698 */ 3699 3700 msix = &sc->jme_msix[i++]; 3701 msix->jme_msix_cpuid = 0; 3702 msix->jme_msix_arg = sc; 3703 msix->jme_msix_func = jme_msix_status; 3704 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3705 msix->jme_msix_intrs |= 3706 sc->jme_cdata.jme_rx_data[r].jme_rx_empty; 3707 } 3708 msix->jme_msix_serialize = &sc->jme_serialize; 3709 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s sts", 3710 device_get_nameunit(dev)); 3711 3712 /* 3713 * Setup TX MSI-X 3714 */ 3715 3716 offset_def = device_get_unit(dev) % ncpus2; 3717 offset = device_getenv_int(dev, "msix.txoff", offset_def); 3718 if (offset >= ncpus2) { 3719 device_printf(dev, "invalid msix.txoff %d, use %d\n", 3720 offset, offset_def); 3721 offset = offset_def; 3722 } 3723 3724 msix = &sc->jme_msix[i++]; 3725 msix->jme_msix_cpuid = offset; 3726 sc->jme_tx_cpuid = msix->jme_msix_cpuid; 3727 msix->jme_msix_arg = &sc->jme_cdata.jme_tx_data; 3728 msix->jme_msix_func = jme_msix_tx; 3729 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO; 3730 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3731 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx", 3732 device_get_nameunit(dev)); 3733 3734 /* 3735 * Setup RX MSI-X 3736 */ 3737 3738 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 3739 offset = 0; 3740 } else { 3741 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 3742 device_get_unit(dev)) % ncpus2; 3743 3744 offset = device_getenv_int(dev, "msix.rxoff", offset_def); 3745 if (offset >= ncpus2 || 3746 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3747 device_printf(dev, "invalid msix.rxoff %d, use %d\n", 3748 offset, offset_def); 3749 offset = offset_def; 3750 } 3751 } 3752 3753 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3754 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3755 3756 msix = &sc->jme_msix[i++]; 3757 msix->jme_msix_cpuid = r + offset; 3758 KKASSERT(msix->jme_msix_cpuid < ncpus2); 3759 msix->jme_msix_arg = rdata; 3760 msix->jme_msix_func = jme_msix_rx; 3761 msix->jme_msix_intrs = rdata->jme_rx_coal; 3762 msix->jme_msix_serialize = &rdata->jme_rx_serialize; 3763 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), 3764 "%s rx%d", device_get_nameunit(dev), r); 3765 } 3766 3767 KKASSERT(i == msix_count); 3768 3769 error = pci_setup_msix(dev); 3770 if (error) 3771 return; 3772 3773 /* Setup jme_msix_cnt early, so we could cleanup */ 3774 sc->jme_msix_cnt = msix_count; 3775 3776 for (i = 0; i < msix_count; ++i) { 3777 msix = &sc->jme_msix[i]; 3778 3779 msix->jme_msix_vector = i + 1; 3780 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector, 3781 &msix->jme_msix_rid, msix->jme_msix_cpuid); 3782 if (error) 3783 goto back; 3784 3785 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3786 &msix->jme_msix_rid, RF_ACTIVE); 3787 if (msix->jme_msix_res == NULL) { 3788 error = ENOMEM; 3789 goto back; 3790 } 3791 } 3792 3793 for (i = 0; i < JME_INTR_CNT; ++i) { 3794 uint32_t intr_mask = (1 << i); 3795 int x; 3796 3797 if ((JME_INTRS & intr_mask) == 0) 3798 continue; 3799 3800 for (x = 0; x < msix_count; ++x) { 3801 msix = &sc->jme_msix[x]; 3802 if (msix->jme_msix_intrs & intr_mask) { 3803 int reg, shift; 3804 3805 reg = i / JME_MSINUM_FACTOR; 3806 KKASSERT(reg < JME_MSINUM_CNT); 3807 3808 shift = (i % JME_MSINUM_FACTOR) * 4; 3809 3810 sc->jme_msinum[reg] |= 3811 (msix->jme_msix_vector << shift); 3812 3813 break; 3814 } 3815 } 3816 } 3817 3818 if (bootverbose) { 3819 for (i = 0; i < JME_MSINUM_CNT; ++i) { 3820 device_printf(dev, "MSINUM%d: %#x\n", i, 3821 sc->jme_msinum[i]); 3822 } 3823 } 3824 3825 pci_enable_msix(dev); 3826 sc->jme_irq_type = PCI_INTR_TYPE_MSIX; 3827 3828 back: 3829 if (error) 3830 jme_msix_free(dev); 3831 } 3832 3833 static int 3834 jme_intr_alloc(device_t dev) 3835 { 3836 struct jme_softc *sc = device_get_softc(dev); 3837 u_int irq_flags; 3838 3839 jme_msix_try_alloc(dev); 3840 3841 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3842 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable, 3843 &sc->jme_irq_rid, &irq_flags); 3844 3845 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3846 &sc->jme_irq_rid, irq_flags); 3847 if (sc->jme_irq_res == NULL) { 3848 device_printf(dev, "can't allocate irq\n"); 3849 return ENXIO; 3850 } 3851 sc->jme_tx_cpuid = rman_get_cpuid(sc->jme_irq_res); 3852 } 3853 return 0; 3854 } 3855 3856 static void 3857 jme_msix_free(device_t dev) 3858 { 3859 struct jme_softc *sc = device_get_softc(dev); 3860 int i; 3861 3862 KKASSERT(sc->jme_msix_cnt > 1); 3863 3864 for (i = 0; i < sc->jme_msix_cnt; ++i) { 3865 struct jme_msix_data *msix = &sc->jme_msix[i]; 3866 3867 if (msix->jme_msix_res != NULL) { 3868 bus_release_resource(dev, SYS_RES_IRQ, 3869 msix->jme_msix_rid, msix->jme_msix_res); 3870 msix->jme_msix_res = NULL; 3871 } 3872 if (msix->jme_msix_rid >= 0) { 3873 pci_release_msix_vector(dev, msix->jme_msix_rid); 3874 msix->jme_msix_rid = -1; 3875 } 3876 } 3877 pci_teardown_msix(dev); 3878 } 3879 3880 static void 3881 jme_intr_free(device_t dev) 3882 { 3883 struct jme_softc *sc = device_get_softc(dev); 3884 3885 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3886 if (sc->jme_irq_res != NULL) { 3887 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid, 3888 sc->jme_irq_res); 3889 } 3890 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI) 3891 pci_release_msi(dev); 3892 } else { 3893 jme_msix_free(dev); 3894 } 3895 } 3896 3897 static void 3898 jme_msix_tx(void *xtdata) 3899 { 3900 struct jme_txdata *tdata = xtdata; 3901 struct jme_softc *sc = tdata->jme_sc; 3902 struct ifnet *ifp = &sc->arpcom.ac_if; 3903 3904 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3905 3906 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3907 3908 CSR_WRITE_4(sc, JME_INTR_STATUS, 3909 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP); 3910 3911 if (ifp->if_flags & IFF_RUNNING) { 3912 jme_txeof(tdata); 3913 if (!ifq_is_empty(&ifp->if_snd)) 3914 if_devstart(ifp); 3915 } 3916 3917 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3918 } 3919 3920 static void 3921 jme_msix_rx(void *xrdata) 3922 { 3923 struct jme_rxdata *rdata = xrdata; 3924 struct jme_softc *sc = rdata->jme_sc; 3925 struct ifnet *ifp = &sc->arpcom.ac_if; 3926 3927 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3928 3929 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, rdata->jme_rx_coal); 3930 3931 CSR_WRITE_4(sc, JME_INTR_STATUS, 3932 rdata->jme_rx_coal | rdata->jme_rx_comp); 3933 3934 if (ifp->if_flags & IFF_RUNNING) 3935 jme_rxeof(rdata, -1); 3936 3937 CSR_WRITE_4(sc, JME_INTR_MASK_SET, rdata->jme_rx_coal); 3938 } 3939 3940 static void 3941 jme_msix_status(void *xsc) 3942 { 3943 struct jme_softc *sc = xsc; 3944 struct ifnet *ifp = &sc->arpcom.ac_if; 3945 uint32_t status; 3946 3947 ASSERT_SERIALIZED(&sc->jme_serialize); 3948 3949 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_RXQ_DESC_EMPTY); 3950 3951 status = CSR_READ_4(sc, JME_INTR_STATUS); 3952 3953 if (status & INTR_RXQ_DESC_EMPTY) { 3954 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3955 if (ifp->if_flags & IFF_RUNNING) 3956 jme_rx_restart(sc, status); 3957 } 3958 3959 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_RXQ_DESC_EMPTY); 3960 } 3961 3962 static void 3963 jme_rx_restart(struct jme_softc *sc, uint32_t status) 3964 { 3965 int i; 3966 3967 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3968 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 3969 3970 if (status & rdata->jme_rx_empty) { 3971 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3972 jme_rxeof(rdata, -1); 3973 #ifdef JME_RSS_DEBUG 3974 rdata->jme_rx_emp++; 3975 #endif 3976 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3977 } 3978 } 3979 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 3980 RXCSR_RXQ_START); 3981 } 3982 3983 static void 3984 jme_set_msinum(struct jme_softc *sc) 3985 { 3986 int i; 3987 3988 for (i = 0; i < JME_MSINUM_CNT; ++i) 3989 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]); 3990 } 3991 3992 static int 3993 jme_intr_setup(device_t dev) 3994 { 3995 struct jme_softc *sc = device_get_softc(dev); 3996 int error; 3997 3998 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 3999 return jme_msix_setup(dev); 4000 4001 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, 4002 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize); 4003 if (error) { 4004 device_printf(dev, "could not set up interrupt handler.\n"); 4005 return error; 4006 } 4007 4008 return 0; 4009 } 4010 4011 static void 4012 jme_intr_teardown(device_t dev) 4013 { 4014 struct jme_softc *sc = device_get_softc(dev); 4015 4016 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 4017 jme_msix_teardown(dev, sc->jme_msix_cnt); 4018 else 4019 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle); 4020 } 4021 4022 static int 4023 jme_msix_setup(device_t dev) 4024 { 4025 struct jme_softc *sc = device_get_softc(dev); 4026 int x; 4027 4028 for (x = 0; x < sc->jme_msix_cnt; ++x) { 4029 struct jme_msix_data *msix = &sc->jme_msix[x]; 4030 int error; 4031 4032 error = bus_setup_intr_descr(dev, msix->jme_msix_res, 4033 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg, 4034 &msix->jme_msix_handle, msix->jme_msix_serialize, 4035 msix->jme_msix_desc); 4036 if (error) { 4037 device_printf(dev, "could not set up %s " 4038 "interrupt handler.\n", msix->jme_msix_desc); 4039 jme_msix_teardown(dev, x); 4040 return error; 4041 } 4042 } 4043 return 0; 4044 } 4045 4046 static void 4047 jme_msix_teardown(device_t dev, int msix_count) 4048 { 4049 struct jme_softc *sc = device_get_softc(dev); 4050 int x; 4051 4052 for (x = 0; x < msix_count; ++x) { 4053 struct jme_msix_data *msix = &sc->jme_msix[x]; 4054 4055 bus_teardown_intr(dev, msix->jme_msix_res, 4056 msix->jme_msix_handle); 4057 } 4058 } 4059 4060 static void 4061 jme_serialize_skipmain(struct jme_softc *sc) 4062 { 4063 lwkt_serialize_array_enter(sc->jme_serialize_arr, 4064 sc->jme_serialize_cnt, 1); 4065 } 4066 4067 static void 4068 jme_deserialize_skipmain(struct jme_softc *sc) 4069 { 4070 lwkt_serialize_array_exit(sc->jme_serialize_arr, 4071 sc->jme_serialize_cnt, 1); 4072 } 4073 4074 static void 4075 jme_enable_intr(struct jme_softc *sc) 4076 { 4077 int i; 4078 4079 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4080 lwkt_serialize_handler_enable(sc->jme_serialize_arr[i]); 4081 4082 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 4083 } 4084 4085 static void 4086 jme_disable_intr(struct jme_softc *sc) 4087 { 4088 int i; 4089 4090 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 4091 4092 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4093 lwkt_serialize_handler_disable(sc->jme_serialize_arr[i]); 4094 } 4095