1 /* 2 * Copyright (c) 2001-2013, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IX_H_ 33 #define _IF_IX_H_ 34 35 /* Tunables */ 36 37 /* 38 * MSI-X count 39 */ 40 #define IX_MAX_MSIX 64 41 #define IX_MAX_MSIX_82598 16 42 43 /* 44 * RX ring count 45 */ 46 #define IX_MAX_RXRING 16 47 #define IX_MAX_RXRING_X550 64 48 #define IX_MIN_RXRING_RSS 2 49 50 /* 51 * TX ring count 52 */ 53 #define IX_MAX_TXRING 16 54 #define IX_MAX_TXRING_82598 32 55 #define IX_MAX_TXRING_82599 64 56 #define IX_MAX_TXRING_X540 64 57 #define IX_MAX_TXRING_X550 64 58 59 /* 60 * Default number of segments received before writing to RX related registers 61 */ 62 #define IX_DEF_RXWREG_NSEGS 32 63 64 /* 65 * Default number of segments sent before writing to TX related registers 66 */ 67 #define IX_DEF_TXWREG_NSEGS 8 68 69 /* 70 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 71 * number of transmit descriptors allocated by the driver. Increasing this 72 * value allows the driver to queue more transmits. Each descriptor is 16 73 * bytes. Performance tests have show the 2K value to be optimal for top 74 * performance. 75 */ 76 #define IX_DEF_TXD 1024 77 #define IX_PERF_TXD 2048 78 #define IX_MAX_TXD 4096 79 #define IX_MIN_TXD 64 80 81 /* 82 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 83 * number of receive descriptors allocated for each RX queue. Increasing this 84 * value allows the driver to buffer more incoming packets. Each descriptor 85 * is 16 bytes. A receive buffer is also allocated for each descriptor. 86 * 87 * Note: with 8 rings and a dual port card, it is possible to bump up 88 * against the system mbuf pool limit, you can tune nmbclusters 89 * to adjust for this. 90 */ 91 #define IX_DEF_RXD 1024 92 #define IX_PERF_RXD 2048 93 #define IX_MAX_RXD 4096 94 #define IX_MIN_RXD 64 95 96 /* Alignment for rings */ 97 #define IX_DBA_ALIGN 128 98 99 #define IX_MAX_FRAME_SIZE 9728 100 #define IX_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN) 101 #define IX_MAX_MTU (IX_MAX_FRAME_SIZE - IX_MTU_HDR) 102 103 104 /* Flow control constants */ 105 #define IX_FC_PAUSE 0xFFFF 106 #define IX_FC_HI 0x20000 107 #define IX_FC_LO 0x10000 108 109 /* 110 * RSS related registers 111 */ 112 #define IX_NRSSRK 10 113 #define IX_RSSRK_SIZE 4 114 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \ 115 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \ 116 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \ 117 key[(i) * IX_RSSRK_SIZE + 3] << 24) 118 #define IX_NRETA 32 119 #define IX_NRETA_X550 128 120 #define IX_RETA_SIZE 4 121 122 /* 123 * EITR 124 */ 125 #define IX_EITR_INTVL_MASK_82598 0xffff 126 #define IX_EITR_INTVL_MASK 0x0fff 127 #define IX_EITR_INTVL_RSVD_MASK 0x0007 128 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR 129 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR 130 131 /* 132 * Used for optimizing small rx mbufs. Effort is made to keep the copy 133 * small and aligned for the CPU L1 cache. 134 * 135 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 136 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 137 * wasted. Getting 64 byte alignment, which _should_ be ideal for 138 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 139 * in observed efficiency of the optimization, 97.9% -> 81.8%. 140 */ 141 #define IX_RX_COPY_LEN 160 142 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN) 143 144 #define IX_MAX_MCASTADDR 128 145 146 #define IX_MSIX_BAR_82598 3 147 #define IX_MSIX_BAR_82599 4 148 149 #define IX_TSO_SIZE (IP_MAXPACKET + \ 150 sizeof(struct ether_vlan_header)) 151 152 /* 153 * MUST be less than 38. Though 82598 does not have this limit, 154 * we don't want long TX chain. 33 should be large enough even 155 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header). 156 * 157 * Reference: 158 * - 82599 datasheet 7.2.1.1 159 * - X540 datasheet 7.2.1.1 160 */ 161 #define IX_MAX_SCATTER 33 162 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */ 163 164 /* MSI and legacy interrupt */ 165 #define IX_TX_INTR_VEC 0 166 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC) 167 #define IX_RX0_INTR_VEC 1 168 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC) 169 #define IX_RX1_INTR_VEC 2 170 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC) 171 172 #define IX_INTR_RATE 8000 173 #define IX_MSIX_RX_RATE 8000 174 #define IX_MSIX_TX_RATE 6000 175 176 /* IOCTL define to gather SFP+ Diagnostic data */ 177 #define SIOCGI2C SIOCGIFGENERIC 178 179 /* TX checksum offload */ 180 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 181 182 #define IX_EICR_STATUS (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \ 183 IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \ 184 IXGBE_EICR_TS) 185 186 /* This is used to get SFP+ module data */ 187 struct ix_i2c_req { 188 uint8_t dev_addr; 189 uint8_t offset; 190 uint8_t len; 191 uint8_t data[8]; 192 }; 193 194 struct ix_tx_buf { 195 struct mbuf *m_head; 196 bus_dmamap_t map; 197 }; 198 199 struct ix_rx_buf { 200 struct mbuf *m_head; 201 struct mbuf *fmp; 202 struct mbuf *lmp; 203 bus_dmamap_t map; 204 bus_addr_t paddr; 205 u_int flags; 206 #define IX_RX_COPY 0x1 207 }; 208 209 struct ix_softc; 210 211 struct ix_tx_ring { 212 struct lwkt_serialize tx_serialize; 213 struct ifaltq_subque *tx_ifsq; 214 struct ix_softc *tx_sc; 215 volatile uint32_t *tx_hdr; 216 union ixgbe_adv_tx_desc *tx_base; 217 struct ix_tx_buf *tx_buf; 218 bus_dma_tag_t tx_tag; 219 uint16_t tx_flags; 220 #define IX_TXFLAG_ENABLED 0x1 221 uint16_t tx_pad; 222 uint32_t tx_idx; 223 uint16_t tx_avail; 224 uint16_t tx_next_avail; 225 uint16_t tx_next_clean; 226 uint16_t tx_ndesc; 227 uint16_t tx_wreg_nsegs; 228 uint16_t tx_intr_nsegs; 229 uint16_t tx_nsegs; 230 int16_t tx_intr_vec; 231 int tx_intr_cpuid; 232 uint32_t tx_eims; 233 uint32_t tx_eims_val; 234 struct ifsubq_watchdog tx_watchdog; 235 236 bus_dma_tag_t tx_base_dtag; 237 bus_dmamap_t tx_base_map; 238 bus_addr_t tx_base_paddr; 239 240 bus_dma_tag_t tx_hdr_dtag; 241 bus_dmamap_t tx_hdr_map; 242 bus_addr_t tx_hdr_paddr; 243 } __cachealign; 244 245 struct ix_rx_ring { 246 struct lwkt_serialize rx_serialize; 247 struct ix_softc *rx_sc; 248 union ixgbe_adv_rx_desc *rx_base; 249 struct ix_rx_buf *rx_buf; 250 bus_dma_tag_t rx_tag; 251 bus_dmamap_t rx_sparemap; 252 uint32_t rx_idx; 253 uint16_t rx_flags; 254 #define IX_RXRING_FLAG_LRO 0x01 255 #define IX_RXRING_FLAG_DISC 0x02 256 uint16_t rx_next_check; 257 uint16_t rx_ndesc; 258 uint16_t rx_mbuf_sz; 259 uint16_t rx_wreg_nsegs; 260 int16_t rx_intr_vec; 261 uint32_t rx_eims; 262 uint32_t rx_eims_val; 263 struct ix_tx_ring *rx_txr; /* piggybacked TX ring */ 264 265 #ifdef IX_RSS_DEBUG 266 u_long rx_pkts; 267 #endif 268 269 bus_dma_tag_t rx_base_dtag; 270 bus_dmamap_t rx_base_map; 271 bus_addr_t rx_base_paddr; 272 } __cachealign; 273 274 struct ix_intr_data { 275 struct lwkt_serialize *intr_serialize; 276 driver_intr_t *intr_func; 277 void *intr_hand; 278 struct resource *intr_res; 279 void *intr_funcarg; 280 int intr_rid; 281 int intr_cpuid; 282 int intr_rate; 283 int intr_use; 284 #define IX_INTR_USE_RXTX 0 285 #define IX_INTR_USE_STATUS 1 286 #define IX_INTR_USE_RX 2 287 #define IX_INTR_USE_TX 3 288 const char *intr_desc; 289 char intr_desc0[64]; 290 }; 291 292 struct ix_softc { 293 struct arpcom arpcom; 294 295 struct ixgbe_hw hw; 296 struct ixgbe_osdep osdep; 297 298 struct lwkt_serialize main_serialize; 299 uint32_t intr_mask; 300 301 boolean_t link_active; 302 303 int rx_ring_inuse; 304 int tx_ring_inuse; 305 306 struct ix_rx_ring *rx_rings; 307 struct ix_tx_ring *tx_rings; 308 309 struct callout timer; 310 int timer_cpuid; 311 312 int ifm_media; /* IFM_ */ 313 uint32_t link_speed; 314 bool link_up; 315 boolean_t sfp_probe; /* plyggable optics */ 316 317 struct ixgbe_hw_stats stats; 318 319 int rx_ring_cnt; 320 int rx_ring_msix; 321 322 int tx_ring_cnt; 323 int tx_ring_msix; 324 325 int intr_type; 326 int intr_cnt; 327 struct ix_intr_data *intr_data; 328 329 device_t dev; 330 bus_dma_tag_t parent_tag; 331 struct ifmedia media; 332 333 struct resource *mem_res; 334 int mem_rid; 335 336 struct resource *msix_mem_res; 337 int msix_mem_rid; 338 339 int nserialize; 340 struct lwkt_serialize **serializes; 341 342 uint8_t *mta; /* Multicast array memory */ 343 344 int if_flags; 345 int advspeed; /* advertised link speeds */ 346 uint32_t wufc; /* power management */ 347 uint16_t dmac; /* DMA coalescing */ 348 uint16_t max_frame_size; 349 int16_t sts_msix_vec; /* status MSI-X vector */ 350 351 int rx_npoll_off; 352 int tx_npoll_off; 353 354 #ifdef IX_RSS_DEBUG 355 int rss_debug; 356 #endif 357 }; 358 359 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 360 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 361 362 #endif /* _IF_IX_H_ */ 363