1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/sysctl.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/endian.h> 37 #include <sys/firmware.h> 38 #include <sys/limits.h> 39 #include <sys/module.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/libkern.h> 43 44 #include <sys/bus.h> 45 #include <sys/resource.h> 46 #include <machine/clock.h> 47 48 #include <bus/pci/pcireg.h> 49 #include <bus/pci/pcivar.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/ifq_var.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/if_ether.h> 64 #include <netinet/ip.h> 65 66 #include <netproto/802_11/ieee80211_var.h> 67 #include <netproto/802_11/ieee80211_radiotap.h> 68 #include <netproto/802_11/ieee80211_regdomain.h> 69 #include <netproto/802_11/ieee80211_ratectl.h> 70 71 #include "if_iwnreg.h" 72 #include "if_iwnvar.h" 73 74 static int iwn_pci_probe(device_t); 75 static int iwn_pci_attach(device_t); 76 static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 77 static void iwn_radiotap_attach(struct iwn_softc *); 78 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 79 const char name[IFNAMSIZ], int unit, int opmode, 80 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 81 const uint8_t mac[IEEE80211_ADDR_LEN]); 82 static void iwn_vap_delete(struct ieee80211vap *); 83 static int iwn_cleanup(device_t); 84 static int iwn_pci_detach(device_t); 85 static int iwn_nic_lock(struct iwn_softc *); 86 static int iwn_eeprom_lock(struct iwn_softc *); 87 static int iwn_init_otprom(struct iwn_softc *); 88 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 89 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 90 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 91 void **, bus_size_t, bus_size_t, int); 92 static void iwn_dma_contig_free(struct iwn_dma_info *); 93 static int iwn_alloc_sched(struct iwn_softc *); 94 static void iwn_free_sched(struct iwn_softc *); 95 static int iwn_alloc_kw(struct iwn_softc *); 96 static void iwn_free_kw(struct iwn_softc *); 97 static int iwn_alloc_ict(struct iwn_softc *); 98 static void iwn_free_ict(struct iwn_softc *); 99 static int iwn_alloc_fwmem(struct iwn_softc *); 100 static void iwn_free_fwmem(struct iwn_softc *); 101 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 102 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 103 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 104 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 105 int); 106 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 107 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 108 static void iwn5000_ict_reset(struct iwn_softc *); 109 static int iwn_read_eeprom(struct iwn_softc *, 110 uint8_t macaddr[IEEE80211_ADDR_LEN]); 111 static void iwn4965_read_eeprom(struct iwn_softc *); 112 static void iwn4965_print_power_group(struct iwn_softc *, int); 113 static void iwn5000_read_eeprom(struct iwn_softc *); 114 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 115 static void iwn_read_eeprom_band(struct iwn_softc *, int); 116 #if 0 /* HT */ 117 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 118 #endif 119 static void iwn_read_eeprom_channels(struct iwn_softc *, int, 120 uint32_t); 121 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 122 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 123 const uint8_t mac[IEEE80211_ADDR_LEN]); 124 static void iwn_newassoc(struct ieee80211_node *, int); 125 static int iwn_media_change(struct ifnet *); 126 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 127 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 128 struct iwn_rx_data *); 129 static void iwn_timer_callout(void *); 130 static void iwn_calib_reset(struct iwn_softc *); 131 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 132 struct iwn_rx_data *); 133 #if 0 /* HT */ 134 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 135 struct iwn_rx_data *); 136 #endif 137 static void iwn5000_rx_calib_results(struct iwn_softc *, 138 struct iwn_rx_desc *, struct iwn_rx_data *); 139 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 140 struct iwn_rx_data *); 141 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 142 struct iwn_rx_data *); 143 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 144 struct iwn_rx_data *); 145 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 146 uint8_t); 147 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 148 static void iwn_notif_intr(struct iwn_softc *); 149 static void iwn_wakeup_intr(struct iwn_softc *); 150 static void iwn_rftoggle_intr(struct iwn_softc *); 151 static void iwn_fatal_intr(struct iwn_softc *); 152 static void iwn_intr(void *); 153 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 154 uint16_t); 155 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 156 uint16_t); 157 #ifdef notyet 158 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 159 #endif 160 static uint8_t iwn_plcp_signal(int); 161 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 162 struct ieee80211_node *, struct iwn_tx_ring *); 163 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 164 const struct ieee80211_bpf_params *); 165 static void iwn_start(struct ifnet *, struct ifaltq_subque *); 166 static void iwn_start_locked(struct ifnet *); 167 static void iwn_watchdog(struct iwn_softc *sc); 168 static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 169 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 170 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 171 int); 172 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 173 int); 174 static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int); 175 static int iwn_add_broadcast_node(struct iwn_softc *, int); 176 static int iwn_wme_update(struct ieee80211com *); 177 static void iwn_update_mcast(struct ifnet *); 178 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 179 static int iwn_set_critical_temp(struct iwn_softc *); 180 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 181 static void iwn4965_power_calibration(struct iwn_softc *, int); 182 static int iwn4965_set_txpower(struct iwn_softc *, 183 struct ieee80211_channel *, int); 184 static int iwn5000_set_txpower(struct iwn_softc *, 185 struct ieee80211_channel *, int); 186 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 187 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 188 static int iwn_get_noise(const struct iwn_rx_general_stats *); 189 static int iwn4965_get_temperature(struct iwn_softc *); 190 static int iwn5000_get_temperature(struct iwn_softc *); 191 static int iwn_init_sensitivity(struct iwn_softc *); 192 static void iwn_collect_noise(struct iwn_softc *, 193 const struct iwn_rx_general_stats *); 194 static int iwn4965_init_gains(struct iwn_softc *); 195 static int iwn5000_init_gains(struct iwn_softc *); 196 static int iwn4965_set_gains(struct iwn_softc *); 197 static int iwn5000_set_gains(struct iwn_softc *); 198 static void iwn_tune_sensitivity(struct iwn_softc *, 199 const struct iwn_rx_stats *); 200 static int iwn_send_sensitivity(struct iwn_softc *); 201 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 202 static int iwn_config(struct iwn_softc *); 203 static int iwn_scan(struct iwn_softc *); 204 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 205 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 206 #if 0 /* HT */ 207 static int iwn_ampdu_rx_start(struct ieee80211com *, 208 struct ieee80211_node *, uint8_t); 209 static void iwn_ampdu_rx_stop(struct ieee80211com *, 210 struct ieee80211_node *, uint8_t); 211 static int iwn_ampdu_tx_start(struct ieee80211com *, 212 struct ieee80211_node *, uint8_t); 213 static void iwn_ampdu_tx_stop(struct ieee80211com *, 214 struct ieee80211_node *, uint8_t); 215 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 216 struct ieee80211_node *, uint8_t, uint16_t); 217 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 218 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 219 struct ieee80211_node *, uint8_t, uint16_t); 220 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 221 #endif 222 static int iwn5000_query_calibration(struct iwn_softc *); 223 static int iwn5000_send_calibration(struct iwn_softc *); 224 static int iwn5000_send_wimax_coex(struct iwn_softc *); 225 static int iwn4965_post_alive(struct iwn_softc *); 226 static int iwn5000_post_alive(struct iwn_softc *); 227 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 228 int); 229 static int iwn4965_load_firmware(struct iwn_softc *); 230 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 231 const uint8_t *, int); 232 static int iwn5000_load_firmware(struct iwn_softc *); 233 static int iwn_read_firmware(struct iwn_softc *); 234 static int iwn_clock_wait(struct iwn_softc *); 235 static int iwn_apm_init(struct iwn_softc *); 236 static void iwn_apm_stop_master(struct iwn_softc *); 237 static void iwn_apm_stop(struct iwn_softc *); 238 static int iwn4965_nic_config(struct iwn_softc *); 239 static int iwn5000_nic_config(struct iwn_softc *); 240 static int iwn_hw_prepare(struct iwn_softc *); 241 static int iwn_hw_init(struct iwn_softc *); 242 static void iwn_hw_stop(struct iwn_softc *); 243 static void iwn_init_locked(struct iwn_softc *); 244 static void iwn_init(void *); 245 static void iwn_stop_locked(struct iwn_softc *); 246 static void iwn_stop(struct iwn_softc *); 247 static void iwn_scan_start(struct ieee80211com *); 248 static void iwn_scan_end(struct ieee80211com *); 249 static void iwn_set_channel(struct ieee80211com *); 250 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 251 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 252 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 253 struct ieee80211_channel *); 254 static int iwn_setregdomain(struct ieee80211com *, 255 struct ieee80211_regdomain *, int, 256 struct ieee80211_channel []); 257 static void iwn_hw_reset_task(void *, int); 258 static void iwn_radio_on_task(void *, int); 259 static void iwn_radio_off_task(void *, int); 260 static void iwn_sysctlattach(struct iwn_softc *); 261 static int iwn_pci_shutdown(device_t); 262 static int iwn_pci_suspend(device_t); 263 static int iwn_pci_resume(device_t); 264 265 #define IWN_DEBUG 266 #ifdef IWN_DEBUG 267 enum { 268 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 269 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 270 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 271 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 272 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 273 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 274 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 275 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 276 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 277 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 278 IWN_DEBUG_NODE = 0x00000400, /* node management */ 279 IWN_DEBUG_LED = 0x00000800, /* led management */ 280 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 281 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 282 IWN_DEBUG_ANY = 0xffffffff 283 }; 284 285 #define DPRINTF(sc, m, fmt, ...) do { \ 286 if (sc->sc_debug & (m)) \ 287 kprintf(fmt, __VA_ARGS__); \ 288 } while (0) 289 290 static const char *iwn_intr_str(uint8_t); 291 #else 292 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 293 #endif 294 295 struct iwn_ident { 296 uint16_t vendor; 297 uint16_t device; 298 const char *name; 299 }; 300 301 static const struct iwn_ident iwn_ident_table [] = { 302 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" }, 303 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" }, 304 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" }, 305 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" }, 306 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" }, 307 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" }, 308 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" }, 309 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" }, 310 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" }, 311 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" }, 312 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" }, 313 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" }, 314 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" }, 315 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" }, 316 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" }, 317 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" }, 318 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" }, 319 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" }, 320 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" }, 321 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" }, 322 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" }, 323 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" }, 324 { 0x8086, 0x08AE, "Intel(R) Centrino Wireless-N 100" }, 325 { 0, 0, NULL } 326 }; 327 328 static const struct iwn_hal iwn4965_hal = { 329 iwn4965_load_firmware, 330 iwn4965_read_eeprom, 331 iwn4965_post_alive, 332 iwn4965_nic_config, 333 iwn4965_update_sched, 334 iwn4965_get_temperature, 335 iwn4965_get_rssi, 336 iwn4965_set_txpower, 337 iwn4965_init_gains, 338 iwn4965_set_gains, 339 iwn4965_add_node, 340 iwn4965_tx_done, 341 #if 0 /* HT */ 342 iwn4965_ampdu_tx_start, 343 iwn4965_ampdu_tx_stop, 344 #endif 345 IWN4965_NTXQUEUES, 346 IWN4965_NDMACHNLS, 347 IWN4965_ID_BROADCAST, 348 IWN4965_RXONSZ, 349 IWN4965_SCHEDSZ, 350 IWN4965_FW_TEXT_MAXSZ, 351 IWN4965_FW_DATA_MAXSZ, 352 IWN4965_FWSZ, 353 IWN4965_SCHED_TXFACT 354 }; 355 356 static const struct iwn_hal iwn5000_hal = { 357 iwn5000_load_firmware, 358 iwn5000_read_eeprom, 359 iwn5000_post_alive, 360 iwn5000_nic_config, 361 iwn5000_update_sched, 362 iwn5000_get_temperature, 363 iwn5000_get_rssi, 364 iwn5000_set_txpower, 365 iwn5000_init_gains, 366 iwn5000_set_gains, 367 iwn5000_add_node, 368 iwn5000_tx_done, 369 #if 0 /* HT */ 370 iwn5000_ampdu_tx_start, 371 iwn5000_ampdu_tx_stop, 372 #endif 373 IWN5000_NTXQUEUES, 374 IWN5000_NDMACHNLS, 375 IWN5000_ID_BROADCAST, 376 IWN5000_RXONSZ, 377 IWN5000_SCHEDSZ, 378 IWN5000_FW_TEXT_MAXSZ, 379 IWN5000_FW_DATA_MAXSZ, 380 IWN5000_FWSZ, 381 IWN5000_SCHED_TXFACT 382 }; 383 384 static int 385 iwn_pci_probe(device_t dev) 386 { 387 const struct iwn_ident *ident; 388 389 /* no wlan serializer needed */ 390 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 391 if (pci_get_vendor(dev) == ident->vendor && 392 pci_get_device(dev) == ident->device) { 393 device_set_desc(dev, ident->name); 394 return 0; 395 } 396 } 397 return ENXIO; 398 } 399 400 static int 401 iwn_pci_attach(device_t dev) 402 { 403 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 404 struct ieee80211com *ic; 405 struct ifnet *ifp; 406 const struct iwn_hal *hal; 407 uint32_t tmp; 408 int i, error; 409 #ifdef OLD_MSI 410 int result; 411 #endif 412 uint8_t macaddr[IEEE80211_ADDR_LEN]; 413 char ethstr[ETHER_ADDRSTRLEN + 1]; 414 415 wlan_serialize_enter(); 416 417 sc->sc_dev = dev; 418 sc->sc_dmat = NULL; 419 420 if (bus_dma_tag_create(sc->sc_dmat, 421 1, 0, 422 BUS_SPACE_MAXADDR_32BIT, 423 BUS_SPACE_MAXADDR, 424 NULL, NULL, 425 BUS_SPACE_MAXSIZE, 426 IWN_MAX_SCATTER, 427 BUS_SPACE_MAXSIZE, 428 BUS_DMA_ALLOCNOW, 429 &sc->sc_dmat)) { 430 device_printf(dev, "cannot allocate DMA tag\n"); 431 error = ENOMEM; 432 goto fail; 433 } 434 435 436 437 /* prepare sysctl tree for use in sub modules */ 438 sysctl_ctx_init(&sc->sc_sysctl_ctx); 439 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 440 SYSCTL_STATIC_CHILDREN(_hw), 441 OID_AUTO, 442 device_get_nameunit(sc->sc_dev), 443 CTLFLAG_RD, 0, ""); 444 445 /* 446 * Get the offset of the PCI Express Capability Structure in PCI 447 * Configuration Space. 448 */ 449 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 450 if (error != 0) { 451 device_printf(dev, "PCIe capability structure not found!\n"); 452 goto fail2; 453 } 454 455 /* Clear device-specific "PCI retry timeout" register (41h). */ 456 pci_write_config(dev, 0x41, 0, 1); 457 458 /* Hardware bug workaround. */ 459 tmp = pci_read_config(dev, PCIR_COMMAND, 1); 460 if (tmp & PCIM_CMD_INTxDIS) { 461 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 462 __func__); 463 tmp &= ~PCIM_CMD_INTxDIS; 464 pci_write_config(dev, PCIR_COMMAND, tmp, 1); 465 } 466 467 /* Enable bus-mastering. */ 468 pci_enable_busmaster(dev); 469 470 sc->mem_rid = PCIR_BAR(0); 471 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 472 RF_ACTIVE); 473 if (sc->mem == NULL ) { 474 device_printf(dev, "could not allocate memory resources\n"); 475 error = ENOMEM; 476 goto fail2; 477 } 478 479 sc->sc_st = rman_get_bustag(sc->mem); 480 sc->sc_sh = rman_get_bushandle(sc->mem); 481 sc->irq_rid = 0; 482 #ifdef OLD_MSI 483 if ((result = pci_msi_count(dev)) == 1 && 484 pci_alloc_msi(dev, &result) == 0) 485 sc->irq_rid = 1; 486 #endif 487 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 488 RF_ACTIVE | RF_SHAREABLE); 489 if (sc->irq == NULL) { 490 device_printf(dev, "could not allocate interrupt resource\n"); 491 error = ENOMEM; 492 goto fail; 493 } 494 495 callout_init(&sc->sc_timer_to); 496 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset_task, sc ); 497 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on_task, sc ); 498 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off_task, sc ); 499 500 /* Attach Hardware Abstraction Layer. */ 501 hal = iwn_hal_attach(sc); 502 if (hal == NULL) { 503 error = ENXIO; /* XXX: Wrong error code? */ 504 goto fail; 505 } 506 507 error = iwn_hw_prepare(sc); 508 if (error != 0) { 509 device_printf(dev, "hardware not ready, error %d\n", error); 510 goto fail; 511 } 512 513 /* Allocate DMA memory for firmware transfers. */ 514 error = iwn_alloc_fwmem(sc); 515 if (error != 0) { 516 device_printf(dev, 517 "could not allocate memory for firmware, error %d\n", 518 error); 519 goto fail; 520 } 521 522 /* Allocate "Keep Warm" page. */ 523 error = iwn_alloc_kw(sc); 524 if (error != 0) { 525 device_printf(dev, 526 "could not allocate \"Keep Warm\" page, error %d\n", error); 527 goto fail; 528 } 529 530 /* Allocate ICT table for 5000 Series. */ 531 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 532 (error = iwn_alloc_ict(sc)) != 0) { 533 device_printf(dev, 534 "%s: could not allocate ICT table, error %d\n", 535 __func__, error); 536 goto fail; 537 } 538 539 /* Allocate TX scheduler "rings". */ 540 error = iwn_alloc_sched(sc); 541 if (error != 0) { 542 device_printf(dev, 543 "could not allocate TX scheduler rings, error %d\n", 544 error); 545 goto fail; 546 } 547 548 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */ 549 for (i = 0; i < hal->ntxqs; i++) { 550 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i); 551 if (error != 0) { 552 device_printf(dev, 553 "could not allocate Tx ring %d, error %d\n", 554 i, error); 555 goto fail; 556 } 557 } 558 559 /* Allocate RX ring. */ 560 error = iwn_alloc_rx_ring(sc, &sc->rxq); 561 if (error != 0 ){ 562 device_printf(dev, 563 "could not allocate Rx ring, error %d\n", error); 564 goto fail; 565 } 566 567 /* Clear pending interrupts. */ 568 IWN_WRITE(sc, IWN_INT, 0xffffffff); 569 570 /* Count the number of available chains. */ 571 sc->ntxchains = 572 ((sc->txchainmask >> 2) & 1) + 573 ((sc->txchainmask >> 1) & 1) + 574 ((sc->txchainmask >> 0) & 1); 575 sc->nrxchains = 576 ((sc->rxchainmask >> 2) & 1) + 577 ((sc->rxchainmask >> 1) & 1) + 578 ((sc->rxchainmask >> 0) & 1); 579 580 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 581 if (ifp == NULL) { 582 device_printf(dev, "can not allocate ifnet structure\n"); 583 goto fail; 584 } 585 ic = ifp->if_l2com; 586 587 ic->ic_ifp = ifp; 588 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 589 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 590 591 /* Set device capabilities. */ 592 ic->ic_caps = 593 IEEE80211_C_STA /* station mode supported */ 594 | IEEE80211_C_MONITOR /* monitor mode supported */ 595 | IEEE80211_C_TXPMGT /* tx power management */ 596 | IEEE80211_C_SHSLOT /* short slot time supported */ 597 | IEEE80211_C_WPA 598 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 599 | IEEE80211_C_BGSCAN /* background scanning */ 600 #if 0 601 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 602 #endif 603 | IEEE80211_C_WME /* WME */ 604 ; 605 #if 0 /* HT */ 606 /* XXX disable until HT channel setup works */ 607 ic->ic_htcaps = 608 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 609 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 610 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 611 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 612 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 613 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 614 /* s/w capabilities */ 615 | IEEE80211_HTC_HT /* HT operation */ 616 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 617 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 618 ; 619 620 /* Set HT capabilities. */ 621 ic->ic_htcaps = 622 #if IWN_RBUF_SIZE == 8192 623 IEEE80211_HTCAP_AMSDU7935 | 624 #endif 625 IEEE80211_HTCAP_CBW20_40 | 626 IEEE80211_HTCAP_SGI20 | 627 IEEE80211_HTCAP_SGI40; 628 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 629 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 630 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 631 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 632 else 633 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 634 #endif 635 636 /* Read MAC address, channels, etc from EEPROM. */ 637 error = iwn_read_eeprom(sc, macaddr); 638 if (error != 0) { 639 device_printf(dev, "could not read EEPROM, error %d\n", 640 error); 641 goto fail; 642 } 643 644 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %s\n", 645 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 646 kether_ntoa(macaddr, ethstr)); 647 648 #if 0 /* HT */ 649 /* Set supported HT rates. */ 650 ic->ic_sup_mcs[0] = 0xff; 651 if (sc->nrxchains > 1) 652 ic->ic_sup_mcs[1] = 0xff; 653 if (sc->nrxchains > 2) 654 ic->ic_sup_mcs[2] = 0xff; 655 #endif 656 657 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 658 ifp->if_softc = sc; 659 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 660 ifp->if_init = iwn_init; 661 ifp->if_ioctl = iwn_ioctl; 662 ifp->if_start = iwn_start; 663 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 664 ifq_set_ready(&ifp->if_snd); 665 666 ieee80211_ifattach(ic, macaddr); 667 ic->ic_vap_create = iwn_vap_create; 668 ic->ic_vap_delete = iwn_vap_delete; 669 ic->ic_raw_xmit = iwn_raw_xmit; 670 ic->ic_node_alloc = iwn_node_alloc; 671 ic->ic_newassoc = iwn_newassoc; 672 ic->ic_wme.wme_update = iwn_wme_update; 673 ic->ic_update_mcast = iwn_update_mcast; 674 ic->ic_scan_start = iwn_scan_start; 675 ic->ic_scan_end = iwn_scan_end; 676 ic->ic_set_channel = iwn_set_channel; 677 ic->ic_scan_curchan = iwn_scan_curchan; 678 ic->ic_scan_mindwell = iwn_scan_mindwell; 679 ic->ic_setregdomain = iwn_setregdomain; 680 #if 0 /* HT */ 681 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 682 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 683 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 684 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 685 #endif 686 687 iwn_radiotap_attach(sc); 688 iwn_sysctlattach(sc); 689 690 /* 691 * Hook our interrupt after all initialization is complete. 692 */ 693 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 694 iwn_intr, sc, &sc->sc_ih, 695 &wlan_global_serializer); 696 if (error != 0) { 697 device_printf(dev, "could not set up interrupt, error %d\n", 698 error); 699 goto fail; 700 } 701 702 ieee80211_announce(ic); 703 wlan_serialize_exit(); 704 return 0; 705 fail: 706 iwn_cleanup(dev); 707 fail2: 708 wlan_serialize_exit(); 709 return error; 710 } 711 712 static const struct iwn_hal * 713 iwn_hal_attach(struct iwn_softc *sc) 714 { 715 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 716 717 switch (sc->hw_type) { 718 case IWN_HW_REV_TYPE_4965: 719 sc->sc_hal = &iwn4965_hal; 720 sc->limits = &iwn4965_sensitivity_limits; 721 sc->fwname = "iwn4965fw"; 722 sc->txchainmask = IWN_ANT_AB; 723 sc->rxchainmask = IWN_ANT_ABC; 724 break; 725 case IWN_HW_REV_TYPE_5100: 726 sc->sc_hal = &iwn5000_hal; 727 sc->limits = &iwn5000_sensitivity_limits; 728 sc->fwname = "iwn5000fw"; 729 sc->txchainmask = IWN_ANT_B; 730 sc->rxchainmask = IWN_ANT_AB; 731 break; 732 case IWN_HW_REV_TYPE_5150: 733 sc->sc_hal = &iwn5000_hal; 734 sc->limits = &iwn5150_sensitivity_limits; 735 sc->fwname = "iwn5150fw"; 736 sc->txchainmask = IWN_ANT_A; 737 sc->rxchainmask = IWN_ANT_AB; 738 break; 739 case IWN_HW_REV_TYPE_5300: 740 case IWN_HW_REV_TYPE_5350: 741 sc->sc_hal = &iwn5000_hal; 742 sc->limits = &iwn5000_sensitivity_limits; 743 sc->fwname = "iwn5000fw"; 744 sc->txchainmask = IWN_ANT_ABC; 745 sc->rxchainmask = IWN_ANT_ABC; 746 break; 747 case IWN_HW_REV_TYPE_1000: 748 sc->sc_hal = &iwn5000_hal; 749 sc->limits = &iwn1000_sensitivity_limits; 750 sc->fwname = "iwn1000fw"; 751 sc->txchainmask = IWN_ANT_A; 752 sc->rxchainmask = IWN_ANT_AB; 753 break; 754 case IWN_HW_REV_TYPE_6000: 755 sc->sc_hal = &iwn5000_hal; 756 sc->limits = &iwn6000_sensitivity_limits; 757 sc->fwname = "iwn6000fw"; 758 switch (pci_get_device(sc->sc_dev)) { 759 case 0x422C: 760 case 0x4239: 761 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 762 sc->txchainmask = IWN_ANT_BC; 763 sc->rxchainmask = IWN_ANT_BC; 764 break; 765 default: 766 sc->txchainmask = IWN_ANT_ABC; 767 sc->rxchainmask = IWN_ANT_ABC; 768 break; 769 } 770 break; 771 case IWN_HW_REV_TYPE_6050: 772 sc->sc_hal = &iwn5000_hal; 773 sc->limits = &iwn6000_sensitivity_limits; 774 sc->fwname = "iwn6000fw"; 775 sc->txchainmask = IWN_ANT_AB; 776 sc->rxchainmask = IWN_ANT_AB; 777 break; 778 default: 779 device_printf(sc->sc_dev, "adapter type %d not supported\n", 780 sc->hw_type); 781 return NULL; 782 } 783 return sc->sc_hal; 784 } 785 786 /* 787 * Attach the interface to 802.11 radiotap. 788 */ 789 static void 790 iwn_radiotap_attach(struct iwn_softc *sc) 791 { 792 struct ifnet *ifp = sc->sc_ifp; 793 struct ieee80211com *ic = ifp->if_l2com; 794 795 ieee80211_radiotap_attach(ic, 796 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 797 IWN_TX_RADIOTAP_PRESENT, 798 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 799 IWN_RX_RADIOTAP_PRESENT); 800 } 801 802 static struct ieee80211vap * 803 iwn_vap_create(struct ieee80211com *ic, 804 const char name[IFNAMSIZ], int unit, int opmode, int flags, 805 const uint8_t bssid[IEEE80211_ADDR_LEN], 806 const uint8_t mac[IEEE80211_ADDR_LEN]) 807 { 808 struct iwn_vap *ivp; 809 struct ieee80211vap *vap; 810 811 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 812 return NULL; 813 ivp = (struct iwn_vap *) kmalloc(sizeof(struct iwn_vap), 814 M_80211_VAP, M_INTWAIT | M_ZERO); 815 if (ivp == NULL) 816 return NULL; 817 vap = &ivp->iv_vap; 818 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 819 vap->iv_bmissthreshold = 10; /* override default */ 820 /* Override with driver methods. */ 821 ivp->iv_newstate = vap->iv_newstate; 822 vap->iv_newstate = iwn_newstate; 823 824 ieee80211_ratectl_init(vap); 825 /* Complete setup. */ 826 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 827 ic->ic_opmode = opmode; 828 return vap; 829 } 830 831 static void 832 iwn_vap_delete(struct ieee80211vap *vap) 833 { 834 struct iwn_vap *ivp = IWN_VAP(vap); 835 836 ieee80211_ratectl_deinit(vap); 837 ieee80211_vap_detach(vap); 838 kfree(ivp, M_80211_VAP); 839 } 840 841 static int 842 iwn_cleanup(device_t dev) 843 { 844 struct iwn_softc *sc = device_get_softc(dev); 845 struct ifnet *ifp = sc->sc_ifp; 846 struct ieee80211com *ic; 847 int i; 848 849 if (ifp != NULL) { 850 ic = ifp->if_l2com; 851 852 ieee80211_draintask(ic, &sc->sc_reinit_task); 853 ieee80211_draintask(ic, &sc->sc_radioon_task); 854 ieee80211_draintask(ic, &sc->sc_radiooff_task); 855 856 iwn_stop(sc); 857 callout_stop(&sc->sc_timer_to); 858 ieee80211_ifdetach(ic); 859 } 860 861 /* cleanup sysctl nodes */ 862 sysctl_ctx_free(&sc->sc_sysctl_ctx); 863 864 /* Free DMA resources. */ 865 iwn_free_rx_ring(sc, &sc->rxq); 866 if (sc->sc_hal != NULL) 867 for (i = 0; i < sc->sc_hal->ntxqs; i++) 868 iwn_free_tx_ring(sc, &sc->txq[i]); 869 iwn_free_sched(sc); 870 iwn_free_kw(sc); 871 if (sc->ict != NULL) { 872 iwn_free_ict(sc); 873 sc->ict = NULL; 874 } 875 iwn_free_fwmem(sc); 876 877 if (sc->irq != NULL) { 878 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 879 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 880 if (sc->irq_rid == 1) 881 pci_release_msi(dev); 882 sc->irq = NULL; 883 } 884 885 if (sc->mem != NULL) { 886 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 887 sc->mem = NULL; 888 } 889 890 if (ifp != NULL) { 891 if_free(ifp); 892 sc->sc_ifp = NULL; 893 } 894 895 return 0; 896 } 897 898 static int 899 iwn_pci_detach(device_t dev) 900 { 901 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 902 903 wlan_serialize_enter(); 904 iwn_cleanup(dev); 905 bus_dma_tag_destroy(sc->sc_dmat); 906 wlan_serialize_exit(); 907 908 return 0; 909 } 910 911 static int 912 iwn_nic_lock(struct iwn_softc *sc) 913 { 914 int ntries; 915 916 /* Request exclusive access to NIC. */ 917 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 918 919 /* Spin until we actually get the lock. */ 920 for (ntries = 0; ntries < 1000; ntries++) { 921 if ((IWN_READ(sc, IWN_GP_CNTRL) & 922 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 923 IWN_GP_CNTRL_MAC_ACCESS_ENA) 924 return 0; 925 DELAY(10); 926 } 927 return ETIMEDOUT; 928 } 929 930 static __inline void 931 iwn_nic_unlock(struct iwn_softc *sc) 932 { 933 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 934 } 935 936 static __inline uint32_t 937 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 938 { 939 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 940 IWN_BARRIER_READ_WRITE(sc); 941 return IWN_READ(sc, IWN_PRPH_RDATA); 942 } 943 944 static __inline void 945 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 946 { 947 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 948 IWN_BARRIER_WRITE(sc); 949 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 950 } 951 952 static __inline void 953 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 954 { 955 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 956 } 957 958 static __inline void 959 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 960 { 961 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 962 } 963 964 static __inline void 965 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 966 const uint32_t *data, int count) 967 { 968 for (; count > 0; count--, data++, addr += 4) 969 iwn_prph_write(sc, addr, *data); 970 } 971 972 static __inline uint32_t 973 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 974 { 975 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 976 IWN_BARRIER_READ_WRITE(sc); 977 return IWN_READ(sc, IWN_MEM_RDATA); 978 } 979 980 static __inline void 981 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 982 { 983 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 984 IWN_BARRIER_WRITE(sc); 985 IWN_WRITE(sc, IWN_MEM_WDATA, data); 986 } 987 988 static __inline void 989 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 990 { 991 uint32_t tmp; 992 993 tmp = iwn_mem_read(sc, addr & ~3); 994 if (addr & 3) 995 tmp = (tmp & 0x0000ffff) | data << 16; 996 else 997 tmp = (tmp & 0xffff0000) | data; 998 iwn_mem_write(sc, addr & ~3, tmp); 999 } 1000 1001 static __inline void 1002 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1003 int count) 1004 { 1005 for (; count > 0; count--, addr += 4) 1006 *data++ = iwn_mem_read(sc, addr); 1007 } 1008 1009 static __inline void 1010 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1011 int count) 1012 { 1013 for (; count > 0; count--, addr += 4) 1014 iwn_mem_write(sc, addr, val); 1015 } 1016 1017 static int 1018 iwn_eeprom_lock(struct iwn_softc *sc) 1019 { 1020 int i, ntries; 1021 1022 for (i = 0; i < 100; i++) { 1023 /* Request exclusive access to EEPROM. */ 1024 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1025 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1026 1027 /* Spin until we actually get the lock. */ 1028 for (ntries = 0; ntries < 100; ntries++) { 1029 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1030 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1031 return 0; 1032 DELAY(10); 1033 } 1034 } 1035 return ETIMEDOUT; 1036 } 1037 1038 static __inline void 1039 iwn_eeprom_unlock(struct iwn_softc *sc) 1040 { 1041 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1042 } 1043 1044 /* 1045 * Initialize access by host to One Time Programmable ROM. 1046 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1047 */ 1048 static int 1049 iwn_init_otprom(struct iwn_softc *sc) 1050 { 1051 uint16_t prev, base, next; 1052 int count, error; 1053 1054 /* Wait for clock stabilization before accessing prph. */ 1055 error = iwn_clock_wait(sc); 1056 if (error != 0) 1057 return error; 1058 1059 error = iwn_nic_lock(sc); 1060 if (error != 0) 1061 return error; 1062 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1063 DELAY(5); 1064 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1065 iwn_nic_unlock(sc); 1066 1067 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1068 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1069 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1070 IWN_RESET_LINK_PWR_MGMT_DIS); 1071 } 1072 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1073 /* Clear ECC status. */ 1074 IWN_SETBITS(sc, IWN_OTP_GP, 1075 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1076 1077 /* 1078 * Find the block before last block (contains the EEPROM image) 1079 * for HW without OTP shadow RAM. 1080 */ 1081 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1082 /* Switch to absolute addressing mode. */ 1083 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1084 base = prev = 0; 1085 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1086 error = iwn_read_prom_data(sc, base, &next, 2); 1087 if (error != 0) 1088 return error; 1089 if (next == 0) /* End of linked-list. */ 1090 break; 1091 prev = base; 1092 base = le16toh(next); 1093 } 1094 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1095 return EIO; 1096 /* Skip "next" word. */ 1097 sc->prom_base = prev + 1; 1098 } 1099 return 0; 1100 } 1101 1102 static int 1103 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1104 { 1105 uint32_t val, tmp; 1106 int ntries; 1107 uint8_t *out = data; 1108 1109 addr += sc->prom_base; 1110 for (; count > 0; count -= 2, addr++) { 1111 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1112 for (ntries = 0; ntries < 10; ntries++) { 1113 val = IWN_READ(sc, IWN_EEPROM); 1114 if (val & IWN_EEPROM_READ_VALID) 1115 break; 1116 DELAY(5); 1117 } 1118 if (ntries == 10) { 1119 device_printf(sc->sc_dev, 1120 "timeout reading ROM at 0x%x\n", addr); 1121 return ETIMEDOUT; 1122 } 1123 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1124 /* OTPROM, check for ECC errors. */ 1125 tmp = IWN_READ(sc, IWN_OTP_GP); 1126 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1127 device_printf(sc->sc_dev, 1128 "OTPROM ECC error at 0x%x\n", addr); 1129 return EIO; 1130 } 1131 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1132 /* Correctable ECC error, clear bit. */ 1133 IWN_SETBITS(sc, IWN_OTP_GP, 1134 IWN_OTP_GP_ECC_CORR_STTS); 1135 } 1136 } 1137 *out++ = val >> 16; 1138 if (count > 1) 1139 *out++ = val >> 24; 1140 } 1141 return 0; 1142 } 1143 1144 static void 1145 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1146 { 1147 if (error != 0) 1148 return; 1149 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1150 *(bus_addr_t *)arg = segs[0].ds_addr; 1151 } 1152 1153 static int 1154 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1155 void **kvap, bus_size_t size, bus_size_t alignment, int flags) 1156 { 1157 int error; 1158 1159 dma->size = size; 1160 dma->tag = NULL; 1161 1162 error = bus_dma_tag_create(sc->sc_dmat, alignment, 1163 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1164 1, size, flags, &dma->tag); 1165 if (error != 0) { 1166 device_printf(sc->sc_dev, 1167 "%s: bus_dma_tag_create failed, error %d\n", 1168 __func__, error); 1169 goto fail; 1170 } 1171 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1172 flags | BUS_DMA_ZERO, &dma->map); 1173 if (error != 0) { 1174 device_printf(sc->sc_dev, 1175 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error); 1176 goto fail; 1177 } 1178 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 1179 size, iwn_dma_map_addr, &dma->paddr, flags); 1180 if (error != 0) { 1181 device_printf(sc->sc_dev, 1182 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 1183 goto fail; 1184 } 1185 1186 if (kvap != NULL) 1187 *kvap = dma->vaddr; 1188 return 0; 1189 fail: 1190 iwn_dma_contig_free(dma); 1191 return error; 1192 } 1193 1194 static void 1195 iwn_dma_contig_free(struct iwn_dma_info *dma) 1196 { 1197 if (dma->tag != NULL) { 1198 if (dma->map != NULL) { 1199 if (dma->paddr == 0) { 1200 bus_dmamap_sync(dma->tag, dma->map, 1201 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1202 bus_dmamap_unload(dma->tag, dma->map); 1203 } 1204 bus_dmamap_destroy(dma->tag, dma->map); 1205 } 1206 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1207 bus_dma_tag_destroy(dma->tag); 1208 } 1209 } 1210 1211 static int 1212 iwn_alloc_sched(struct iwn_softc *sc) 1213 { 1214 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1215 return iwn_dma_contig_alloc(sc, &sc->sched_dma, 1216 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT); 1217 } 1218 1219 static void 1220 iwn_free_sched(struct iwn_softc *sc) 1221 { 1222 iwn_dma_contig_free(&sc->sched_dma); 1223 } 1224 1225 static int 1226 iwn_alloc_kw(struct iwn_softc *sc) 1227 { 1228 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1229 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096, 1230 BUS_DMA_NOWAIT); 1231 } 1232 1233 static void 1234 iwn_free_kw(struct iwn_softc *sc) 1235 { 1236 iwn_dma_contig_free(&sc->kw_dma); 1237 } 1238 1239 static int 1240 iwn_alloc_ict(struct iwn_softc *sc) 1241 { 1242 /* ICT table must be aligned on a 4KB boundary. */ 1243 return iwn_dma_contig_alloc(sc, &sc->ict_dma, 1244 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT); 1245 } 1246 1247 static void 1248 iwn_free_ict(struct iwn_softc *sc) 1249 { 1250 iwn_dma_contig_free(&sc->ict_dma); 1251 } 1252 1253 static int 1254 iwn_alloc_fwmem(struct iwn_softc *sc) 1255 { 1256 /* Must be aligned on a 16-byte boundary. */ 1257 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, 1258 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT); 1259 } 1260 1261 static void 1262 iwn_free_fwmem(struct iwn_softc *sc) 1263 { 1264 iwn_dma_contig_free(&sc->fw_dma); 1265 } 1266 1267 static int 1268 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1269 { 1270 bus_size_t size; 1271 int i, error; 1272 1273 ring->cur = 0; 1274 1275 /* Allocate RX descriptors (256-byte aligned). */ 1276 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1277 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1278 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1279 if (error != 0) { 1280 device_printf(sc->sc_dev, 1281 "%s: could not allocate Rx ring DMA memory, error %d\n", 1282 __func__, error); 1283 goto fail; 1284 } 1285 1286 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1287 BUS_SPACE_MAXADDR_32BIT, 1288 BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1, 1289 MJUMPAGESIZE, BUS_DMA_NOWAIT, &ring->data_dmat); 1290 if (error != 0) { 1291 device_printf(sc->sc_dev, 1292 "%s: bus_dma_tag_create_failed, error %d\n", 1293 __func__, error); 1294 goto fail; 1295 } 1296 1297 /* Allocate RX status area (16-byte aligned). */ 1298 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, 1299 (void **)&ring->stat, sizeof (struct iwn_rx_status), 1300 16, BUS_DMA_NOWAIT); 1301 if (error != 0) { 1302 device_printf(sc->sc_dev, 1303 "%s: could not allocate Rx status DMA memory, error %d\n", 1304 __func__, error); 1305 goto fail; 1306 } 1307 1308 /* 1309 * Allocate and map RX buffers. 1310 */ 1311 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1312 struct iwn_rx_data *data = &ring->data[i]; 1313 bus_addr_t paddr; 1314 1315 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1316 if (error != 0) { 1317 device_printf(sc->sc_dev, 1318 "%s: bus_dmamap_create failed, error %d\n", 1319 __func__, error); 1320 goto fail; 1321 } 1322 1323 data->m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, 1324 MJUMPAGESIZE); 1325 if (data->m == NULL) { 1326 device_printf(sc->sc_dev, 1327 "%s: could not allocate rx mbuf\n", __func__); 1328 error = ENOMEM; 1329 goto fail; 1330 } 1331 1332 /* Map page. */ 1333 error = bus_dmamap_load(ring->data_dmat, data->map, 1334 mtod(data->m, caddr_t), MJUMPAGESIZE, 1335 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 1336 if (error != 0 && error != EFBIG) { 1337 device_printf(sc->sc_dev, 1338 "%s: bus_dmamap_load failed, error %d\n", 1339 __func__, error); 1340 m_freem(data->m); 1341 error = ENOMEM; /* XXX unique code */ 1342 goto fail; 1343 } 1344 bus_dmamap_sync(ring->data_dmat, data->map, 1345 BUS_DMASYNC_PREWRITE); 1346 1347 /* Set physical address of RX buffer (256-byte aligned). */ 1348 ring->desc[i] = htole32(paddr >> 8); 1349 } 1350 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1351 BUS_DMASYNC_PREWRITE); 1352 return 0; 1353 fail: 1354 iwn_free_rx_ring(sc, ring); 1355 return error; 1356 } 1357 1358 static void 1359 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1360 { 1361 int ntries; 1362 1363 if (iwn_nic_lock(sc) == 0) { 1364 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1365 for (ntries = 0; ntries < 1000; ntries++) { 1366 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1367 IWN_FH_RX_STATUS_IDLE) 1368 break; 1369 DELAY(10); 1370 } 1371 iwn_nic_unlock(sc); 1372 #ifdef IWN_DEBUG 1373 if (ntries == 1000) 1374 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 1375 "timeout resetting Rx ring"); 1376 #endif 1377 } 1378 ring->cur = 0; 1379 sc->last_rx_valid = 0; 1380 } 1381 1382 static void 1383 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1384 { 1385 int i; 1386 1387 iwn_dma_contig_free(&ring->desc_dma); 1388 iwn_dma_contig_free(&ring->stat_dma); 1389 1390 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1391 struct iwn_rx_data *data = &ring->data[i]; 1392 1393 if (data->m != NULL) { 1394 bus_dmamap_sync(ring->data_dmat, data->map, 1395 BUS_DMASYNC_POSTREAD); 1396 bus_dmamap_unload(ring->data_dmat, data->map); 1397 m_freem(data->m); 1398 } 1399 if (data->map != NULL) 1400 bus_dmamap_destroy(ring->data_dmat, data->map); 1401 } 1402 } 1403 1404 static int 1405 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1406 { 1407 bus_size_t size; 1408 bus_addr_t paddr; 1409 int i, error; 1410 1411 ring->qid = qid; 1412 ring->queued = 0; 1413 ring->cur = 0; 1414 1415 /* Allocate TX descriptors (256-byte aligned.) */ 1416 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc); 1417 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1418 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1419 if (error != 0) { 1420 device_printf(sc->sc_dev, 1421 "%s: could not allocate TX ring DMA memory, error %d\n", 1422 __func__, error); 1423 goto fail; 1424 } 1425 1426 /* 1427 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1428 * to allocate commands space for other rings. 1429 */ 1430 if (qid > 4) 1431 return 0; 1432 1433 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd); 1434 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, 1435 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT); 1436 if (error != 0) { 1437 device_printf(sc->sc_dev, 1438 "%s: could not allocate TX cmd DMA memory, error %d\n", 1439 __func__, error); 1440 goto fail; 1441 } 1442 1443 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1444 BUS_SPACE_MAXADDR_32BIT, 1445 BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, IWN_MAX_SCATTER - 1, 1446 MJUMPAGESIZE, BUS_DMA_NOWAIT, &ring->data_dmat); 1447 if (error != 0) { 1448 device_printf(sc->sc_dev, 1449 "%s: bus_dma_tag_create_failed, error %d\n", 1450 __func__, error); 1451 goto fail; 1452 } 1453 1454 paddr = ring->cmd_dma.paddr; 1455 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1456 struct iwn_tx_data *data = &ring->data[i]; 1457 1458 data->cmd_paddr = paddr; 1459 data->scratch_paddr = paddr + 12; 1460 paddr += sizeof (struct iwn_tx_cmd); 1461 1462 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1463 if (error != 0) { 1464 device_printf(sc->sc_dev, 1465 "%s: bus_dmamap_create failed, error %d\n", 1466 __func__, error); 1467 goto fail; 1468 } 1469 bus_dmamap_sync(ring->data_dmat, data->map, 1470 BUS_DMASYNC_PREWRITE); 1471 } 1472 return 0; 1473 fail: 1474 iwn_free_tx_ring(sc, ring); 1475 return error; 1476 } 1477 1478 static void 1479 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1480 { 1481 int i; 1482 1483 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1484 struct iwn_tx_data *data = &ring->data[i]; 1485 1486 if (data->m != NULL) { 1487 bus_dmamap_unload(ring->data_dmat, data->map); 1488 m_freem(data->m); 1489 data->m = NULL; 1490 } 1491 } 1492 /* Clear TX descriptors. */ 1493 memset(ring->desc, 0, ring->desc_dma.size); 1494 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1495 BUS_DMASYNC_PREWRITE); 1496 sc->qfullmsk &= ~(1 << ring->qid); 1497 ring->queued = 0; 1498 ring->cur = 0; 1499 } 1500 1501 static void 1502 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1503 { 1504 int i; 1505 1506 iwn_dma_contig_free(&ring->desc_dma); 1507 iwn_dma_contig_free(&ring->cmd_dma); 1508 1509 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1510 struct iwn_tx_data *data = &ring->data[i]; 1511 1512 if (data->m != NULL) { 1513 bus_dmamap_sync(ring->data_dmat, data->map, 1514 BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(ring->data_dmat, data->map); 1516 m_freem(data->m); 1517 } 1518 if (data->map != NULL) 1519 bus_dmamap_destroy(ring->data_dmat, data->map); 1520 } 1521 } 1522 1523 static void 1524 iwn5000_ict_reset(struct iwn_softc *sc) 1525 { 1526 /* Disable interrupts. */ 1527 IWN_WRITE(sc, IWN_INT_MASK, 0); 1528 1529 /* Reset ICT table. */ 1530 memset(sc->ict, 0, IWN_ICT_SIZE); 1531 sc->ict_cur = 0; 1532 1533 /* Set physical address of ICT table (4KB aligned.) */ 1534 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1535 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1536 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1537 1538 /* Enable periodic RX interrupt. */ 1539 sc->int_mask |= IWN_INT_RX_PERIODIC; 1540 /* Switch to ICT interrupt mode in driver. */ 1541 sc->sc_flags |= IWN_FLAG_USE_ICT; 1542 1543 /* Re-enable interrupts. */ 1544 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1545 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1546 } 1547 1548 static int 1549 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1550 { 1551 const struct iwn_hal *hal = sc->sc_hal; 1552 int error; 1553 uint16_t val; 1554 1555 /* Check whether adapter has an EEPROM or an OTPROM. */ 1556 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1557 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1558 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1559 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1560 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1561 1562 /* Adapter has to be powered on for EEPROM access to work. */ 1563 error = iwn_apm_init(sc); 1564 if (error != 0) { 1565 device_printf(sc->sc_dev, 1566 "%s: could not power ON adapter, error %d\n", 1567 __func__, error); 1568 return error; 1569 } 1570 1571 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1572 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1573 return EIO; 1574 } 1575 error = iwn_eeprom_lock(sc); 1576 if (error != 0) { 1577 device_printf(sc->sc_dev, 1578 "%s: could not lock ROM, error %d\n", 1579 __func__, error); 1580 return error; 1581 } 1582 1583 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1584 error = iwn_init_otprom(sc); 1585 if (error != 0) { 1586 device_printf(sc->sc_dev, 1587 "%s: could not initialize OTPROM, error %d\n", 1588 __func__, error); 1589 return error; 1590 } 1591 } 1592 1593 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1594 sc->rfcfg = le16toh(val); 1595 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1596 1597 /* Read MAC address. */ 1598 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1599 1600 /* Read adapter-specific information from EEPROM. */ 1601 hal->read_eeprom(sc); 1602 1603 iwn_apm_stop(sc); /* Power OFF adapter. */ 1604 1605 iwn_eeprom_unlock(sc); 1606 return 0; 1607 } 1608 1609 static void 1610 iwn4965_read_eeprom(struct iwn_softc *sc) 1611 { 1612 uint32_t addr; 1613 int i; 1614 uint16_t val; 1615 1616 /* Read regulatory domain (4 ASCII characters.) */ 1617 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1618 1619 /* Read the list of authorized channels (20MHz ones only.) */ 1620 for (i = 0; i < 5; i++) { 1621 addr = iwn4965_regulatory_bands[i]; 1622 iwn_read_eeprom_channels(sc, i, addr); 1623 } 1624 1625 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1626 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1627 sc->maxpwr2GHz = val & 0xff; 1628 sc->maxpwr5GHz = val >> 8; 1629 /* Check that EEPROM values are within valid range. */ 1630 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1631 sc->maxpwr5GHz = 38; 1632 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1633 sc->maxpwr2GHz = 38; 1634 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1635 sc->maxpwr2GHz, sc->maxpwr5GHz); 1636 1637 /* Read samples for each TX power group. */ 1638 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1639 sizeof sc->bands); 1640 1641 /* Read voltage at which samples were taken. */ 1642 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1643 sc->eeprom_voltage = (int16_t)le16toh(val); 1644 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1645 sc->eeprom_voltage); 1646 1647 #ifdef IWN_DEBUG 1648 /* Print samples. */ 1649 if (sc->sc_debug & IWN_DEBUG_ANY) { 1650 for (i = 0; i < IWN_NBANDS; i++) 1651 iwn4965_print_power_group(sc, i); 1652 } 1653 #endif 1654 } 1655 1656 #ifdef IWN_DEBUG 1657 static void 1658 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1659 { 1660 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1661 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1662 int j, c; 1663 1664 kprintf("===band %d===\n", i); 1665 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1666 kprintf("chan1 num=%d\n", chans[0].num); 1667 for (c = 0; c < 2; c++) { 1668 for (j = 0; j < IWN_NSAMPLES; j++) { 1669 kprintf("chain %d, sample %d: temp=%d gain=%d " 1670 "power=%d pa_det=%d\n", c, j, 1671 chans[0].samples[c][j].temp, 1672 chans[0].samples[c][j].gain, 1673 chans[0].samples[c][j].power, 1674 chans[0].samples[c][j].pa_det); 1675 } 1676 } 1677 kprintf("chan2 num=%d\n", chans[1].num); 1678 for (c = 0; c < 2; c++) { 1679 for (j = 0; j < IWN_NSAMPLES; j++) { 1680 kprintf("chain %d, sample %d: temp=%d gain=%d " 1681 "power=%d pa_det=%d\n", c, j, 1682 chans[1].samples[c][j].temp, 1683 chans[1].samples[c][j].gain, 1684 chans[1].samples[c][j].power, 1685 chans[1].samples[c][j].pa_det); 1686 } 1687 } 1688 } 1689 #endif 1690 1691 static void 1692 iwn5000_read_eeprom(struct iwn_softc *sc) 1693 { 1694 struct iwn5000_eeprom_calib_hdr hdr; 1695 int32_t temp, volt; 1696 uint32_t addr, base; 1697 int i; 1698 uint16_t val; 1699 1700 /* Read regulatory domain (4 ASCII characters.) */ 1701 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1702 base = le16toh(val); 1703 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1704 sc->eeprom_domain, 4); 1705 1706 /* Read the list of authorized channels (20MHz ones only.) */ 1707 for (i = 0; i < 5; i++) { 1708 addr = base + iwn5000_regulatory_bands[i]; 1709 iwn_read_eeprom_channels(sc, i, addr); 1710 } 1711 1712 /* Read enhanced TX power information for 6000 Series. */ 1713 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1714 iwn_read_eeprom_enhinfo(sc); 1715 1716 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1717 base = le16toh(val); 1718 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1719 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1720 "%s: calib version=%u pa type=%u voltage=%u\n", 1721 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1722 sc->calib_ver = hdr.version; 1723 1724 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1725 /* Compute temperature offset. */ 1726 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1727 temp = le16toh(val); 1728 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1729 volt = le16toh(val); 1730 sc->temp_off = temp - (volt / -5); 1731 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1732 temp, volt, sc->temp_off); 1733 } else { 1734 /* Read crystal calibration. */ 1735 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1736 &sc->eeprom_crystal, sizeof (uint32_t)); 1737 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1738 le32toh(sc->eeprom_crystal)); 1739 } 1740 } 1741 1742 /* 1743 * Translate EEPROM flags to net80211. 1744 */ 1745 static uint32_t 1746 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1747 { 1748 uint32_t nflags; 1749 1750 nflags = 0; 1751 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1752 nflags |= IEEE80211_CHAN_PASSIVE; 1753 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1754 nflags |= IEEE80211_CHAN_NOADHOC; 1755 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1756 nflags |= IEEE80211_CHAN_DFS; 1757 /* XXX apparently IBSS may still be marked */ 1758 nflags |= IEEE80211_CHAN_NOADHOC; 1759 } 1760 1761 return nflags; 1762 } 1763 1764 static void 1765 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1766 { 1767 struct ifnet *ifp = sc->sc_ifp; 1768 struct ieee80211com *ic = ifp->if_l2com; 1769 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1770 const struct iwn_chan_band *band = &iwn_bands[n]; 1771 struct ieee80211_channel *c; 1772 int i, chan, nflags; 1773 1774 for (i = 0; i < band->nchan; i++) { 1775 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1776 DPRINTF(sc, IWN_DEBUG_RESET, 1777 "skip chan %d flags 0x%x maxpwr %d\n", 1778 band->chan[i], channels[i].flags, 1779 channels[i].maxpwr); 1780 continue; 1781 } 1782 chan = band->chan[i]; 1783 nflags = iwn_eeprom_channel_flags(&channels[i]); 1784 1785 DPRINTF(sc, IWN_DEBUG_RESET, 1786 "add chan %d flags 0x%x maxpwr %d\n", 1787 chan, channels[i].flags, channels[i].maxpwr); 1788 1789 c = &ic->ic_channels[ic->ic_nchans++]; 1790 c->ic_ieee = chan; 1791 c->ic_maxregpower = channels[i].maxpwr; 1792 c->ic_maxpower = 2*c->ic_maxregpower; 1793 1794 /* Save maximum allowed TX power for this channel. */ 1795 sc->maxpwr[chan] = channels[i].maxpwr; 1796 1797 if (n == 0) { /* 2GHz band */ 1798 c->ic_freq = ieee80211_ieee2mhz(chan, 1799 IEEE80211_CHAN_G); 1800 1801 /* G =>'s B is supported */ 1802 c->ic_flags = IEEE80211_CHAN_B | nflags; 1803 1804 c = &ic->ic_channels[ic->ic_nchans++]; 1805 c[0] = c[-1]; 1806 c->ic_flags = IEEE80211_CHAN_G | nflags; 1807 } else { /* 5GHz band */ 1808 c->ic_freq = ieee80211_ieee2mhz(chan, 1809 IEEE80211_CHAN_A); 1810 c->ic_flags = IEEE80211_CHAN_A | nflags; 1811 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1812 } 1813 #if 0 /* HT */ 1814 /* XXX no constraints on using HT20 */ 1815 /* add HT20, HT40 added separately */ 1816 c = &ic->ic_channels[ic->ic_nchans++]; 1817 c[0] = c[-1]; 1818 c->ic_flags |= IEEE80211_CHAN_HT20; 1819 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1820 #endif 1821 } 1822 } 1823 1824 #if 0 /* HT */ 1825 static void 1826 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1827 { 1828 struct ifnet *ifp = sc->sc_ifp; 1829 struct ieee80211com *ic = ifp->if_l2com; 1830 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1831 const struct iwn_chan_band *band = &iwn_bands[n]; 1832 struct ieee80211_channel *c, *cent, *extc; 1833 int i; 1834 1835 for (i = 0; i < band->nchan; i++) { 1836 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1837 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1838 DPRINTF(sc, IWN_DEBUG_RESET, 1839 "skip chan %d flags 0x%x maxpwr %d\n", 1840 band->chan[i], channels[i].flags, 1841 channels[i].maxpwr); 1842 continue; 1843 } 1844 /* 1845 * Each entry defines an HT40 channel pair; find the 1846 * center channel, then the extension channel above. 1847 */ 1848 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1849 band->flags & ~IEEE80211_CHAN_HT); 1850 if (cent == NULL) { /* XXX shouldn't happen */ 1851 device_printf(sc->sc_dev, 1852 "%s: no entry for channel %d\n", 1853 __func__, band->chan[i]); 1854 continue; 1855 } 1856 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1857 band->flags & ~IEEE80211_CHAN_HT); 1858 if (extc == NULL) { 1859 DPRINTF(sc, IWN_DEBUG_RESET, 1860 "skip chan %d, extension channel not found\n", 1861 band->chan[i]); 1862 continue; 1863 } 1864 1865 DPRINTF(sc, IWN_DEBUG_RESET, 1866 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1867 band->chan[i], channels[i].flags, channels[i].maxpwr); 1868 1869 c = &ic->ic_channels[ic->ic_nchans++]; 1870 c[0] = cent[0]; 1871 c->ic_extieee = extc->ic_ieee; 1872 c->ic_flags &= ~IEEE80211_CHAN_HT; 1873 c->ic_flags |= IEEE80211_CHAN_HT40U; 1874 c = &ic->ic_channels[ic->ic_nchans++]; 1875 c[0] = extc[0]; 1876 c->ic_extieee = cent->ic_ieee; 1877 c->ic_flags &= ~IEEE80211_CHAN_HT; 1878 c->ic_flags |= IEEE80211_CHAN_HT40D; 1879 } 1880 } 1881 #endif 1882 1883 static void 1884 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1885 { 1886 struct ifnet *ifp = sc->sc_ifp; 1887 struct ieee80211com *ic = ifp->if_l2com; 1888 1889 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1890 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1891 1892 if (n < 5) 1893 iwn_read_eeprom_band(sc, n); 1894 #if 0 /* HT */ 1895 else 1896 iwn_read_eeprom_ht40(sc, n); 1897 #endif 1898 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1899 } 1900 1901 static void 1902 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1903 { 1904 struct iwn_eeprom_enhinfo enhinfo[35]; 1905 uint16_t val, base; 1906 int8_t maxpwr; 1907 int i; 1908 1909 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1910 base = le16toh(val); 1911 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1912 enhinfo, sizeof enhinfo); 1913 1914 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1915 for (i = 0; i < NELEM(enhinfo); i++) { 1916 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1917 continue; /* Skip invalid entries. */ 1918 1919 maxpwr = 0; 1920 if (sc->txchainmask & IWN_ANT_A) 1921 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1922 if (sc->txchainmask & IWN_ANT_B) 1923 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1924 if (sc->txchainmask & IWN_ANT_C) 1925 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1926 if (sc->ntxchains == 2) 1927 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1928 else if (sc->ntxchains == 3) 1929 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1930 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1931 1932 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 1933 maxpwr); 1934 sc->enh_maxpwr[i] = maxpwr; 1935 } 1936 } 1937 1938 static struct ieee80211_node * 1939 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1940 { 1941 return kmalloc(sizeof (struct iwn_node), M_80211_NODE,M_INTWAIT | M_ZERO); 1942 } 1943 1944 static void 1945 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1946 { 1947 /* XXX move */ 1948 //if (!isnew) { 1949 ieee80211_ratectl_node_deinit(ni); 1950 //} 1951 1952 ieee80211_ratectl_node_init(ni); 1953 } 1954 1955 static int 1956 iwn_media_change(struct ifnet *ifp) 1957 { 1958 int error = ieee80211_media_change(ifp); 1959 /* NB: only the fixed rate can change and that doesn't need a reset */ 1960 return (error == ENETRESET ? 0 : error); 1961 } 1962 1963 static int 1964 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1965 { 1966 struct iwn_vap *ivp = IWN_VAP(vap); 1967 struct ieee80211com *ic = vap->iv_ic; 1968 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1969 int error; 1970 1971 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1972 ieee80211_state_name[vap->iv_state], 1973 ieee80211_state_name[nstate]); 1974 1975 callout_stop(&sc->sc_timer_to); 1976 1977 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) { 1978 /* !AUTH -> AUTH requires adapter config */ 1979 /* Reset state to handle reassociations correctly. */ 1980 sc->rxon.associd = 0; 1981 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1982 iwn_calib_reset(sc); 1983 error = iwn_auth(sc, vap); 1984 } 1985 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) { 1986 /* 1987 * !RUN -> RUN requires setting the association id 1988 * which is done with a firmware cmd. We also defer 1989 * starting the timers until that work is done. 1990 */ 1991 error = iwn_run(sc, vap); 1992 } 1993 if (nstate == IEEE80211_S_RUN) { 1994 /* 1995 * RUN -> RUN transition; just restart the timers. 1996 */ 1997 iwn_calib_reset(sc); 1998 } 1999 return ivp->iv_newstate(vap, nstate, arg); 2000 } 2001 2002 /* 2003 * Process an RX_PHY firmware notification. This is usually immediately 2004 * followed by an MPDU_RX_DONE notification. 2005 */ 2006 static void 2007 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2008 struct iwn_rx_data *data) 2009 { 2010 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2011 2012 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2013 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2014 2015 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2016 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2017 sc->last_rx_valid = 1; 2018 } 2019 2020 static void 2021 iwn_timer_callout(void *arg) 2022 { 2023 struct iwn_softc *sc = arg; 2024 uint32_t flags = 0; 2025 2026 wlan_serialize_enter(); 2027 if (sc->calib_cnt && --sc->calib_cnt == 0) { 2028 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2029 "send statistics request"); 2030 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2031 sizeof flags, 1); 2032 sc->calib_cnt = 60; /* do calibration every 60s */ 2033 } 2034 iwn_watchdog(sc); /* NB: piggyback tx watchdog */ 2035 callout_reset(&sc->sc_timer_to, hz, iwn_timer_callout, sc); 2036 wlan_serialize_exit(); 2037 } 2038 2039 static void 2040 iwn_calib_reset(struct iwn_softc *sc) 2041 { 2042 callout_reset(&sc->sc_timer_to, hz, iwn_timer_callout, sc); 2043 sc->calib_cnt = 60; /* do calibration every 60s */ 2044 } 2045 2046 /* 2047 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2048 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2049 */ 2050 static void 2051 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2052 struct iwn_rx_data *data) 2053 { 2054 const struct iwn_hal *hal = sc->sc_hal; 2055 struct ifnet *ifp = sc->sc_ifp; 2056 struct ieee80211com *ic = ifp->if_l2com; 2057 struct iwn_rx_ring *ring = &sc->rxq; 2058 struct ieee80211_frame *wh; 2059 struct ieee80211_node *ni; 2060 struct mbuf *m, *m1; 2061 struct iwn_rx_stat *stat; 2062 caddr_t head; 2063 bus_addr_t paddr; 2064 uint32_t flags; 2065 int error, len, rssi, nf; 2066 2067 if (desc->type == IWN_MPDU_RX_DONE) { 2068 /* Check for prior RX_PHY notification. */ 2069 if (!sc->last_rx_valid) { 2070 DPRINTF(sc, IWN_DEBUG_ANY, 2071 "%s: missing RX_PHY\n", __func__); 2072 ifp->if_ierrors++; 2073 return; 2074 } 2075 sc->last_rx_valid = 0; 2076 stat = &sc->last_rx_stat; 2077 } else 2078 stat = (struct iwn_rx_stat *)(desc + 1); 2079 2080 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2081 2082 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2083 device_printf(sc->sc_dev, 2084 "%s: invalid rx statistic header, len %d\n", 2085 __func__, stat->cfg_phy_len); 2086 ifp->if_ierrors++; 2087 return; 2088 } 2089 if (desc->type == IWN_MPDU_RX_DONE) { 2090 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2091 head = (caddr_t)(mpdu + 1); 2092 len = le16toh(mpdu->len); 2093 } else { 2094 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2095 len = le16toh(stat->len); 2096 } 2097 2098 flags = le32toh(*(uint32_t *)(head + len)); 2099 2100 /* Discard frames with a bad FCS early. */ 2101 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2102 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n", 2103 __func__, flags); 2104 ifp->if_ierrors++; 2105 return; 2106 } 2107 /* Discard frames that are too short. */ 2108 if (len < sizeof (*wh)) { 2109 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2110 __func__, len); 2111 ifp->if_ierrors++; 2112 return; 2113 } 2114 2115 /* XXX don't need mbuf, just dma buffer */ 2116 m1 = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 2117 if (m1 == NULL) { 2118 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2119 __func__); 2120 ifp->if_ierrors++; 2121 return; 2122 } 2123 bus_dmamap_unload(ring->data_dmat, data->map); 2124 2125 error = bus_dmamap_load(ring->data_dmat, data->map, 2126 mtod(m1, caddr_t), MJUMPAGESIZE, 2127 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2128 if (error != 0 && error != EFBIG) { 2129 device_printf(sc->sc_dev, 2130 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2131 m_freem(m1); 2132 ifp->if_ierrors++; 2133 return; 2134 } 2135 2136 m = data->m; 2137 data->m = m1; 2138 /* Update RX descriptor. */ 2139 ring->desc[ring->cur] = htole32(paddr >> 8); 2140 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2141 BUS_DMASYNC_PREWRITE); 2142 2143 /* Finalize mbuf. */ 2144 m->m_pkthdr.rcvif = ifp; 2145 m->m_data = head; 2146 m->m_pkthdr.len = m->m_len = len; 2147 2148 rssi = hal->get_rssi(sc, stat); 2149 2150 /* Grab a reference to the source node. */ 2151 wh = mtod(m, struct ieee80211_frame *); 2152 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2153 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2154 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2155 2156 if (ieee80211_radiotap_active(ic)) { 2157 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2158 2159 tap->wr_tsft = htole64(stat->tstamp); 2160 tap->wr_flags = 0; 2161 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2162 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2163 switch (stat->rate) { 2164 /* CCK rates. */ 2165 case 10: tap->wr_rate = 2; break; 2166 case 20: tap->wr_rate = 4; break; 2167 case 55: tap->wr_rate = 11; break; 2168 case 110: tap->wr_rate = 22; break; 2169 /* OFDM rates. */ 2170 case 0xd: tap->wr_rate = 12; break; 2171 case 0xf: tap->wr_rate = 18; break; 2172 case 0x5: tap->wr_rate = 24; break; 2173 case 0x7: tap->wr_rate = 36; break; 2174 case 0x9: tap->wr_rate = 48; break; 2175 case 0xb: tap->wr_rate = 72; break; 2176 case 0x1: tap->wr_rate = 96; break; 2177 case 0x3: tap->wr_rate = 108; break; 2178 /* Unknown rate: should not happen. */ 2179 default: tap->wr_rate = 0; 2180 } 2181 tap->wr_dbm_antsignal = rssi; 2182 tap->wr_dbm_antnoise = nf; 2183 } 2184 2185 /* Send the frame to the 802.11 layer. */ 2186 if (ni != NULL) { 2187 (void) ieee80211_input(ni, m, rssi - nf, nf); 2188 /* Node is no longer needed. */ 2189 ieee80211_free_node(ni); 2190 } else { 2191 (void) ieee80211_input_all(ic, m, rssi - nf, nf); 2192 } 2193 } 2194 2195 #if 0 /* HT */ 2196 /* Process an incoming Compressed BlockAck. */ 2197 static void 2198 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2199 struct iwn_rx_data *data) 2200 { 2201 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2202 struct iwn_tx_ring *txq; 2203 2204 txq = &sc->txq[letoh16(ba->qid)]; 2205 /* XXX TBD */ 2206 } 2207 #endif 2208 2209 /* 2210 * Process a CALIBRATION_RESULT notification sent by the initialization 2211 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2212 */ 2213 static void 2214 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2215 struct iwn_rx_data *data) 2216 { 2217 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2218 int len, idx = -1; 2219 2220 /* Runtime firmware should not send such a notification. */ 2221 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2222 return; 2223 2224 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2225 len = (le32toh(desc->len) & 0x3fff) - 4; 2226 2227 switch (calib->code) { 2228 case IWN5000_PHY_CALIB_DC: 2229 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2230 sc->hw_type == IWN_HW_REV_TYPE_6050) 2231 idx = 0; 2232 break; 2233 case IWN5000_PHY_CALIB_LO: 2234 idx = 1; 2235 break; 2236 case IWN5000_PHY_CALIB_TX_IQ: 2237 idx = 2; 2238 break; 2239 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2240 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2241 sc->hw_type != IWN_HW_REV_TYPE_5150) 2242 idx = 3; 2243 break; 2244 case IWN5000_PHY_CALIB_BASE_BAND: 2245 idx = 4; 2246 break; 2247 } 2248 if (idx == -1) /* Ignore other results. */ 2249 return; 2250 2251 /* Save calibration result. */ 2252 if (sc->calibcmd[idx].buf != NULL) 2253 kfree(sc->calibcmd[idx].buf, M_DEVBUF); 2254 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT); 2255 if (sc->calibcmd[idx].buf == NULL) { 2256 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2257 "not enough memory for calibration result %d\n", 2258 calib->code); 2259 return; 2260 } 2261 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2262 "saving calibration result code=%d len=%d\n", calib->code, len); 2263 sc->calibcmd[idx].len = len; 2264 memcpy(sc->calibcmd[idx].buf, calib, len); 2265 } 2266 2267 /* 2268 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2269 * The latter is sent by the firmware after each received beacon. 2270 */ 2271 static void 2272 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2273 struct iwn_rx_data *data) 2274 { 2275 const struct iwn_hal *hal = sc->sc_hal; 2276 struct ifnet *ifp = sc->sc_ifp; 2277 struct ieee80211com *ic = ifp->if_l2com; 2278 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2279 struct iwn_calib_state *calib = &sc->calib; 2280 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2281 int temp; 2282 2283 /* Beacon stats are meaningful only when associated and not scanning. */ 2284 if (vap->iv_state != IEEE80211_S_RUN || 2285 (ic->ic_flags & IEEE80211_F_SCAN)) 2286 return; 2287 2288 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2289 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type); 2290 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */ 2291 2292 /* Test if temperature has changed. */ 2293 if (stats->general.temp != sc->rawtemp) { 2294 /* Convert "raw" temperature to degC. */ 2295 sc->rawtemp = stats->general.temp; 2296 temp = hal->get_temperature(sc); 2297 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2298 __func__, temp); 2299 2300 /* Update TX power if need be (4965AGN only.) */ 2301 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2302 iwn4965_power_calibration(sc, temp); 2303 } 2304 2305 if (desc->type != IWN_BEACON_STATISTICS) 2306 return; /* Reply to a statistics request. */ 2307 2308 sc->noise = iwn_get_noise(&stats->rx.general); 2309 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2310 2311 /* Test that RSSI and noise are present in stats report. */ 2312 if (le32toh(stats->rx.general.flags) != 1) { 2313 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2314 "received statistics without RSSI"); 2315 return; 2316 } 2317 2318 if (calib->state == IWN_CALIB_STATE_ASSOC) 2319 iwn_collect_noise(sc, &stats->rx.general); 2320 else if (calib->state == IWN_CALIB_STATE_RUN) 2321 iwn_tune_sensitivity(sc, &stats->rx); 2322 } 2323 2324 /* 2325 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2326 * and 5000 adapters have different incompatible TX status formats. 2327 */ 2328 static void 2329 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2330 struct iwn_rx_data *data) 2331 { 2332 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2333 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2334 2335 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2336 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2337 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2338 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2339 le32toh(stat->status)); 2340 2341 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2342 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2343 } 2344 2345 static void 2346 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2347 struct iwn_rx_data *data) 2348 { 2349 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2350 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2351 2352 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2353 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2354 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2355 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2356 le32toh(stat->status)); 2357 2358 #ifdef notyet 2359 /* Reset TX scheduler slot. */ 2360 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2361 #endif 2362 2363 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2364 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2365 } 2366 2367 /* 2368 * Adapter-independent backend for TX_DONE firmware notifications. 2369 */ 2370 static void 2371 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2372 uint8_t status) 2373 { 2374 struct ifnet *ifp = sc->sc_ifp; 2375 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2376 struct iwn_tx_data *data = &ring->data[desc->idx]; 2377 struct mbuf *m; 2378 struct ieee80211_node *ni; 2379 struct ieee80211vap *vap; 2380 2381 KASSERT(data->ni != NULL, ("no node")); 2382 2383 /* Unmap and free mbuf. */ 2384 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2385 bus_dmamap_unload(ring->data_dmat, data->map); 2386 m = data->m, data->m = NULL; 2387 ni = data->ni, data->ni = NULL; 2388 vap = ni->ni_vap; 2389 2390 if (m->m_flags & M_TXCB) { 2391 /* 2392 * Channels marked for "radar" require traffic to be received 2393 * to unlock before we can transmit. Until traffic is seen 2394 * any attempt to transmit is returned immediately with status 2395 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2396 * happen on first authenticate after scanning. To workaround 2397 * this we ignore a failure of this sort in AUTH state so the 2398 * 802.11 layer will fall back to using a timeout to wait for 2399 * the AUTH reply. This allows the firmware time to see 2400 * traffic so a subsequent retry of AUTH succeeds. It's 2401 * unclear why the firmware does not maintain state for 2402 * channels recently visited as this would allow immediate 2403 * use of the channel after a scan (where we see traffic). 2404 */ 2405 if (status == IWN_TX_FAIL_TX_LOCKED && 2406 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2407 ieee80211_process_callback(ni, m, 0); 2408 else 2409 ieee80211_process_callback(ni, m, 2410 (status & IWN_TX_FAIL) != 0); 2411 } 2412 2413 /* 2414 * Update rate control statistics for the node. 2415 */ 2416 if (status & 0x80) { 2417 ifp->if_oerrors++; 2418 ieee80211_ratectl_tx_complete(vap, ni, 2419 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2420 } else { 2421 ieee80211_ratectl_tx_complete(vap, ni, 2422 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2423 } 2424 m_freem(m); 2425 ieee80211_free_node(ni); 2426 2427 sc->sc_tx_timer = 0; 2428 if (--ring->queued < IWN_TX_RING_LOMARK) { 2429 sc->qfullmsk &= ~(1 << ring->qid); 2430 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 2431 ifq_clr_oactive(&ifp->if_snd); 2432 iwn_start_locked(ifp); 2433 } 2434 } 2435 } 2436 2437 /* 2438 * Process a "command done" firmware notification. This is where we wakeup 2439 * processes waiting for a synchronous command completion. 2440 */ 2441 static void 2442 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2443 { 2444 struct iwn_tx_ring *ring = &sc->txq[4]; 2445 struct iwn_tx_data *data; 2446 2447 if ((desc->qid & 0xf) != 4) 2448 return; /* Not a command ack. */ 2449 2450 data = &ring->data[desc->idx]; 2451 2452 /* If the command was mapped in an mbuf, free it. */ 2453 if (data->m != NULL) { 2454 bus_dmamap_unload(ring->data_dmat, data->map); 2455 m_freem(data->m); 2456 data->m = NULL; 2457 } 2458 wakeup(&ring->desc[desc->idx]); 2459 } 2460 2461 /* 2462 * Process an INT_FH_RX or INT_SW_RX interrupt. 2463 */ 2464 static void 2465 iwn_notif_intr(struct iwn_softc *sc) 2466 { 2467 struct ifnet *ifp = sc->sc_ifp; 2468 struct ieee80211com *ic = ifp->if_l2com; 2469 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2470 uint16_t hw; 2471 2472 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2473 BUS_DMASYNC_POSTREAD); 2474 2475 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2476 while (sc->rxq.cur != hw) { 2477 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2478 struct iwn_rx_desc *desc; 2479 2480 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2481 BUS_DMASYNC_POSTREAD); 2482 desc = mtod(data->m, struct iwn_rx_desc *); 2483 2484 DPRINTF(sc, IWN_DEBUG_RECV, 2485 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2486 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2487 desc->type, iwn_intr_str(desc->type), 2488 le16toh(desc->len)); 2489 2490 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2491 iwn_cmd_done(sc, desc); 2492 2493 switch (desc->type) { 2494 case IWN_RX_PHY: 2495 iwn_rx_phy(sc, desc, data); 2496 break; 2497 2498 case IWN_RX_DONE: /* 4965AGN only. */ 2499 case IWN_MPDU_RX_DONE: 2500 /* An 802.11 frame has been received. */ 2501 iwn_rx_done(sc, desc, data); 2502 break; 2503 2504 #if 0 /* HT */ 2505 case IWN_RX_COMPRESSED_BA: 2506 /* A Compressed BlockAck has been received. */ 2507 iwn_rx_compressed_ba(sc, desc, data); 2508 break; 2509 #endif 2510 2511 case IWN_TX_DONE: 2512 /* An 802.11 frame has been transmitted. */ 2513 sc->sc_hal->tx_done(sc, desc, data); 2514 break; 2515 2516 case IWN_RX_STATISTICS: 2517 case IWN_BEACON_STATISTICS: 2518 iwn_rx_statistics(sc, desc, data); 2519 break; 2520 2521 case IWN_BEACON_MISSED: 2522 { 2523 struct iwn_beacon_missed *miss = 2524 (struct iwn_beacon_missed *)(desc + 1); 2525 int misses; 2526 2527 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2528 BUS_DMASYNC_POSTREAD); 2529 misses = le32toh(miss->consecutive); 2530 2531 /* XXX not sure why we're notified w/ zero */ 2532 if (misses == 0) 2533 break; 2534 DPRINTF(sc, IWN_DEBUG_STATE, 2535 "%s: beacons missed %d/%d\n", __func__, 2536 misses, le32toh(miss->total)); 2537 2538 /* 2539 * If more than 5 consecutive beacons are missed, 2540 * reinitialize the sensitivity state machine. 2541 */ 2542 if (vap->iv_state == IEEE80211_S_RUN && misses > 5) 2543 (void) iwn_init_sensitivity(sc); 2544 if (misses >= vap->iv_bmissthreshold) 2545 ieee80211_beacon_miss(ic); 2546 break; 2547 } 2548 case IWN_UC_READY: 2549 { 2550 struct iwn_ucode_info *uc = 2551 (struct iwn_ucode_info *)(desc + 1); 2552 2553 /* The microcontroller is ready. */ 2554 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2555 BUS_DMASYNC_POSTREAD); 2556 DPRINTF(sc, IWN_DEBUG_RESET, 2557 "microcode alive notification version=%d.%d " 2558 "subtype=%x alive=%x\n", uc->major, uc->minor, 2559 uc->subtype, le32toh(uc->valid)); 2560 2561 if (le32toh(uc->valid) != 1) { 2562 device_printf(sc->sc_dev, 2563 "microcontroller initialization failed"); 2564 break; 2565 } 2566 if (uc->subtype == IWN_UCODE_INIT) { 2567 /* Save microcontroller report. */ 2568 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2569 } 2570 /* Save the address of the error log in SRAM. */ 2571 sc->errptr = le32toh(uc->errptr); 2572 break; 2573 } 2574 case IWN_STATE_CHANGED: 2575 { 2576 uint32_t *status = (uint32_t *)(desc + 1); 2577 2578 /* 2579 * State change allows hardware switch change to be 2580 * noted. However, we handle this in iwn_intr as we 2581 * get both the enable/disble intr. 2582 */ 2583 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2584 BUS_DMASYNC_POSTREAD); 2585 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2586 le32toh(*status)); 2587 break; 2588 } 2589 case IWN_START_SCAN: 2590 { 2591 struct iwn_start_scan *scan = 2592 (struct iwn_start_scan *)(desc + 1); 2593 2594 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2595 BUS_DMASYNC_POSTREAD); 2596 DPRINTF(sc, IWN_DEBUG_ANY, 2597 "%s: scanning channel %d status %x\n", 2598 __func__, scan->chan, le32toh(scan->status)); 2599 break; 2600 } 2601 case IWN_STOP_SCAN: 2602 { 2603 struct iwn_stop_scan *scan = 2604 (struct iwn_stop_scan *)(desc + 1); 2605 2606 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2607 BUS_DMASYNC_POSTREAD); 2608 DPRINTF(sc, IWN_DEBUG_STATE, 2609 "scan finished nchan=%d status=%d chan=%d\n", 2610 scan->nchan, scan->status, scan->chan); 2611 2612 ieee80211_scan_next(vap); 2613 break; 2614 } 2615 case IWN5000_CALIBRATION_RESULT: 2616 iwn5000_rx_calib_results(sc, desc, data); 2617 break; 2618 2619 case IWN5000_CALIBRATION_DONE: 2620 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2621 wakeup(sc); 2622 break; 2623 } 2624 2625 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2626 } 2627 2628 /* Tell the firmware what we have processed. */ 2629 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2630 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2631 } 2632 2633 /* 2634 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2635 * from power-down sleep mode. 2636 */ 2637 static void 2638 iwn_wakeup_intr(struct iwn_softc *sc) 2639 { 2640 int qid; 2641 2642 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2643 __func__); 2644 2645 /* Wakeup RX and TX rings. */ 2646 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2647 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2648 struct iwn_tx_ring *ring = &sc->txq[qid]; 2649 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2650 } 2651 } 2652 2653 static void 2654 iwn_rftoggle_intr(struct iwn_softc *sc) 2655 { 2656 struct ifnet *ifp = sc->sc_ifp; 2657 struct ieee80211com *ic = ifp->if_l2com; 2658 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2659 2660 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2661 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2662 if (tmp & IWN_GP_CNTRL_RFKILL) 2663 ieee80211_runtask(ic, &sc->sc_radioon_task); 2664 else 2665 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2666 } 2667 2668 /* 2669 * Dump the error log of the firmware when a firmware panic occurs. Although 2670 * we can't debug the firmware because it is neither open source nor free, it 2671 * can help us to identify certain classes of problems. 2672 */ 2673 static void 2674 iwn_fatal_intr(struct iwn_softc *sc) 2675 { 2676 const struct iwn_hal *hal = sc->sc_hal; 2677 struct iwn_fw_dump dump; 2678 int i; 2679 2680 /* Force a complete recalibration on next init. */ 2681 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2682 2683 /* Check that the error log address is valid. */ 2684 if (sc->errptr < IWN_FW_DATA_BASE || 2685 sc->errptr + sizeof (dump) > 2686 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2687 kprintf("%s: bad firmware error log address 0x%08x\n", 2688 __func__, sc->errptr); 2689 return; 2690 } 2691 if (iwn_nic_lock(sc) != 0) { 2692 kprintf("%s: could not read firmware error log\n", 2693 __func__); 2694 return; 2695 } 2696 /* Read firmware error log from SRAM. */ 2697 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2698 sizeof (dump) / sizeof (uint32_t)); 2699 iwn_nic_unlock(sc); 2700 2701 if (dump.valid == 0) { 2702 kprintf("%s: firmware error log is empty\n", 2703 __func__); 2704 return; 2705 } 2706 kprintf("firmware error log:\n"); 2707 kprintf(" error type = \"%s\" (0x%08X)\n", 2708 (dump.id < NELEM(iwn_fw_errmsg)) ? 2709 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2710 dump.id); 2711 kprintf(" program counter = 0x%08X\n", dump.pc); 2712 kprintf(" source line = 0x%08X\n", dump.src_line); 2713 kprintf(" error data = 0x%08X%08X\n", 2714 dump.error_data[0], dump.error_data[1]); 2715 kprintf(" branch link = 0x%08X%08X\n", 2716 dump.branch_link[0], dump.branch_link[1]); 2717 kprintf(" interrupt link = 0x%08X%08X\n", 2718 dump.interrupt_link[0], dump.interrupt_link[1]); 2719 kprintf(" time = %u\n", dump.time[0]); 2720 2721 /* Dump driver status (TX and RX rings) while we're here. */ 2722 kprintf("driver status:\n"); 2723 for (i = 0; i < hal->ntxqs; i++) { 2724 struct iwn_tx_ring *ring = &sc->txq[i]; 2725 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2726 i, ring->qid, ring->cur, ring->queued); 2727 } 2728 kprintf(" rx ring: cur=%d\n", sc->rxq.cur); 2729 } 2730 2731 static void 2732 iwn_intr(void *arg) 2733 { 2734 struct iwn_softc *sc = arg; 2735 struct ifnet *ifp = sc->sc_ifp; 2736 uint32_t r1, r2, tmp; 2737 2738 /* Disable interrupts. */ 2739 IWN_WRITE(sc, IWN_INT_MASK, 0); 2740 2741 /* Read interrupts from ICT (fast) or from registers (slow). */ 2742 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2743 tmp = 0; 2744 while (sc->ict[sc->ict_cur] != 0) { 2745 tmp |= sc->ict[sc->ict_cur]; 2746 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2747 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2748 } 2749 tmp = le32toh(tmp); 2750 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2751 tmp = 0; 2752 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2753 tmp |= 0x8000; 2754 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2755 r2 = 0; /* Unused. */ 2756 } else { 2757 r1 = IWN_READ(sc, IWN_INT); 2758 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2759 return; /* Hardware gone! */ 2760 r2 = IWN_READ(sc, IWN_FH_INT); 2761 } 2762 2763 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2764 2765 if (r1 == 0 && r2 == 0) 2766 goto done; /* Interrupt not for us. */ 2767 2768 /* Acknowledge interrupts. */ 2769 IWN_WRITE(sc, IWN_INT, r1); 2770 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2771 IWN_WRITE(sc, IWN_FH_INT, r2); 2772 2773 if (r1 & IWN_INT_RF_TOGGLED) { 2774 iwn_rftoggle_intr(sc); 2775 goto done; 2776 } 2777 if (r1 & IWN_INT_CT_REACHED) { 2778 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2779 __func__); 2780 } 2781 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2782 iwn_fatal_intr(sc); 2783 ifp->if_flags &= ~IFF_UP; 2784 iwn_stop_locked(sc); 2785 goto done; 2786 } 2787 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2788 (r2 & IWN_FH_INT_RX)) { 2789 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2790 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2791 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2792 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2793 IWN_INT_PERIODIC_DIS); 2794 iwn_notif_intr(sc); 2795 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2796 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2797 IWN_INT_PERIODIC_ENA); 2798 } 2799 } else 2800 iwn_notif_intr(sc); 2801 } 2802 2803 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2804 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2805 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2806 wakeup(sc); /* FH DMA transfer completed. */ 2807 } 2808 2809 if (r1 & IWN_INT_ALIVE) 2810 wakeup(sc); /* Firmware is alive. */ 2811 2812 if (r1 & IWN_INT_WAKEUP) 2813 iwn_wakeup_intr(sc); 2814 2815 done: 2816 /* Re-enable interrupts. */ 2817 if (ifp->if_flags & IFF_UP) 2818 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2819 } 2820 2821 /* 2822 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2823 * 5000 adapters use a slightly different format.) 2824 */ 2825 static void 2826 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2827 uint16_t len) 2828 { 2829 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2830 2831 *w = htole16(len + 8); 2832 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2833 BUS_DMASYNC_PREWRITE); 2834 if (idx < IWN_SCHED_WINSZ) { 2835 *(w + IWN_TX_RING_COUNT) = *w; 2836 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2837 BUS_DMASYNC_PREWRITE); 2838 } 2839 } 2840 2841 static void 2842 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2843 uint16_t len) 2844 { 2845 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2846 2847 *w = htole16(id << 12 | (len + 8)); 2848 2849 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2850 BUS_DMASYNC_PREWRITE); 2851 if (idx < IWN_SCHED_WINSZ) { 2852 *(w + IWN_TX_RING_COUNT) = *w; 2853 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2854 BUS_DMASYNC_PREWRITE); 2855 } 2856 } 2857 2858 #ifdef notyet 2859 static void 2860 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2861 { 2862 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2863 2864 *w = (*w & htole16(0xf000)) | htole16(1); 2865 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2866 BUS_DMASYNC_PREWRITE); 2867 if (idx < IWN_SCHED_WINSZ) { 2868 *(w + IWN_TX_RING_COUNT) = *w; 2869 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2870 BUS_DMASYNC_PREWRITE); 2871 } 2872 } 2873 #endif 2874 2875 static uint8_t 2876 iwn_plcp_signal(int rate) { 2877 int i; 2878 2879 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 2880 if (rate == iwn_rates[i].rate) 2881 return i; 2882 } 2883 2884 return 0; 2885 } 2886 2887 static int 2888 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2889 struct iwn_tx_ring *ring) 2890 { 2891 const struct iwn_hal *hal = sc->sc_hal; 2892 const struct ieee80211_txparam *tp; 2893 const struct iwn_rate *rinfo; 2894 struct ieee80211vap *vap = ni->ni_vap; 2895 struct ieee80211com *ic = ni->ni_ic; 2896 struct iwn_node *wn = (void *)ni; 2897 struct iwn_tx_desc *desc; 2898 struct iwn_tx_data *data; 2899 struct iwn_tx_cmd *cmd; 2900 struct iwn_cmd_data *tx; 2901 struct ieee80211_frame *wh; 2902 struct ieee80211_key *k = NULL; 2903 struct mbuf *mnew; 2904 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 2905 uint32_t flags; 2906 u_int hdrlen; 2907 int totlen, error, pad, nsegs = 0, i, rate; 2908 uint8_t ridx, type, txant; 2909 2910 wh = mtod(m, struct ieee80211_frame *); 2911 hdrlen = ieee80211_anyhdrsize(wh); 2912 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2913 2914 desc = &ring->desc[ring->cur]; 2915 data = &ring->data[ring->cur]; 2916 2917 /* Choose a TX rate index. */ 2918 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 2919 if (type == IEEE80211_FC0_TYPE_MGT) 2920 rate = tp->mgmtrate; 2921 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2922 rate = tp->mcastrate; 2923 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2924 rate = tp->ucastrate; 2925 else { 2926 /* XXX pass pktlen */ 2927 ieee80211_ratectl_rate(ni, NULL, 0); 2928 2929 rate = ni->ni_txrate; 2930 } 2931 ridx = iwn_plcp_signal(rate); 2932 rinfo = &iwn_rates[ridx]; 2933 2934 /* Encrypt the frame if need be. */ 2935 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2936 k = ieee80211_crypto_encap(ni, m); 2937 if (k == NULL) { 2938 m_freem(m); 2939 return ENOBUFS; 2940 } 2941 /* Packet header may have moved, reset our local pointer. */ 2942 wh = mtod(m, struct ieee80211_frame *); 2943 } 2944 totlen = m->m_pkthdr.len; 2945 2946 if (ieee80211_radiotap_active_vap(vap)) { 2947 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2948 2949 tap->wt_flags = 0; 2950 tap->wt_rate = rinfo->rate; 2951 if (k != NULL) 2952 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2953 2954 ieee80211_radiotap_tx(vap, m); 2955 } 2956 2957 /* Prepare TX firmware command. */ 2958 cmd = &ring->cmd[ring->cur]; 2959 cmd->code = IWN_CMD_TX_DATA; 2960 cmd->flags = 0; 2961 cmd->qid = ring->qid; 2962 cmd->idx = ring->cur; 2963 2964 tx = (struct iwn_cmd_data *)cmd->data; 2965 /* NB: No need to clear tx, all fields are reinitialized here. */ 2966 tx->scratch = 0; /* clear "scratch" area */ 2967 2968 flags = 0; 2969 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) 2970 flags |= IWN_TX_NEED_ACK; 2971 if ((wh->i_fc[0] & 2972 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2973 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2974 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2975 2976 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2977 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2978 2979 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2980 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2981 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2982 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 2983 flags |= IWN_TX_NEED_RTS; 2984 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2985 ridx >= IWN_RIDX_OFDM6) { 2986 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2987 flags |= IWN_TX_NEED_CTS; 2988 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2989 flags |= IWN_TX_NEED_RTS; 2990 } 2991 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2992 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2993 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2994 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2995 flags |= IWN_TX_NEED_PROTECTION; 2996 } else 2997 flags |= IWN_TX_FULL_TXOP; 2998 } 2999 } 3000 3001 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3002 type != IEEE80211_FC0_TYPE_DATA) 3003 tx->id = hal->broadcast_id; 3004 else 3005 tx->id = wn->id; 3006 3007 if (type == IEEE80211_FC0_TYPE_MGT) { 3008 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3009 3010 /* Tell HW to set timestamp in probe responses. */ 3011 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3012 flags |= IWN_TX_INSERT_TSTAMP; 3013 3014 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3015 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3016 tx->timeout = htole16(3); 3017 else 3018 tx->timeout = htole16(2); 3019 } else 3020 tx->timeout = htole16(0); 3021 3022 if (hdrlen & 3) { 3023 /* First segment length must be a multiple of 4. */ 3024 flags |= IWN_TX_NEED_PADDING; 3025 pad = 4 - (hdrlen & 3); 3026 } else 3027 pad = 0; 3028 3029 tx->len = htole16(totlen); 3030 tx->tid = 0; 3031 tx->rts_ntries = 60; 3032 tx->data_ntries = 15; 3033 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3034 tx->plcp = rinfo->plcp; 3035 tx->rflags = rinfo->flags; 3036 if (tx->id == hal->broadcast_id) { 3037 /* Group or management frame. */ 3038 tx->linkq = 0; 3039 /* XXX Alternate between antenna A and B? */ 3040 txant = IWN_LSB(sc->txchainmask); 3041 tx->rflags |= IWN_RFLAG_ANT(txant); 3042 } else { 3043 tx->linkq = IWN_RIDX_OFDM54 - ridx; 3044 flags |= IWN_TX_LINKQ; /* enable MRR */ 3045 } 3046 3047 /* Set physical address of "scratch area". */ 3048 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3049 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3050 3051 /* Copy 802.11 header in TX command. */ 3052 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3053 3054 /* Trim 802.11 header. */ 3055 m_adj(m, hdrlen); 3056 tx->security = 0; 3057 tx->flags = htole32(flags); 3058 3059 if (m->m_len > 0) { 3060 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 3061 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3062 if (error == EFBIG) { 3063 /* too many fragments, linearize */ 3064 mnew = m_defrag(m, MB_DONTWAIT); 3065 if (mnew == NULL) { 3066 device_printf(sc->sc_dev, 3067 "%s: could not defrag mbuf\n", __func__); 3068 m_freem(m); 3069 return ENOBUFS; 3070 } 3071 m = mnew; 3072 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 3073 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3074 } 3075 if (error != 0) { 3076 device_printf(sc->sc_dev, 3077 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n", 3078 __func__, error); 3079 m_freem(m); 3080 return error; 3081 } 3082 } 3083 3084 data->m = m; 3085 data->ni = ni; 3086 3087 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3088 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3089 3090 /* Fill TX descriptor. */ 3091 desc->nsegs = 1 + nsegs; 3092 /* First DMA segment is used by the TX command. */ 3093 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3094 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3095 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3096 /* Other DMA segments are for data payload. */ 3097 for (i = 1; i <= nsegs; i++) { 3098 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3099 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3100 segs[i - 1].ds_len << 4); 3101 } 3102 3103 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3104 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3105 BUS_DMASYNC_PREWRITE); 3106 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3107 BUS_DMASYNC_PREWRITE); 3108 3109 #ifdef notyet 3110 /* Update TX scheduler. */ 3111 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3112 #endif 3113 3114 /* Kick TX ring. */ 3115 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3116 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3117 3118 /* Mark TX ring as full if we reach a certain threshold. */ 3119 if (++ring->queued > IWN_TX_RING_HIMARK) 3120 sc->qfullmsk |= 1 << ring->qid; 3121 3122 return 0; 3123 } 3124 3125 static int 3126 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3127 struct ieee80211_node *ni, struct iwn_tx_ring *ring, 3128 const struct ieee80211_bpf_params *params) 3129 { 3130 const struct iwn_hal *hal = sc->sc_hal; 3131 const struct iwn_rate *rinfo; 3132 struct ifnet *ifp = sc->sc_ifp; 3133 struct ieee80211vap *vap = ni->ni_vap; 3134 struct ieee80211com *ic = ifp->if_l2com; 3135 struct iwn_tx_cmd *cmd; 3136 struct iwn_cmd_data *tx; 3137 struct ieee80211_frame *wh; 3138 struct iwn_tx_desc *desc; 3139 struct iwn_tx_data *data; 3140 struct mbuf *mnew; 3141 bus_addr_t paddr; 3142 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 3143 uint32_t flags; 3144 u_int hdrlen; 3145 int totlen, error, pad, nsegs = 0, i, rate; 3146 uint8_t ridx, type, txant; 3147 3148 wh = mtod(m, struct ieee80211_frame *); 3149 hdrlen = ieee80211_anyhdrsize(wh); 3150 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3151 3152 desc = &ring->desc[ring->cur]; 3153 data = &ring->data[ring->cur]; 3154 3155 /* Choose a TX rate index. */ 3156 rate = params->ibp_rate0; 3157 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3158 /* XXX fall back to mcast/mgmt rate? */ 3159 m_freem(m); 3160 return EINVAL; 3161 } 3162 ridx = iwn_plcp_signal(rate); 3163 rinfo = &iwn_rates[ridx]; 3164 3165 totlen = m->m_pkthdr.len; 3166 3167 /* Prepare TX firmware command. */ 3168 cmd = &ring->cmd[ring->cur]; 3169 cmd->code = IWN_CMD_TX_DATA; 3170 cmd->flags = 0; 3171 cmd->qid = ring->qid; 3172 cmd->idx = ring->cur; 3173 3174 tx = (struct iwn_cmd_data *)cmd->data; 3175 /* NB: No need to clear tx, all fields are reinitialized here. */ 3176 tx->scratch = 0; /* clear "scratch" area */ 3177 3178 flags = 0; 3179 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3180 flags |= IWN_TX_NEED_ACK; 3181 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3182 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3183 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3184 flags &= ~IWN_TX_NEED_RTS; 3185 flags |= IWN_TX_NEED_PROTECTION; 3186 } else 3187 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3188 } 3189 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3190 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3191 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3192 flags &= ~IWN_TX_NEED_CTS; 3193 flags |= IWN_TX_NEED_PROTECTION; 3194 } else 3195 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3196 } 3197 if (type == IEEE80211_FC0_TYPE_MGT) { 3198 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3199 3200 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3201 flags |= IWN_TX_INSERT_TSTAMP; 3202 3203 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3204 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3205 tx->timeout = htole16(3); 3206 else 3207 tx->timeout = htole16(2); 3208 } else 3209 tx->timeout = htole16(0); 3210 3211 if (hdrlen & 3) { 3212 /* First segment length must be a multiple of 4. */ 3213 flags |= IWN_TX_NEED_PADDING; 3214 pad = 4 - (hdrlen & 3); 3215 } else 3216 pad = 0; 3217 3218 if (ieee80211_radiotap_active_vap(vap)) { 3219 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3220 3221 tap->wt_flags = 0; 3222 tap->wt_rate = rate; 3223 3224 ieee80211_radiotap_tx(vap, m); 3225 } 3226 3227 tx->len = htole16(totlen); 3228 tx->tid = 0; 3229 tx->id = hal->broadcast_id; 3230 tx->rts_ntries = params->ibp_try1; 3231 tx->data_ntries = params->ibp_try0; 3232 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3233 tx->plcp = rinfo->plcp; 3234 tx->rflags = rinfo->flags; 3235 /* Group or management frame. */ 3236 tx->linkq = 0; 3237 txant = IWN_LSB(sc->txchainmask); 3238 tx->rflags |= IWN_RFLAG_ANT(txant); 3239 /* Set physical address of "scratch area". */ 3240 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd); 3241 tx->loaddr = htole32(IWN_LOADDR(paddr)); 3242 tx->hiaddr = IWN_HIADDR(paddr); 3243 3244 /* Copy 802.11 header in TX command. */ 3245 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3246 3247 /* Trim 802.11 header. */ 3248 m_adj(m, hdrlen); 3249 tx->security = 0; 3250 tx->flags = htole32(flags); 3251 3252 if (m->m_len > 0) { 3253 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 3254 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3255 if (error == EFBIG) { 3256 /* Too many fragments, linearize. */ 3257 mnew = m_defrag(m, MB_DONTWAIT); 3258 if (mnew == NULL) { 3259 device_printf(sc->sc_dev, 3260 "%s: could not defrag mbuf\n", __func__); 3261 m_freem(m); 3262 return ENOBUFS; 3263 } 3264 m = mnew; 3265 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 3266 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3267 } 3268 if (error != 0) { 3269 device_printf(sc->sc_dev, 3270 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n", 3271 __func__, error); 3272 m_freem(m); 3273 return error; 3274 } 3275 } 3276 3277 data->m = m; 3278 data->ni = ni; 3279 3280 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3281 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3282 3283 /* Fill TX descriptor. */ 3284 desc->nsegs = 1 + nsegs; 3285 /* First DMA segment is used by the TX command. */ 3286 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3287 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3288 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3289 /* Other DMA segments are for data payload. */ 3290 for (i = 1; i <= nsegs; i++) { 3291 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3292 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3293 segs[i - 1].ds_len << 4); 3294 } 3295 3296 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3297 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3298 BUS_DMASYNC_PREWRITE); 3299 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3300 BUS_DMASYNC_PREWRITE); 3301 3302 #ifdef notyet 3303 /* Update TX scheduler. */ 3304 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3305 #endif 3306 3307 /* Kick TX ring. */ 3308 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3309 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3310 3311 /* Mark TX ring as full if we reach a certain threshold. */ 3312 if (++ring->queued > IWN_TX_RING_HIMARK) 3313 sc->qfullmsk |= 1 << ring->qid; 3314 3315 return 0; 3316 } 3317 3318 static int 3319 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3320 const struct ieee80211_bpf_params *params) 3321 { 3322 struct ieee80211com *ic = ni->ni_ic; 3323 struct ifnet *ifp = ic->ic_ifp; 3324 struct iwn_softc *sc = ifp->if_softc; 3325 struct iwn_tx_ring *txq; 3326 int error = 0; 3327 3328 if ((ifp->if_flags & IFF_RUNNING) == 0) { 3329 ieee80211_free_node(ni); 3330 m_freem(m); 3331 return ENETDOWN; 3332 } 3333 3334 if (params == NULL) 3335 txq = &sc->txq[M_WME_GETAC(m)]; 3336 else 3337 txq = &sc->txq[params->ibp_pri & 3]; 3338 3339 if (params == NULL) { 3340 /* 3341 * Legacy path; interpret frame contents to decide 3342 * precisely how to send the frame. 3343 */ 3344 error = iwn_tx_data(sc, m, ni, txq); 3345 } else { 3346 /* 3347 * Caller supplied explicit parameters to use in 3348 * sending the frame. 3349 */ 3350 error = iwn_tx_data_raw(sc, m, ni, txq, params); 3351 } 3352 if (error != 0) { 3353 /* NB: m is reclaimed on tx failure */ 3354 ieee80211_free_node(ni); 3355 ifp->if_oerrors++; 3356 } 3357 return error; 3358 } 3359 3360 static void 3361 iwn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3362 { 3363 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 3364 wlan_serialize_enter(); 3365 iwn_start_locked(ifp); 3366 wlan_serialize_exit(); 3367 } 3368 3369 static void 3370 iwn_start_locked(struct ifnet *ifp) 3371 { 3372 struct iwn_softc *sc = ifp->if_softc; 3373 struct ieee80211_node *ni; 3374 struct iwn_tx_ring *txq; 3375 struct mbuf *m; 3376 int pri; 3377 3378 for (;;) { 3379 if (sc->qfullmsk != 0) { 3380 ifq_set_oactive(&ifp->if_snd); 3381 break; 3382 } 3383 m = ifq_dequeue(&ifp->if_snd, NULL); 3384 if (m == NULL) 3385 break; 3386 KKASSERT(M_TRAILINGSPACE(m) >= 0); 3387 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3388 pri = M_WME_GETAC(m); 3389 txq = &sc->txq[pri]; 3390 if (iwn_tx_data(sc, m, ni, txq) != 0) { 3391 ifp->if_oerrors++; 3392 ieee80211_free_node(ni); 3393 break; 3394 } 3395 sc->sc_tx_timer = 5; 3396 } 3397 } 3398 3399 static void 3400 iwn_watchdog(struct iwn_softc *sc) 3401 { 3402 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 3403 struct ifnet *ifp = sc->sc_ifp; 3404 struct ieee80211com *ic = ifp->if_l2com; 3405 3406 if_printf(ifp, "device timeout\n"); 3407 ieee80211_runtask(ic, &sc->sc_reinit_task); 3408 } 3409 } 3410 3411 static int 3412 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 3413 { 3414 struct iwn_softc *sc = ifp->if_softc; 3415 struct ieee80211com *ic = ifp->if_l2com; 3416 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3417 struct ifreq *ifr = (struct ifreq *) data; 3418 int error = 0, startall = 0, stop = 0; 3419 3420 switch (cmd) { 3421 case SIOCSIFFLAGS: 3422 if (ifp->if_flags & IFF_UP) { 3423 if (!(ifp->if_flags & IFF_RUNNING)) { 3424 iwn_init_locked(sc); 3425 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3426 startall = 1; 3427 else 3428 stop = 1; 3429 } 3430 } else { 3431 if (ifp->if_flags & IFF_RUNNING) 3432 iwn_stop_locked(sc); 3433 } 3434 if (startall) 3435 ieee80211_start_all(ic); 3436 else if (vap != NULL && stop) 3437 ieee80211_stop(vap); 3438 break; 3439 case SIOCGIFMEDIA: 3440 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3441 break; 3442 case SIOCGIFADDR: 3443 error = ether_ioctl(ifp, cmd, data); 3444 break; 3445 default: 3446 error = EINVAL; 3447 break; 3448 } 3449 return error; 3450 } 3451 3452 /* 3453 * Send a command to the firmware. 3454 */ 3455 static int 3456 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3457 { 3458 struct iwn_tx_ring *ring = &sc->txq[4]; 3459 struct iwn_tx_desc *desc; 3460 struct iwn_tx_data *data; 3461 struct iwn_tx_cmd *cmd; 3462 struct mbuf *m; 3463 bus_addr_t paddr; 3464 int totlen, error; 3465 3466 desc = &ring->desc[ring->cur]; 3467 data = &ring->data[ring->cur]; 3468 totlen = 4 + size; 3469 3470 if (size > sizeof cmd->data) { 3471 /* Command is too large to fit in a descriptor. */ 3472 if (totlen > MJUMPAGESIZE) 3473 return EINVAL; 3474 m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3475 if (m == NULL) 3476 return ENOMEM; 3477 cmd = mtod(m, struct iwn_tx_cmd *); 3478 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3479 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3480 if (error != 0) { 3481 m_freem(m); 3482 return error; 3483 } 3484 data->m = m; 3485 } else { 3486 cmd = &ring->cmd[ring->cur]; 3487 paddr = data->cmd_paddr; 3488 } 3489 3490 cmd->code = code; 3491 cmd->flags = 0; 3492 cmd->qid = ring->qid; 3493 cmd->idx = ring->cur; 3494 memcpy(cmd->data, buf, size); 3495 3496 desc->nsegs = 1; 3497 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3498 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3499 3500 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3501 __func__, iwn_intr_str(cmd->code), cmd->code, 3502 cmd->flags, cmd->qid, cmd->idx); 3503 3504 if (size > sizeof cmd->data) { 3505 bus_dmamap_sync(ring->data_dmat, data->map, 3506 BUS_DMASYNC_PREWRITE); 3507 } else { 3508 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3509 BUS_DMASYNC_PREWRITE); 3510 } 3511 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3512 BUS_DMASYNC_PREWRITE); 3513 3514 #ifdef notyet 3515 /* Update TX scheduler. */ 3516 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3517 #endif 3518 3519 /* Kick command ring. */ 3520 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3521 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3522 3523 if (async) 3524 error = 0; 3525 else 3526 error = zsleep(desc, &wlan_global_serializer, 0, "iwncmd", hz); 3527 return error; 3528 } 3529 3530 static int 3531 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3532 { 3533 struct iwn4965_node_info hnode; 3534 caddr_t src, dst; 3535 3536 /* 3537 * We use the node structure for 5000 Series internally (it is 3538 * a superset of the one for 4965AGN). We thus copy the common 3539 * fields before sending the command. 3540 */ 3541 src = (caddr_t)node; 3542 dst = (caddr_t)&hnode; 3543 memcpy(dst, src, 48); 3544 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3545 memcpy(dst + 48, src + 72, 20); 3546 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3547 } 3548 3549 static int 3550 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3551 { 3552 /* Direct mapping. */ 3553 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3554 } 3555 3556 #if 0 /* HT */ 3557 static const uint8_t iwn_ridx_to_plcp[] = { 3558 10, 20, 55, 110, /* CCK */ 3559 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */ 3560 }; 3561 static const uint8_t iwn_siso_mcs_to_plcp[] = { 3562 0, 0, 0, 0, /* CCK */ 3563 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */ 3564 }; 3565 static const uint8_t iwn_mimo_mcs_to_plcp[] = { 3566 0, 0, 0, 0, /* CCK */ 3567 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */ 3568 }; 3569 #endif 3570 static const uint8_t iwn_prev_ridx[] = { 3571 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */ 3572 0, 0, 1, 5, /* CCK */ 3573 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */ 3574 }; 3575 3576 /* 3577 * Configure hardware link parameters for the specified 3578 * node operating on the specified channel. 3579 */ 3580 static int 3581 iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async) 3582 { 3583 struct ifnet *ifp = sc->sc_ifp; 3584 struct ieee80211com *ic = ifp->if_l2com; 3585 struct iwn_cmd_link_quality linkq; 3586 const struct iwn_rate *rinfo; 3587 int i; 3588 uint8_t txant, ridx; 3589 3590 /* Use the first valid TX antenna. */ 3591 txant = IWN_LSB(sc->txchainmask); 3592 3593 memset(&linkq, 0, sizeof linkq); 3594 linkq.id = id; 3595 linkq.antmsk_1stream = txant; 3596 linkq.antmsk_2stream = IWN_ANT_AB; 3597 linkq.ampdu_max = 31; 3598 linkq.ampdu_threshold = 3; 3599 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3600 3601 #if 0 /* HT */ 3602 if (IEEE80211_IS_CHAN_HT(c)) 3603 linkq.mimo = 1; 3604 #endif 3605 3606 if (id == IWN_ID_BSS) 3607 ridx = IWN_RIDX_OFDM54; 3608 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) 3609 ridx = IWN_RIDX_OFDM6; 3610 else 3611 ridx = IWN_RIDX_CCK1; 3612 3613 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3614 rinfo = &iwn_rates[ridx]; 3615 #if 0 /* HT */ 3616 if (IEEE80211_IS_CHAN_HT40(c)) { 3617 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx] 3618 | IWN_RIDX_MCS; 3619 linkq.retry[i].rflags = IWN_RFLAG_HT 3620 | IWN_RFLAG_HT40; 3621 /* XXX shortGI */ 3622 } else if (IEEE80211_IS_CHAN_HT(c)) { 3623 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx] 3624 | IWN_RIDX_MCS; 3625 linkq.retry[i].rflags = IWN_RFLAG_HT; 3626 /* XXX shortGI */ 3627 } else 3628 #endif 3629 { 3630 linkq.retry[i].plcp = rinfo->plcp; 3631 linkq.retry[i].rflags = rinfo->flags; 3632 } 3633 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3634 ridx = iwn_prev_ridx[ridx]; 3635 } 3636 #ifdef IWN_DEBUG 3637 if (sc->sc_debug & IWN_DEBUG_STATE) { 3638 kprintf("%s: set link quality for node %d, mimo %d ssmask %d\n", 3639 __func__, id, linkq.mimo, linkq.antmsk_1stream); 3640 kprintf("%s:", __func__); 3641 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) 3642 kprintf(" %d:%x", linkq.retry[i].plcp, 3643 linkq.retry[i].rflags); 3644 kprintf("\n"); 3645 } 3646 #endif 3647 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3648 } 3649 3650 /* 3651 * Broadcast node is used to send group-addressed and management frames. 3652 */ 3653 static int 3654 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3655 { 3656 const struct iwn_hal *hal = sc->sc_hal; 3657 struct ifnet *ifp = sc->sc_ifp; 3658 struct iwn_node_info node; 3659 int error; 3660 3661 memset(&node, 0, sizeof node); 3662 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3663 node.id = hal->broadcast_id; 3664 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3665 error = hal->add_node(sc, &node, async); 3666 if (error != 0) 3667 return error; 3668 3669 error = iwn_set_link_quality(sc, hal->broadcast_id, async); 3670 return error; 3671 } 3672 3673 static int 3674 iwn_wme_update(struct ieee80211com *ic) 3675 { 3676 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3677 #define IWN_TXOP_TO_US(v) (v<<5) 3678 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3679 struct iwn_edca_params cmd; 3680 int i; 3681 3682 memset(&cmd, 0, sizeof cmd); 3683 cmd.flags = htole32(IWN_EDCA_UPDATE); 3684 for (i = 0; i < WME_NUM_AC; i++) { 3685 const struct wmeParams *wmep = 3686 &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 3687 cmd.ac[i].aifsn = wmep->wmep_aifsn; 3688 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin)); 3689 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax)); 3690 cmd.ac[i].txoplimit = 3691 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit)); 3692 } 3693 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/); 3694 return 0; 3695 #undef IWN_TXOP_TO_US 3696 #undef IWN_EXP2 3697 } 3698 3699 static void 3700 iwn_update_mcast(struct ifnet *ifp) 3701 { 3702 /* Ignore */ 3703 } 3704 3705 static void 3706 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3707 { 3708 struct iwn_cmd_led led; 3709 3710 /* Clear microcode LED ownership. */ 3711 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3712 3713 led.which = which; 3714 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3715 led.off = off; 3716 led.on = on; 3717 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3718 } 3719 3720 /* 3721 * Set the critical temperature at which the firmware will stop the radio 3722 * and notify us. 3723 */ 3724 static int 3725 iwn_set_critical_temp(struct iwn_softc *sc) 3726 { 3727 struct iwn_critical_temp crit; 3728 int32_t temp; 3729 3730 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3731 3732 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3733 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3734 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3735 temp = IWN_CTOK(110); 3736 else 3737 temp = 110; 3738 memset(&crit, 0, sizeof crit); 3739 crit.tempR = htole32(temp); 3740 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", 3741 temp); 3742 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3743 } 3744 3745 static int 3746 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3747 { 3748 struct iwn_cmd_timing cmd; 3749 uint64_t val, mod; 3750 3751 memset(&cmd, 0, sizeof cmd); 3752 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3753 cmd.bintval = htole16(ni->ni_intval); 3754 cmd.lintval = htole16(10); 3755 3756 /* Compute remaining time until next beacon. */ 3757 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3758 mod = le64toh(cmd.tstamp) % val; 3759 cmd.binitval = htole32((uint32_t)(val - mod)); 3760 3761 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3762 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3763 3764 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3765 } 3766 3767 static void 3768 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3769 { 3770 struct ifnet *ifp = sc->sc_ifp; 3771 struct ieee80211com *ic = ifp->if_l2com; 3772 3773 /* Adjust TX power if need be (delta >= 3 degC.) */ 3774 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3775 __func__, sc->temp, temp); 3776 if (abs(temp - sc->temp) >= 3) { 3777 /* Record temperature of last calibration. */ 3778 sc->temp = temp; 3779 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 3780 } 3781 } 3782 3783 /* 3784 * Set TX power for current channel (each rate has its own power settings). 3785 * This function takes into account the regulatory information from EEPROM, 3786 * the current temperature and the current voltage. 3787 */ 3788 static int 3789 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3790 int async) 3791 { 3792 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3793 #define fdivround(a, b, n) \ 3794 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3795 /* Linear interpolation. */ 3796 #define interpolate(x, x1, y1, x2, y2, n) \ 3797 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3798 3799 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3800 struct ifnet *ifp = sc->sc_ifp; 3801 struct ieee80211com *ic = ifp->if_l2com; 3802 struct iwn_ucode_info *uc = &sc->ucode_info; 3803 struct iwn4965_cmd_txpower cmd; 3804 struct iwn4965_eeprom_chan_samples *chans; 3805 int32_t vdiff, tdiff; 3806 int i, c, grp, maxpwr; 3807 const uint8_t *rf_gain, *dsp_gain; 3808 uint8_t chan; 3809 3810 /* Retrieve channel number. */ 3811 chan = ieee80211_chan2ieee(ic, ch); 3812 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 3813 chan); 3814 3815 memset(&cmd, 0, sizeof cmd); 3816 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3817 cmd.chan = chan; 3818 3819 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3820 maxpwr = sc->maxpwr5GHz; 3821 rf_gain = iwn4965_rf_gain_5ghz; 3822 dsp_gain = iwn4965_dsp_gain_5ghz; 3823 } else { 3824 maxpwr = sc->maxpwr2GHz; 3825 rf_gain = iwn4965_rf_gain_2ghz; 3826 dsp_gain = iwn4965_dsp_gain_2ghz; 3827 } 3828 3829 /* Compute voltage compensation. */ 3830 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3831 if (vdiff > 0) 3832 vdiff *= 2; 3833 if (abs(vdiff) > 2) 3834 vdiff = 0; 3835 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3836 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3837 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 3838 3839 /* Get channel attenuation group. */ 3840 if (chan <= 20) /* 1-20 */ 3841 grp = 4; 3842 else if (chan <= 43) /* 34-43 */ 3843 grp = 0; 3844 else if (chan <= 70) /* 44-70 */ 3845 grp = 1; 3846 else if (chan <= 124) /* 71-124 */ 3847 grp = 2; 3848 else /* 125-200 */ 3849 grp = 3; 3850 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3851 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 3852 3853 /* Get channel sub-band. */ 3854 for (i = 0; i < IWN_NBANDS; i++) 3855 if (sc->bands[i].lo != 0 && 3856 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3857 break; 3858 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3859 return EINVAL; 3860 chans = sc->bands[i].chans; 3861 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3862 "%s: chan %d sub-band=%d\n", __func__, chan, i); 3863 3864 for (c = 0; c < 2; c++) { 3865 uint8_t power, gain, temp; 3866 int maxchpwr, pwr, ridx, idx; 3867 3868 power = interpolate(chan, 3869 chans[0].num, chans[0].samples[c][1].power, 3870 chans[1].num, chans[1].samples[c][1].power, 1); 3871 gain = interpolate(chan, 3872 chans[0].num, chans[0].samples[c][1].gain, 3873 chans[1].num, chans[1].samples[c][1].gain, 1); 3874 temp = interpolate(chan, 3875 chans[0].num, chans[0].samples[c][1].temp, 3876 chans[1].num, chans[1].samples[c][1].temp, 1); 3877 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3878 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 3879 __func__, c, power, gain, temp); 3880 3881 /* Compute temperature compensation. */ 3882 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3883 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3884 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 3885 __func__, tdiff, sc->temp, temp); 3886 3887 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3888 /* Convert dBm to half-dBm. */ 3889 maxchpwr = sc->maxpwr[chan] * 2; 3890 if ((ridx / 8) & 1) 3891 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3892 3893 pwr = maxpwr; 3894 3895 /* Adjust TX power based on rate. */ 3896 if ((ridx % 8) == 5) 3897 pwr -= 15; /* OFDM48: -7.5dB */ 3898 else if ((ridx % 8) == 6) 3899 pwr -= 17; /* OFDM54: -8.5dB */ 3900 else if ((ridx % 8) == 7) 3901 pwr -= 20; /* OFDM60: -10dB */ 3902 else 3903 pwr -= 10; /* Others: -5dB */ 3904 3905 /* Do not exceed channel max TX power. */ 3906 if (pwr > maxchpwr) 3907 pwr = maxchpwr; 3908 3909 idx = gain - (pwr - power) - tdiff - vdiff; 3910 if ((ridx / 8) & 1) /* MIMO */ 3911 idx += (int32_t)le32toh(uc->atten[grp][c]); 3912 3913 if (cmd.band == 0) 3914 idx += 9; /* 5GHz */ 3915 if (ridx == IWN_RIDX_MAX) 3916 idx += 5; /* CCK */ 3917 3918 /* Make sure idx stays in a valid range. */ 3919 if (idx < 0) 3920 idx = 0; 3921 else if (idx > IWN4965_MAX_PWR_INDEX) 3922 idx = IWN4965_MAX_PWR_INDEX; 3923 3924 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3925 "%s: Tx chain %d, rate idx %d: power=%d\n", 3926 __func__, c, ridx, idx); 3927 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3928 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3929 } 3930 } 3931 3932 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3933 "%s: set tx power for chan %d\n", __func__, chan); 3934 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3935 3936 #undef interpolate 3937 #undef fdivround 3938 } 3939 3940 static int 3941 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3942 int async) 3943 { 3944 struct iwn5000_cmd_txpower cmd; 3945 3946 /* 3947 * TX power calibration is handled automatically by the firmware 3948 * for 5000 Series. 3949 */ 3950 memset(&cmd, 0, sizeof cmd); 3951 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3952 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3953 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3954 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 3955 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3956 } 3957 3958 /* 3959 * Retrieve the maximum RSSI (in dBm) among receivers. 3960 */ 3961 static int 3962 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3963 { 3964 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 3965 uint8_t mask, agc; 3966 int rssi; 3967 3968 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3969 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3970 3971 rssi = 0; 3972 #if 0 3973 if (mask & IWN_ANT_A) /* Ant A */ 3974 rssi = max(rssi, phy->rssi[0]); 3975 if (mask & IWN_ATH_B) /* Ant B */ 3976 rssi = max(rssi, phy->rssi[2]); 3977 if (mask & IWN_ANT_C) /* Ant C */ 3978 rssi = max(rssi, phy->rssi[4]); 3979 #else 3980 rssi = max(rssi, phy->rssi[0]); 3981 rssi = max(rssi, phy->rssi[2]); 3982 rssi = max(rssi, phy->rssi[4]); 3983 #endif 3984 3985 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d " 3986 "result %d\n", __func__, agc, mask, 3987 phy->rssi[0], phy->rssi[2], phy->rssi[4], 3988 rssi - agc - IWN_RSSI_TO_DBM); 3989 return rssi - agc - IWN_RSSI_TO_DBM; 3990 } 3991 3992 static int 3993 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3994 { 3995 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 3996 int rssi; 3997 uint8_t agc; 3998 3999 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4000 4001 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4002 le16toh(phy->rssi[1]) & 0xff); 4003 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4004 4005 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d " 4006 "result %d\n", __func__, agc, 4007 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4008 rssi - agc - IWN_RSSI_TO_DBM); 4009 return rssi - agc - IWN_RSSI_TO_DBM; 4010 } 4011 4012 /* 4013 * Retrieve the average noise (in dBm) among receivers. 4014 */ 4015 static int 4016 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4017 { 4018 int i, total, nbant, noise; 4019 4020 total = nbant = 0; 4021 for (i = 0; i < 3; i++) { 4022 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4023 continue; 4024 total += noise; 4025 nbant++; 4026 } 4027 /* There should be at least one antenna but check anyway. */ 4028 return (nbant == 0) ? -127 : (total / nbant) - 107; 4029 } 4030 4031 /* 4032 * Compute temperature (in degC) from last received statistics. 4033 */ 4034 static int 4035 iwn4965_get_temperature(struct iwn_softc *sc) 4036 { 4037 struct iwn_ucode_info *uc = &sc->ucode_info; 4038 int32_t r1, r2, r3, r4, temp; 4039 4040 r1 = le32toh(uc->temp[0].chan20MHz); 4041 r2 = le32toh(uc->temp[1].chan20MHz); 4042 r3 = le32toh(uc->temp[2].chan20MHz); 4043 r4 = le32toh(sc->rawtemp); 4044 4045 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 4046 return 0; 4047 4048 /* Sign-extend 23-bit R4 value to 32-bit. */ 4049 r4 = (r4 << 8) >> 8; 4050 /* Compute temperature in Kelvin. */ 4051 temp = (259 * (r4 - r2)) / (r3 - r1); 4052 temp = (temp * 97) / 100 + 8; 4053 4054 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4055 IWN_KTOC(temp)); 4056 return IWN_KTOC(temp); 4057 } 4058 4059 static int 4060 iwn5000_get_temperature(struct iwn_softc *sc) 4061 { 4062 int32_t temp; 4063 4064 /* 4065 * Temperature is not used by the driver for 5000 Series because 4066 * TX power calibration is handled by firmware. We export it to 4067 * users through the sensor framework though. 4068 */ 4069 temp = le32toh(sc->rawtemp); 4070 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4071 temp = (temp / -5) + sc->temp_off; 4072 temp = IWN_KTOC(temp); 4073 } 4074 return temp; 4075 } 4076 4077 /* 4078 * Initialize sensitivity calibration state machine. 4079 */ 4080 static int 4081 iwn_init_sensitivity(struct iwn_softc *sc) 4082 { 4083 const struct iwn_hal *hal = sc->sc_hal; 4084 struct iwn_calib_state *calib = &sc->calib; 4085 uint32_t flags; 4086 int error; 4087 4088 /* Reset calibration state machine. */ 4089 memset(calib, 0, sizeof (*calib)); 4090 calib->state = IWN_CALIB_STATE_INIT; 4091 calib->cck_state = IWN_CCK_STATE_HIFA; 4092 /* Set initial correlation values. */ 4093 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4094 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4095 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4096 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4097 calib->cck_x4 = 125; 4098 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4099 calib->energy_cck = sc->limits->energy_cck; 4100 4101 /* Write initial sensitivity. */ 4102 error = iwn_send_sensitivity(sc); 4103 if (error != 0) 4104 return error; 4105 4106 /* Write initial gains. */ 4107 error = hal->init_gains(sc); 4108 if (error != 0) 4109 return error; 4110 4111 /* Request statistics at each beacon interval. */ 4112 flags = 0; 4113 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__); 4114 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4115 } 4116 4117 /* 4118 * Collect noise and RSSI statistics for the first 20 beacons received 4119 * after association and use them to determine connected antennas and 4120 * to set differential gains. 4121 */ 4122 static void 4123 iwn_collect_noise(struct iwn_softc *sc, 4124 const struct iwn_rx_general_stats *stats) 4125 { 4126 const struct iwn_hal *hal = sc->sc_hal; 4127 struct iwn_calib_state *calib = &sc->calib; 4128 uint32_t val; 4129 int i; 4130 4131 /* Accumulate RSSI and noise for all 3 antennas. */ 4132 for (i = 0; i < 3; i++) { 4133 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4134 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4135 } 4136 /* NB: We update differential gains only once after 20 beacons. */ 4137 if (++calib->nbeacons < 20) 4138 return; 4139 4140 /* Determine highest average RSSI. */ 4141 val = MAX(calib->rssi[0], calib->rssi[1]); 4142 val = MAX(calib->rssi[2], val); 4143 4144 /* Determine which antennas are connected. */ 4145 sc->chainmask = sc->rxchainmask; 4146 for (i = 0; i < 3; i++) 4147 if (val - calib->rssi[i] > 15 * 20) 4148 sc->chainmask &= ~(1 << i); 4149 4150 /* If none of the TX antennas are connected, keep at least one. */ 4151 if ((sc->chainmask & sc->txchainmask) == 0) 4152 sc->chainmask |= IWN_LSB(sc->txchainmask); 4153 4154 (void)hal->set_gains(sc); 4155 calib->state = IWN_CALIB_STATE_RUN; 4156 4157 #ifdef notyet 4158 /* XXX Disable RX chains with no antennas connected. */ 4159 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4160 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4161 #endif 4162 4163 #if 0 4164 /* XXX: not yet */ 4165 /* Enable power-saving mode if requested by user. */ 4166 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4167 (void)iwn_set_pslevel(sc, 0, 3, 1); 4168 #endif 4169 } 4170 4171 static int 4172 iwn4965_init_gains(struct iwn_softc *sc) 4173 { 4174 struct iwn_phy_calib_gain cmd; 4175 4176 memset(&cmd, 0, sizeof cmd); 4177 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4178 /* Differential gains initially set to 0 for all 3 antennas. */ 4179 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4180 "%s: setting initial differential gains\n", __func__); 4181 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4182 } 4183 4184 static int 4185 iwn5000_init_gains(struct iwn_softc *sc) 4186 { 4187 struct iwn_phy_calib cmd; 4188 4189 memset(&cmd, 0, sizeof cmd); 4190 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 4191 cmd.ngroups = 1; 4192 cmd.isvalid = 1; 4193 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4194 "%s: setting initial differential gains\n", __func__); 4195 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4196 } 4197 4198 static int 4199 iwn4965_set_gains(struct iwn_softc *sc) 4200 { 4201 struct iwn_calib_state *calib = &sc->calib; 4202 struct iwn_phy_calib_gain cmd; 4203 int i, delta, noise; 4204 4205 /* Get minimal noise among connected antennas. */ 4206 noise = INT_MAX; /* NB: There's at least one antenna. */ 4207 for (i = 0; i < 3; i++) 4208 if (sc->chainmask & (1 << i)) 4209 noise = MIN(calib->noise[i], noise); 4210 4211 memset(&cmd, 0, sizeof cmd); 4212 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4213 /* Set differential gains for connected antennas. */ 4214 for (i = 0; i < 3; i++) { 4215 if (sc->chainmask & (1 << i)) { 4216 /* Compute attenuation (in unit of 1.5dB). */ 4217 delta = (noise - (int32_t)calib->noise[i]) / 30; 4218 /* NB: delta <= 0 */ 4219 /* Limit to [-4.5dB,0]. */ 4220 cmd.gain[i] = MIN(abs(delta), 3); 4221 if (delta < 0) 4222 cmd.gain[i] |= 1 << 2; /* sign bit */ 4223 } 4224 } 4225 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4226 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4227 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4228 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4229 } 4230 4231 static int 4232 iwn5000_set_gains(struct iwn_softc *sc) 4233 { 4234 struct iwn_calib_state *calib = &sc->calib; 4235 struct iwn_phy_calib_gain cmd; 4236 int i, ant, delta, div; 4237 4238 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4239 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4240 4241 memset(&cmd, 0, sizeof cmd); 4242 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 4243 cmd.ngroups = 1; 4244 cmd.isvalid = 1; 4245 /* Get first available RX antenna as referential. */ 4246 ant = IWN_LSB(sc->rxchainmask); 4247 /* Set differential gains for other antennas. */ 4248 for (i = ant + 1; i < 3; i++) { 4249 if (sc->chainmask & (1 << i)) { 4250 /* The delta is relative to antenna "ant". */ 4251 delta = ((int32_t)calib->noise[ant] - 4252 (int32_t)calib->noise[i]) / div; 4253 /* Limit to [-4.5dB,+4.5dB]. */ 4254 cmd.gain[i - 1] = MIN(abs(delta), 3); 4255 if (delta < 0) 4256 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4257 } 4258 } 4259 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4260 "setting differential gains Ant B/C: %x/%x (%x)\n", 4261 cmd.gain[0], cmd.gain[1], sc->chainmask); 4262 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4263 } 4264 4265 /* 4266 * Tune RF RX sensitivity based on the number of false alarms detected 4267 * during the last beacon period. 4268 */ 4269 static void 4270 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4271 { 4272 #define inc(val, inc, max) \ 4273 if ((val) < (max)) { \ 4274 if ((val) < (max) - (inc)) \ 4275 (val) += (inc); \ 4276 else \ 4277 (val) = (max); \ 4278 needs_update = 1; \ 4279 } 4280 #define dec(val, dec, min) \ 4281 if ((val) > (min)) { \ 4282 if ((val) > (min) + (dec)) \ 4283 (val) -= (dec); \ 4284 else \ 4285 (val) = (min); \ 4286 needs_update = 1; \ 4287 } 4288 4289 const struct iwn_sensitivity_limits *limits = sc->limits; 4290 struct iwn_calib_state *calib = &sc->calib; 4291 uint32_t val, rxena, fa; 4292 uint32_t energy[3], energy_min; 4293 uint8_t noise[3], noise_ref; 4294 int i, needs_update = 0; 4295 4296 /* Check that we've been enabled long enough. */ 4297 rxena = le32toh(stats->general.load); 4298 if (rxena == 0) 4299 return; 4300 4301 /* Compute number of false alarms since last call for OFDM. */ 4302 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4303 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4304 fa *= 200 * 1024; /* 200TU */ 4305 4306 /* Save counters values for next call. */ 4307 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4308 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4309 4310 if (fa > 50 * rxena) { 4311 /* High false alarm count, decrease sensitivity. */ 4312 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4313 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4314 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4315 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4316 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4317 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4318 4319 } else if (fa < 5 * rxena) { 4320 /* Low false alarm count, increase sensitivity. */ 4321 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4322 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4323 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4324 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4325 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4326 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4327 } 4328 4329 /* Compute maximum noise among 3 receivers. */ 4330 for (i = 0; i < 3; i++) 4331 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4332 val = MAX(noise[0], noise[1]); 4333 val = MAX(noise[2], val); 4334 /* Insert it into our samples table. */ 4335 calib->noise_samples[calib->cur_noise_sample] = val; 4336 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4337 4338 /* Compute maximum noise among last 20 samples. */ 4339 noise_ref = calib->noise_samples[0]; 4340 for (i = 1; i < 20; i++) 4341 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4342 4343 /* Compute maximum energy among 3 receivers. */ 4344 for (i = 0; i < 3; i++) 4345 energy[i] = le32toh(stats->general.energy[i]); 4346 val = MIN(energy[0], energy[1]); 4347 val = MIN(energy[2], val); 4348 /* Insert it into our samples table. */ 4349 calib->energy_samples[calib->cur_energy_sample] = val; 4350 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4351 4352 /* Compute minimum energy among last 10 samples. */ 4353 energy_min = calib->energy_samples[0]; 4354 for (i = 1; i < 10; i++) 4355 energy_min = MAX(energy_min, calib->energy_samples[i]); 4356 energy_min += 6; 4357 4358 /* Compute number of false alarms since last call for CCK. */ 4359 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4360 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4361 fa *= 200 * 1024; /* 200TU */ 4362 4363 /* Save counters values for next call. */ 4364 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4365 calib->fa_cck = le32toh(stats->cck.fa); 4366 4367 if (fa > 50 * rxena) { 4368 /* High false alarm count, decrease sensitivity. */ 4369 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4370 "%s: CCK high false alarm count: %u\n", __func__, fa); 4371 calib->cck_state = IWN_CCK_STATE_HIFA; 4372 calib->low_fa = 0; 4373 4374 if (calib->cck_x4 > 160) { 4375 calib->noise_ref = noise_ref; 4376 if (calib->energy_cck > 2) 4377 dec(calib->energy_cck, 2, energy_min); 4378 } 4379 if (calib->cck_x4 < 160) { 4380 calib->cck_x4 = 161; 4381 needs_update = 1; 4382 } else 4383 inc(calib->cck_x4, 3, limits->max_cck_x4); 4384 4385 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4386 4387 } else if (fa < 5 * rxena) { 4388 /* Low false alarm count, increase sensitivity. */ 4389 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4390 "%s: CCK low false alarm count: %u\n", __func__, fa); 4391 calib->cck_state = IWN_CCK_STATE_LOFA; 4392 calib->low_fa++; 4393 4394 if (calib->cck_state != IWN_CCK_STATE_INIT && 4395 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4396 calib->low_fa > 100)) { 4397 inc(calib->energy_cck, 2, limits->min_energy_cck); 4398 dec(calib->cck_x4, 3, limits->min_cck_x4); 4399 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4400 } 4401 } else { 4402 /* Not worth to increase or decrease sensitivity. */ 4403 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4404 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4405 calib->low_fa = 0; 4406 calib->noise_ref = noise_ref; 4407 4408 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4409 /* Previous interval had many false alarms. */ 4410 dec(calib->energy_cck, 8, energy_min); 4411 } 4412 calib->cck_state = IWN_CCK_STATE_INIT; 4413 } 4414 4415 if (needs_update) 4416 (void)iwn_send_sensitivity(sc); 4417 #undef dec 4418 #undef inc 4419 } 4420 4421 static int 4422 iwn_send_sensitivity(struct iwn_softc *sc) 4423 { 4424 struct iwn_calib_state *calib = &sc->calib; 4425 struct iwn_sensitivity_cmd cmd; 4426 4427 memset(&cmd, 0, sizeof cmd); 4428 cmd.which = IWN_SENSITIVITY_WORKTBL; 4429 /* OFDM modulation. */ 4430 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4431 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4432 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4433 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4434 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4435 cmd.energy_ofdm_th = htole16(62); 4436 /* CCK modulation. */ 4437 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4438 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4439 cmd.energy_cck = htole16(calib->energy_cck); 4440 /* Barker modulation: use default values. */ 4441 cmd.corr_barker = htole16(190); 4442 cmd.corr_barker_mrc = htole16(390); 4443 4444 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4445 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4446 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4447 calib->ofdm_mrc_x4, calib->cck_x4, 4448 calib->cck_mrc_x4, calib->energy_cck); 4449 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4450 } 4451 4452 /* 4453 * Set STA mode power saving level (between 0 and 5). 4454 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4455 */ 4456 static int 4457 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4458 { 4459 const struct iwn_pmgt *pmgt; 4460 struct iwn_pmgt_cmd cmd; 4461 uint32_t max, skip_dtim; 4462 uint32_t tmp; 4463 int i; 4464 4465 /* Select which PS parameters to use. */ 4466 if (dtim <= 2) 4467 pmgt = &iwn_pmgt[0][level]; 4468 else if (dtim <= 10) 4469 pmgt = &iwn_pmgt[1][level]; 4470 else 4471 pmgt = &iwn_pmgt[2][level]; 4472 4473 memset(&cmd, 0, sizeof cmd); 4474 if (level != 0) /* not CAM */ 4475 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4476 if (level == 5) 4477 cmd.flags |= htole16(IWN_PS_FAST_PD); 4478 /* Retrieve PCIe Active State Power Management (ASPM). */ 4479 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4480 if (!(tmp & 0x1)) /* L0s Entry disabled. */ 4481 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4482 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4483 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4484 4485 if (dtim == 0) { 4486 dtim = 1; 4487 skip_dtim = 0; 4488 } else 4489 skip_dtim = pmgt->skip_dtim; 4490 if (skip_dtim != 0) { 4491 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4492 max = pmgt->intval[4]; 4493 if (max == (uint32_t)-1) 4494 max = dtim * (skip_dtim + 1); 4495 else if (max > dtim) 4496 max = (max / dtim) * dtim; 4497 } else 4498 max = dtim; 4499 for (i = 0; i < 5; i++) 4500 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4501 4502 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4503 level); 4504 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4505 } 4506 4507 static int 4508 iwn_config(struct iwn_softc *sc) 4509 { 4510 const struct iwn_hal *hal = sc->sc_hal; 4511 struct ifnet *ifp = sc->sc_ifp; 4512 struct ieee80211com *ic = ifp->if_l2com; 4513 struct iwn_bluetooth bluetooth; 4514 uint32_t txmask; 4515 int error; 4516 uint16_t rxchain; 4517 4518 /* Configure valid TX chains for 5000 Series. */ 4519 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4520 txmask = htole32(sc->txchainmask); 4521 DPRINTF(sc, IWN_DEBUG_RESET, 4522 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4523 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4524 sizeof txmask, 0); 4525 if (error != 0) { 4526 device_printf(sc->sc_dev, 4527 "%s: could not configure valid TX chains, " 4528 "error %d\n", __func__, error); 4529 return error; 4530 } 4531 } 4532 4533 /* Configure bluetooth coexistence. */ 4534 memset(&bluetooth, 0, sizeof bluetooth); 4535 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4536 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4537 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4538 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n", 4539 __func__); 4540 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4541 if (error != 0) { 4542 device_printf(sc->sc_dev, 4543 "%s: could not configure bluetooth coexistence, error %d\n", 4544 __func__, error); 4545 return error; 4546 } 4547 4548 /* Set mode, channel, RX filter and enable RX. */ 4549 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4550 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4551 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4552 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4553 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4554 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4555 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4556 switch (ic->ic_opmode) { 4557 case IEEE80211_M_STA: 4558 sc->rxon.mode = IWN_MODE_STA; 4559 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4560 break; 4561 case IEEE80211_M_MONITOR: 4562 sc->rxon.mode = IWN_MODE_MONITOR; 4563 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4564 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4565 break; 4566 default: 4567 /* Should not get there. */ 4568 break; 4569 } 4570 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4571 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4572 sc->rxon.ht_single_mask = 0xff; 4573 sc->rxon.ht_dual_mask = 0xff; 4574 sc->rxon.ht_triple_mask = 0xff; 4575 rxchain = 4576 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4577 IWN_RXCHAIN_MIMO_COUNT(2) | 4578 IWN_RXCHAIN_IDLE_COUNT(2); 4579 sc->rxon.rxchain = htole16(rxchain); 4580 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4581 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4582 if (error != 0) { 4583 device_printf(sc->sc_dev, 4584 "%s: RXON command failed\n", __func__); 4585 return error; 4586 } 4587 4588 error = iwn_add_broadcast_node(sc, 0); 4589 if (error != 0) { 4590 device_printf(sc->sc_dev, 4591 "%s: could not add broadcast node\n", __func__); 4592 return error; 4593 } 4594 4595 /* Configuration has changed, set TX power accordingly. */ 4596 error = hal->set_txpower(sc, ic->ic_curchan, 0); 4597 if (error != 0) { 4598 device_printf(sc->sc_dev, 4599 "%s: could not set TX power\n", __func__); 4600 return error; 4601 } 4602 4603 error = iwn_set_critical_temp(sc); 4604 if (error != 0) { 4605 device_printf(sc->sc_dev, 4606 "%s: ccould not set critical temperature\n", __func__); 4607 return error; 4608 } 4609 4610 /* Set power saving level to CAM during initialization. */ 4611 error = iwn_set_pslevel(sc, 0, 0, 0); 4612 if (error != 0) { 4613 device_printf(sc->sc_dev, 4614 "%s: could not set power saving level\n", __func__); 4615 return error; 4616 } 4617 return 0; 4618 } 4619 4620 static int 4621 iwn_scan(struct iwn_softc *sc) 4622 { 4623 struct ifnet *ifp = sc->sc_ifp; 4624 struct ieee80211com *ic = ifp->if_l2com; 4625 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4626 struct iwn_scan_hdr *hdr; 4627 struct iwn_cmd_data *tx; 4628 struct iwn_scan_essid *essid; 4629 struct iwn_scan_chan *chan; 4630 struct ieee80211_frame *wh; 4631 struct ieee80211_rateset *rs; 4632 struct ieee80211_channel *c; 4633 int buflen, error, nrates; 4634 uint16_t rxchain; 4635 uint8_t *buf, *frm, txant; 4636 4637 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO); 4638 hdr = (struct iwn_scan_hdr *)buf; 4639 4640 /* 4641 * Move to the next channel if no frames are received within 10ms 4642 * after sending the probe request. 4643 */ 4644 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4645 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4646 4647 /* Select antennas for scanning. */ 4648 rxchain = 4649 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4650 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4651 IWN_RXCHAIN_DRIVER_FORCE; 4652 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4653 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4654 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4655 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4656 } else /* Use all available RX antennas. */ 4657 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4658 hdr->rxchain = htole16(rxchain); 4659 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4660 4661 tx = (struct iwn_cmd_data *)(hdr + 1); 4662 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4663 tx->id = sc->sc_hal->broadcast_id; 4664 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4665 4666 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4667 /* Send probe requests at 6Mbps. */ 4668 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4669 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4670 } else { 4671 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4672 /* Send probe requests at 1Mbps. */ 4673 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4674 tx->rflags = IWN_RFLAG_CCK; 4675 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4676 } 4677 /* Use the first valid TX antenna. */ 4678 txant = IWN_LSB(sc->txchainmask); 4679 tx->rflags |= IWN_RFLAG_ANT(txant); 4680 4681 essid = (struct iwn_scan_essid *)(tx + 1); 4682 if (ss->ss_ssid[0].len != 0) { 4683 essid[0].id = IEEE80211_ELEMID_SSID; 4684 essid[0].len = ss->ss_ssid[0].len; 4685 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4686 } 4687 4688 /* 4689 * Build a probe request frame. Most of the following code is a 4690 * copy & paste of what is done in net80211. 4691 */ 4692 wh = (struct ieee80211_frame *)(essid + 20); 4693 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4694 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4695 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4696 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4697 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4698 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4699 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4700 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4701 4702 frm = (uint8_t *)(wh + 1); 4703 4704 /* Add SSID IE. */ 4705 *frm++ = IEEE80211_ELEMID_SSID; 4706 *frm++ = ss->ss_ssid[0].len; 4707 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4708 frm += ss->ss_ssid[0].len; 4709 4710 /* Add supported rates IE. */ 4711 *frm++ = IEEE80211_ELEMID_RATES; 4712 nrates = rs->rs_nrates; 4713 if (nrates > IEEE80211_RATE_SIZE) 4714 nrates = IEEE80211_RATE_SIZE; 4715 *frm++ = nrates; 4716 memcpy(frm, rs->rs_rates, nrates); 4717 frm += nrates; 4718 4719 /* Add supported xrates IE. */ 4720 if (rs->rs_nrates > IEEE80211_RATE_SIZE) { 4721 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 4722 *frm++ = IEEE80211_ELEMID_XRATES; 4723 *frm++ = (uint8_t)nrates; 4724 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 4725 frm += nrates; 4726 } 4727 4728 /* Set length of probe request. */ 4729 tx->len = htole16(frm - (uint8_t *)wh); 4730 4731 c = ic->ic_curchan; 4732 chan = (struct iwn_scan_chan *)frm; 4733 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4734 chan->flags = 0; 4735 if (ss->ss_nssid > 0) 4736 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4737 chan->dsp_gain = 0x6e; 4738 if (IEEE80211_IS_CHAN_5GHZ(c) && 4739 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4740 chan->rf_gain = 0x3b; 4741 chan->active = htole16(24); 4742 chan->passive = htole16(110); 4743 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4744 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4745 chan->rf_gain = 0x3b; 4746 chan->active = htole16(24); 4747 if (sc->rxon.associd) 4748 chan->passive = htole16(78); 4749 else 4750 chan->passive = htole16(110); 4751 hdr->crc_threshold = 0xffff; 4752 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4753 chan->rf_gain = 0x28; 4754 chan->active = htole16(36); 4755 chan->passive = htole16(120); 4756 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4757 } else { 4758 chan->rf_gain = 0x28; 4759 chan->active = htole16(36); 4760 if (sc->rxon.associd) 4761 chan->passive = htole16(88); 4762 else 4763 chan->passive = htole16(120); 4764 hdr->crc_threshold = 0xffff; 4765 } 4766 4767 DPRINTF(sc, IWN_DEBUG_STATE, 4768 "%s: chan %u flags 0x%x rf_gain 0x%x " 4769 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 4770 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 4771 chan->active, chan->passive); 4772 4773 hdr->nchan++; 4774 chan++; 4775 buflen = (uint8_t *)chan - buf; 4776 hdr->len = htole16(buflen); 4777 4778 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 4779 hdr->nchan); 4780 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4781 kfree(buf, M_DEVBUF); 4782 return error; 4783 } 4784 4785 static int 4786 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 4787 { 4788 const struct iwn_hal *hal = sc->sc_hal; 4789 struct ifnet *ifp = sc->sc_ifp; 4790 struct ieee80211com *ic = ifp->if_l2com; 4791 struct ieee80211_node *ni = vap->iv_bss; 4792 char ethstr[3][ETHER_ADDRSTRLEN + 1]; 4793 int error; 4794 4795 sc->calib.state = IWN_CALIB_STATE_INIT; 4796 4797 /* Update adapter configuration. */ 4798 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4799 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4800 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4801 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4802 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4803 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4804 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4805 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4806 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4807 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4808 sc->rxon.cck_mask = 0; 4809 sc->rxon.ofdm_mask = 0x15; 4810 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4811 sc->rxon.cck_mask = 0x03; 4812 sc->rxon.ofdm_mask = 0; 4813 } else { 4814 /* XXX assume 802.11b/g */ 4815 sc->rxon.cck_mask = 0x0f; 4816 sc->rxon.ofdm_mask = 0x15; 4817 } 4818 DPRINTF(sc, IWN_DEBUG_STATE, 4819 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4820 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4821 "myaddr %s wlap %s bssid %s associd %d filter 0x%x\n", 4822 __func__, 4823 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4824 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4825 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4826 le16toh(sc->rxon.rxchain), 4827 kether_ntoa(sc->rxon.myaddr, ethstr[0]), 4828 kether_ntoa(sc->rxon.wlap, ethstr[1]), 4829 kether_ntoa(sc->rxon.bssid, ethstr[2]), 4830 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4831 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4832 if (error != 0) { 4833 device_printf(sc->sc_dev, 4834 "%s: RXON command failed, error %d\n", __func__, error); 4835 return error; 4836 } 4837 4838 /* Configuration has changed, set TX power accordingly. */ 4839 error = hal->set_txpower(sc, ni->ni_chan, 1); 4840 if (error != 0) { 4841 device_printf(sc->sc_dev, 4842 "%s: could not set Tx power, error %d\n", __func__, error); 4843 return error; 4844 } 4845 /* 4846 * Reconfiguring RXON clears the firmware nodes table so we must 4847 * add the broadcast node again. 4848 */ 4849 error = iwn_add_broadcast_node(sc, 1); 4850 if (error != 0) { 4851 device_printf(sc->sc_dev, 4852 "%s: could not add broadcast node, error %d\n", 4853 __func__, error); 4854 return error; 4855 } 4856 return 0; 4857 } 4858 4859 /* 4860 * Configure the adapter for associated state. 4861 */ 4862 static int 4863 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 4864 { 4865 #define MS(v,x) (((v) & x) >> x##_S) 4866 const struct iwn_hal *hal = sc->sc_hal; 4867 struct ifnet *ifp = sc->sc_ifp; 4868 struct ieee80211com *ic = ifp->if_l2com; 4869 struct ieee80211_node *ni = vap->iv_bss; 4870 struct iwn_node_info node; 4871 char ethstr[3][ETHER_ADDRSTRLEN + 1]; 4872 int error; 4873 4874 sc->calib.state = IWN_CALIB_STATE_INIT; 4875 4876 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4877 /* Link LED blinks while monitoring. */ 4878 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4879 return 0; 4880 } 4881 error = iwn_set_timing(sc, ni); 4882 if (error != 0) { 4883 device_printf(sc->sc_dev, 4884 "%s: could not set timing, error %d\n", __func__, error); 4885 return error; 4886 } 4887 4888 /* Update adapter configuration. */ 4889 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4890 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4891 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4892 /* Short preamble and slot time are negotiated when associating. */ 4893 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4894 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4895 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4896 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4897 else 4898 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4899 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4900 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4901 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4902 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4903 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4904 sc->rxon.cck_mask = 0; 4905 sc->rxon.ofdm_mask = 0x15; 4906 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4907 sc->rxon.cck_mask = 0x03; 4908 sc->rxon.ofdm_mask = 0; 4909 } else { 4910 /* XXX assume 802.11b/g */ 4911 sc->rxon.cck_mask = 0x0f; 4912 sc->rxon.ofdm_mask = 0x15; 4913 } 4914 #if 0 /* HT */ 4915 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 4916 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 4917 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 4918 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 4919 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 4920 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 4921 else 4922 sc->rxon.flags |= htole32(IWN_RXON_HT20); 4923 sc->rxon.rxchain = htole16( 4924 IWN_RXCHAIN_VALID(3) 4925 | IWN_RXCHAIN_MIMO_COUNT(3) 4926 | IWN_RXCHAIN_IDLE_COUNT(1) 4927 | IWN_RXCHAIN_MIMO_FORCE); 4928 4929 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 4930 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 4931 } else 4932 maxrxampdu = ampdudensity = 0; 4933 #endif 4934 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4935 4936 DPRINTF(sc, IWN_DEBUG_STATE, 4937 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4938 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4939 "myaddr %s wlap %s bssid %s associd %d filter 0x%x\n", 4940 __func__, 4941 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4942 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4943 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4944 le16toh(sc->rxon.rxchain), 4945 kether_ntoa(sc->rxon.myaddr, ethstr[0]), 4946 kether_ntoa(sc->rxon.wlap, ethstr[1]), 4947 kether_ntoa(sc->rxon.bssid, ethstr[2]), 4948 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4949 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4950 if (error != 0) { 4951 device_printf(sc->sc_dev, 4952 "%s: could not update configuration, error %d\n", 4953 __func__, error); 4954 return error; 4955 } 4956 4957 /* Configuration has changed, set TX power accordingly. */ 4958 error = hal->set_txpower(sc, ni->ni_chan, 1); 4959 if (error != 0) { 4960 device_printf(sc->sc_dev, 4961 "%s: could not set Tx power, error %d\n", __func__, error); 4962 return error; 4963 } 4964 4965 /* Add BSS node. */ 4966 memset(&node, 0, sizeof node); 4967 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4968 node.id = IWN_ID_BSS; 4969 #ifdef notyet 4970 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4971 IWN_AMDPU_DENSITY(5)); /* 2us */ 4972 #endif 4973 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n", 4974 __func__, node.id, le32toh(node.htflags)); 4975 error = hal->add_node(sc, &node, 1); 4976 if (error != 0) { 4977 device_printf(sc->sc_dev, "could not add BSS node\n"); 4978 return error; 4979 } 4980 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n", 4981 node.id); 4982 error = iwn_set_link_quality(sc, node.id, 1); 4983 if (error != 0) { 4984 device_printf(sc->sc_dev, 4985 "%s: could not setup MRR for node %d, error %d\n", 4986 __func__, node.id, error); 4987 return error; 4988 } 4989 4990 error = iwn_init_sensitivity(sc); 4991 if (error != 0) { 4992 device_printf(sc->sc_dev, 4993 "%s: could not set sensitivity, error %d\n", 4994 __func__, error); 4995 return error; 4996 } 4997 4998 /* Start periodic calibration timer. */ 4999 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5000 iwn_calib_reset(sc); 5001 5002 /* Link LED always on while associated. */ 5003 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5004 5005 return 0; 5006 #undef MS 5007 } 5008 5009 #if 0 /* HT */ 5010 /* 5011 * This function is called by upper layer when an ADDBA request is received 5012 * from another STA and before the ADDBA response is sent. 5013 */ 5014 static int 5015 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5016 uint8_t tid) 5017 { 5018 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5019 struct iwn_softc *sc = ic->ic_softc; 5020 struct iwn_node *wn = (void *)ni; 5021 struct iwn_node_info node; 5022 5023 memset(&node, 0, sizeof node); 5024 node.id = wn->id; 5025 node.control = IWN_NODE_UPDATE; 5026 node.flags = IWN_FLAG_SET_ADDBA; 5027 node.addba_tid = tid; 5028 node.addba_ssn = htole16(ba->ba_winstart); 5029 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5030 wn->id, tid, ba->ba_winstart)); 5031 return sc->sc_hal->add_node(sc, &node, 1); 5032 } 5033 5034 /* 5035 * This function is called by upper layer on teardown of an HT-immediate 5036 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 5037 */ 5038 static void 5039 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5040 uint8_t tid) 5041 { 5042 struct iwn_softc *sc = ic->ic_softc; 5043 struct iwn_node *wn = (void *)ni; 5044 struct iwn_node_info node; 5045 5046 memset(&node, 0, sizeof node); 5047 node.id = wn->id; 5048 node.control = IWN_NODE_UPDATE; 5049 node.flags = IWN_FLAG_SET_DELBA; 5050 node.delba_tid = tid; 5051 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5052 (void)sc->sc_hal->add_node(sc, &node, 1); 5053 } 5054 5055 /* 5056 * This function is called by upper layer when an ADDBA response is received 5057 * from another STA. 5058 */ 5059 static int 5060 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5061 uint8_t tid) 5062 { 5063 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5064 struct iwn_softc *sc = ic->ic_softc; 5065 const struct iwn_hal *hal = sc->sc_hal; 5066 struct iwn_node *wn = (void *)ni; 5067 struct iwn_node_info node; 5068 int error; 5069 5070 /* Enable TX for the specified RA/TID. */ 5071 wn->disable_tid &= ~(1 << tid); 5072 memset(&node, 0, sizeof node); 5073 node.id = wn->id; 5074 node.control = IWN_NODE_UPDATE; 5075 node.flags = IWN_FLAG_SET_DISABLE_TID; 5076 node.disable_tid = htole16(wn->disable_tid); 5077 error = hal->add_node(sc, &node, 1); 5078 if (error != 0) 5079 return error; 5080 5081 if ((error = iwn_nic_lock(sc)) != 0) 5082 return error; 5083 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5084 iwn_nic_unlock(sc); 5085 return 0; 5086 } 5087 5088 static void 5089 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5090 uint8_t tid) 5091 { 5092 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5093 struct iwn_softc *sc = ic->ic_softc; 5094 int error; 5095 5096 error = iwn_nic_lock(sc); 5097 if (error != 0) 5098 return; 5099 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5100 iwn_nic_unlock(sc); 5101 } 5102 5103 static void 5104 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5105 uint8_t tid, uint16_t ssn) 5106 { 5107 struct iwn_node *wn = (void *)ni; 5108 int qid = 7 + tid; 5109 5110 /* Stop TX scheduler while we're changing its configuration. */ 5111 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5112 IWN4965_TXQ_STATUS_CHGACT); 5113 5114 /* Assign RA/TID translation to the queue. */ 5115 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5116 wn->id << 4 | tid); 5117 5118 /* Enable chain-building mode for the queue. */ 5119 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5120 5121 /* Set starting sequence number from the ADDBA request. */ 5122 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5123 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5124 5125 /* Set scheduler window size. */ 5126 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5127 IWN_SCHED_WINSZ); 5128 /* Set scheduler frame limit. */ 5129 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5130 IWN_SCHED_LIMIT << 16); 5131 5132 /* Enable interrupts for the queue. */ 5133 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5134 5135 /* Mark the queue as active. */ 5136 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5137 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5138 iwn_tid2fifo[tid] << 1); 5139 } 5140 5141 static void 5142 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5143 { 5144 int qid = 7 + tid; 5145 5146 /* Stop TX scheduler while we're changing its configuration. */ 5147 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5148 IWN4965_TXQ_STATUS_CHGACT); 5149 5150 /* Set starting sequence number from the ADDBA request. */ 5151 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5152 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5153 5154 /* Disable interrupts for the queue. */ 5155 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5156 5157 /* Mark the queue as inactive. */ 5158 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5159 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5160 } 5161 5162 static void 5163 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5164 uint8_t tid, uint16_t ssn) 5165 { 5166 struct iwn_node *wn = (void *)ni; 5167 int qid = 10 + tid; 5168 5169 /* Stop TX scheduler while we're changing its configuration. */ 5170 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5171 IWN5000_TXQ_STATUS_CHGACT); 5172 5173 /* Assign RA/TID translation to the queue. */ 5174 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5175 wn->id << 4 | tid); 5176 5177 /* Enable chain-building mode for the queue. */ 5178 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5179 5180 /* Enable aggregation for the queue. */ 5181 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5182 5183 /* Set starting sequence number from the ADDBA request. */ 5184 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5185 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5186 5187 /* Set scheduler window size and frame limit. */ 5188 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5189 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5190 5191 /* Enable interrupts for the queue. */ 5192 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5193 5194 /* Mark the queue as active. */ 5195 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5196 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5197 } 5198 5199 static void 5200 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5201 { 5202 int qid = 10 + tid; 5203 5204 /* Stop TX scheduler while we're changing its configuration. */ 5205 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5206 IWN5000_TXQ_STATUS_CHGACT); 5207 5208 /* Disable aggregation for the queue. */ 5209 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5210 5211 /* Set starting sequence number from the ADDBA request. */ 5212 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5213 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5214 5215 /* Disable interrupts for the queue. */ 5216 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5217 5218 /* Mark the queue as inactive. */ 5219 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5220 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5221 } 5222 #endif 5223 5224 /* 5225 * Query calibration tables from the initialization firmware. We do this 5226 * only once at first boot. Called from a process context. 5227 */ 5228 static int 5229 iwn5000_query_calibration(struct iwn_softc *sc) 5230 { 5231 struct iwn5000_calib_config cmd; 5232 int error; 5233 5234 memset(&cmd, 0, sizeof cmd); 5235 cmd.ucode.once.enable = 0xffffffff; 5236 cmd.ucode.once.start = 0xffffffff; 5237 cmd.ucode.once.send = 0xffffffff; 5238 cmd.ucode.flags = 0xffffffff; 5239 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5240 __func__); 5241 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5242 if (error != 0) 5243 return error; 5244 5245 /* Wait at most two seconds for calibration to complete. */ 5246 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5247 error = zsleep(sc, &wlan_global_serializer, 5248 0, "iwninit", 2 * hz); 5249 } 5250 return error; 5251 } 5252 5253 /* 5254 * Send calibration results to the runtime firmware. These results were 5255 * obtained on first boot from the initialization firmware. 5256 */ 5257 static int 5258 iwn5000_send_calibration(struct iwn_softc *sc) 5259 { 5260 int idx, error; 5261 5262 for (idx = 0; idx < 5; idx++) { 5263 if (sc->calibcmd[idx].buf == NULL) 5264 continue; /* No results available. */ 5265 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5266 "send calibration result idx=%d len=%d\n", 5267 idx, sc->calibcmd[idx].len); 5268 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5269 sc->calibcmd[idx].len, 0); 5270 if (error != 0) { 5271 device_printf(sc->sc_dev, 5272 "%s: could not send calibration result, error %d\n", 5273 __func__, error); 5274 return error; 5275 } 5276 } 5277 return 0; 5278 } 5279 5280 static int 5281 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5282 { 5283 struct iwn5000_wimax_coex wimax; 5284 5285 #ifdef notyet 5286 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5287 /* Enable WiMAX coexistence for combo adapters. */ 5288 wimax.flags = 5289 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5290 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5291 IWN_WIMAX_COEX_STA_TABLE_VALID | 5292 IWN_WIMAX_COEX_ENABLE; 5293 memcpy(wimax.events, iwn6050_wimax_events, 5294 sizeof iwn6050_wimax_events); 5295 } else 5296 #endif 5297 { 5298 /* Disable WiMAX coexistence. */ 5299 wimax.flags = 0; 5300 memset(wimax.events, 0, sizeof wimax.events); 5301 } 5302 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5303 __func__); 5304 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5305 } 5306 5307 /* 5308 * This function is called after the runtime firmware notifies us of its 5309 * readiness (called in a process context.) 5310 */ 5311 static int 5312 iwn4965_post_alive(struct iwn_softc *sc) 5313 { 5314 int error, qid; 5315 5316 if ((error = iwn_nic_lock(sc)) != 0) 5317 return error; 5318 5319 /* Clear TX scheduler state in SRAM. */ 5320 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5321 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5322 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5323 5324 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5325 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5326 5327 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5328 5329 /* Disable chain mode for all our 16 queues. */ 5330 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5331 5332 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5333 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5334 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5335 5336 /* Set scheduler window size. */ 5337 iwn_mem_write(sc, sc->sched_base + 5338 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5339 /* Set scheduler frame limit. */ 5340 iwn_mem_write(sc, sc->sched_base + 5341 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5342 IWN_SCHED_LIMIT << 16); 5343 } 5344 5345 /* Enable interrupts for all our 16 queues. */ 5346 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5347 /* Identify TX FIFO rings (0-7). */ 5348 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5349 5350 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5351 for (qid = 0; qid < 7; qid++) { 5352 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5353 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5354 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5355 } 5356 iwn_nic_unlock(sc); 5357 return 0; 5358 } 5359 5360 /* 5361 * This function is called after the initialization or runtime firmware 5362 * notifies us of its readiness (called in a process context.) 5363 */ 5364 static int 5365 iwn5000_post_alive(struct iwn_softc *sc) 5366 { 5367 int error, qid; 5368 5369 /* Switch to using ICT interrupt mode. */ 5370 iwn5000_ict_reset(sc); 5371 5372 error = iwn_nic_lock(sc); 5373 if (error != 0) 5374 return error; 5375 5376 /* Clear TX scheduler state in SRAM. */ 5377 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5378 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5379 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5380 5381 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5382 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5383 5384 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5385 5386 /* Enable chain mode for all queues, except command queue. */ 5387 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5388 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5389 5390 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5391 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5392 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5393 5394 iwn_mem_write(sc, sc->sched_base + 5395 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5396 /* Set scheduler window size and frame limit. */ 5397 iwn_mem_write(sc, sc->sched_base + 5398 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5399 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5400 } 5401 5402 /* Enable interrupts for all our 20 queues. */ 5403 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5404 /* Identify TX FIFO rings (0-7). */ 5405 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5406 5407 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5408 for (qid = 0; qid < 7; qid++) { 5409 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5410 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5411 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5412 } 5413 iwn_nic_unlock(sc); 5414 5415 /* Configure WiMAX coexistence for combo adapters. */ 5416 error = iwn5000_send_wimax_coex(sc); 5417 if (error != 0) { 5418 device_printf(sc->sc_dev, 5419 "%s: could not configure WiMAX coexistence, error %d\n", 5420 __func__, error); 5421 return error; 5422 } 5423 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5424 struct iwn5000_phy_calib_crystal cmd; 5425 5426 /* Perform crystal calibration. */ 5427 memset(&cmd, 0, sizeof cmd); 5428 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5429 cmd.ngroups = 1; 5430 cmd.isvalid = 1; 5431 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5432 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5433 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5434 "sending crystal calibration %d, %d\n", 5435 cmd.cap_pin[0], cmd.cap_pin[1]); 5436 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5437 if (error != 0) { 5438 device_printf(sc->sc_dev, 5439 "%s: crystal calibration failed, error %d\n", 5440 __func__, error); 5441 return error; 5442 } 5443 } 5444 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5445 /* Query calibration from the initialization firmware. */ 5446 error = iwn5000_query_calibration(sc); 5447 if (error != 0) { 5448 device_printf(sc->sc_dev, 5449 "%s: could not query calibration, error %d\n", 5450 __func__, error); 5451 return error; 5452 } 5453 /* 5454 * We have the calibration results now, reboot with the 5455 * runtime firmware (call ourselves recursively!) 5456 */ 5457 iwn_hw_stop(sc); 5458 error = iwn_hw_init(sc); 5459 } else { 5460 /* Send calibration results to runtime firmware. */ 5461 error = iwn5000_send_calibration(sc); 5462 } 5463 return error; 5464 } 5465 5466 /* 5467 * The firmware boot code is small and is intended to be copied directly into 5468 * the NIC internal memory (no DMA transfer.) 5469 */ 5470 static int 5471 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5472 { 5473 int error, ntries; 5474 5475 size /= sizeof (uint32_t); 5476 5477 error = iwn_nic_lock(sc); 5478 if (error != 0) 5479 return error; 5480 5481 /* Copy microcode image into NIC memory. */ 5482 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5483 (const uint32_t *)ucode, size); 5484 5485 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5486 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5487 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5488 5489 /* Start boot load now. */ 5490 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5491 5492 /* Wait for transfer to complete. */ 5493 for (ntries = 0; ntries < 1000; ntries++) { 5494 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5495 IWN_BSM_WR_CTRL_START)) 5496 break; 5497 DELAY(10); 5498 } 5499 if (ntries == 1000) { 5500 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5501 __func__); 5502 iwn_nic_unlock(sc); 5503 return ETIMEDOUT; 5504 } 5505 5506 /* Enable boot after power up. */ 5507 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5508 5509 iwn_nic_unlock(sc); 5510 return 0; 5511 } 5512 5513 static int 5514 iwn4965_load_firmware(struct iwn_softc *sc) 5515 { 5516 struct iwn_fw_info *fw = &sc->fw; 5517 struct iwn_dma_info *dma = &sc->fw_dma; 5518 int error; 5519 5520 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5521 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5522 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5523 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5524 fw->init.text, fw->init.textsz); 5525 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5526 5527 /* Tell adapter where to find initialization sections. */ 5528 error = iwn_nic_lock(sc); 5529 if (error != 0) 5530 return error; 5531 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5532 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5533 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5534 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5535 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5536 iwn_nic_unlock(sc); 5537 5538 /* Load firmware boot code. */ 5539 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5540 if (error != 0) { 5541 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5542 __func__); 5543 return error; 5544 } 5545 /* Now press "execute". */ 5546 IWN_WRITE(sc, IWN_RESET, 0); 5547 5548 /* Wait at most one second for first alive notification. */ 5549 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 5550 if (error) { 5551 device_printf(sc->sc_dev, 5552 "%s: timeout waiting for adapter to initialize, error %d\n", 5553 __func__, error); 5554 return error; 5555 } 5556 5557 /* Retrieve current temperature for initial TX power calibration. */ 5558 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5559 sc->temp = iwn4965_get_temperature(sc); 5560 5561 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5562 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5563 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5564 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5565 fw->main.text, fw->main.textsz); 5566 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5567 5568 /* Tell adapter where to find runtime sections. */ 5569 error = iwn_nic_lock(sc); 5570 if (error != 0) 5571 return error; 5572 5573 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5574 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5575 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5576 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5577 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5578 IWN_FW_UPDATED | fw->main.textsz); 5579 iwn_nic_unlock(sc); 5580 5581 return 0; 5582 } 5583 5584 static int 5585 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5586 const uint8_t *section, int size) 5587 { 5588 struct iwn_dma_info *dma = &sc->fw_dma; 5589 int error; 5590 5591 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5592 memcpy(dma->vaddr, section, size); 5593 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5594 5595 error = iwn_nic_lock(sc); 5596 if (error != 0) 5597 return error; 5598 5599 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5600 IWN_FH_TX_CONFIG_DMA_PAUSE); 5601 5602 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5603 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5604 IWN_LOADDR(dma->paddr)); 5605 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5606 IWN_HIADDR(dma->paddr) << 28 | size); 5607 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5608 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5609 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5610 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5611 5612 /* Kick Flow Handler to start DMA transfer. */ 5613 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5614 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5615 5616 iwn_nic_unlock(sc); 5617 5618 /* 5619 * Wait at most five seconds for FH DMA transfer to complete. 5620 */ 5621 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 5622 return (error); 5623 } 5624 5625 static int 5626 iwn5000_load_firmware(struct iwn_softc *sc) 5627 { 5628 struct iwn_fw_part *fw; 5629 int error; 5630 5631 /* Load the initialization firmware on first boot only. */ 5632 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5633 &sc->fw.main : &sc->fw.init; 5634 5635 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5636 fw->text, fw->textsz); 5637 if (error != 0) { 5638 device_printf(sc->sc_dev, 5639 "%s: could not load firmware %s section, error %d\n", 5640 __func__, ".text", error); 5641 return error; 5642 } 5643 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5644 fw->data, fw->datasz); 5645 if (error != 0) { 5646 device_printf(sc->sc_dev, 5647 "%s: could not load firmware %s section, error %d\n", 5648 __func__, ".data", error); 5649 return error; 5650 } 5651 5652 /* Now press "execute". */ 5653 IWN_WRITE(sc, IWN_RESET, 0); 5654 return 0; 5655 } 5656 5657 static int 5658 iwn_read_firmware(struct iwn_softc *sc) 5659 { 5660 const struct iwn_hal *hal = sc->sc_hal; 5661 struct iwn_fw_info *fw = &sc->fw; 5662 const uint32_t *ptr; 5663 uint32_t rev; 5664 size_t size; 5665 int wlan_serialized; 5666 5667 /* 5668 * Read firmware image from filesystem. The firmware can block 5669 * in a taskq and deadlock against our serializer so unlock 5670 * while we do tihs. 5671 */ 5672 wlan_serialized = IS_SERIALIZED(&wlan_global_serializer); 5673 if (wlan_serialized) 5674 wlan_serialize_exit(); 5675 sc->fw_fp = firmware_get(sc->fwname); 5676 if (wlan_serialized) 5677 wlan_serialize_enter(); 5678 if (sc->fw_fp == NULL) { 5679 device_printf(sc->sc_dev, 5680 "%s: could not load firmare image \"%s\"\n", __func__, 5681 sc->fwname); 5682 return EINVAL; 5683 } 5684 5685 size = sc->fw_fp->datasize; 5686 if (size < 28) { 5687 device_printf(sc->sc_dev, 5688 "%s: truncated firmware header: %zu bytes\n", 5689 __func__, size); 5690 return EINVAL; 5691 } 5692 5693 /* Process firmware header. */ 5694 ptr = (const uint32_t *)sc->fw_fp->data; 5695 rev = le32toh(*ptr++); 5696 /* Check firmware API version. */ 5697 if (IWN_FW_API(rev) <= 1) { 5698 device_printf(sc->sc_dev, 5699 "%s: bad firmware, need API version >=2\n", __func__); 5700 return EINVAL; 5701 } 5702 if (IWN_FW_API(rev) >= 3) { 5703 /* Skip build number (version 2 header). */ 5704 size -= 4; 5705 ptr++; 5706 } 5707 fw->main.textsz = le32toh(*ptr++); 5708 fw->main.datasz = le32toh(*ptr++); 5709 fw->init.textsz = le32toh(*ptr++); 5710 fw->init.datasz = le32toh(*ptr++); 5711 fw->boot.textsz = le32toh(*ptr++); 5712 size -= 24; 5713 5714 /* Sanity-check firmware header. */ 5715 if (fw->main.textsz > hal->fw_text_maxsz || 5716 fw->main.datasz > hal->fw_data_maxsz || 5717 fw->init.textsz > hal->fw_text_maxsz || 5718 fw->init.datasz > hal->fw_data_maxsz || 5719 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5720 (fw->boot.textsz & 3) != 0) { 5721 device_printf(sc->sc_dev, "%s: invalid firmware header\n", 5722 __func__); 5723 return EINVAL; 5724 } 5725 5726 /* Check that all firmware sections fit. */ 5727 if (fw->main.textsz + fw->main.datasz + fw->init.textsz + 5728 fw->init.datasz + fw->boot.textsz > size) { 5729 device_printf(sc->sc_dev, 5730 "%s: firmware file too short: %zu bytes\n", 5731 __func__, size); 5732 return EINVAL; 5733 } 5734 5735 /* Get pointers to firmware sections. */ 5736 fw->main.text = (const uint8_t *)ptr; 5737 fw->main.data = fw->main.text + fw->main.textsz; 5738 fw->init.text = fw->main.data + fw->main.datasz; 5739 fw->init.data = fw->init.text + fw->init.textsz; 5740 fw->boot.text = fw->init.data + fw->init.datasz; 5741 5742 return 0; 5743 } 5744 5745 static int 5746 iwn_clock_wait(struct iwn_softc *sc) 5747 { 5748 int ntries; 5749 5750 /* Set "initialization complete" bit. */ 5751 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5752 5753 /* Wait for clock stabilization. */ 5754 for (ntries = 0; ntries < 2500; ntries++) { 5755 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5756 return 0; 5757 DELAY(10); 5758 } 5759 device_printf(sc->sc_dev, 5760 "%s: timeout waiting for clock stabilization\n", __func__); 5761 return ETIMEDOUT; 5762 } 5763 5764 static int 5765 iwn_apm_init(struct iwn_softc *sc) 5766 { 5767 uint32_t tmp; 5768 int error; 5769 5770 /* Disable L0s exit timer (NMI bug workaround.) */ 5771 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5772 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5773 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5774 5775 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5776 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5777 5778 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5779 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5780 5781 /* Retrieve PCIe Active State Power Management (ASPM). */ 5782 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 5783 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5784 if (tmp & 0x02) /* L1 Entry enabled. */ 5785 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5786 else 5787 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5788 5789 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5790 sc->hw_type != IWN_HW_REV_TYPE_6000 && 5791 sc->hw_type != IWN_HW_REV_TYPE_6050) 5792 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5793 5794 /* Wait for clock stabilization before accessing prph. */ 5795 error = iwn_clock_wait(sc); 5796 if (error != 0) 5797 return error; 5798 5799 error = iwn_nic_lock(sc); 5800 if (error != 0) 5801 return error; 5802 5803 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5804 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5805 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5806 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5807 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5808 } else { 5809 /* Enable DMA. */ 5810 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5811 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5812 } 5813 DELAY(20); 5814 5815 /* Disable L1-Active. */ 5816 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5817 iwn_nic_unlock(sc); 5818 5819 return 0; 5820 } 5821 5822 static void 5823 iwn_apm_stop_master(struct iwn_softc *sc) 5824 { 5825 int ntries; 5826 5827 /* Stop busmaster DMA activity. */ 5828 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5829 for (ntries = 0; ntries < 100; ntries++) { 5830 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5831 return; 5832 DELAY(10); 5833 } 5834 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", 5835 __func__); 5836 } 5837 5838 static void 5839 iwn_apm_stop(struct iwn_softc *sc) 5840 { 5841 iwn_apm_stop_master(sc); 5842 5843 /* Reset the entire device. */ 5844 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5845 DELAY(10); 5846 /* Clear "initialization complete" bit. */ 5847 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5848 } 5849 5850 static int 5851 iwn4965_nic_config(struct iwn_softc *sc) 5852 { 5853 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5854 /* 5855 * I don't believe this to be correct but this is what the 5856 * vendor driver is doing. Probably the bits should not be 5857 * shifted in IWN_RFCFG_*. 5858 */ 5859 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5860 IWN_RFCFG_TYPE(sc->rfcfg) | 5861 IWN_RFCFG_STEP(sc->rfcfg) | 5862 IWN_RFCFG_DASH(sc->rfcfg)); 5863 } 5864 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5865 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5866 return 0; 5867 } 5868 5869 static int 5870 iwn5000_nic_config(struct iwn_softc *sc) 5871 { 5872 uint32_t tmp; 5873 int error; 5874 5875 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5876 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5877 IWN_RFCFG_TYPE(sc->rfcfg) | 5878 IWN_RFCFG_STEP(sc->rfcfg) | 5879 IWN_RFCFG_DASH(sc->rfcfg)); 5880 } 5881 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5882 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5883 5884 error = iwn_nic_lock(sc); 5885 if (error != 0) 5886 return error; 5887 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5888 5889 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5890 /* 5891 * Select first Switching Voltage Regulator (1.32V) to 5892 * solve a stability issue related to noisy DC2DC line 5893 * in the silicon of 1000 Series. 5894 */ 5895 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5896 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5897 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5898 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5899 } 5900 iwn_nic_unlock(sc); 5901 5902 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5903 /* Use internal power amplifier only. */ 5904 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5905 } 5906 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 5907 /* Indicate that ROM calibration version is >=6. */ 5908 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5909 } 5910 return 0; 5911 } 5912 5913 /* 5914 * Take NIC ownership over Intel Active Management Technology (AMT). 5915 */ 5916 static int 5917 iwn_hw_prepare(struct iwn_softc *sc) 5918 { 5919 int ntries; 5920 5921 /* Check if hardware is ready. */ 5922 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5923 for (ntries = 0; ntries < 5; ntries++) { 5924 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5925 IWN_HW_IF_CONFIG_NIC_READY) 5926 return 0; 5927 DELAY(10); 5928 } 5929 5930 /* Hardware not ready, force into ready state. */ 5931 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5932 for (ntries = 0; ntries < 15000; ntries++) { 5933 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5934 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5935 break; 5936 DELAY(10); 5937 } 5938 if (ntries == 15000) 5939 return ETIMEDOUT; 5940 5941 /* Hardware should be ready now. */ 5942 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5943 for (ntries = 0; ntries < 5; ntries++) { 5944 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5945 IWN_HW_IF_CONFIG_NIC_READY) 5946 return 0; 5947 DELAY(10); 5948 } 5949 return ETIMEDOUT; 5950 } 5951 5952 static int 5953 iwn_hw_init(struct iwn_softc *sc) 5954 { 5955 const struct iwn_hal *hal = sc->sc_hal; 5956 int error, chnl, qid; 5957 5958 /* Clear pending interrupts. */ 5959 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5960 5961 error = iwn_apm_init(sc); 5962 if (error != 0) { 5963 device_printf(sc->sc_dev, 5964 "%s: could not power ON adapter, error %d\n", 5965 __func__, error); 5966 goto done; 5967 } 5968 5969 /* Select VMAIN power source. */ 5970 error = iwn_nic_lock(sc); 5971 if (error != 0) 5972 goto done; 5973 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5974 iwn_nic_unlock(sc); 5975 5976 /* Perform adapter-specific initialization. */ 5977 error = hal->nic_config(sc); 5978 if (error != 0) 5979 goto done; 5980 5981 /* Initialize RX ring. */ 5982 error = iwn_nic_lock(sc); 5983 if (error != 0) 5984 goto done; 5985 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5986 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5987 /* Set physical address of RX ring (256-byte aligned.) */ 5988 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5989 /* Set physical address of RX status (16-byte aligned.) */ 5990 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5991 /* Enable RX. */ 5992 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5993 IWN_FH_RX_CONFIG_ENA | 5994 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5995 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5996 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5997 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5998 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5999 iwn_nic_unlock(sc); 6000 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6001 6002 error = iwn_nic_lock(sc); 6003 if (error != 0) 6004 goto done; 6005 6006 /* Initialize TX scheduler. */ 6007 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6008 6009 /* Set physical address of "keep warm" page (16-byte aligned.) */ 6010 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6011 6012 /* Initialize TX rings. */ 6013 for (qid = 0; qid < hal->ntxqs; qid++) { 6014 struct iwn_tx_ring *txq = &sc->txq[qid]; 6015 6016 /* Set physical address of TX ring (256-byte aligned.) */ 6017 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6018 txq->desc_dma.paddr >> 8); 6019 } 6020 iwn_nic_unlock(sc); 6021 6022 /* Enable DMA channels. */ 6023 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6024 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6025 IWN_FH_TX_CONFIG_DMA_ENA | 6026 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6027 } 6028 6029 /* Clear "radio off" and "commands blocked" bits. */ 6030 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6031 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6032 6033 /* Clear pending interrupts. */ 6034 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6035 /* Enable interrupt coalescing. */ 6036 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6037 /* Enable interrupts. */ 6038 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6039 6040 /* _Really_ make sure "radio off" bit is cleared! */ 6041 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6042 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6043 6044 error = hal->load_firmware(sc); 6045 if (error != 0) { 6046 device_printf(sc->sc_dev, 6047 "%s: could not load firmware, error %d\n", 6048 __func__, error); 6049 goto done; 6050 } 6051 /* Wait at most one second for firmware alive notification. */ 6052 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 6053 if (error != 0) { 6054 device_printf(sc->sc_dev, 6055 "%s: timeout waiting for adapter to initialize, error %d\n", 6056 __func__, error); 6057 goto done; 6058 } 6059 /* Do post-firmware initialization. */ 6060 error = hal->post_alive(sc); 6061 done: 6062 return error; 6063 } 6064 6065 static void 6066 iwn_hw_stop(struct iwn_softc *sc) 6067 { 6068 const struct iwn_hal *hal = sc->sc_hal; 6069 uint32_t tmp; 6070 int chnl, qid, ntries; 6071 6072 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6073 6074 /* Disable interrupts. */ 6075 IWN_WRITE(sc, IWN_INT_MASK, 0); 6076 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6077 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6078 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6079 6080 /* Make sure we no longer hold the NIC lock. */ 6081 iwn_nic_unlock(sc); 6082 6083 /* Stop TX scheduler. */ 6084 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6085 6086 /* Stop all DMA channels. */ 6087 if (iwn_nic_lock(sc) == 0) { 6088 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6089 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6090 for (ntries = 0; ntries < 200; ntries++) { 6091 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 6092 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 6093 IWN_FH_TX_STATUS_IDLE(chnl)) 6094 break; 6095 DELAY(10); 6096 } 6097 } 6098 iwn_nic_unlock(sc); 6099 } 6100 6101 /* Stop RX ring. */ 6102 iwn_reset_rx_ring(sc, &sc->rxq); 6103 6104 /* Reset all TX rings. */ 6105 for (qid = 0; qid < hal->ntxqs; qid++) 6106 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6107 6108 if (iwn_nic_lock(sc) == 0) { 6109 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6110 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6111 iwn_nic_unlock(sc); 6112 } 6113 DELAY(5); 6114 6115 /* Power OFF adapter. */ 6116 iwn_apm_stop(sc); 6117 } 6118 6119 static void 6120 iwn_init_locked(struct iwn_softc *sc) 6121 { 6122 struct ifnet *ifp = sc->sc_ifp; 6123 int error; 6124 int wlan_serializer_needed; 6125 6126 /* 6127 * The kernel generic firmware loader can wind up calling this 6128 * without the wlan serializer, while the wlan subsystem will 6129 * call it with the serializer. 6130 * 6131 * Make sure we hold the serializer or we will have timing issues 6132 * with the wlan subsystem. 6133 */ 6134 wlan_serializer_needed = !IS_SERIALIZED(&wlan_global_serializer); 6135 if (wlan_serializer_needed) 6136 wlan_serialize_enter(); 6137 6138 error = iwn_hw_prepare(sc); 6139 if (error != 0) { 6140 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n", 6141 __func__, error); 6142 goto fail; 6143 } 6144 6145 /* Initialize interrupt mask to default value. */ 6146 sc->int_mask = IWN_INT_MASK_DEF; 6147 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6148 6149 /* Check that the radio is not disabled by hardware switch. */ 6150 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6151 device_printf(sc->sc_dev, 6152 "radio is disabled by hardware switch\n"); 6153 6154 /* Enable interrupts to get RF toggle notifications. */ 6155 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6156 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6157 if (wlan_serializer_needed) 6158 wlan_serialize_exit(); 6159 return; 6160 } 6161 6162 /* Read firmware images from the filesystem. */ 6163 error = iwn_read_firmware(sc); 6164 if (error != 0) { 6165 device_printf(sc->sc_dev, 6166 "%s: could not read firmware, error %d\n", 6167 __func__, error); 6168 goto fail; 6169 } 6170 6171 /* Initialize hardware and upload firmware. */ 6172 error = iwn_hw_init(sc); 6173 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6174 sc->fw_fp = NULL; 6175 if (error != 0) { 6176 device_printf(sc->sc_dev, 6177 "%s: could not initialize hardware, error %d\n", 6178 __func__, error); 6179 goto fail; 6180 } 6181 6182 /* Configure adapter now that it is ready. */ 6183 error = iwn_config(sc); 6184 if (error != 0) { 6185 device_printf(sc->sc_dev, 6186 "%s: could not configure device, error %d\n", 6187 __func__, error); 6188 goto fail; 6189 } 6190 6191 ifq_clr_oactive(&ifp->if_snd); 6192 ifp->if_flags |= IFF_RUNNING; 6193 if (wlan_serializer_needed) 6194 wlan_serialize_exit(); 6195 return; 6196 6197 fail: 6198 iwn_stop_locked(sc); 6199 if (wlan_serializer_needed) 6200 wlan_serialize_exit(); 6201 } 6202 6203 static void 6204 iwn_init(void *arg) 6205 { 6206 struct iwn_softc *sc = arg; 6207 struct ifnet *ifp = sc->sc_ifp; 6208 struct ieee80211com *ic = ifp->if_l2com; 6209 6210 wlan_serialize_enter(); 6211 iwn_init_locked(sc); 6212 wlan_serialize_exit(); 6213 6214 if (ifp->if_flags & IFF_RUNNING) 6215 ieee80211_start_all(ic); 6216 } 6217 6218 static void 6219 iwn_stop_locked(struct iwn_softc *sc) 6220 { 6221 struct ifnet *ifp = sc->sc_ifp; 6222 6223 sc->sc_tx_timer = 0; 6224 callout_stop(&sc->sc_timer_to); 6225 ifp->if_flags &= ~IFF_RUNNING; 6226 ifq_clr_oactive(&ifp->if_snd); 6227 6228 /* Power OFF hardware. */ 6229 iwn_hw_stop(sc); 6230 } 6231 6232 static void 6233 iwn_stop(struct iwn_softc *sc) 6234 { 6235 wlan_serialize_enter(); 6236 iwn_stop_locked(sc); 6237 wlan_serialize_exit(); 6238 } 6239 6240 /* 6241 * Callback from net80211 to start a scan. 6242 */ 6243 static void 6244 iwn_scan_start(struct ieee80211com *ic) 6245 { 6246 struct ifnet *ifp = ic->ic_ifp; 6247 struct iwn_softc *sc = ifp->if_softc; 6248 6249 /* make the link LED blink while we're scanning */ 6250 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6251 } 6252 6253 /* 6254 * Callback from net80211 to terminate a scan. 6255 */ 6256 static void 6257 iwn_scan_end(struct ieee80211com *ic) 6258 { 6259 struct ifnet *ifp = ic->ic_ifp; 6260 struct iwn_softc *sc = ifp->if_softc; 6261 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6262 6263 if (vap->iv_state == IEEE80211_S_RUN) { 6264 /* Set link LED to ON status if we are associated */ 6265 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6266 } 6267 } 6268 6269 /* 6270 * Callback from net80211 to force a channel change. 6271 */ 6272 static void 6273 iwn_set_channel(struct ieee80211com *ic) 6274 { 6275 const struct ieee80211_channel *c = ic->ic_curchan; 6276 struct ifnet *ifp = ic->ic_ifp; 6277 struct iwn_softc *sc = ifp->if_softc; 6278 6279 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6280 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6281 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6282 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6283 } 6284 6285 /* 6286 * Callback from net80211 to start scanning of the current channel. 6287 */ 6288 static void 6289 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6290 { 6291 struct ieee80211vap *vap = ss->ss_vap; 6292 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6293 int error; 6294 6295 error = iwn_scan(sc); 6296 if (error != 0) 6297 ieee80211_cancel_scan(vap); 6298 } 6299 6300 /* 6301 * Callback from net80211 to handle the minimum dwell time being met. 6302 * The intent is to terminate the scan but we just let the firmware 6303 * notify us when it's finished as we have no safe way to abort it. 6304 */ 6305 static void 6306 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6307 { 6308 /* NB: don't try to abort scan; wait for firmware to finish */ 6309 } 6310 6311 static struct iwn_eeprom_chan * 6312 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 6313 { 6314 int i, j; 6315 6316 for (j = 0; j < 7; j++) { 6317 for (i = 0; i < iwn_bands[j].nchan; i++) { 6318 if (iwn_bands[j].chan[i] == c->ic_ieee) 6319 return &sc->eeprom_channels[j][i]; 6320 } 6321 } 6322 6323 return NULL; 6324 } 6325 6326 /* 6327 * Enforce flags read from EEPROM. 6328 */ 6329 static int 6330 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 6331 int nchan, struct ieee80211_channel chans[]) 6332 { 6333 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6334 int i; 6335 6336 for (i = 0; i < nchan; i++) { 6337 struct ieee80211_channel *c = &chans[i]; 6338 struct iwn_eeprom_chan *channel; 6339 6340 channel = iwn_find_eeprom_channel(sc, c); 6341 if (channel == NULL) { 6342 if_printf(ic->ic_ifp, 6343 "%s: invalid channel %u freq %u/0x%x\n", 6344 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 6345 return EINVAL; 6346 } 6347 c->ic_flags |= iwn_eeprom_channel_flags(channel); 6348 } 6349 6350 return 0; 6351 } 6352 6353 static void 6354 iwn_hw_reset_task(void *arg0, int pending) 6355 { 6356 struct iwn_softc *sc = arg0; 6357 struct ifnet *ifp; 6358 struct ieee80211com *ic; 6359 6360 wlan_serialize_enter(); 6361 ifp = sc->sc_ifp; 6362 ic = ifp->if_l2com; 6363 iwn_stop_locked(sc); 6364 iwn_init_locked(sc); 6365 ieee80211_notify_radio(ic, 1); 6366 wlan_serialize_exit(); 6367 } 6368 6369 static void 6370 iwn_radio_on_task(void *arg0, int pending) 6371 { 6372 struct iwn_softc *sc = arg0; 6373 struct ifnet *ifp; 6374 struct ieee80211com *ic; 6375 struct ieee80211vap *vap; 6376 6377 wlan_serialize_enter(); 6378 ifp = sc->sc_ifp; 6379 ic = ifp->if_l2com; 6380 vap = TAILQ_FIRST(&ic->ic_vaps); 6381 if (vap != NULL) { 6382 iwn_init_locked(sc); 6383 ieee80211_init(vap); 6384 } 6385 wlan_serialize_exit(); 6386 } 6387 6388 static void 6389 iwn_radio_off_task(void *arg0, int pending) 6390 { 6391 struct iwn_softc *sc = arg0; 6392 struct ifnet *ifp; 6393 struct ieee80211com *ic; 6394 struct ieee80211vap *vap; 6395 6396 wlan_serialize_enter(); 6397 ifp = sc->sc_ifp; 6398 ic = ifp->if_l2com; 6399 vap = TAILQ_FIRST(&ic->ic_vaps); 6400 iwn_stop_locked(sc); 6401 if (vap != NULL) 6402 ieee80211_stop(vap); 6403 6404 /* Enable interrupts to get RF toggle notification. */ 6405 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6406 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6407 wlan_serialize_exit(); 6408 } 6409 6410 static void 6411 iwn_sysctlattach(struct iwn_softc *sc) 6412 { 6413 struct sysctl_ctx_list *ctx; 6414 struct sysctl_oid *tree; 6415 6416 ctx = &sc->sc_sysctl_ctx; 6417 tree = sc->sc_sysctl_tree; 6418 if (tree == NULL) { 6419 device_printf(sc->sc_dev, "can't add sysctl node\n"); 6420 return; 6421 } 6422 6423 #ifdef IWN_DEBUG 6424 sc->sc_debug = 0; 6425 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6426 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 6427 #endif 6428 } 6429 6430 static int 6431 iwn_pci_shutdown(device_t dev) 6432 { 6433 struct iwn_softc *sc = device_get_softc(dev); 6434 6435 wlan_serialize_enter(); 6436 iwn_stop_locked(sc); 6437 wlan_serialize_exit(); 6438 6439 return 0; 6440 } 6441 6442 static int 6443 iwn_pci_suspend(device_t dev) 6444 { 6445 struct iwn_softc *sc = device_get_softc(dev); 6446 struct ifnet *ifp = sc->sc_ifp; 6447 struct ieee80211com *ic = ifp->if_l2com; 6448 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6449 6450 wlan_serialize_enter(); 6451 iwn_stop_locked(sc); 6452 if (vap != NULL) 6453 ieee80211_stop(vap); 6454 wlan_serialize_exit(); 6455 6456 return 0; 6457 } 6458 6459 static int 6460 iwn_pci_resume(device_t dev) 6461 { 6462 struct iwn_softc *sc = device_get_softc(dev); 6463 struct ifnet *ifp; 6464 struct ieee80211com *ic; 6465 struct ieee80211vap *vap; 6466 6467 wlan_serialize_enter(); 6468 ifp = sc->sc_ifp; 6469 ic = ifp->if_l2com; 6470 vap = TAILQ_FIRST(&ic->ic_vaps); 6471 /* Clear device-specific "PCI retry timeout" register (41h). */ 6472 pci_write_config(dev, 0x41, 0, 1); 6473 6474 if (ifp->if_flags & IFF_UP) { 6475 iwn_init_locked(sc); 6476 if (vap != NULL) 6477 ieee80211_init(vap); 6478 if (ifp->if_flags & IFF_RUNNING) 6479 iwn_start_locked(ifp); 6480 } 6481 wlan_serialize_exit(); 6482 6483 return 0; 6484 } 6485 6486 #ifdef IWN_DEBUG 6487 static const char * 6488 iwn_intr_str(uint8_t cmd) 6489 { 6490 switch (cmd) { 6491 /* Notifications */ 6492 case IWN_UC_READY: return "UC_READY"; 6493 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 6494 case IWN_TX_DONE: return "TX_DONE"; 6495 case IWN_START_SCAN: return "START_SCAN"; 6496 case IWN_STOP_SCAN: return "STOP_SCAN"; 6497 case IWN_RX_STATISTICS: return "RX_STATS"; 6498 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 6499 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 6500 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 6501 case IWN_RX_PHY: return "RX_PHY"; 6502 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 6503 case IWN_RX_DONE: return "RX_DONE"; 6504 6505 /* Command Notifications */ 6506 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 6507 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 6508 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 6509 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 6510 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 6511 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 6512 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 6513 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 6514 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 6515 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 6516 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 6517 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 6518 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 6519 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 6520 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 6521 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 6522 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 6523 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 6524 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 6525 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 6526 } 6527 return "UNKNOWN INTR NOTIF/CMD"; 6528 } 6529 #endif /* IWN_DEBUG */ 6530 6531 static device_method_t iwn_methods[] = { 6532 /* Device interface */ 6533 DEVMETHOD(device_probe, iwn_pci_probe), 6534 DEVMETHOD(device_attach, iwn_pci_attach), 6535 DEVMETHOD(device_detach, iwn_pci_detach), 6536 DEVMETHOD(device_shutdown, iwn_pci_shutdown), 6537 DEVMETHOD(device_suspend, iwn_pci_suspend), 6538 DEVMETHOD(device_resume, iwn_pci_resume), 6539 { 0, 0 } 6540 }; 6541 6542 static driver_t iwn_driver = { 6543 "iwn", 6544 iwn_methods, 6545 sizeof (struct iwn_softc) 6546 }; 6547 static devclass_t iwn_devclass; 6548 6549 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 6550 MODULE_DEPEND(iwn, pci, 1, 1, 1); 6551 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 6552 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 6553 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1); 6554