124a8d46aSMatthew Dillon /* $OpenBSD: if_iwmvar.h,v 1.7 2015/03/02 13:51:10 jsg Exp $ */
224a8d46aSMatthew Dillon
324a8d46aSMatthew Dillon /*
424a8d46aSMatthew Dillon * Copyright (c) 2014 genua mbh <info@genua.de>
524a8d46aSMatthew Dillon * Copyright (c) 2014 Fixup Software Ltd.
624a8d46aSMatthew Dillon *
724a8d46aSMatthew Dillon * Permission to use, copy, modify, and distribute this software for any
824a8d46aSMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
924a8d46aSMatthew Dillon * copyright notice and this permission notice appear in all copies.
1024a8d46aSMatthew Dillon *
1124a8d46aSMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1224a8d46aSMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1324a8d46aSMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1424a8d46aSMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1524a8d46aSMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
1624a8d46aSMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1724a8d46aSMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1824a8d46aSMatthew Dillon */
1924a8d46aSMatthew Dillon
2024a8d46aSMatthew Dillon /*-
2124a8d46aSMatthew Dillon * Based on BSD-licensed source modules in the Linux iwlwifi driver,
2224a8d46aSMatthew Dillon * which were used as the reference documentation for this implementation.
2324a8d46aSMatthew Dillon *
2424a8d46aSMatthew Dillon * Driver version we are currently based off of is
2524a8d46aSMatthew Dillon * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
2624a8d46aSMatthew Dillon *
2724a8d46aSMatthew Dillon ***********************************************************************
2824a8d46aSMatthew Dillon *
2924a8d46aSMatthew Dillon * This file is provided under a dual BSD/GPLv2 license. When using or
3024a8d46aSMatthew Dillon * redistributing this file, you may do so under either license.
3124a8d46aSMatthew Dillon *
3224a8d46aSMatthew Dillon * GPL LICENSE SUMMARY
3324a8d46aSMatthew Dillon *
3424a8d46aSMatthew Dillon * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
3524a8d46aSMatthew Dillon *
3624a8d46aSMatthew Dillon * This program is free software; you can redistribute it and/or modify
3724a8d46aSMatthew Dillon * it under the terms of version 2 of the GNU General Public License as
3824a8d46aSMatthew Dillon * published by the Free Software Foundation.
3924a8d46aSMatthew Dillon *
4024a8d46aSMatthew Dillon * This program is distributed in the hope that it will be useful, but
4124a8d46aSMatthew Dillon * WITHOUT ANY WARRANTY; without even the implied warranty of
4224a8d46aSMatthew Dillon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4324a8d46aSMatthew Dillon * General Public License for more details.
4424a8d46aSMatthew Dillon *
4524a8d46aSMatthew Dillon * You should have received a copy of the GNU General Public License
4624a8d46aSMatthew Dillon * along with this program; if not, write to the Free Software
4724a8d46aSMatthew Dillon * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
4824a8d46aSMatthew Dillon * USA
4924a8d46aSMatthew Dillon *
5024a8d46aSMatthew Dillon * The full GNU General Public License is included in this distribution
5124a8d46aSMatthew Dillon * in the file called COPYING.
5224a8d46aSMatthew Dillon *
5324a8d46aSMatthew Dillon * Contact Information:
5424a8d46aSMatthew Dillon * Intel Linux Wireless <ilw@linux.intel.com>
5524a8d46aSMatthew Dillon * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
5624a8d46aSMatthew Dillon *
5724a8d46aSMatthew Dillon *
5824a8d46aSMatthew Dillon * BSD LICENSE
5924a8d46aSMatthew Dillon *
6024a8d46aSMatthew Dillon * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
6124a8d46aSMatthew Dillon * All rights reserved.
6224a8d46aSMatthew Dillon *
6324a8d46aSMatthew Dillon * Redistribution and use in source and binary forms, with or without
6424a8d46aSMatthew Dillon * modification, are permitted provided that the following conditions
6524a8d46aSMatthew Dillon * are met:
6624a8d46aSMatthew Dillon *
6724a8d46aSMatthew Dillon * * Redistributions of source code must retain the above copyright
6824a8d46aSMatthew Dillon * notice, this list of conditions and the following disclaimer.
6924a8d46aSMatthew Dillon * * Redistributions in binary form must reproduce the above copyright
7024a8d46aSMatthew Dillon * notice, this list of conditions and the following disclaimer in
7124a8d46aSMatthew Dillon * the documentation and/or other materials provided with the
7224a8d46aSMatthew Dillon * distribution.
7324a8d46aSMatthew Dillon * * Neither the name Intel Corporation nor the names of its
7424a8d46aSMatthew Dillon * contributors may be used to endorse or promote products derived
7524a8d46aSMatthew Dillon * from this software without specific prior written permission.
7624a8d46aSMatthew Dillon *
7724a8d46aSMatthew Dillon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7824a8d46aSMatthew Dillon * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
7924a8d46aSMatthew Dillon * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
8024a8d46aSMatthew Dillon * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
8124a8d46aSMatthew Dillon * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
8224a8d46aSMatthew Dillon * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
8324a8d46aSMatthew Dillon * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
8424a8d46aSMatthew Dillon * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
8524a8d46aSMatthew Dillon * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8624a8d46aSMatthew Dillon * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
8724a8d46aSMatthew Dillon * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8824a8d46aSMatthew Dillon */
8924a8d46aSMatthew Dillon
9024a8d46aSMatthew Dillon /*-
9124a8d46aSMatthew Dillon * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
9224a8d46aSMatthew Dillon *
9324a8d46aSMatthew Dillon * Permission to use, copy, modify, and distribute this software for any
9424a8d46aSMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
9524a8d46aSMatthew Dillon * copyright notice and this permission notice appear in all copies.
9624a8d46aSMatthew Dillon *
9724a8d46aSMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9824a8d46aSMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9924a8d46aSMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10024a8d46aSMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10124a8d46aSMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
10224a8d46aSMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
10324a8d46aSMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
10424a8d46aSMatthew Dillon */
10524a8d46aSMatthew Dillon
10624a8d46aSMatthew Dillon struct iwm_rx_radiotap_header {
10724a8d46aSMatthew Dillon struct ieee80211_radiotap_header wr_ihdr;
10824a8d46aSMatthew Dillon uint64_t wr_tsft;
10924a8d46aSMatthew Dillon uint8_t wr_flags;
11024a8d46aSMatthew Dillon uint8_t wr_rate;
11124a8d46aSMatthew Dillon uint16_t wr_chan_freq;
11224a8d46aSMatthew Dillon uint16_t wr_chan_flags;
11324a8d46aSMatthew Dillon int8_t wr_dbm_antsignal;
11424a8d46aSMatthew Dillon int8_t wr_dbm_antnoise;
1156acbba79SMatthew Dillon } __packed __aligned(8);
11624a8d46aSMatthew Dillon
11724a8d46aSMatthew Dillon #define IWM_RX_RADIOTAP_PRESENT \
11824a8d46aSMatthew Dillon ((1 << IEEE80211_RADIOTAP_TSFT) | \
11924a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_FLAGS) | \
12024a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_RATE) | \
12124a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_CHANNEL) | \
12224a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
12324a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
12424a8d46aSMatthew Dillon
12524a8d46aSMatthew Dillon struct iwm_tx_radiotap_header {
12624a8d46aSMatthew Dillon struct ieee80211_radiotap_header wt_ihdr;
12724a8d46aSMatthew Dillon uint8_t wt_flags;
12824a8d46aSMatthew Dillon uint8_t wt_rate;
12924a8d46aSMatthew Dillon uint16_t wt_chan_freq;
13024a8d46aSMatthew Dillon uint16_t wt_chan_flags;
13124a8d46aSMatthew Dillon } __packed;
13224a8d46aSMatthew Dillon
13324a8d46aSMatthew Dillon #define IWM_TX_RADIOTAP_PRESENT \
13424a8d46aSMatthew Dillon ((1 << IEEE80211_RADIOTAP_FLAGS) | \
13524a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_RATE) | \
13624a8d46aSMatthew Dillon (1 << IEEE80211_RADIOTAP_CHANNEL))
13724a8d46aSMatthew Dillon
13824a8d46aSMatthew Dillon
139ff4d1fc3SImre Vadász #define IWM_UCODE_SECTION_MAX 16
14024a8d46aSMatthew Dillon
141ff4d1fc3SImre Vadász /**
142ff4d1fc3SImre Vadász * enum iwm_ucode_type
143ff4d1fc3SImre Vadász *
144ff4d1fc3SImre Vadász * The type of ucode.
145ff4d1fc3SImre Vadász *
146ff4d1fc3SImre Vadász * @IWM_UCODE_REGULAR: Normal runtime ucode
147ff4d1fc3SImre Vadász * @IWM_UCODE_INIT: Initial ucode
148ff4d1fc3SImre Vadász * @IWM_UCODE_WOWLAN: Wake on Wireless enabled ucode
149ff4d1fc3SImre Vadász * @IWM_UCODE_REGULAR_USNIFFER: Normal runtime ucode when using usniffer image
150ff4d1fc3SImre Vadász */
15124a8d46aSMatthew Dillon enum iwm_ucode_type {
152ff4d1fc3SImre Vadász IWM_UCODE_REGULAR,
153ff4d1fc3SImre Vadász IWM_UCODE_INIT,
154ff4d1fc3SImre Vadász IWM_UCODE_WOWLAN,
155ff4d1fc3SImre Vadász IWM_UCODE_REGULAR_USNIFFER,
15624a8d46aSMatthew Dillon IWM_UCODE_TYPE_MAX
15724a8d46aSMatthew Dillon };
15824a8d46aSMatthew Dillon
159757eecf0SImre Vadász struct iwm_ucode_capabilities {
160757eecf0SImre Vadász uint32_t max_probe_length;
161757eecf0SImre Vadász uint32_t n_scan_channels;
162757eecf0SImre Vadász uint32_t flags;
163757eecf0SImre Vadász uint8_t enabled_api[howmany(IWM_NUM_UCODE_TLV_API, NBBY)];
164757eecf0SImre Vadász uint8_t enabled_capa[howmany(IWM_NUM_UCODE_TLV_CAPA, NBBY)];
165757eecf0SImre Vadász };
166757eecf0SImre Vadász
167e98ee77aSImre Vadász /* one for each uCode image (inst/data, init/runtime/wowlan) */
168e98ee77aSImre Vadász struct iwm_fw_desc {
169e98ee77aSImre Vadász const void *data; /* vmalloc'ed data */
170e98ee77aSImre Vadász uint32_t len; /* size in bytes */
171e98ee77aSImre Vadász uint32_t offset; /* offset in the device */
172e98ee77aSImre Vadász };
173e98ee77aSImre Vadász
1744b1006a6SImre Vadász struct iwm_fw_img {
1754b1006a6SImre Vadász struct iwm_fw_desc sec[IWM_UCODE_SECTION_MAX];
17624a8d46aSMatthew Dillon int fw_count;
177e98ee77aSImre Vadász int is_dual_cpus;
178a8524cc6SImre Vadász uint32_t paging_mem_size;
1794b1006a6SImre Vadász };
1804b1006a6SImre Vadász
1814b1006a6SImre Vadász struct iwm_fw_info {
1824b1006a6SImre Vadász const struct firmware *fw_fp;
1834b1006a6SImre Vadász
1844b1006a6SImre Vadász /* ucode images */
1854b1006a6SImre Vadász struct iwm_fw_img img[IWM_UCODE_TYPE_MAX];
1864b1006a6SImre Vadász
1874b1006a6SImre Vadász struct iwm_ucode_capabilities ucode_capa;
188cbb82693SImre Vadász
189cbb82693SImre Vadász uint32_t phy_config;
190cbb82693SImre Vadász uint8_t valid_tx_ant;
191cbb82693SImre Vadász uint8_t valid_rx_ant;
19224a8d46aSMatthew Dillon };
19324a8d46aSMatthew Dillon
19424a8d46aSMatthew Dillon struct iwm_nvm_data {
19524a8d46aSMatthew Dillon int n_hw_addrs;
19624a8d46aSMatthew Dillon uint8_t hw_addr[IEEE80211_ADDR_LEN];
19724a8d46aSMatthew Dillon
19824a8d46aSMatthew Dillon int sku_cap_band_24GHz_enable;
19924a8d46aSMatthew Dillon int sku_cap_band_52GHz_enable;
20024a8d46aSMatthew Dillon int sku_cap_11n_enable;
20124a8d46aSMatthew Dillon int sku_cap_amt_enable;
20224a8d46aSMatthew Dillon int sku_cap_ipan_enable;
20324a8d46aSMatthew Dillon
20424a8d46aSMatthew Dillon uint8_t radio_cfg_type;
20524a8d46aSMatthew Dillon uint8_t radio_cfg_step;
20624a8d46aSMatthew Dillon uint8_t radio_cfg_dash;
20724a8d46aSMatthew Dillon uint8_t radio_cfg_pnum;
20824a8d46aSMatthew Dillon uint8_t valid_tx_ant, valid_rx_ant;
20977de6c2dSImre Vadász #define IWM_NUM_CHANNELS 39
210e8951a47SImre Vadász #define IWM_NUM_CHANNELS_8000 51
21177de6c2dSImre Vadász
21224a8d46aSMatthew Dillon uint16_t nvm_version;
21324a8d46aSMatthew Dillon uint8_t max_tx_pwr_half_dbm;
21439f8331bSImre Vadász
2150593e39cSImre Vadász boolean_t lar_enabled;
21639f8331bSImre Vadász uint16_t nvm_ch_flags[];
21724a8d46aSMatthew Dillon };
21824a8d46aSMatthew Dillon
21924a8d46aSMatthew Dillon /* max bufs per tfd the driver will use */
22024a8d46aSMatthew Dillon #define IWM_MAX_CMD_TBS_PER_TFD 2
22124a8d46aSMatthew Dillon
22224a8d46aSMatthew Dillon struct iwm_rx_packet;
22324a8d46aSMatthew Dillon struct iwm_host_cmd {
22424a8d46aSMatthew Dillon const void *data[IWM_MAX_CMD_TBS_PER_TFD];
22524a8d46aSMatthew Dillon struct iwm_rx_packet *resp_pkt;
22624a8d46aSMatthew Dillon unsigned long _rx_page_addr;
22724a8d46aSMatthew Dillon uint32_t _rx_page_order;
22824a8d46aSMatthew Dillon int handler_status;
22924a8d46aSMatthew Dillon
23024a8d46aSMatthew Dillon uint32_t flags;
23145078908SImre Vadász uint32_t id;
23224a8d46aSMatthew Dillon uint16_t len[IWM_MAX_CMD_TBS_PER_TFD];
23324a8d46aSMatthew Dillon uint8_t dataflags[IWM_MAX_CMD_TBS_PER_TFD];
23424a8d46aSMatthew Dillon };
23524a8d46aSMatthew Dillon
23624a8d46aSMatthew Dillon /*
23724a8d46aSMatthew Dillon * DMA glue is from iwn
23824a8d46aSMatthew Dillon */
23924a8d46aSMatthew Dillon
24024a8d46aSMatthew Dillon typedef caddr_t iwm_caddr_t;
24124a8d46aSMatthew Dillon typedef void *iwm_hookarg_t;
24224a8d46aSMatthew Dillon
24324a8d46aSMatthew Dillon struct iwm_dma_info {
24424a8d46aSMatthew Dillon bus_dma_tag_t tag;
24524a8d46aSMatthew Dillon bus_dmamap_t map;
24624a8d46aSMatthew Dillon bus_dma_segment_t seg;
24724a8d46aSMatthew Dillon bus_addr_t paddr;
24824a8d46aSMatthew Dillon void *vaddr;
24924a8d46aSMatthew Dillon bus_size_t size;
25024a8d46aSMatthew Dillon };
25124a8d46aSMatthew Dillon
2528a5b1999SImre Vadász /**
2538a5b1999SImre Vadász * struct iwm_fw_paging
2548a5b1999SImre Vadász * @fw_paging_block: dma memory info
2558a5b1999SImre Vadász * @fw_paging_size: page size
2568a5b1999SImre Vadász */
2578a5b1999SImre Vadász struct iwm_fw_paging {
2588a5b1999SImre Vadász struct iwm_dma_info fw_paging_block;
2598a5b1999SImre Vadász uint32_t fw_paging_size;
2608a5b1999SImre Vadász };
2618a5b1999SImre Vadász
26224a8d46aSMatthew Dillon #define IWM_TX_RING_COUNT 256
26324a8d46aSMatthew Dillon #define IWM_TX_RING_LOMARK 192
26424a8d46aSMatthew Dillon #define IWM_TX_RING_HIMARK 224
26524a8d46aSMatthew Dillon
26624a8d46aSMatthew Dillon struct iwm_tx_data {
26724a8d46aSMatthew Dillon bus_dmamap_t map;
26824a8d46aSMatthew Dillon bus_addr_t cmd_paddr;
26924a8d46aSMatthew Dillon bus_addr_t scratch_paddr;
27024a8d46aSMatthew Dillon struct mbuf *m;
27124a8d46aSMatthew Dillon struct iwm_node *in;
27224a8d46aSMatthew Dillon int done;
27324a8d46aSMatthew Dillon };
27424a8d46aSMatthew Dillon
27524a8d46aSMatthew Dillon struct iwm_tx_ring {
27624a8d46aSMatthew Dillon struct iwm_dma_info desc_dma;
27724a8d46aSMatthew Dillon struct iwm_dma_info cmd_dma;
27824a8d46aSMatthew Dillon struct iwm_tfd *desc;
27924a8d46aSMatthew Dillon struct iwm_device_cmd *cmd;
28024a8d46aSMatthew Dillon bus_dma_tag_t data_dmat;
28124a8d46aSMatthew Dillon struct iwm_tx_data data[IWM_TX_RING_COUNT];
28224a8d46aSMatthew Dillon int qid;
28324a8d46aSMatthew Dillon int queued;
28424a8d46aSMatthew Dillon int cur;
28524a8d46aSMatthew Dillon };
28624a8d46aSMatthew Dillon
2876acbba79SMatthew Dillon #define IWM_RX_LEGACY_RING_COUNT 256
2886acbba79SMatthew Dillon #define IWM_RX_MQ_RING_COUNT 512
2896acbba79SMatthew Dillon
29024a8d46aSMatthew Dillon #define IWM_RBUF_SIZE 4096
29124a8d46aSMatthew Dillon
29224a8d46aSMatthew Dillon #define IWM_MAX_SCATTER 20
29324a8d46aSMatthew Dillon
29424a8d46aSMatthew Dillon struct iwm_rx_data {
29524a8d46aSMatthew Dillon struct mbuf *m;
29624a8d46aSMatthew Dillon bus_dmamap_t map;
29724a8d46aSMatthew Dillon };
29824a8d46aSMatthew Dillon
29924a8d46aSMatthew Dillon struct iwm_rx_ring {
3006acbba79SMatthew Dillon struct iwm_dma_info free_desc_dma;
3016acbba79SMatthew Dillon struct iwm_dma_info used_desc_dma;
30224a8d46aSMatthew Dillon struct iwm_dma_info stat_dma;
30324a8d46aSMatthew Dillon struct iwm_dma_info buf_dma;
3046acbba79SMatthew Dillon void *desc;
30524a8d46aSMatthew Dillon struct iwm_rb_status *stat;
3066acbba79SMatthew Dillon struct iwm_rx_data data[512];
307cc440b26SImre Vadász bus_dmamap_t spare_map; /* for iwm_rx_addbuf() */
30824a8d46aSMatthew Dillon bus_dma_tag_t data_dmat;
30924a8d46aSMatthew Dillon int cur;
31024a8d46aSMatthew Dillon };
31124a8d46aSMatthew Dillon
31224a8d46aSMatthew Dillon #define IWM_CMD_RESP_MAX PAGE_SIZE
31324a8d46aSMatthew Dillon
3146acbba79SMatthew Dillon #define IWM_TE_SESSION_PROTECTION_MAX_TIME_MS 500
3156acbba79SMatthew Dillon #define IWM_TE_SESSION_PROTECTION_MIN_TIME_MS 400
31624a8d46aSMatthew Dillon
31724a8d46aSMatthew Dillon /*
31824a8d46aSMatthew Dillon * Command headers are in iwl-trans.h, which is full of all
31924a8d46aSMatthew Dillon * kinds of other junk, so we just replicate the structures here.
32024a8d46aSMatthew Dillon * First the software bits:
32124a8d46aSMatthew Dillon */
32224a8d46aSMatthew Dillon enum IWM_CMD_MODE {
32324a8d46aSMatthew Dillon IWM_CMD_SYNC = 0,
32424a8d46aSMatthew Dillon IWM_CMD_ASYNC = (1 << 0),
32524a8d46aSMatthew Dillon IWM_CMD_WANT_SKB = (1 << 1),
32624a8d46aSMatthew Dillon IWM_CMD_SEND_IN_RFKILL = (1 << 2),
32724a8d46aSMatthew Dillon };
32824a8d46aSMatthew Dillon enum iwm_hcmd_dataflag {
32924a8d46aSMatthew Dillon IWM_HCMD_DFL_NOCOPY = (1 << 0),
33024a8d46aSMatthew Dillon IWM_HCMD_DFL_DUP = (1 << 1),
33124a8d46aSMatthew Dillon };
33224a8d46aSMatthew Dillon
33324a8d46aSMatthew Dillon struct iwm_int_sta {
33424a8d46aSMatthew Dillon uint32_t sta_id;
33524a8d46aSMatthew Dillon uint32_t tfd_queue_msk;
33624a8d46aSMatthew Dillon };
33724a8d46aSMatthew Dillon
3386acbba79SMatthew Dillon struct iwm_phy_ctxt {
33924a8d46aSMatthew Dillon uint16_t id;
34024a8d46aSMatthew Dillon uint16_t color;
34124a8d46aSMatthew Dillon uint32_t ref;
34224a8d46aSMatthew Dillon struct ieee80211_channel *channel;
34324a8d46aSMatthew Dillon };
34424a8d46aSMatthew Dillon
34524a8d46aSMatthew Dillon struct iwm_bf_data {
34624a8d46aSMatthew Dillon int bf_enabled; /* filtering */
34724a8d46aSMatthew Dillon int ba_enabled; /* abort */
34824a8d46aSMatthew Dillon int ave_beacon_signal;
34924a8d46aSMatthew Dillon int last_cqm_event;
35024a8d46aSMatthew Dillon };
35124a8d46aSMatthew Dillon
35224a8d46aSMatthew Dillon struct iwm_vap {
35324a8d46aSMatthew Dillon struct ieee80211vap iv_vap;
35424a8d46aSMatthew Dillon int is_uploaded;
3558a41b10aSImre Vadász int iv_auth;
35624a8d46aSMatthew Dillon
35777de6c2dSImre Vadász int (*iv_newstate)(struct ieee80211vap *,
35877de6c2dSImre Vadász enum ieee80211_state, int);
3590cf16dd2SImre Vadász
3606acbba79SMatthew Dillon struct iwm_phy_ctxt *phy_ctxt;
361f16ef749SImre Vadász
362f16ef749SImre Vadász uint16_t id;
363f16ef749SImre Vadász uint16_t color;
364b8bd6cd7SImre Vadász
365b8bd6cd7SImre Vadász boolean_t have_wme;
366b8bd6cd7SImre Vadász /*
367b8bd6cd7SImre Vadász * QoS data from net80211, need to store this here
368b8bd6cd7SImre Vadász * as net80211 has a separate callback but we need
369b8bd6cd7SImre Vadász * to have the data for the MAC context
370b8bd6cd7SImre Vadász */
371b8bd6cd7SImre Vadász struct {
372b8bd6cd7SImre Vadász uint16_t cw_min;
373b8bd6cd7SImre Vadász uint16_t cw_max;
374b8bd6cd7SImre Vadász uint16_t edca_txop;
375b8bd6cd7SImre Vadász uint8_t aifsn;
376b8bd6cd7SImre Vadász } queue_params[WME_NUM_AC];
377dc2e69bdSImre Vadász
378dc2e69bdSImre Vadász /* indicates that this interface requires PS to be disabled */
379dc2e69bdSImre Vadász boolean_t ps_disabled;
38024a8d46aSMatthew Dillon };
38124a8d46aSMatthew Dillon #define IWM_VAP(_vap) ((struct iwm_vap *)(_vap))
38224a8d46aSMatthew Dillon
38377de6c2dSImre Vadász struct iwm_node {
38477de6c2dSImre Vadász struct ieee80211_node in_ni;
38577de6c2dSImre Vadász
38677de6c2dSImre Vadász /* status "bits" */
38777de6c2dSImre Vadász int in_assoc;
38877de6c2dSImre Vadász
38977de6c2dSImre Vadász struct iwm_lq_cmd in_lq;
39077de6c2dSImre Vadász };
39177de6c2dSImre Vadász #define IWM_NODE(_ni) ((struct iwm_node *)(_ni))
39277de6c2dSImre Vadász
39377de6c2dSImre Vadász #define IWM_STATION_ID 0
394edfc8a07SImre Vadász #define IWM_AUX_STA_ID 1
39577de6c2dSImre Vadász
39677de6c2dSImre Vadász #define IWM_DEFAULT_MACID 0
39777de6c2dSImre Vadász #define IWM_DEFAULT_COLOR 0
39877de6c2dSImre Vadász #define IWM_DEFAULT_TSFID 0
39977de6c2dSImre Vadász
40077de6c2dSImre Vadász #define IWM_ICT_SIZE 4096
40177de6c2dSImre Vadász #define IWM_ICT_COUNT (IWM_ICT_SIZE / sizeof (uint32_t))
40277de6c2dSImre Vadász #define IWM_ICT_PADDR_SHIFT 12
40377de6c2dSImre Vadász
40427d11320SImre Vadász struct iwm_cfg;
405cc8d6ccfSImre Vadász
40624a8d46aSMatthew Dillon struct iwm_softc {
40724a8d46aSMatthew Dillon device_t sc_dev;
40877de6c2dSImre Vadász uint32_t sc_debug;
409ebd4ceabSImre Vadász int sc_attached;
41045bc40b1SMatthew Dillon
41177de6c2dSImre Vadász struct lock sc_lk;
41277de6c2dSImre Vadász struct mbufq sc_snd;
41377de6c2dSImre Vadász struct ieee80211com sc_ic;
4146acbba79SMatthew Dillon #if !defined(__DragonFly__)
4156acbba79SMatthew Dillon struct ieee80211_ratectl_tx_status sc_txs;
4166acbba79SMatthew Dillon #endif
41745bc40b1SMatthew Dillon
41877de6c2dSImre Vadász int sc_flags;
41977de6c2dSImre Vadász #define IWM_FLAG_USE_ICT (1 << 0)
42077de6c2dSImre Vadász #define IWM_FLAG_HW_INITED (1 << 1)
42177de6c2dSImre Vadász #define IWM_FLAG_STOPPED (1 << 2)
42277de6c2dSImre Vadász #define IWM_FLAG_RFKILL (1 << 3)
42377de6c2dSImre Vadász #define IWM_FLAG_BUSY (1 << 4)
424edfc8a07SImre Vadász #define IWM_FLAG_SCANNING (1 << 5)
4251f249c98SImre Vadász #define IWM_FLAG_SCAN_RUNNING (1 << 6)
426706a3044SImre Vadász #define IWM_FLAG_TE_ACTIVE (1 << 7)
42724a8d46aSMatthew Dillon
42824a8d46aSMatthew Dillon struct intr_config_hook sc_preinit_hook;
42924a8d46aSMatthew Dillon struct callout sc_watchdog_to;
43022380cddSImre Vadász struct callout sc_led_blink_to;
43124a8d46aSMatthew Dillon
43224a8d46aSMatthew Dillon struct task init_task;
43324a8d46aSMatthew Dillon
43424a8d46aSMatthew Dillon struct resource *sc_irq;
43524a8d46aSMatthew Dillon struct resource *sc_mem;
43624a8d46aSMatthew Dillon bus_space_tag_t sc_st;
43724a8d46aSMatthew Dillon bus_space_handle_t sc_sh;
43824a8d46aSMatthew Dillon bus_size_t sc_sz;
43924a8d46aSMatthew Dillon bus_dma_tag_t sc_dmat;
44024a8d46aSMatthew Dillon void *sc_ih;
44124a8d46aSMatthew Dillon
44224a8d46aSMatthew Dillon /* TX scheduler rings. */
44324a8d46aSMatthew Dillon struct iwm_dma_info sched_dma;
444a7697ea0SImre Vadász uint32_t scd_base_addr;
44524a8d46aSMatthew Dillon
44624a8d46aSMatthew Dillon /* TX/RX rings. */
4476acbba79SMatthew Dillon struct iwm_tx_ring txq[IWM_MAX_QUEUES];
44824a8d46aSMatthew Dillon struct iwm_rx_ring rxq;
44924a8d46aSMatthew Dillon int qfullmsk;
45024a8d46aSMatthew Dillon
45124a8d46aSMatthew Dillon /* ICT table. */
45224a8d46aSMatthew Dillon struct iwm_dma_info ict_dma;
45324a8d46aSMatthew Dillon int ict_cur;
45424a8d46aSMatthew Dillon
45524a8d46aSMatthew Dillon int sc_hw_rev;
45624a8d46aSMatthew Dillon int sc_hw_id;
45724a8d46aSMatthew Dillon
45824a8d46aSMatthew Dillon struct iwm_dma_info kw_dma;
45924a8d46aSMatthew Dillon struct iwm_dma_info fw_dma;
46024a8d46aSMatthew Dillon
46124a8d46aSMatthew Dillon int sc_fw_chunk_done;
46224a8d46aSMatthew Dillon
463a7697ea0SImre Vadász enum iwm_ucode_type cur_ucode;
464a7697ea0SImre Vadász int ucode_loaded;
465edfc8a07SImre Vadász char sc_fwver[32];
46624a8d46aSMatthew Dillon
467edfc8a07SImre Vadász char sc_fw_mcc[3];
46824a8d46aSMatthew Dillon
46924a8d46aSMatthew Dillon int sc_intmask;
47024a8d46aSMatthew Dillon
47124a8d46aSMatthew Dillon /*
47224a8d46aSMatthew Dillon * So why do we need a separate stopped flag and a generation?
47377de6c2dSImre Vadász * the former protects the device from issuing commands when it's
47424a8d46aSMatthew Dillon * stopped (duh). The latter protects against race from a very
47524a8d46aSMatthew Dillon * fast stop/unstop cycle where threads waiting for responses do
47624a8d46aSMatthew Dillon * not have a chance to run in between. Notably: we want to stop
47724a8d46aSMatthew Dillon * the device from interrupt context when it craps out, so we
47824a8d46aSMatthew Dillon * don't have the luxury of waiting for quiescense.
47924a8d46aSMatthew Dillon */
48024a8d46aSMatthew Dillon int sc_generation;
48124a8d46aSMatthew Dillon
48224a8d46aSMatthew Dillon struct iwm_fw_info sc_fw;
48324a8d46aSMatthew Dillon struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX];
48424a8d46aSMatthew Dillon
485cc8d6ccfSImre Vadász const struct iwm_cfg *cfg;
48639f8331bSImre Vadász struct iwm_nvm_data *nvm_data;
487c1019b6bSImre Vadász struct iwm_phy_db *sc_phy_db;
48824a8d46aSMatthew Dillon
48924a8d46aSMatthew Dillon struct iwm_bf_data sc_bf;
49024a8d46aSMatthew Dillon
49124a8d46aSMatthew Dillon int sc_tx_timer;
49224a8d46aSMatthew Dillon
49324a8d46aSMatthew Dillon int sc_scan_last_antenna;
49424a8d46aSMatthew Dillon
49524a8d46aSMatthew Dillon int sc_fixed_ridx;
49624a8d46aSMatthew Dillon
49724a8d46aSMatthew Dillon int sc_staid;
49824a8d46aSMatthew Dillon int sc_nodecolor;
49924a8d46aSMatthew Dillon
50024a8d46aSMatthew Dillon uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX];
50124a8d46aSMatthew Dillon int sc_wantresp;
50224a8d46aSMatthew Dillon
503*4cbc7cf9SMichael Neumann struct taskqueue *sc_tq;
50424a8d46aSMatthew Dillon struct task sc_es_task;
505*4cbc7cf9SMichael Neumann struct task sc_rftoggle_task;
50624a8d46aSMatthew Dillon
50724a8d46aSMatthew Dillon struct iwm_rx_phy_info sc_last_phy_info;
50824a8d46aSMatthew Dillon int sc_ampdu_ref;
50924a8d46aSMatthew Dillon
51024a8d46aSMatthew Dillon struct iwm_int_sta sc_aux_sta;
51124a8d46aSMatthew Dillon
51224a8d46aSMatthew Dillon /* phy contexts. we only use the first one */
5136acbba79SMatthew Dillon struct iwm_phy_ctxt sc_phyctxt[IWM_NUM_PHY_CTX];
51424a8d46aSMatthew Dillon
515*4cbc7cf9SMichael Neumann struct iwm_notif_statistics sc_stats;
51624a8d46aSMatthew Dillon int sc_noise;
51724a8d46aSMatthew Dillon
51877de6c2dSImre Vadász struct iwm_rx_radiotap_header sc_rxtap;
51977de6c2dSImre Vadász struct iwm_tx_radiotap_header sc_txtap;
52024a8d46aSMatthew Dillon
52124a8d46aSMatthew Dillon int sc_max_rssi;
52294dc1dadSImre Vadász
52394dc1dadSImre Vadász struct iwm_notif_wait_data *sc_notif_wait;
524ce43f57fSImre Vadász
525ce43f57fSImre Vadász int cmd_hold_nic_awake;
526a7697ea0SImre Vadász
527a7697ea0SImre Vadász /* Firmware status */
5283820e2bfSImre Vadász uint32_t error_event_table[2];
529a7697ea0SImre Vadász uint32_t log_event_table;
530a7697ea0SImre Vadász uint32_t umac_error_event_table;
531a7697ea0SImre Vadász int support_umac_log;
5328a5b1999SImre Vadász
5338a5b1999SImre Vadász /*
5348a5b1999SImre Vadász * Paging parameters - All of the parameters should be set by the
5358a5b1999SImre Vadász * opmode when paging is enabled
5368a5b1999SImre Vadász */
5378a5b1999SImre Vadász struct iwm_fw_paging fw_paging_db[IWM_NUM_OF_FW_PAGING_BLOCKS];
5388a5b1999SImre Vadász uint16_t num_of_paging_blk;
5398a5b1999SImre Vadász uint16_t num_of_pages_in_last_blk;
54089f579e9SImre Vadász
54189f579e9SImre Vadász boolean_t last_ebs_successful;
542d7002a79SImre Vadász
543cb650b01SImre Vadász /* last smart fifo state that was successfully sent to firmware */
544cb650b01SImre Vadász enum iwm_sf_state sf_state;
545cb650b01SImre Vadász
546d7002a79SImre Vadász /* Indicate if device power save is allowed */
547d7002a79SImre Vadász boolean_t sc_ps_disabled;
54808a7ad5aSImre Vadász
54908a7ad5aSImre Vadász int sc_ltr_enabled;
5508a41b10aSImre Vadász
5518a41b10aSImre Vadász /* Track firmware state for STA association. */
5528a41b10aSImre Vadász int sc_firmware_state;
553706a3044SImre Vadász
554706a3044SImre Vadász /* Unique ID (assigned by the firmware) of the current Time Event. */
555706a3044SImre Vadász uint32_t sc_time_event_uid;
556e8cb7158SImre Vadász
557e8cb7158SImre Vadász /* Duration of the Time Event in TU. */
558e8cb7158SImre Vadász uint32_t sc_time_event_duration;
559e8cb7158SImre Vadász
560e8cb7158SImre Vadász /* Expected end of the Time Event in HZ ticks. */
561e8cb7158SImre Vadász int sc_time_event_end_ticks;
56224a8d46aSMatthew Dillon };
56324a8d46aSMatthew Dillon
56477de6c2dSImre Vadász #define IWM_LOCK_INIT(_sc) \
5656acbba79SMatthew Dillon lockinit(&(_sc)->sc_lk, device_get_nameunit((_sc)->sc_dev), \
5666acbba79SMatthew Dillon 0, 0);
56777de6c2dSImre Vadász #define IWM_LOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_EXCLUSIVE)
56877de6c2dSImre Vadász #define IWM_UNLOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_RELEASE)
56977de6c2dSImre Vadász #define IWM_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lk)
5706acbba79SMatthew Dillon
5716acbba79SMatthew Dillon static inline bool
iwm_fw_has_api(struct iwm_softc * sc,unsigned int api)5726acbba79SMatthew Dillon iwm_fw_has_api(struct iwm_softc *sc, unsigned int api)
5736acbba79SMatthew Dillon {
5746acbba79SMatthew Dillon return isset(sc->sc_fw.ucode_capa.enabled_api, api);
5756acbba79SMatthew Dillon }
5766acbba79SMatthew Dillon
5776acbba79SMatthew Dillon static inline bool
iwm_fw_has_capa(struct iwm_softc * sc,unsigned int capa)5786acbba79SMatthew Dillon iwm_fw_has_capa(struct iwm_softc *sc, unsigned int capa)
5796acbba79SMatthew Dillon {
5806acbba79SMatthew Dillon return isset(sc->sc_fw.ucode_capa.enabled_capa, capa);
5816acbba79SMatthew Dillon }
582