1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 /* 36 * 80003ES2LAN Gigabit Ethernet Controller (Copper) 37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 38 */ 39 40 #include "e1000_api.h" 41 42 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 43 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 44 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 45 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 46 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 47 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 48 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 49 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 *data); 52 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 53 u32 offset, 54 u16 data); 55 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 58 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 59 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 60 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 61 u16 *duplex); 62 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 63 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 64 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 65 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 66 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 67 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 68 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 69 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 70 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 71 u16 *data); 72 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 73 u16 data); 74 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 75 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 76 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 77 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 78 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 79 80 /* 81 * A table for the GG82563 cable length where the range is defined 82 * with a lower bound at "index" and the upper bound at 83 * "index + 5". 84 */ 85 static const u16 e1000_gg82563_cable_length_table[] = { 86 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 87 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 88 (sizeof(e1000_gg82563_cable_length_table) / \ 89 sizeof(e1000_gg82563_cable_length_table[0])) 90 91 /** 92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 93 * @hw: pointer to the HW structure 94 **/ 95 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 96 { 97 struct e1000_phy_info *phy = &hw->phy; 98 s32 ret_val; 99 100 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 101 102 if (hw->phy.media_type != e1000_media_type_copper) { 103 phy->type = e1000_phy_none; 104 return E1000_SUCCESS; 105 } else { 106 phy->ops.power_up = e1000_power_up_phy_copper; 107 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 108 } 109 110 phy->addr = 1; 111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 112 phy->reset_delay_us = 100; 113 phy->type = e1000_phy_gg82563; 114 115 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 116 phy->ops.check_polarity = e1000_check_polarity_m88; 117 phy->ops.check_reset_block = e1000_check_reset_block_generic; 118 phy->ops.commit = e1000_phy_sw_reset_generic; 119 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 120 phy->ops.get_info = e1000_get_phy_info_m88; 121 phy->ops.release = e1000_release_phy_80003es2lan; 122 phy->ops.reset = e1000_phy_hw_reset_generic; 123 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 124 125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 126 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 127 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 128 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 129 130 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 131 132 /* This can only be done after all function pointers are setup. */ 133 ret_val = e1000_get_phy_id(hw); 134 135 /* Verify phy id */ 136 if (phy->id != GG82563_E_PHY_ID) 137 return -E1000_ERR_PHY; 138 139 return ret_val; 140 } 141 142 /** 143 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 144 * @hw: pointer to the HW structure 145 **/ 146 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 147 { 148 struct e1000_nvm_info *nvm = &hw->nvm; 149 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 150 u16 size; 151 152 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 153 154 nvm->opcode_bits = 8; 155 nvm->delay_usec = 1; 156 switch (nvm->override) { 157 case e1000_nvm_override_spi_large: 158 nvm->page_size = 32; 159 nvm->address_bits = 16; 160 break; 161 case e1000_nvm_override_spi_small: 162 nvm->page_size = 8; 163 nvm->address_bits = 8; 164 break; 165 default: 166 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 167 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 168 break; 169 } 170 171 nvm->type = e1000_nvm_eeprom_spi; 172 173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 174 E1000_EECD_SIZE_EX_SHIFT); 175 176 /* 177 * Added to a constant, "size" becomes the left-shift value 178 * for setting word_size. 179 */ 180 size += NVM_WORD_SIZE_BASE_SHIFT; 181 182 /* EEPROM access above 16k is unsupported */ 183 if (size > 14) 184 size = 14; 185 nvm->word_size = 1 << size; 186 187 /* Function Pointers */ 188 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 189 nvm->ops.read = e1000_read_nvm_eerd; 190 nvm->ops.release = e1000_release_nvm_80003es2lan; 191 nvm->ops.update = e1000_update_nvm_checksum_generic; 192 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 193 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 194 nvm->ops.write = e1000_write_nvm_80003es2lan; 195 196 return E1000_SUCCESS; 197 } 198 199 /** 200 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 201 * @hw: pointer to the HW structure 202 **/ 203 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 204 { 205 struct e1000_mac_info *mac = &hw->mac; 206 207 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 208 209 /* Set media type and media-dependent function pointers */ 210 switch (hw->device_id) { 211 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 212 hw->phy.media_type = e1000_media_type_internal_serdes; 213 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 214 mac->ops.setup_physical_interface = 215 e1000_setup_fiber_serdes_link_generic; 216 break; 217 default: 218 hw->phy.media_type = e1000_media_type_copper; 219 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 220 mac->ops.setup_physical_interface = 221 e1000_setup_copper_link_80003es2lan; 222 break; 223 } 224 225 /* Set mta register count */ 226 mac->mta_reg_count = 128; 227 /* Set rar entry count */ 228 mac->rar_entry_count = E1000_RAR_ENTRIES; 229 /* Set if part includes ASF firmware */ 230 mac->asf_firmware_present = TRUE; 231 /* FWSM register */ 232 mac->has_fwsm = TRUE; 233 /* ARC supported; valid only if manageability features are enabled. */ 234 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 235 E1000_FWSM_MODE_MASK); 236 /* Adaptive IFS not supported */ 237 mac->adaptive_ifs = FALSE; 238 239 /* Function pointers */ 240 241 /* bus type/speed/width */ 242 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 243 /* reset */ 244 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 245 /* hw initialization */ 246 mac->ops.init_hw = e1000_init_hw_80003es2lan; 247 /* link setup */ 248 mac->ops.setup_link = e1000_setup_link_generic; 249 /* check management mode */ 250 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 251 /* multicast address update */ 252 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 253 /* writing VFTA */ 254 mac->ops.write_vfta = e1000_write_vfta_generic; 255 /* clearing VFTA */ 256 mac->ops.clear_vfta = e1000_clear_vfta_generic; 257 /* read mac address */ 258 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 259 /* ID LED init */ 260 mac->ops.id_led_init = e1000_id_led_init_generic; 261 /* blink LED */ 262 mac->ops.blink_led = e1000_blink_led_generic; 263 /* setup LED */ 264 mac->ops.setup_led = e1000_setup_led_generic; 265 /* cleanup LED */ 266 mac->ops.cleanup_led = e1000_cleanup_led_generic; 267 /* turn on/off LED */ 268 mac->ops.led_on = e1000_led_on_generic; 269 mac->ops.led_off = e1000_led_off_generic; 270 /* clear hardware counters */ 271 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 272 /* link info */ 273 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 274 275 /* set lan id for port to determine which phy lock to use */ 276 hw->mac.ops.set_lan_id(hw); 277 278 return E1000_SUCCESS; 279 } 280 281 /** 282 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 283 * @hw: pointer to the HW structure 284 * 285 * Called to initialize all function pointers and parameters. 286 **/ 287 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 288 { 289 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 290 291 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 292 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 293 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 294 } 295 296 /** 297 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 298 * @hw: pointer to the HW structure 299 * 300 * A wrapper to acquire access rights to the correct PHY. 301 **/ 302 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 303 { 304 u16 mask; 305 306 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 307 308 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 309 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 310 } 311 312 /** 313 * e1000_release_phy_80003es2lan - Release rights to access PHY 314 * @hw: pointer to the HW structure 315 * 316 * A wrapper to release access rights to the correct PHY. 317 **/ 318 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 319 { 320 u16 mask; 321 322 DEBUGFUNC("e1000_release_phy_80003es2lan"); 323 324 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 325 e1000_release_swfw_sync_80003es2lan(hw, mask); 326 } 327 328 /** 329 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 330 * @hw: pointer to the HW structure 331 * 332 * Acquire the semaphore to access the Kumeran interface. 333 * 334 **/ 335 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 336 { 337 u16 mask; 338 339 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 340 341 mask = E1000_SWFW_CSR_SM; 342 343 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 344 } 345 346 /** 347 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 348 * @hw: pointer to the HW structure 349 * 350 * Release the semaphore used to access the Kumeran interface 351 **/ 352 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 353 { 354 u16 mask; 355 356 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 357 358 mask = E1000_SWFW_CSR_SM; 359 360 e1000_release_swfw_sync_80003es2lan(hw, mask); 361 } 362 363 /** 364 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 365 * @hw: pointer to the HW structure 366 * 367 * Acquire the semaphore to access the EEPROM. 368 **/ 369 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 370 { 371 s32 ret_val; 372 373 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 374 375 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 376 if (ret_val) 377 return ret_val; 378 379 ret_val = e1000_acquire_nvm_generic(hw); 380 381 if (ret_val) 382 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 383 384 return ret_val; 385 } 386 387 /** 388 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 389 * @hw: pointer to the HW structure 390 * 391 * Release the semaphore used to access the EEPROM. 392 **/ 393 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 394 { 395 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 396 397 e1000_release_nvm_generic(hw); 398 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 399 } 400 401 /** 402 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 403 * @hw: pointer to the HW structure 404 * @mask: specifies which semaphore to acquire 405 * 406 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 407 * will also specify which port we're acquiring the lock for. 408 **/ 409 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 410 { 411 u32 swfw_sync; 412 u32 swmask = mask; 413 u32 fwmask = mask << 16; 414 s32 i = 0; 415 s32 timeout = 50; 416 417 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 418 419 while (i < timeout) { 420 if (e1000_get_hw_semaphore_generic(hw)) 421 return -E1000_ERR_SWFW_SYNC; 422 423 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 424 if (!(swfw_sync & (fwmask | swmask))) 425 break; 426 427 /* 428 * Firmware currently using resource (fwmask) 429 * or other software thread using resource (swmask) 430 */ 431 e1000_put_hw_semaphore_generic(hw); 432 msec_delay_irq(5); 433 i++; 434 } 435 436 if (i == timeout) { 437 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 438 return -E1000_ERR_SWFW_SYNC; 439 } 440 441 swfw_sync |= swmask; 442 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 443 444 e1000_put_hw_semaphore_generic(hw); 445 446 return E1000_SUCCESS; 447 } 448 449 /** 450 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 451 * @hw: pointer to the HW structure 452 * @mask: specifies which semaphore to acquire 453 * 454 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 455 * will also specify which port we're releasing the lock for. 456 **/ 457 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 458 { 459 u32 swfw_sync; 460 461 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 462 463 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 464 ; /* Empty */ 465 466 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 467 swfw_sync &= ~mask; 468 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 469 470 e1000_put_hw_semaphore_generic(hw); 471 } 472 473 /** 474 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 475 * @hw: pointer to the HW structure 476 * @offset: offset of the register to read 477 * @data: pointer to the data returned from the operation 478 * 479 * Read the GG82563 PHY register. 480 **/ 481 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 482 u32 offset, u16 *data) 483 { 484 s32 ret_val; 485 u32 page_select; 486 u16 temp; 487 488 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 489 490 ret_val = e1000_acquire_phy_80003es2lan(hw); 491 if (ret_val) 492 return ret_val; 493 494 /* Select Configuration Page */ 495 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 496 page_select = GG82563_PHY_PAGE_SELECT; 497 } else { 498 /* 499 * Use Alternative Page Select register to access 500 * registers 30 and 31 501 */ 502 page_select = GG82563_PHY_PAGE_SELECT_ALT; 503 } 504 505 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 506 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 507 if (ret_val) { 508 e1000_release_phy_80003es2lan(hw); 509 return ret_val; 510 } 511 512 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 513 /* 514 * The "ready" bit in the MDIC register may be incorrectly set 515 * before the device has completed the "Page Select" MDI 516 * transaction. So we wait 200us after each MDI command... 517 */ 518 usec_delay(200); 519 520 /* ...and verify the command was successful. */ 521 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 522 523 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 524 e1000_release_phy_80003es2lan(hw); 525 return -E1000_ERR_PHY; 526 } 527 528 usec_delay(200); 529 530 ret_val = e1000_read_phy_reg_mdic(hw, 531 MAX_PHY_REG_ADDRESS & offset, 532 data); 533 534 usec_delay(200); 535 } else { 536 ret_val = e1000_read_phy_reg_mdic(hw, 537 MAX_PHY_REG_ADDRESS & offset, 538 data); 539 } 540 541 e1000_release_phy_80003es2lan(hw); 542 543 return ret_val; 544 } 545 546 /** 547 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 548 * @hw: pointer to the HW structure 549 * @offset: offset of the register to read 550 * @data: value to write to the register 551 * 552 * Write to the GG82563 PHY register. 553 **/ 554 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 555 u32 offset, u16 data) 556 { 557 s32 ret_val; 558 u32 page_select; 559 u16 temp; 560 561 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 562 563 ret_val = e1000_acquire_phy_80003es2lan(hw); 564 if (ret_val) 565 return ret_val; 566 567 /* Select Configuration Page */ 568 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 569 page_select = GG82563_PHY_PAGE_SELECT; 570 } else { 571 /* 572 * Use Alternative Page Select register to access 573 * registers 30 and 31 574 */ 575 page_select = GG82563_PHY_PAGE_SELECT_ALT; 576 } 577 578 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 579 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 580 if (ret_val) { 581 e1000_release_phy_80003es2lan(hw); 582 return ret_val; 583 } 584 585 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 586 /* 587 * The "ready" bit in the MDIC register may be incorrectly set 588 * before the device has completed the "Page Select" MDI 589 * transaction. So we wait 200us after each MDI command... 590 */ 591 usec_delay(200); 592 593 /* ...and verify the command was successful. */ 594 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 595 596 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 597 e1000_release_phy_80003es2lan(hw); 598 return -E1000_ERR_PHY; 599 } 600 601 usec_delay(200); 602 603 ret_val = e1000_write_phy_reg_mdic(hw, 604 MAX_PHY_REG_ADDRESS & offset, 605 data); 606 607 usec_delay(200); 608 } else { 609 ret_val = e1000_write_phy_reg_mdic(hw, 610 MAX_PHY_REG_ADDRESS & offset, 611 data); 612 } 613 614 e1000_release_phy_80003es2lan(hw); 615 616 return ret_val; 617 } 618 619 /** 620 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 621 * @hw: pointer to the HW structure 622 * @offset: offset of the register to read 623 * @words: number of words to write 624 * @data: buffer of data to write to the NVM 625 * 626 * Write "words" of data to the ESB2 NVM. 627 **/ 628 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 629 u16 words, u16 *data) 630 { 631 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 632 633 return e1000_write_nvm_spi(hw, offset, words, data); 634 } 635 636 /** 637 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 638 * @hw: pointer to the HW structure 639 * 640 * Wait a specific amount of time for manageability processes to complete. 641 * This is a function pointer entry point called by the phy module. 642 **/ 643 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 644 { 645 s32 timeout = PHY_CFG_TIMEOUT; 646 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 647 648 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 649 650 if (hw->bus.func == 1) 651 mask = E1000_NVM_CFG_DONE_PORT_1; 652 653 while (timeout) { 654 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 655 break; 656 msec_delay(1); 657 timeout--; 658 } 659 if (!timeout) { 660 DEBUGOUT("MNG configuration cycle has not completed.\n"); 661 return -E1000_ERR_RESET; 662 } 663 664 return E1000_SUCCESS; 665 } 666 667 /** 668 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 669 * @hw: pointer to the HW structure 670 * 671 * Force the speed and duplex settings onto the PHY. This is a 672 * function pointer entry point called by the phy module. 673 **/ 674 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 675 { 676 s32 ret_val; 677 u16 phy_data; 678 bool link; 679 680 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 681 682 if (!(hw->phy.ops.read_reg)) 683 return E1000_SUCCESS; 684 685 /* 686 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 687 * forced whenever speed and duplex are forced. 688 */ 689 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 690 if (ret_val) 691 return ret_val; 692 693 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 694 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 695 if (ret_val) 696 return ret_val; 697 698 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 699 700 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 701 if (ret_val) 702 return ret_val; 703 704 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 705 706 /* Reset the phy to commit changes. */ 707 phy_data |= MII_CR_RESET; 708 709 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 710 if (ret_val) 711 return ret_val; 712 713 usec_delay(1); 714 715 if (hw->phy.autoneg_wait_to_complete) { 716 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 717 718 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 719 100000, &link); 720 if (ret_val) 721 return ret_val; 722 723 if (!link) { 724 /* 725 * We didn't get link. 726 * Reset the DSP and cross our fingers. 727 */ 728 ret_val = e1000_phy_reset_dsp_generic(hw); 729 if (ret_val) 730 return ret_val; 731 } 732 733 /* Try once more */ 734 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 735 100000, &link); 736 if (ret_val) 737 return ret_val; 738 } 739 740 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 741 &phy_data); 742 if (ret_val) 743 return ret_val; 744 745 /* 746 * Resetting the phy means we need to verify the TX_CLK corresponds 747 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 748 */ 749 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 750 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 751 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 752 else 753 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 754 755 /* 756 * In addition, we must re-enable CRS on Tx for both half and full 757 * duplex. 758 */ 759 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 760 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 761 phy_data); 762 763 return ret_val; 764 } 765 766 /** 767 * e1000_get_cable_length_80003es2lan - Set approximate cable length 768 * @hw: pointer to the HW structure 769 * 770 * Find the approximate cable length as measured by the GG82563 PHY. 771 * This is a function pointer entry point called by the phy module. 772 **/ 773 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 774 { 775 struct e1000_phy_info *phy = &hw->phy; 776 s32 ret_val = E1000_SUCCESS; 777 u16 phy_data, index; 778 779 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 780 781 if (!(hw->phy.ops.read_reg)) 782 return E1000_SUCCESS; 783 784 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 785 if (ret_val) 786 return ret_val; 787 788 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 789 790 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 791 return -E1000_ERR_PHY; 792 793 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 794 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 795 796 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 797 798 return E1000_SUCCESS; 799 } 800 801 /** 802 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 803 * @hw: pointer to the HW structure 804 * @speed: pointer to speed buffer 805 * @duplex: pointer to duplex buffer 806 * 807 * Retrieve the current speed and duplex configuration. 808 **/ 809 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 810 u16 *duplex) 811 { 812 s32 ret_val; 813 814 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 815 816 if (hw->phy.media_type == e1000_media_type_copper) { 817 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 818 duplex); 819 hw->phy.ops.cfg_on_link_up(hw); 820 } else { 821 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 822 speed, 823 duplex); 824 } 825 826 return ret_val; 827 } 828 829 /** 830 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 831 * @hw: pointer to the HW structure 832 * 833 * Perform a global reset to the ESB2 controller. 834 **/ 835 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 836 { 837 u32 ctrl; 838 s32 ret_val; 839 u16 kum_reg_data; 840 841 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 842 843 /* 844 * Prevent the PCI-E bus from sticking if there is no TLP connection 845 * on the last TLP read/write transaction when MAC is reset. 846 */ 847 ret_val = e1000_disable_pcie_master_generic(hw); 848 if (ret_val) 849 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 850 851 DEBUGOUT("Masking off all interrupts\n"); 852 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 853 854 E1000_WRITE_REG(hw, E1000_RCTL, 0); 855 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 856 E1000_WRITE_FLUSH(hw); 857 858 msec_delay(10); 859 860 ctrl = E1000_READ_REG(hw, E1000_CTRL); 861 862 ret_val = e1000_acquire_phy_80003es2lan(hw); 863 DEBUGOUT("Issuing a global reset to MAC\n"); 864 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 865 e1000_release_phy_80003es2lan(hw); 866 867 /* Disable IBIST slave mode (far-end loopback) */ 868 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 869 &kum_reg_data); 870 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 871 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 872 kum_reg_data); 873 874 ret_val = e1000_get_auto_rd_done_generic(hw); 875 if (ret_val) 876 /* We don't want to continue accessing MAC registers. */ 877 return ret_val; 878 879 /* Clear any pending interrupt events. */ 880 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 881 E1000_READ_REG(hw, E1000_ICR); 882 883 return e1000_check_alt_mac_addr_generic(hw); 884 } 885 886 /** 887 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 888 * @hw: pointer to the HW structure 889 * 890 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 891 **/ 892 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 893 { 894 struct e1000_mac_info *mac = &hw->mac; 895 u32 reg_data; 896 s32 ret_val; 897 u16 kum_reg_data; 898 u16 i; 899 900 DEBUGFUNC("e1000_init_hw_80003es2lan"); 901 902 e1000_initialize_hw_bits_80003es2lan(hw); 903 904 /* Initialize identification LED */ 905 ret_val = mac->ops.id_led_init(hw); 906 if (ret_val) 907 DEBUGOUT("Error initializing identification LED\n"); 908 /* This is not fatal and we should not stop init due to this */ 909 910 /* Disabling VLAN filtering */ 911 DEBUGOUT("Initializing the IEEE VLAN\n"); 912 mac->ops.clear_vfta(hw); 913 914 /* Setup the receive address. */ 915 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 916 917 /* Zero out the Multicast HASH table */ 918 DEBUGOUT("Zeroing the MTA\n"); 919 for (i = 0; i < mac->mta_reg_count; i++) 920 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 921 922 /* Setup link and flow control */ 923 ret_val = mac->ops.setup_link(hw); 924 925 /* Disable IBIST slave mode (far-end loopback) */ 926 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 927 &kum_reg_data); 928 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 929 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 930 kum_reg_data); 931 932 /* Set the transmit descriptor write-back policy */ 933 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 934 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 935 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 936 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 937 938 /* ...for both queues. */ 939 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 940 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 941 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 942 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 943 944 /* Enable retransmit on late collisions */ 945 reg_data = E1000_READ_REG(hw, E1000_TCTL); 946 reg_data |= E1000_TCTL_RTLC; 947 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 948 949 /* Configure Gigabit Carry Extend Padding */ 950 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 951 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 952 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 953 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 954 955 /* Configure Transmit Inter-Packet Gap */ 956 reg_data = E1000_READ_REG(hw, E1000_TIPG); 957 reg_data &= ~E1000_TIPG_IPGT_MASK; 958 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 959 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 960 961 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 962 reg_data &= ~0x00100000; 963 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 964 965 /* default to TRUE to enable the MDIC W/A */ 966 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 967 968 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 969 E1000_KMRNCTRLSTA_OFFSET >> 970 E1000_KMRNCTRLSTA_OFFSET_SHIFT, 971 &i); 972 if (!ret_val) { 973 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 974 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 975 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 976 } 977 978 /* 979 * Clear all of the statistics registers (clear on read). It is 980 * important that we do this after we have tried to establish link 981 * because the symbol error count will increment wildly if there 982 * is no link. 983 */ 984 e1000_clear_hw_cntrs_80003es2lan(hw); 985 986 return ret_val; 987 } 988 989 /** 990 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 991 * @hw: pointer to the HW structure 992 * 993 * Initializes required hardware-dependent bits needed for normal operation. 994 **/ 995 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 996 { 997 u32 reg; 998 999 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 1000 1001 /* Transmit Descriptor Control 0 */ 1002 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1003 reg |= (1 << 22); 1004 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1005 1006 /* Transmit Descriptor Control 1 */ 1007 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1008 reg |= (1 << 22); 1009 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1010 1011 /* Transmit Arbitration Control 0 */ 1012 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1013 reg &= ~(0xF << 27); /* 30:27 */ 1014 if (hw->phy.media_type != e1000_media_type_copper) 1015 reg &= ~(1 << 20); 1016 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1017 1018 /* Transmit Arbitration Control 1 */ 1019 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1020 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1021 reg &= ~(1 << 28); 1022 else 1023 reg |= (1 << 28); 1024 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1025 1026 /* 1027 * Disable IPv6 extension header parsing because some malformed 1028 * IPv6 headers can hang the Rx. 1029 */ 1030 reg = E1000_READ_REG(hw, E1000_RFCTL); 1031 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1032 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1033 1034 return; 1035 } 1036 1037 /** 1038 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1039 * @hw: pointer to the HW structure 1040 * 1041 * Setup some GG82563 PHY registers for obtaining link 1042 **/ 1043 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1044 { 1045 struct e1000_phy_info *phy = &hw->phy; 1046 s32 ret_val; 1047 u32 ctrl_ext; 1048 u16 data; 1049 1050 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1051 1052 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1053 if (ret_val) 1054 return ret_val; 1055 1056 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1057 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1058 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1059 1060 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1061 if (ret_val) 1062 return ret_val; 1063 1064 /* 1065 * Options: 1066 * MDI/MDI-X = 0 (default) 1067 * 0 - Auto for all speeds 1068 * 1 - MDI mode 1069 * 2 - MDI-X mode 1070 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1071 */ 1072 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1073 if (ret_val) 1074 return ret_val; 1075 1076 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1077 1078 switch (phy->mdix) { 1079 case 1: 1080 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1081 break; 1082 case 2: 1083 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1084 break; 1085 case 0: 1086 default: 1087 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1088 break; 1089 } 1090 1091 /* 1092 * Options: 1093 * disable_polarity_correction = 0 (default) 1094 * Automatic Correction for Reversed Cable Polarity 1095 * 0 - Disabled 1096 * 1 - Enabled 1097 */ 1098 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1099 if (phy->disable_polarity_correction) 1100 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1101 1102 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1103 if (ret_val) 1104 return ret_val; 1105 1106 /* SW Reset the PHY so all changes take effect */ 1107 ret_val = hw->phy.ops.commit(hw); 1108 if (ret_val) { 1109 DEBUGOUT("Error Resetting the PHY\n"); 1110 return ret_val; 1111 } 1112 1113 /* Bypass Rx and Tx FIFO's */ 1114 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1115 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1116 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1117 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1118 if (ret_val) 1119 return ret_val; 1120 1121 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1122 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data); 1123 if (ret_val) 1124 return ret_val; 1125 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1126 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1127 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data); 1128 if (ret_val) 1129 return ret_val; 1130 1131 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1132 if (ret_val) 1133 return ret_val; 1134 1135 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1136 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1137 if (ret_val) 1138 return ret_val; 1139 1140 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1141 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1142 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1143 1144 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1145 if (ret_val) 1146 return ret_val; 1147 1148 /* 1149 * Do not init these registers when the HW is in IAMT mode, since the 1150 * firmware will have already initialized them. We only initialize 1151 * them if the HW is not in IAMT mode. 1152 */ 1153 if (!hw->mac.ops.check_mng_mode(hw)) { 1154 /* Enable Electrical Idle on the PHY */ 1155 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1156 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1157 data); 1158 if (ret_val) 1159 return ret_val; 1160 1161 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1162 &data); 1163 if (ret_val) 1164 return ret_val; 1165 1166 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1167 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1168 data); 1169 if (ret_val) 1170 return ret_val; 1171 } 1172 1173 /* 1174 * Workaround: Disable padding in Kumeran interface in the MAC 1175 * and in the PHY to avoid CRC errors. 1176 */ 1177 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1178 if (ret_val) 1179 return ret_val; 1180 1181 data |= GG82563_ICR_DIS_PADDING; 1182 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1183 if (ret_val) 1184 return ret_val; 1185 1186 return E1000_SUCCESS; 1187 } 1188 1189 /** 1190 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1191 * @hw: pointer to the HW structure 1192 * 1193 * Essentially a wrapper for setting up all things "copper" related. 1194 * This is a function pointer entry point called by the mac module. 1195 **/ 1196 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1197 { 1198 u32 ctrl; 1199 s32 ret_val; 1200 u16 reg_data; 1201 1202 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1203 1204 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1205 ctrl |= E1000_CTRL_SLU; 1206 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1207 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1208 1209 /* 1210 * Set the mac to wait the maximum time between each 1211 * iteration and increase the max iterations when 1212 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1213 */ 1214 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1215 0xFFFF); 1216 if (ret_val) 1217 return ret_val; 1218 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1219 ®_data); 1220 if (ret_val) 1221 return ret_val; 1222 reg_data |= 0x3F; 1223 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1224 reg_data); 1225 if (ret_val) 1226 return ret_val; 1227 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1228 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data); 1229 if (ret_val) 1230 return ret_val; 1231 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1232 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1233 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data); 1234 if (ret_val) 1235 return ret_val; 1236 1237 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1238 if (ret_val) 1239 return ret_val; 1240 1241 return e1000_setup_copper_link_generic(hw); 1242 } 1243 1244 /** 1245 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1246 * @hw: pointer to the HW structure 1247 * @duplex: current duplex setting 1248 * 1249 * Configure the KMRN interface by applying last minute quirks for 1250 * 10/100 operation. 1251 **/ 1252 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1253 { 1254 s32 ret_val = E1000_SUCCESS; 1255 u16 speed; 1256 u16 duplex; 1257 1258 DEBUGFUNC("e1000_configure_on_link_up"); 1259 1260 if (hw->phy.media_type == e1000_media_type_copper) { 1261 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1262 &duplex); 1263 if (ret_val) 1264 return ret_val; 1265 1266 if (speed == SPEED_1000) 1267 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1268 else 1269 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1270 } 1271 1272 return ret_val; 1273 } 1274 1275 /** 1276 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1277 * @hw: pointer to the HW structure 1278 * @duplex: current duplex setting 1279 * 1280 * Configure the KMRN interface by applying last minute quirks for 1281 * 10/100 operation. 1282 **/ 1283 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1284 { 1285 s32 ret_val; 1286 u32 tipg; 1287 u32 i = 0; 1288 u16 reg_data, reg_data2; 1289 1290 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1291 1292 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1293 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1294 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1295 reg_data); 1296 if (ret_val) 1297 return ret_val; 1298 1299 /* Configure Transmit Inter-Packet Gap */ 1300 tipg = E1000_READ_REG(hw, E1000_TIPG); 1301 tipg &= ~E1000_TIPG_IPGT_MASK; 1302 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1303 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1304 1305 do { 1306 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1307 ®_data); 1308 if (ret_val) 1309 return ret_val; 1310 1311 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1312 ®_data2); 1313 if (ret_val) 1314 return ret_val; 1315 i++; 1316 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1317 1318 if (duplex == HALF_DUPLEX) 1319 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1320 else 1321 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1322 1323 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1324 } 1325 1326 /** 1327 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1328 * @hw: pointer to the HW structure 1329 * 1330 * Configure the KMRN interface by applying last minute quirks for 1331 * gigabit operation. 1332 **/ 1333 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1334 { 1335 s32 ret_val; 1336 u16 reg_data, reg_data2; 1337 u32 tipg; 1338 u32 i = 0; 1339 1340 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1341 1342 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1343 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1344 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); 1345 if (ret_val) 1346 return ret_val; 1347 1348 /* Configure Transmit Inter-Packet Gap */ 1349 tipg = E1000_READ_REG(hw, E1000_TIPG); 1350 tipg &= ~E1000_TIPG_IPGT_MASK; 1351 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1352 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1353 1354 do { 1355 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1356 ®_data); 1357 if (ret_val) 1358 return ret_val; 1359 1360 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1361 ®_data2); 1362 if (ret_val) 1363 return ret_val; 1364 i++; 1365 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1366 1367 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1368 1369 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1370 } 1371 1372 /** 1373 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1374 * @hw: pointer to the HW structure 1375 * @offset: register offset to be read 1376 * @data: pointer to the read data 1377 * 1378 * Acquire semaphore, then read the PHY register at offset 1379 * using the kumeran interface. The information retrieved is stored in data. 1380 * Release the semaphore before exiting. 1381 **/ 1382 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1383 u16 *data) 1384 { 1385 u32 kmrnctrlsta; 1386 s32 ret_val = E1000_SUCCESS; 1387 1388 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1389 1390 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1391 if (ret_val) 1392 return ret_val; 1393 1394 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1395 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1396 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1397 E1000_WRITE_FLUSH(hw); 1398 1399 usec_delay(2); 1400 1401 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1402 *data = (u16)kmrnctrlsta; 1403 1404 e1000_release_mac_csr_80003es2lan(hw); 1405 1406 return ret_val; 1407 } 1408 1409 /** 1410 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1411 * @hw: pointer to the HW structure 1412 * @offset: register offset to write to 1413 * @data: data to write at register offset 1414 * 1415 * Acquire semaphore, then write the data to PHY register 1416 * at the offset using the kumeran interface. Release semaphore 1417 * before exiting. 1418 **/ 1419 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1420 u16 data) 1421 { 1422 u32 kmrnctrlsta; 1423 s32 ret_val = E1000_SUCCESS; 1424 1425 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1426 1427 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1428 if (ret_val) 1429 return ret_val; 1430 1431 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1432 E1000_KMRNCTRLSTA_OFFSET) | data; 1433 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1434 E1000_WRITE_FLUSH(hw); 1435 1436 usec_delay(2); 1437 1438 e1000_release_mac_csr_80003es2lan(hw); 1439 1440 return ret_val; 1441 } 1442 1443 /** 1444 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1445 * @hw: pointer to the HW structure 1446 **/ 1447 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1448 { 1449 s32 ret_val = E1000_SUCCESS; 1450 1451 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1452 1453 /* 1454 * If there's an alternate MAC address place it in RAR0 1455 * so that it will override the Si installed default perm 1456 * address. 1457 */ 1458 ret_val = e1000_check_alt_mac_addr_generic(hw); 1459 if (ret_val) 1460 return ret_val; 1461 1462 return e1000_read_mac_addr_generic(hw); 1463 } 1464 1465 /** 1466 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1467 * @hw: pointer to the HW structure 1468 * 1469 * In the case of a PHY power down to save power, or to turn off link during a 1470 * driver unload, or wake on lan is not enabled, remove the link. 1471 **/ 1472 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1473 { 1474 /* If the management interface is not enabled, then power down */ 1475 if (!(hw->mac.ops.check_mng_mode(hw) || 1476 hw->phy.ops.check_reset_block(hw))) 1477 e1000_power_down_phy_copper(hw); 1478 1479 return; 1480 } 1481 1482 /** 1483 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1484 * @hw: pointer to the HW structure 1485 * 1486 * Clears the hardware counters by reading the counter registers. 1487 **/ 1488 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1489 { 1490 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1491 1492 e1000_clear_hw_cntrs_base_generic(hw); 1493 1494 E1000_READ_REG(hw, E1000_PRC64); 1495 E1000_READ_REG(hw, E1000_PRC127); 1496 E1000_READ_REG(hw, E1000_PRC255); 1497 E1000_READ_REG(hw, E1000_PRC511); 1498 E1000_READ_REG(hw, E1000_PRC1023); 1499 E1000_READ_REG(hw, E1000_PRC1522); 1500 E1000_READ_REG(hw, E1000_PTC64); 1501 E1000_READ_REG(hw, E1000_PTC127); 1502 E1000_READ_REG(hw, E1000_PTC255); 1503 E1000_READ_REG(hw, E1000_PTC511); 1504 E1000_READ_REG(hw, E1000_PTC1023); 1505 E1000_READ_REG(hw, E1000_PTC1522); 1506 1507 E1000_READ_REG(hw, E1000_ALGNERRC); 1508 E1000_READ_REG(hw, E1000_RXERRC); 1509 E1000_READ_REG(hw, E1000_TNCRS); 1510 E1000_READ_REG(hw, E1000_CEXTERR); 1511 E1000_READ_REG(hw, E1000_TSCTC); 1512 E1000_READ_REG(hw, E1000_TSCTFC); 1513 1514 E1000_READ_REG(hw, E1000_MGTPRC); 1515 E1000_READ_REG(hw, E1000_MGTPDC); 1516 E1000_READ_REG(hw, E1000_MGTPTC); 1517 1518 E1000_READ_REG(hw, E1000_IAC); 1519 E1000_READ_REG(hw, E1000_ICRXOC); 1520 1521 E1000_READ_REG(hw, E1000_ICRXPTC); 1522 E1000_READ_REG(hw, E1000_ICRXATC); 1523 E1000_READ_REG(hw, E1000_ICTXPTC); 1524 E1000_READ_REG(hw, E1000_ICTXATC); 1525 E1000_READ_REG(hw, E1000_ICTXQEC); 1526 E1000_READ_REG(hw, E1000_ICTXQMTC); 1527 E1000_READ_REG(hw, E1000_ICRXDMTC); 1528 } 1529