1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.32 2005/05/31 08:27:47 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 170 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 176 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 180 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 185 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 186 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 187 { 0, -1, NULL }, 188 }; 189 190 static int fxp_probe(device_t dev); 191 static int fxp_attach(device_t dev); 192 static int fxp_detach(device_t dev); 193 static int fxp_shutdown(device_t dev); 194 static int fxp_suspend(device_t dev); 195 static int fxp_resume(device_t dev); 196 197 static void fxp_intr(void *xsc); 198 static void fxp_intr_body(struct fxp_softc *sc, 199 u_int8_t statack, int count); 200 201 static void fxp_init(void *xsc); 202 static void fxp_tick(void *xsc); 203 static void fxp_powerstate_d0(device_t dev); 204 static void fxp_start(struct ifnet *ifp); 205 static void fxp_stop(struct fxp_softc *sc); 206 static void fxp_release(device_t dev); 207 static int fxp_ioctl(struct ifnet *ifp, u_long command, 208 caddr_t data, struct ucred *); 209 static void fxp_watchdog(struct ifnet *ifp); 210 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 211 static int fxp_mc_addrs(struct fxp_softc *sc); 212 static void fxp_mc_setup(struct fxp_softc *sc); 213 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 214 int autosize); 215 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 216 u_int16_t data); 217 static void fxp_autosize_eeprom(struct fxp_softc *sc); 218 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 219 int offset, int words); 220 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 221 int offset, int words); 222 static int fxp_ifmedia_upd(struct ifnet *ifp); 223 static void fxp_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 226 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 227 struct ifmediareq *ifmr); 228 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 229 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 230 int value); 231 static void fxp_load_ucode(struct fxp_softc *sc); 232 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 233 int low, int high); 234 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 235 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 236 #ifdef DEVICE_POLLING 237 static poll_handler_t fxp_poll; 238 #endif 239 240 static void fxp_lwcopy(volatile u_int32_t *src, 241 volatile u_int32_t *dst); 242 static void fxp_scb_wait(struct fxp_softc *sc); 243 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 244 static void fxp_dma_wait(volatile u_int16_t *status, 245 struct fxp_softc *sc); 246 247 static device_method_t fxp_methods[] = { 248 /* Device interface */ 249 DEVMETHOD(device_probe, fxp_probe), 250 DEVMETHOD(device_attach, fxp_attach), 251 DEVMETHOD(device_detach, fxp_detach), 252 DEVMETHOD(device_shutdown, fxp_shutdown), 253 DEVMETHOD(device_suspend, fxp_suspend), 254 DEVMETHOD(device_resume, fxp_resume), 255 256 /* MII interface */ 257 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 258 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 259 260 { 0, 0 } 261 }; 262 263 static driver_t fxp_driver = { 264 "fxp", 265 fxp_methods, 266 sizeof(struct fxp_softc), 267 }; 268 269 static devclass_t fxp_devclass; 270 271 DECLARE_DUMMY_MODULE(if_fxp); 272 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 273 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 274 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 275 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 276 277 static int fxp_rnr; 278 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 279 280 /* 281 * Copy a 16-bit aligned 32-bit quantity. 282 */ 283 static void 284 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 285 { 286 #ifdef __i386__ 287 *dst = *src; 288 #else 289 volatile u_int16_t *a = (volatile u_int16_t *)src; 290 volatile u_int16_t *b = (volatile u_int16_t *)dst; 291 292 b[0] = a[0]; 293 b[1] = a[1]; 294 #endif 295 } 296 297 /* 298 * Wait for the previous command to be accepted (but not necessarily 299 * completed). 300 */ 301 static void 302 fxp_scb_wait(struct fxp_softc *sc) 303 { 304 int i = 10000; 305 306 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 307 DELAY(2); 308 if (i == 0) { 309 if_printf(&sc->arpcom.ac_if, 310 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 311 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 312 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 313 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 314 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 315 } 316 } 317 318 static void 319 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 320 { 321 322 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 323 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 324 fxp_scb_wait(sc); 325 } 326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 327 } 328 329 static void 330 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 331 { 332 int i = 10000; 333 334 while (!(*status & FXP_CB_STATUS_C) && --i) 335 DELAY(2); 336 if (i == 0) 337 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 338 } 339 340 /* 341 * Return identification string if this is device is ours. 342 */ 343 static int 344 fxp_probe(device_t dev) 345 { 346 u_int16_t devid; 347 u_int8_t revid; 348 struct fxp_ident *ident; 349 350 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 351 devid = pci_get_device(dev); 352 revid = pci_get_revid(dev); 353 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 354 if (ident->devid == devid && 355 (ident->revid == revid || ident->revid == -1)) { 356 device_set_desc(dev, ident->name); 357 return (0); 358 } 359 } 360 } 361 return (ENXIO); 362 } 363 364 static void 365 fxp_powerstate_d0(device_t dev) 366 { 367 u_int32_t iobase, membase, irq; 368 369 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 370 /* Save important PCI config data. */ 371 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 372 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 373 irq = pci_read_config(dev, PCIR_INTLINE, 4); 374 375 /* Reset the power state. */ 376 device_printf(dev, "chip is in D%d power mode " 377 "-- setting to D0\n", pci_get_powerstate(dev)); 378 379 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 380 381 /* Restore PCI config data. */ 382 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 383 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 384 pci_write_config(dev, PCIR_INTLINE, irq, 4); 385 } 386 } 387 388 static int 389 fxp_attach(device_t dev) 390 { 391 int error = 0; 392 struct fxp_softc *sc = device_get_softc(dev); 393 struct ifnet *ifp; 394 u_int32_t val; 395 u_int16_t data; 396 int i, rid, m1, m2, prefer_iomap; 397 int s; 398 399 bzero(sc, sizeof(*sc)); 400 callout_init(&sc->fxp_stat_timer); 401 sysctl_ctx_init(&sc->sysctl_ctx); 402 403 s = splimp(); 404 405 /* 406 * Enable bus mastering. Enable memory space too, in case 407 * BIOS/Prom forgot about it. 408 */ 409 pci_enable_busmaster(dev); 410 pci_enable_io(dev, SYS_RES_MEMORY); 411 val = pci_read_config(dev, PCIR_COMMAND, 2); 412 413 fxp_powerstate_d0(dev); 414 415 /* 416 * Figure out which we should try first - memory mapping or i/o mapping? 417 * We default to memory mapping. Then we accept an override from the 418 * command line. Then we check to see which one is enabled. 419 */ 420 m1 = PCIM_CMD_MEMEN; 421 m2 = PCIM_CMD_PORTEN; 422 prefer_iomap = 0; 423 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 424 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 425 m1 = PCIM_CMD_PORTEN; 426 m2 = PCIM_CMD_MEMEN; 427 } 428 429 if (val & m1) { 430 sc->rtp = 431 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 432 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 433 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 434 RF_ACTIVE); 435 } 436 if (sc->mem == NULL && (val & m2)) { 437 sc->rtp = 438 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 439 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 440 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 441 RF_ACTIVE); 442 } 443 444 if (!sc->mem) { 445 device_printf(dev, "could not map device registers\n"); 446 error = ENXIO; 447 goto fail; 448 } 449 if (bootverbose) { 450 device_printf(dev, "using %s space register mapping\n", 451 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 452 } 453 454 sc->sc_st = rman_get_bustag(sc->mem); 455 sc->sc_sh = rman_get_bushandle(sc->mem); 456 457 /* 458 * Allocate our interrupt. 459 */ 460 rid = 0; 461 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 462 RF_SHAREABLE | RF_ACTIVE); 463 if (sc->irq == NULL) { 464 device_printf(dev, "could not map interrupt\n"); 465 error = ENXIO; 466 goto fail; 467 } 468 469 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 470 fxp_intr, sc, &sc->ih, NULL); 471 if (error) { 472 device_printf(dev, "could not setup irq\n"); 473 goto fail; 474 } 475 476 /* 477 * Reset to a stable state. 478 */ 479 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 480 DELAY(10); 481 482 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 483 M_DEVBUF, M_WAITOK | M_ZERO); 484 485 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 486 M_WAITOK | M_ZERO); 487 488 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 489 490 /* 491 * Pre-allocate our receive buffers. 492 */ 493 for (i = 0; i < FXP_NRFABUFS; i++) { 494 if (fxp_add_rfabuf(sc, NULL) != 0) { 495 goto failmem; 496 } 497 } 498 499 /* 500 * Find out how large of an SEEPROM we have. 501 */ 502 fxp_autosize_eeprom(sc); 503 504 /* 505 * Determine whether we must use the 503 serial interface. 506 */ 507 fxp_read_eeprom(sc, &data, 6, 1); 508 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 509 (data & FXP_PHY_SERIAL_ONLY)) 510 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 511 512 /* 513 * Create the sysctl tree 514 */ 515 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 516 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 517 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 518 if (sc->sysctl_tree == NULL) 519 goto fail; 520 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 521 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 522 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 523 "FXP driver receive interrupt microcode bundling delay"); 524 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 525 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 526 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 527 "FXP driver receive interrupt microcode bundle size limit"); 528 529 /* 530 * Pull in device tunables. 531 */ 532 sc->tunable_int_delay = TUNABLE_INT_DELAY; 533 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 534 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 535 "int_delay", &sc->tunable_int_delay); 536 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 537 "bundle_max", &sc->tunable_bundle_max); 538 539 /* 540 * Find out the chip revision; lump all 82557 revs together. 541 */ 542 fxp_read_eeprom(sc, &data, 5, 1); 543 if ((data >> 8) == 1) 544 sc->revision = FXP_REV_82557; 545 else 546 sc->revision = pci_get_revid(dev); 547 548 /* 549 * Enable workarounds for certain chip revision deficiencies. 550 * 551 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 552 * some systems based a normal 82559 design, have a defect where 553 * the chip can cause a PCI protocol violation if it receives 554 * a CU_RESUME command when it is entering the IDLE state. The 555 * workaround is to disable Dynamic Standby Mode, so the chip never 556 * deasserts CLKRUN#, and always remains in an active state. 557 * 558 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 559 */ 560 i = pci_get_device(dev); 561 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 562 sc->revision >= FXP_REV_82559_A0) { 563 fxp_read_eeprom(sc, &data, 10, 1); 564 if (data & 0x02) { /* STB enable */ 565 u_int16_t cksum; 566 int i; 567 568 device_printf(dev, 569 "Disabling dynamic standby mode in EEPROM\n"); 570 data &= ~0x02; 571 fxp_write_eeprom(sc, &data, 10, 1); 572 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 573 cksum = 0; 574 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 575 fxp_read_eeprom(sc, &data, i, 1); 576 cksum += data; 577 } 578 i = (1 << sc->eeprom_size) - 1; 579 cksum = 0xBABA - cksum; 580 fxp_read_eeprom(sc, &data, i, 1); 581 fxp_write_eeprom(sc, &cksum, i, 1); 582 device_printf(dev, 583 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 584 i, data, cksum); 585 #if 1 586 /* 587 * If the user elects to continue, try the software 588 * workaround, as it is better than nothing. 589 */ 590 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 591 #endif 592 } 593 } 594 595 /* 596 * If we are not a 82557 chip, we can enable extended features. 597 */ 598 if (sc->revision != FXP_REV_82557) { 599 /* 600 * If MWI is enabled in the PCI configuration, and there 601 * is a valid cacheline size (8 or 16 dwords), then tell 602 * the board to turn on MWI. 603 */ 604 if (val & PCIM_CMD_MWRICEN && 605 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 606 sc->flags |= FXP_FLAG_MWI_ENABLE; 607 608 /* turn on the extended TxCB feature */ 609 sc->flags |= FXP_FLAG_EXT_TXCB; 610 611 /* enable reception of long frames for VLAN */ 612 sc->flags |= FXP_FLAG_LONG_PKT_EN; 613 } 614 615 /* 616 * Read MAC address. 617 */ 618 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 619 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 620 device_printf(dev, "10Mbps\n"); 621 if (bootverbose) { 622 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 623 pci_get_vendor(dev), pci_get_device(dev), 624 pci_get_subvendor(dev), pci_get_subdevice(dev), 625 pci_get_revid(dev)); 626 fxp_read_eeprom(sc, &data, 10, 1); 627 device_printf(dev, "Dynamic Standby mode is %s\n", 628 data & 0x02 ? "enabled" : "disabled"); 629 } 630 631 /* 632 * If this is only a 10Mbps device, then there is no MII, and 633 * the PHY will use a serial interface instead. 634 * 635 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 636 * doesn't have a programming interface of any sort. The 637 * media is sensed automatically based on how the link partner 638 * is configured. This is, in essence, manual configuration. 639 */ 640 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 641 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 642 fxp_serial_ifmedia_sts); 643 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 644 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 645 } else { 646 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 647 fxp_ifmedia_sts)) { 648 device_printf(dev, "MII without any PHY!\n"); 649 error = ENXIO; 650 goto fail; 651 } 652 } 653 654 ifp = &sc->arpcom.ac_if; 655 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 656 ifp->if_baudrate = 100000000; 657 ifp->if_init = fxp_init; 658 ifp->if_softc = sc; 659 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 660 ifp->if_ioctl = fxp_ioctl; 661 ifp->if_start = fxp_start; 662 #ifdef DEVICE_POLLING 663 ifp->if_poll = fxp_poll; 664 #endif 665 ifp->if_watchdog = fxp_watchdog; 666 667 /* 668 * Attach the interface. 669 */ 670 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 671 672 /* 673 * Tell the upper layer(s) we support long frames. 674 */ 675 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 676 677 /* 678 * Let the system queue as many packets as we have available 679 * TX descriptors. 680 */ 681 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 682 ifq_set_ready(&ifp->if_snd); 683 684 splx(s); 685 return (0); 686 687 failmem: 688 device_printf(dev, "Failed to malloc memory\n"); 689 error = ENOMEM; 690 fail: 691 splx(s); 692 fxp_release(dev); 693 return (error); 694 } 695 696 /* 697 * release all resources 698 */ 699 static void 700 fxp_release(device_t dev) 701 { 702 struct fxp_softc *sc; 703 704 sc = device_get_softc(dev); 705 bus_generic_detach(dev); 706 if (sc->miibus) 707 device_delete_child(dev, sc->miibus); 708 709 if (sc->cbl_base) 710 free(sc->cbl_base, M_DEVBUF); 711 if (sc->fxp_stats) 712 free(sc->fxp_stats, M_DEVBUF); 713 if (sc->mcsp) 714 free(sc->mcsp, M_DEVBUF); 715 if (sc->rfa_headm) 716 m_freem(sc->rfa_headm); 717 718 if (sc->ih) 719 bus_teardown_intr(dev, sc->irq, sc->ih); 720 if (sc->irq) 721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 722 if (sc->mem) 723 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 724 725 sysctl_ctx_free(&sc->sysctl_ctx); 726 } 727 728 /* 729 * Detach interface. 730 */ 731 static int 732 fxp_detach(device_t dev) 733 { 734 struct fxp_softc *sc = device_get_softc(dev); 735 int s; 736 737 /* disable interrupts */ 738 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 739 740 s = splimp(); 741 742 /* 743 * Stop DMA and drop transmit queue. 744 */ 745 fxp_stop(sc); 746 747 /* 748 * Close down routes etc. 749 */ 750 ether_ifdetach(&sc->arpcom.ac_if); 751 752 /* 753 * Free all media structures. 754 */ 755 ifmedia_removeall(&sc->sc_media); 756 757 splx(s); 758 759 /* Release our allocated resources. */ 760 fxp_release(dev); 761 762 return (0); 763 } 764 765 /* 766 * Device shutdown routine. Called at system shutdown after sync. The 767 * main purpose of this routine is to shut off receiver DMA so that 768 * kernel memory doesn't get clobbered during warmboot. 769 */ 770 static int 771 fxp_shutdown(device_t dev) 772 { 773 /* 774 * Make sure that DMA is disabled prior to reboot. Not doing 775 * do could allow DMA to corrupt kernel memory during the 776 * reboot before the driver initializes. 777 */ 778 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 779 return (0); 780 } 781 782 /* 783 * Device suspend routine. Stop the interface and save some PCI 784 * settings in case the BIOS doesn't restore them properly on 785 * resume. 786 */ 787 static int 788 fxp_suspend(device_t dev) 789 { 790 struct fxp_softc *sc = device_get_softc(dev); 791 int i, s; 792 793 s = splimp(); 794 795 fxp_stop(sc); 796 797 for (i = 0; i < 5; i++) 798 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 799 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 800 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 801 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 802 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 803 804 sc->suspended = 1; 805 806 splx(s); 807 return (0); 808 } 809 810 /* 811 * Device resume routine. Restore some PCI settings in case the BIOS 812 * doesn't, re-enable busmastering, and restart the interface if 813 * appropriate. 814 */ 815 static int 816 fxp_resume(device_t dev) 817 { 818 struct fxp_softc *sc = device_get_softc(dev); 819 struct ifnet *ifp = &sc->arpcom.ac_if; 820 int i, s; 821 822 s = splimp(); 823 824 fxp_powerstate_d0(dev); 825 826 /* better way to do this? */ 827 for (i = 0; i < 5; i++) 828 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 829 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 830 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 831 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 832 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 833 834 /* reenable busmastering and memory space */ 835 pci_enable_busmaster(dev); 836 pci_enable_io(dev, SYS_RES_MEMORY); 837 838 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 839 DELAY(10); 840 841 /* reinitialize interface if necessary */ 842 if (ifp->if_flags & IFF_UP) 843 fxp_init(sc); 844 845 sc->suspended = 0; 846 847 splx(s); 848 return (0); 849 } 850 851 static void 852 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 853 { 854 u_int16_t reg; 855 int x; 856 857 /* 858 * Shift in data. 859 */ 860 for (x = 1 << (length - 1); x; x >>= 1) { 861 if (data & x) 862 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 863 else 864 reg = FXP_EEPROM_EECS; 865 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 866 DELAY(1); 867 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 868 DELAY(1); 869 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 870 DELAY(1); 871 } 872 } 873 874 /* 875 * Read from the serial EEPROM. Basically, you manually shift in 876 * the read opcode (one bit at a time) and then shift in the address, 877 * and then you shift out the data (all of this one bit at a time). 878 * The word size is 16 bits, so you have to provide the address for 879 * every 16 bits of data. 880 */ 881 static u_int16_t 882 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 883 { 884 u_int16_t reg, data; 885 int x; 886 887 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 888 /* 889 * Shift in read opcode. 890 */ 891 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 892 /* 893 * Shift in address. 894 */ 895 data = 0; 896 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 897 if (offset & x) 898 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 899 else 900 reg = FXP_EEPROM_EECS; 901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 902 DELAY(1); 903 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 904 DELAY(1); 905 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 906 DELAY(1); 907 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 908 data++; 909 if (autosize && reg == 0) { 910 sc->eeprom_size = data; 911 break; 912 } 913 } 914 /* 915 * Shift out data. 916 */ 917 data = 0; 918 reg = FXP_EEPROM_EECS; 919 for (x = 1 << 15; x; x >>= 1) { 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 921 DELAY(1); 922 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 923 data |= x; 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 925 DELAY(1); 926 } 927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 928 DELAY(1); 929 930 return (data); 931 } 932 933 static void 934 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 935 { 936 int i; 937 938 /* 939 * Erase/write enable. 940 */ 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 942 fxp_eeprom_shiftin(sc, 0x4, 3); 943 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 945 DELAY(1); 946 /* 947 * Shift in write opcode, address, data. 948 */ 949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 950 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 951 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 952 fxp_eeprom_shiftin(sc, data, 16); 953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 954 DELAY(1); 955 /* 956 * Wait for EEPROM to finish up. 957 */ 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 959 DELAY(1); 960 for (i = 0; i < 1000; i++) { 961 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 962 break; 963 DELAY(50); 964 } 965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 966 DELAY(1); 967 /* 968 * Erase/write disable. 969 */ 970 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 971 fxp_eeprom_shiftin(sc, 0x4, 3); 972 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 973 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 974 DELAY(1); 975 } 976 977 /* 978 * From NetBSD: 979 * 980 * Figure out EEPROM size. 981 * 982 * 559's can have either 64-word or 256-word EEPROMs, the 558 983 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 984 * talks about the existance of 16 to 256 word EEPROMs. 985 * 986 * The only known sizes are 64 and 256, where the 256 version is used 987 * by CardBus cards to store CIS information. 988 * 989 * The address is shifted in msb-to-lsb, and after the last 990 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 991 * after which follows the actual data. We try to detect this zero, by 992 * probing the data-out bit in the EEPROM control register just after 993 * having shifted in a bit. If the bit is zero, we assume we've 994 * shifted enough address bits. The data-out should be tri-state, 995 * before this, which should translate to a logical one. 996 */ 997 static void 998 fxp_autosize_eeprom(struct fxp_softc *sc) 999 { 1000 1001 /* guess maximum size of 256 words */ 1002 sc->eeprom_size = 8; 1003 1004 /* autosize */ 1005 (void) fxp_eeprom_getword(sc, 0, 1); 1006 } 1007 1008 static void 1009 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1010 { 1011 int i; 1012 1013 for (i = 0; i < words; i++) 1014 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1015 } 1016 1017 static void 1018 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1019 { 1020 int i; 1021 1022 for (i = 0; i < words; i++) 1023 fxp_eeprom_putword(sc, offset + i, data[i]); 1024 } 1025 1026 /* 1027 * Start packet transmission on the interface. 1028 */ 1029 static void 1030 fxp_start(struct ifnet *ifp) 1031 { 1032 struct fxp_softc *sc = ifp->if_softc; 1033 struct fxp_cb_tx *txp; 1034 1035 /* 1036 * See if we need to suspend xmit until the multicast filter 1037 * has been reprogrammed (which can only be done at the head 1038 * of the command chain). 1039 */ 1040 if (sc->need_mcsetup) { 1041 return; 1042 } 1043 1044 txp = NULL; 1045 1046 /* 1047 * We're finished if there is nothing more to add to the list or if 1048 * we're all filled up with buffers to transmit. 1049 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1050 * a NOP command when needed. 1051 */ 1052 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1053 struct mbuf *m, *mb_head; 1054 int segment, ntries = 0; 1055 1056 /* 1057 * Grab a packet to transmit. The packet is dequeued, 1058 * once we are sure that we have enough free descriptors. 1059 */ 1060 mb_head = ifq_poll(&ifp->if_snd); 1061 if (mb_head == NULL) 1062 break; 1063 1064 /* 1065 * Get pointer to next available tx desc. 1066 */ 1067 txp = sc->cbl_last->next; 1068 1069 /* 1070 * Go through each of the mbufs in the chain and initialize 1071 * the transmit buffer descriptors with the physical address 1072 * and size of the mbuf. 1073 */ 1074 tbdinit: 1075 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1076 if (m->m_len != 0) { 1077 if (segment == FXP_NTXSEG) 1078 break; 1079 txp->tbd[segment].tb_addr = 1080 vtophys(mtod(m, vm_offset_t)); 1081 txp->tbd[segment].tb_size = m->m_len; 1082 segment++; 1083 } 1084 } 1085 if (m != NULL) { 1086 struct mbuf *mn; 1087 1088 /* 1089 * We ran out of segments. We have to recopy this 1090 * mbuf chain first. Bail out if we can't get the 1091 * new buffers. 1092 */ 1093 if (ntries > 0) 1094 break; 1095 mn = m_dup(mb_head, MB_DONTWAIT); 1096 if (mn == NULL) 1097 break; 1098 /* We can transmit the packet, dequeue it. */ 1099 mb_head = ifq_dequeue(&ifp->if_snd); 1100 m_freem(mb_head); 1101 mb_head = mn; 1102 ntries = 1; 1103 goto tbdinit; 1104 } else { 1105 /* Nothing to worry about, just dequeue. */ 1106 mb_head = ifq_dequeue(&ifp->if_snd); 1107 } 1108 1109 txp->tbd_number = segment; 1110 txp->mb_head = mb_head; 1111 txp->cb_status = 0; 1112 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1113 txp->cb_command = 1114 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1115 FXP_CB_COMMAND_S; 1116 } else { 1117 txp->cb_command = 1118 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1119 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1120 /* 1121 * Set a 5 second timer just in case we don't hear 1122 * from the card again. 1123 */ 1124 ifp->if_timer = 5; 1125 } 1126 txp->tx_threshold = tx_threshold; 1127 1128 /* 1129 * Advance the end of list forward. 1130 */ 1131 1132 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1133 sc->cbl_last = txp; 1134 1135 /* 1136 * Advance the beginning of the list forward if there are 1137 * no other packets queued (when nothing is queued, cbl_first 1138 * sits on the last TxCB that was sent out). 1139 */ 1140 if (sc->tx_queued == 0) 1141 sc->cbl_first = txp; 1142 1143 sc->tx_queued++; 1144 1145 BPF_MTAP(ifp, mb_head); 1146 } 1147 1148 /* 1149 * We're finished. If we added to the list, issue a RESUME to get DMA 1150 * going again if suspended. 1151 */ 1152 if (txp != NULL) { 1153 fxp_scb_wait(sc); 1154 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1155 } 1156 } 1157 1158 #ifdef DEVICE_POLLING 1159 1160 static void 1161 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162 { 1163 struct fxp_softc *sc = ifp->if_softc; 1164 u_int8_t statack; 1165 1166 switch(cmd) { 1167 case POLL_REGISTER: 1168 /* disable interrupts */ 1169 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1170 break; 1171 case POLL_DEREGISTER: 1172 /* enable interrupts */ 1173 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1174 break; 1175 default: 1176 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1177 FXP_SCB_STATACK_FR; 1178 if (cmd == POLL_AND_CHECK_STATUS) { 1179 u_int8_t tmp; 1180 1181 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1182 if (tmp == 0xff || tmp == 0) 1183 return; /* nothing to do */ 1184 tmp &= ~statack; 1185 /* ack what we can */ 1186 if (tmp != 0) 1187 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1188 statack |= tmp; 1189 } 1190 fxp_intr_body(sc, statack, count); 1191 break; 1192 } 1193 } 1194 1195 #endif /* DEVICE_POLLING */ 1196 1197 /* 1198 * Process interface interrupts. 1199 */ 1200 static void 1201 fxp_intr(void *xsc) 1202 { 1203 struct fxp_softc *sc = xsc; 1204 u_int8_t statack; 1205 1206 if (sc->suspended) { 1207 return; 1208 } 1209 1210 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1211 /* 1212 * It should not be possible to have all bits set; the 1213 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1214 * all bits are set, this may indicate that the card has 1215 * been physically ejected, so ignore it. 1216 */ 1217 if (statack == 0xff) 1218 return; 1219 1220 /* 1221 * First ACK all the interrupts in this pass. 1222 */ 1223 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1224 fxp_intr_body(sc, statack, -1); 1225 } 1226 } 1227 1228 static void 1229 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1230 { 1231 struct ifnet *ifp = &sc->arpcom.ac_if; 1232 struct mbuf *m; 1233 struct fxp_rfa *rfa; 1234 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1235 1236 if (rnr) 1237 fxp_rnr++; 1238 #ifdef DEVICE_POLLING 1239 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1240 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1241 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1242 rnr = 1; 1243 } 1244 #endif 1245 1246 /* 1247 * Free any finished transmit mbuf chains. 1248 * 1249 * Handle the CNA event likt a CXTNO event. It used to 1250 * be that this event (control unit not ready) was not 1251 * encountered, but it is now with the SMPng modifications. 1252 * The exact sequence of events that occur when the interface 1253 * is brought up are different now, and if this event 1254 * goes unhandled, the configuration/rxfilter setup sequence 1255 * can stall for several seconds. The result is that no 1256 * packets go out onto the wire for about 5 to 10 seconds 1257 * after the interface is ifconfig'ed for the first time. 1258 */ 1259 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1260 struct fxp_cb_tx *txp; 1261 1262 for (txp = sc->cbl_first; sc->tx_queued && 1263 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1264 txp = txp->next) { 1265 if ((m = txp->mb_head) != NULL) { 1266 txp->mb_head = NULL; 1267 sc->tx_queued--; 1268 m_freem(m); 1269 } else { 1270 sc->tx_queued--; 1271 } 1272 } 1273 sc->cbl_first = txp; 1274 ifp->if_timer = 0; 1275 if (sc->tx_queued == 0) { 1276 if (sc->need_mcsetup) 1277 fxp_mc_setup(sc); 1278 } 1279 /* 1280 * Try to start more packets transmitting. 1281 */ 1282 if (!ifq_is_empty(&ifp->if_snd)) 1283 (*ifp->if_start)(ifp); 1284 } 1285 1286 /* 1287 * Just return if nothing happened on the receive side. 1288 */ 1289 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1290 return; 1291 1292 /* 1293 * Process receiver interrupts. If a no-resource (RNR) 1294 * condition exists, get whatever packets we can and 1295 * re-start the receiver. 1296 * 1297 * When using polling, we do not process the list to completion, 1298 * so when we get an RNR interrupt we must defer the restart 1299 * until we hit the last buffer with the C bit set. 1300 * If we run out of cycles and rfa_headm has the C bit set, 1301 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1302 * that the info will be used in the subsequent polling cycle. 1303 */ 1304 for (;;) { 1305 m = sc->rfa_headm; 1306 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1307 RFA_ALIGNMENT_FUDGE); 1308 1309 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1310 if (count >= 0 && count-- == 0) { 1311 if (rnr) { 1312 /* Defer RNR processing until the next time. */ 1313 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1314 rnr = 0; 1315 } 1316 break; 1317 } 1318 #endif /* DEVICE_POLLING */ 1319 1320 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1321 break; 1322 1323 /* 1324 * Remove first packet from the chain. 1325 */ 1326 sc->rfa_headm = m->m_next; 1327 m->m_next = NULL; 1328 1329 /* 1330 * Add a new buffer to the receive chain. 1331 * If this fails, the old buffer is recycled 1332 * instead. 1333 */ 1334 if (fxp_add_rfabuf(sc, m) == 0) { 1335 int total_len; 1336 1337 /* 1338 * Fetch packet length (the top 2 bits of 1339 * actual_size are flags set by the controller 1340 * upon completion), and drop the packet in case 1341 * of bogus length or CRC errors. 1342 */ 1343 total_len = rfa->actual_size & 0x3fff; 1344 if (total_len < sizeof(struct ether_header) || 1345 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1346 sizeof(struct fxp_rfa) || 1347 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1348 m_freem(m); 1349 continue; 1350 } 1351 m->m_pkthdr.len = m->m_len = total_len; 1352 (*ifp->if_input)(ifp, m); 1353 } 1354 } 1355 if (rnr) { 1356 fxp_scb_wait(sc); 1357 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1358 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1359 RFA_ALIGNMENT_FUDGE); 1360 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1361 } 1362 } 1363 1364 /* 1365 * Update packet in/out/collision statistics. The i82557 doesn't 1366 * allow you to access these counters without doing a fairly 1367 * expensive DMA to get _all_ of the statistics it maintains, so 1368 * we do this operation here only once per second. The statistics 1369 * counters in the kernel are updated from the previous dump-stats 1370 * DMA and then a new dump-stats DMA is started. The on-chip 1371 * counters are zeroed when the DMA completes. If we can't start 1372 * the DMA immediately, we don't wait - we just prepare to read 1373 * them again next time. 1374 */ 1375 static void 1376 fxp_tick(void *xsc) 1377 { 1378 struct fxp_softc *sc = xsc; 1379 struct ifnet *ifp = &sc->arpcom.ac_if; 1380 struct fxp_stats *sp = sc->fxp_stats; 1381 struct fxp_cb_tx *txp; 1382 struct mbuf *m; 1383 int s; 1384 1385 ifp->if_opackets += sp->tx_good; 1386 ifp->if_collisions += sp->tx_total_collisions; 1387 if (sp->rx_good) { 1388 ifp->if_ipackets += sp->rx_good; 1389 sc->rx_idle_secs = 0; 1390 } else { 1391 /* 1392 * Receiver's been idle for another second. 1393 */ 1394 sc->rx_idle_secs++; 1395 } 1396 ifp->if_ierrors += 1397 sp->rx_crc_errors + 1398 sp->rx_alignment_errors + 1399 sp->rx_rnr_errors + 1400 sp->rx_overrun_errors; 1401 /* 1402 * If any transmit underruns occured, bump up the transmit 1403 * threshold by another 512 bytes (64 * 8). 1404 */ 1405 if (sp->tx_underruns) { 1406 ifp->if_oerrors += sp->tx_underruns; 1407 if (tx_threshold < 192) 1408 tx_threshold += 64; 1409 } 1410 s = splimp(); 1411 /* 1412 * Release any xmit buffers that have completed DMA. This isn't 1413 * strictly necessary to do here, but it's advantagous for mbufs 1414 * with external storage to be released in a timely manner rather 1415 * than being defered for a potentially long time. This limits 1416 * the delay to a maximum of one second. 1417 */ 1418 for (txp = sc->cbl_first; sc->tx_queued && 1419 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1420 txp = txp->next) { 1421 if ((m = txp->mb_head) != NULL) { 1422 txp->mb_head = NULL; 1423 sc->tx_queued--; 1424 m_freem(m); 1425 } else { 1426 sc->tx_queued--; 1427 } 1428 } 1429 sc->cbl_first = txp; 1430 /* 1431 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1432 * then assume the receiver has locked up and attempt to clear 1433 * the condition by reprogramming the multicast filter. This is 1434 * a work-around for a bug in the 82557 where the receiver locks 1435 * up if it gets certain types of garbage in the syncronization 1436 * bits prior to the packet header. This bug is supposed to only 1437 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1438 * mode as well (perhaps due to a 10/100 speed transition). 1439 */ 1440 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1441 sc->rx_idle_secs = 0; 1442 fxp_mc_setup(sc); 1443 } 1444 /* 1445 * If there is no pending command, start another stats 1446 * dump. Otherwise punt for now. 1447 */ 1448 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1449 /* 1450 * Start another stats dump. 1451 */ 1452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1453 } else { 1454 /* 1455 * A previous command is still waiting to be accepted. 1456 * Just zero our copy of the stats and wait for the 1457 * next timer event to update them. 1458 */ 1459 sp->tx_good = 0; 1460 sp->tx_underruns = 0; 1461 sp->tx_total_collisions = 0; 1462 1463 sp->rx_good = 0; 1464 sp->rx_crc_errors = 0; 1465 sp->rx_alignment_errors = 0; 1466 sp->rx_rnr_errors = 0; 1467 sp->rx_overrun_errors = 0; 1468 } 1469 if (sc->miibus != NULL) 1470 mii_tick(device_get_softc(sc->miibus)); 1471 splx(s); 1472 /* 1473 * Schedule another timeout one second from now. 1474 */ 1475 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1476 } 1477 1478 /* 1479 * Stop the interface. Cancels the statistics updater and resets 1480 * the interface. 1481 */ 1482 static void 1483 fxp_stop(struct fxp_softc *sc) 1484 { 1485 struct ifnet *ifp = &sc->arpcom.ac_if; 1486 struct fxp_cb_tx *txp; 1487 int i; 1488 1489 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1490 ifp->if_timer = 0; 1491 1492 /* 1493 * Cancel stats updater. 1494 */ 1495 callout_stop(&sc->fxp_stat_timer); 1496 1497 /* 1498 * Issue software reset, which also unloads the microcode. 1499 */ 1500 sc->flags &= ~FXP_FLAG_UCODE; 1501 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1502 DELAY(50); 1503 1504 /* 1505 * Release any xmit buffers. 1506 */ 1507 txp = sc->cbl_base; 1508 if (txp != NULL) { 1509 for (i = 0; i < FXP_NTXCB; i++) { 1510 if (txp[i].mb_head != NULL) { 1511 m_freem(txp[i].mb_head); 1512 txp[i].mb_head = NULL; 1513 } 1514 } 1515 } 1516 sc->tx_queued = 0; 1517 1518 /* 1519 * Free all the receive buffers then reallocate/reinitialize 1520 */ 1521 if (sc->rfa_headm != NULL) 1522 m_freem(sc->rfa_headm); 1523 sc->rfa_headm = NULL; 1524 sc->rfa_tailm = NULL; 1525 for (i = 0; i < FXP_NRFABUFS; i++) { 1526 if (fxp_add_rfabuf(sc, NULL) != 0) { 1527 /* 1528 * This "can't happen" - we're at splimp() 1529 * and we just freed all the buffers we need 1530 * above. 1531 */ 1532 panic("fxp_stop: no buffers!"); 1533 } 1534 } 1535 } 1536 1537 /* 1538 * Watchdog/transmission transmit timeout handler. Called when a 1539 * transmission is started on the interface, but no interrupt is 1540 * received before the timeout. This usually indicates that the 1541 * card has wedged for some reason. 1542 */ 1543 static void 1544 fxp_watchdog(struct ifnet *ifp) 1545 { 1546 if_printf(ifp, "device timeout\n"); 1547 ifp->if_oerrors++; 1548 fxp_init(ifp->if_softc); 1549 } 1550 1551 static void 1552 fxp_init(void *xsc) 1553 { 1554 struct fxp_softc *sc = xsc; 1555 struct ifnet *ifp = &sc->arpcom.ac_if; 1556 struct fxp_cb_config *cbp; 1557 struct fxp_cb_ias *cb_ias; 1558 struct fxp_cb_tx *txp; 1559 struct fxp_cb_mcs *mcsp; 1560 int i, prm, s; 1561 1562 s = splimp(); 1563 /* 1564 * Cancel any pending I/O 1565 */ 1566 fxp_stop(sc); 1567 1568 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1569 1570 /* 1571 * Initialize base of CBL and RFA memory. Loading with zero 1572 * sets it up for regular linear addressing. 1573 */ 1574 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1575 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1576 1577 fxp_scb_wait(sc); 1578 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1579 1580 /* 1581 * Initialize base of dump-stats buffer. 1582 */ 1583 fxp_scb_wait(sc); 1584 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1585 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1586 1587 /* 1588 * Attempt to load microcode if requested. 1589 */ 1590 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1591 fxp_load_ucode(sc); 1592 1593 /* 1594 * Initialize the multicast address list. 1595 */ 1596 if (fxp_mc_addrs(sc)) { 1597 mcsp = sc->mcsp; 1598 mcsp->cb_status = 0; 1599 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1600 mcsp->link_addr = -1; 1601 /* 1602 * Start the multicast setup command. 1603 */ 1604 fxp_scb_wait(sc); 1605 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1606 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1607 /* ...and wait for it to complete. */ 1608 fxp_dma_wait(&mcsp->cb_status, sc); 1609 } 1610 1611 /* 1612 * We temporarily use memory that contains the TxCB list to 1613 * construct the config CB. The TxCB list memory is rebuilt 1614 * later. 1615 */ 1616 cbp = (struct fxp_cb_config *) sc->cbl_base; 1617 1618 /* 1619 * This bcopy is kind of disgusting, but there are a bunch of must be 1620 * zero and must be one bits in this structure and this is the easiest 1621 * way to initialize them all to proper values. 1622 */ 1623 bcopy(fxp_cb_config_template, 1624 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1625 sizeof(fxp_cb_config_template)); 1626 1627 cbp->cb_status = 0; 1628 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1629 cbp->link_addr = -1; /* (no) next command */ 1630 cbp->byte_count = 22; /* (22) bytes to config */ 1631 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1632 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1633 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1634 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1635 cbp->type_enable = 0; /* actually reserved */ 1636 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1637 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1638 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1639 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1640 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1641 cbp->late_scb = 0; /* (don't) defer SCB update */ 1642 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1643 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1644 cbp->ci_int = 1; /* interrupt on CU idle */ 1645 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1646 cbp->ext_stats_dis = 1; /* disable extended counters */ 1647 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1648 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1649 cbp->disc_short_rx = !prm; /* discard short packets */ 1650 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1651 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1652 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1653 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1654 cbp->csma_dis = 0; /* (don't) disable link */ 1655 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1656 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1657 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1658 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1659 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1660 cbp->nsai = 1; /* (don't) disable source addr insert */ 1661 cbp->preamble_length = 2; /* (7 byte) preamble */ 1662 cbp->loopback = 0; /* (don't) loopback */ 1663 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1664 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1665 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1666 cbp->promiscuous = prm; /* promiscuous mode */ 1667 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1668 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1669 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1670 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1671 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1672 1673 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1674 cbp->padding = 1; /* (do) pad short tx packets */ 1675 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1676 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1677 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1678 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1679 /* must set wake_en in PMCSR also */ 1680 cbp->force_fdx = 0; /* (don't) force full duplex */ 1681 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1682 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1683 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1684 1685 if (sc->revision == FXP_REV_82557) { 1686 /* 1687 * The 82557 has no hardware flow control, the values 1688 * below are the defaults for the chip. 1689 */ 1690 cbp->fc_delay_lsb = 0; 1691 cbp->fc_delay_msb = 0x40; 1692 cbp->pri_fc_thresh = 3; 1693 cbp->tx_fc_dis = 0; 1694 cbp->rx_fc_restop = 0; 1695 cbp->rx_fc_restart = 0; 1696 cbp->fc_filter = 0; 1697 cbp->pri_fc_loc = 1; 1698 } else { 1699 cbp->fc_delay_lsb = 0x1f; 1700 cbp->fc_delay_msb = 0x01; 1701 cbp->pri_fc_thresh = 3; 1702 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1703 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1704 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1705 cbp->fc_filter = !prm; /* drop FC frames to host */ 1706 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1707 } 1708 1709 /* 1710 * Start the config command/DMA. 1711 */ 1712 fxp_scb_wait(sc); 1713 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1714 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1715 /* ...and wait for it to complete. */ 1716 fxp_dma_wait(&cbp->cb_status, sc); 1717 1718 /* 1719 * Now initialize the station address. Temporarily use the TxCB 1720 * memory area like we did above for the config CB. 1721 */ 1722 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1723 cb_ias->cb_status = 0; 1724 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1725 cb_ias->link_addr = -1; 1726 bcopy(sc->arpcom.ac_enaddr, 1727 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1728 sizeof(sc->arpcom.ac_enaddr)); 1729 1730 /* 1731 * Start the IAS (Individual Address Setup) command/DMA. 1732 */ 1733 fxp_scb_wait(sc); 1734 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1735 /* ...and wait for it to complete. */ 1736 fxp_dma_wait(&cb_ias->cb_status, sc); 1737 1738 /* 1739 * Initialize transmit control block (TxCB) list. 1740 */ 1741 1742 txp = sc->cbl_base; 1743 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1744 for (i = 0; i < FXP_NTXCB; i++) { 1745 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1746 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1747 txp[i].link_addr = 1748 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1749 if (sc->flags & FXP_FLAG_EXT_TXCB) 1750 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1751 else 1752 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1753 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1754 } 1755 /* 1756 * Set the suspend flag on the first TxCB and start the control 1757 * unit. It will execute the NOP and then suspend. 1758 */ 1759 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1760 sc->cbl_first = sc->cbl_last = txp; 1761 sc->tx_queued = 1; 1762 1763 fxp_scb_wait(sc); 1764 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1765 1766 /* 1767 * Initialize receiver buffer area - RFA. 1768 */ 1769 fxp_scb_wait(sc); 1770 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1771 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1773 1774 /* 1775 * Set current media. 1776 */ 1777 if (sc->miibus != NULL) 1778 mii_mediachg(device_get_softc(sc->miibus)); 1779 1780 ifp->if_flags |= IFF_RUNNING; 1781 ifp->if_flags &= ~IFF_OACTIVE; 1782 1783 /* 1784 * Enable interrupts. 1785 */ 1786 #ifdef DEVICE_POLLING 1787 /* 1788 * ... but only do that if we are not polling. And because (presumably) 1789 * the default is interrupts on, we need to disable them explicitly! 1790 */ 1791 if ( ifp->if_flags & IFF_POLLING ) 1792 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1793 else 1794 #endif /* DEVICE_POLLING */ 1795 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1796 splx(s); 1797 1798 /* 1799 * Start stats updater. 1800 */ 1801 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1802 } 1803 1804 static int 1805 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1806 { 1807 1808 return (0); 1809 } 1810 1811 static void 1812 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1813 { 1814 1815 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1816 } 1817 1818 /* 1819 * Change media according to request. 1820 */ 1821 static int 1822 fxp_ifmedia_upd(struct ifnet *ifp) 1823 { 1824 struct fxp_softc *sc = ifp->if_softc; 1825 struct mii_data *mii; 1826 1827 mii = device_get_softc(sc->miibus); 1828 mii_mediachg(mii); 1829 return (0); 1830 } 1831 1832 /* 1833 * Notify the world which media we're using. 1834 */ 1835 static void 1836 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1837 { 1838 struct fxp_softc *sc = ifp->if_softc; 1839 struct mii_data *mii; 1840 1841 mii = device_get_softc(sc->miibus); 1842 mii_pollstat(mii); 1843 ifmr->ifm_active = mii->mii_media_active; 1844 ifmr->ifm_status = mii->mii_media_status; 1845 1846 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1847 sc->cu_resume_bug = 1; 1848 else 1849 sc->cu_resume_bug = 0; 1850 } 1851 1852 /* 1853 * Add a buffer to the end of the RFA buffer list. 1854 * Return 0 if successful, 1 for failure. A failure results in 1855 * adding the 'oldm' (if non-NULL) on to the end of the list - 1856 * tossing out its old contents and recycling it. 1857 * The RFA struct is stuck at the beginning of mbuf cluster and the 1858 * data pointer is fixed up to point just past it. 1859 */ 1860 static int 1861 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1862 { 1863 u_int32_t v; 1864 struct mbuf *m; 1865 struct fxp_rfa *rfa, *p_rfa; 1866 1867 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1868 if (m == NULL) { /* try to recycle the old mbuf instead */ 1869 if (oldm == NULL) 1870 return 1; 1871 m = oldm; 1872 m->m_data = m->m_ext.ext_buf; 1873 } 1874 1875 /* 1876 * Move the data pointer up so that the incoming data packet 1877 * will be 32-bit aligned. 1878 */ 1879 m->m_data += RFA_ALIGNMENT_FUDGE; 1880 1881 /* 1882 * Get a pointer to the base of the mbuf cluster and move 1883 * data start past it. 1884 */ 1885 rfa = mtod(m, struct fxp_rfa *); 1886 m->m_data += sizeof(struct fxp_rfa); 1887 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1888 1889 /* 1890 * Initialize the rest of the RFA. Note that since the RFA 1891 * is misaligned, we cannot store values directly. Instead, 1892 * we use an optimized, inline copy. 1893 */ 1894 1895 rfa->rfa_status = 0; 1896 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1897 rfa->actual_size = 0; 1898 1899 v = -1; 1900 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1901 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1902 1903 /* 1904 * If there are other buffers already on the list, attach this 1905 * one to the end by fixing up the tail to point to this one. 1906 */ 1907 if (sc->rfa_headm != NULL) { 1908 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1909 RFA_ALIGNMENT_FUDGE); 1910 sc->rfa_tailm->m_next = m; 1911 v = vtophys(rfa); 1912 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1913 p_rfa->rfa_control = 0; 1914 } else { 1915 sc->rfa_headm = m; 1916 } 1917 sc->rfa_tailm = m; 1918 1919 return (m == oldm); 1920 } 1921 1922 static volatile int 1923 fxp_miibus_readreg(device_t dev, int phy, int reg) 1924 { 1925 struct fxp_softc *sc = device_get_softc(dev); 1926 int count = 10000; 1927 int value; 1928 1929 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1930 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1931 1932 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1933 && count--) 1934 DELAY(10); 1935 1936 if (count <= 0) 1937 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1938 1939 return (value & 0xffff); 1940 } 1941 1942 static void 1943 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1944 { 1945 struct fxp_softc *sc = device_get_softc(dev); 1946 int count = 10000; 1947 1948 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1949 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1950 (value & 0xffff)); 1951 1952 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1953 count--) 1954 DELAY(10); 1955 1956 if (count <= 0) 1957 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1958 } 1959 1960 static int 1961 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1962 { 1963 struct fxp_softc *sc = ifp->if_softc; 1964 struct ifreq *ifr = (struct ifreq *)data; 1965 struct mii_data *mii; 1966 int s, error = 0; 1967 1968 s = splimp(); 1969 1970 switch (command) { 1971 1972 case SIOCSIFFLAGS: 1973 if (ifp->if_flags & IFF_ALLMULTI) 1974 sc->flags |= FXP_FLAG_ALL_MCAST; 1975 else 1976 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1977 1978 /* 1979 * If interface is marked up and not running, then start it. 1980 * If it is marked down and running, stop it. 1981 * XXX If it's up then re-initialize it. This is so flags 1982 * such as IFF_PROMISC are handled. 1983 */ 1984 if (ifp->if_flags & IFF_UP) { 1985 fxp_init(sc); 1986 } else { 1987 if (ifp->if_flags & IFF_RUNNING) 1988 fxp_stop(sc); 1989 } 1990 break; 1991 1992 case SIOCADDMULTI: 1993 case SIOCDELMULTI: 1994 if (ifp->if_flags & IFF_ALLMULTI) 1995 sc->flags |= FXP_FLAG_ALL_MCAST; 1996 else 1997 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1998 /* 1999 * Multicast list has changed; set the hardware filter 2000 * accordingly. 2001 */ 2002 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2003 fxp_mc_setup(sc); 2004 /* 2005 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2006 * again rather than else {}. 2007 */ 2008 if (sc->flags & FXP_FLAG_ALL_MCAST) 2009 fxp_init(sc); 2010 error = 0; 2011 break; 2012 2013 case SIOCSIFMEDIA: 2014 case SIOCGIFMEDIA: 2015 if (sc->miibus != NULL) { 2016 mii = device_get_softc(sc->miibus); 2017 error = ifmedia_ioctl(ifp, ifr, 2018 &mii->mii_media, command); 2019 } else { 2020 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2021 } 2022 break; 2023 2024 default: 2025 error = ether_ioctl(ifp, command, data); 2026 break; 2027 } 2028 splx(s); 2029 return (error); 2030 } 2031 2032 /* 2033 * Fill in the multicast address list and return number of entries. 2034 */ 2035 static int 2036 fxp_mc_addrs(struct fxp_softc *sc) 2037 { 2038 struct fxp_cb_mcs *mcsp = sc->mcsp; 2039 struct ifnet *ifp = &sc->arpcom.ac_if; 2040 struct ifmultiaddr *ifma; 2041 int nmcasts; 2042 2043 nmcasts = 0; 2044 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2045 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2046 if (ifma->ifma_addr->sa_family != AF_LINK) 2047 continue; 2048 if (nmcasts >= MAXMCADDR) { 2049 sc->flags |= FXP_FLAG_ALL_MCAST; 2050 nmcasts = 0; 2051 break; 2052 } 2053 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2054 (void *)(uintptr_t)(volatile void *) 2055 &sc->mcsp->mc_addr[nmcasts][0], 6); 2056 nmcasts++; 2057 } 2058 } 2059 mcsp->mc_cnt = nmcasts * 6; 2060 return (nmcasts); 2061 } 2062 2063 /* 2064 * Program the multicast filter. 2065 * 2066 * We have an artificial restriction that the multicast setup command 2067 * must be the first command in the chain, so we take steps to ensure 2068 * this. By requiring this, it allows us to keep up the performance of 2069 * the pre-initialized command ring (esp. link pointers) by not actually 2070 * inserting the mcsetup command in the ring - i.e. its link pointer 2071 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2072 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2073 * lead into the regular TxCB ring when it completes. 2074 * 2075 * This function must be called at splimp. 2076 */ 2077 static void 2078 fxp_mc_setup(struct fxp_softc *sc) 2079 { 2080 struct fxp_cb_mcs *mcsp = sc->mcsp; 2081 struct ifnet *ifp = &sc->arpcom.ac_if; 2082 int count; 2083 2084 /* 2085 * If there are queued commands, we must wait until they are all 2086 * completed. If we are already waiting, then add a NOP command 2087 * with interrupt option so that we're notified when all commands 2088 * have been completed - fxp_start() ensures that no additional 2089 * TX commands will be added when need_mcsetup is true. 2090 */ 2091 if (sc->tx_queued) { 2092 struct fxp_cb_tx *txp; 2093 2094 /* 2095 * need_mcsetup will be true if we are already waiting for the 2096 * NOP command to be completed (see below). In this case, bail. 2097 */ 2098 if (sc->need_mcsetup) 2099 return; 2100 sc->need_mcsetup = 1; 2101 2102 /* 2103 * Add a NOP command with interrupt so that we are notified 2104 * when all TX commands have been processed. 2105 */ 2106 txp = sc->cbl_last->next; 2107 txp->mb_head = NULL; 2108 txp->cb_status = 0; 2109 txp->cb_command = FXP_CB_COMMAND_NOP | 2110 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2111 /* 2112 * Advance the end of list forward. 2113 */ 2114 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2115 sc->cbl_last = txp; 2116 sc->tx_queued++; 2117 /* 2118 * Issue a resume in case the CU has just suspended. 2119 */ 2120 fxp_scb_wait(sc); 2121 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2122 /* 2123 * Set a 5 second timer just in case we don't hear from the 2124 * card again. 2125 */ 2126 ifp->if_timer = 5; 2127 2128 return; 2129 } 2130 sc->need_mcsetup = 0; 2131 2132 /* 2133 * Initialize multicast setup descriptor. 2134 */ 2135 mcsp->next = sc->cbl_base; 2136 mcsp->mb_head = NULL; 2137 mcsp->cb_status = 0; 2138 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2139 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2140 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2141 (void) fxp_mc_addrs(sc); 2142 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2143 sc->tx_queued = 1; 2144 2145 /* 2146 * Wait until command unit is not active. This should never 2147 * be the case when nothing is queued, but make sure anyway. 2148 */ 2149 count = 100; 2150 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2151 FXP_SCB_CUS_ACTIVE && --count) 2152 DELAY(10); 2153 if (count == 0) { 2154 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2155 return; 2156 } 2157 2158 /* 2159 * Start the multicast setup command. 2160 */ 2161 fxp_scb_wait(sc); 2162 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2163 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2164 2165 ifp->if_timer = 2; 2166 return; 2167 } 2168 2169 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2170 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2171 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2172 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2173 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2174 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2175 2176 #define UCODE(x) x, sizeof(x) 2177 2178 struct ucode { 2179 u_int32_t revision; 2180 u_int32_t *ucode; 2181 int length; 2182 u_short int_delay_offset; 2183 u_short bundle_max_offset; 2184 } ucode_table[] = { 2185 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2186 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2187 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2188 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2189 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2190 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2191 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2192 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2193 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2194 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2195 { 0, NULL, 0, 0, 0 } 2196 }; 2197 2198 static void 2199 fxp_load_ucode(struct fxp_softc *sc) 2200 { 2201 struct ucode *uc; 2202 struct fxp_cb_ucode *cbp; 2203 2204 for (uc = ucode_table; uc->ucode != NULL; uc++) 2205 if (sc->revision == uc->revision) 2206 break; 2207 if (uc->ucode == NULL) 2208 return; 2209 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2210 cbp->cb_status = 0; 2211 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2212 cbp->link_addr = -1; /* (no) next command */ 2213 memcpy(cbp->ucode, uc->ucode, uc->length); 2214 if (uc->int_delay_offset) 2215 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2216 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2217 if (uc->bundle_max_offset) 2218 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2219 sc->tunable_bundle_max; 2220 /* 2221 * Download the ucode to the chip. 2222 */ 2223 fxp_scb_wait(sc); 2224 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2225 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2226 /* ...and wait for it to complete. */ 2227 fxp_dma_wait(&cbp->cb_status, sc); 2228 if_printf(&sc->arpcom.ac_if, 2229 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2230 sc->tunable_int_delay, 2231 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2232 sc->flags |= FXP_FLAG_UCODE; 2233 } 2234 2235 static int 2236 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2237 { 2238 int error, value; 2239 2240 value = *(int *)arg1; 2241 error = sysctl_handle_int(oidp, &value, 0, req); 2242 if (error || !req->newptr) 2243 return (error); 2244 if (value < low || value > high) 2245 return (EINVAL); 2246 *(int *)arg1 = value; 2247 return (0); 2248 } 2249 2250 /* 2251 * Interrupt delay is expressed in microseconds, a multiplier is used 2252 * to convert this to the appropriate clock ticks before using. 2253 */ 2254 static int 2255 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2256 { 2257 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2258 } 2259 2260 static int 2261 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2262 { 2263 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2264 } 2265