1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.52 2008/05/25 09:44:31 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/interrupt.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 #include <sys/thread2.h> 47 48 #include <net/if.h> 49 #include <net/ifq_var.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef NS 54 #include <netns/ns.h> 55 #include <netns/ns_if.h> 56 #endif 57 58 #include <net/bpf.h> 59 #include <sys/sockio.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <net/ethernet.h> 64 #include <net/if_arp.h> 65 66 #include <vm/vm.h> /* for vtophys */ 67 #include <vm/pmap.h> /* for vtophys */ 68 69 #include <net/if_types.h> 70 #include <net/vlan/if_vlan_var.h> 71 72 #include <bus/pci/pcivar.h> 73 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include "../mii_layer/mii.h" 76 #include "../mii_layer/miivar.h" 77 78 #include "if_fxpreg.h" 79 #include "if_fxpvar.h" 80 #include "rcvbundl.h" 81 82 #include "miibus_if.h" 83 84 /* 85 * NOTE! On the Alpha, we have an alignment constraint. The 86 * card DMAs the packet immediately following the RFA. However, 87 * the first thing in the packet is a 14-byte Ethernet header. 88 * This means that the packet is misaligned. To compensate, 89 * we actually offset the RFA 2 bytes into the cluster. This 90 * alignes the packet after the Ethernet header at a 32-bit 91 * boundary. HOWEVER! This means that the RFA is misaligned! 92 */ 93 #define RFA_ALIGNMENT_FUDGE 2 94 95 /* 96 * Set initial transmit threshold at 64 (512 bytes). This is 97 * increased by 64 (512 bytes) at a time, to maximum of 192 98 * (1536 bytes), if an underrun occurs. 99 */ 100 static int tx_threshold = 64; 101 102 /* 103 * The configuration byte map has several undefined fields which 104 * must be one or must be zero. Set up a template for these bits 105 * only, (assuming a 82557 chip) leaving the actual configuration 106 * to fxp_init. 107 * 108 * See struct fxp_cb_config for the bit definitions. 109 */ 110 static u_char fxp_cb_config_template[] = { 111 0x0, 0x0, /* cb_status */ 112 0x0, 0x0, /* cb_command */ 113 0x0, 0x0, 0x0, 0x0, /* link_addr */ 114 0x0, /* 0 */ 115 0x0, /* 1 */ 116 0x0, /* 2 */ 117 0x0, /* 3 */ 118 0x0, /* 4 */ 119 0x0, /* 5 */ 120 0x32, /* 6 */ 121 0x0, /* 7 */ 122 0x0, /* 8 */ 123 0x0, /* 9 */ 124 0x6, /* 10 */ 125 0x0, /* 11 */ 126 0x0, /* 12 */ 127 0x0, /* 13 */ 128 0xf2, /* 14 */ 129 0x48, /* 15 */ 130 0x0, /* 16 */ 131 0x40, /* 17 */ 132 0xf0, /* 18 */ 133 0x0, /* 19 */ 134 0x3f, /* 20 */ 135 0x5 /* 21 */ 136 }; 137 138 struct fxp_ident { 139 u_int16_t devid; 140 int16_t revid; /* -1 matches anything */ 141 char *name; 142 }; 143 144 /* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150 static struct fxp_ident fxp_ident_table[] = { 151 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 152 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 153 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 162 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 163 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 168 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 169 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 171 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 172 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 173 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 174 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 175 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 176 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 177 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 178 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 179 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 181 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 182 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 183 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 184 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 186 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 187 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 188 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 190 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 191 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 192 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 193 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 194 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 195 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 196 { 0, -1, NULL }, 197 }; 198 199 static int fxp_probe(device_t dev); 200 static int fxp_attach(device_t dev); 201 static int fxp_detach(device_t dev); 202 static int fxp_shutdown(device_t dev); 203 static int fxp_suspend(device_t dev); 204 static int fxp_resume(device_t dev); 205 206 static void fxp_intr(void *xsc); 207 static void fxp_intr_body(struct fxp_softc *sc, 208 u_int8_t statack, int count); 209 210 static void fxp_init(void *xsc); 211 static void fxp_tick(void *xsc); 212 static void fxp_powerstate_d0(device_t dev); 213 static void fxp_start(struct ifnet *ifp); 214 static void fxp_stop(struct fxp_softc *sc); 215 static void fxp_release(device_t dev); 216 static int fxp_ioctl(struct ifnet *ifp, u_long command, 217 caddr_t data, struct ucred *); 218 static void fxp_watchdog(struct ifnet *ifp); 219 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 220 static int fxp_mc_addrs(struct fxp_softc *sc); 221 static void fxp_mc_setup(struct fxp_softc *sc); 222 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 223 int autosize); 224 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 225 u_int16_t data); 226 static void fxp_autosize_eeprom(struct fxp_softc *sc); 227 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 228 int offset, int words); 229 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 230 int offset, int words); 231 static int fxp_ifmedia_upd(struct ifnet *ifp); 232 static void fxp_ifmedia_sts(struct ifnet *ifp, 233 struct ifmediareq *ifmr); 234 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 235 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 236 struct ifmediareq *ifmr); 237 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 238 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 239 int value); 240 static void fxp_load_ucode(struct fxp_softc *sc); 241 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 242 int low, int high); 243 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 244 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 245 #ifdef DEVICE_POLLING 246 static poll_handler_t fxp_poll; 247 #endif 248 249 static void fxp_lwcopy(volatile u_int32_t *src, 250 volatile u_int32_t *dst); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(volatile u_int16_t *status, 254 struct fxp_softc *sc); 255 256 static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270 }; 271 272 static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276 }; 277 278 static devclass_t fxp_devclass; 279 280 DECLARE_DUMMY_MODULE(if_fxp); 281 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 282 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 284 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 285 286 static int fxp_rnr; 287 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 288 289 /* 290 * Copy a 16-bit aligned 32-bit quantity. 291 */ 292 static void 293 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 294 { 295 #ifdef __i386__ 296 *dst = *src; 297 #else 298 volatile u_int16_t *a = (volatile u_int16_t *)src; 299 volatile u_int16_t *b = (volatile u_int16_t *)dst; 300 301 b[0] = a[0]; 302 b[1] = a[1]; 303 #endif 304 } 305 306 /* 307 * Wait for the previous command to be accepted (but not necessarily 308 * completed). 309 */ 310 static void 311 fxp_scb_wait(struct fxp_softc *sc) 312 { 313 int i = 10000; 314 315 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 316 DELAY(2); 317 if (i == 0) { 318 if_printf(&sc->arpcom.ac_if, 319 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 320 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 321 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 322 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 323 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 324 } 325 } 326 327 static void 328 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 329 { 330 331 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 332 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 333 fxp_scb_wait(sc); 334 } 335 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 336 } 337 338 static void 339 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 340 { 341 int i = 10000; 342 343 while (!(*status & FXP_CB_STATUS_C) && --i) 344 DELAY(2); 345 if (i == 0) 346 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 347 } 348 349 /* 350 * Return identification string if this is device is ours. 351 */ 352 static int 353 fxp_probe(device_t dev) 354 { 355 u_int16_t devid; 356 u_int8_t revid; 357 struct fxp_ident *ident; 358 359 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 360 devid = pci_get_device(dev); 361 revid = pci_get_revid(dev); 362 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 363 if (ident->devid == devid && 364 (ident->revid == revid || ident->revid == -1)) { 365 device_set_desc(dev, ident->name); 366 return (0); 367 } 368 } 369 } 370 return (ENXIO); 371 } 372 373 static void 374 fxp_powerstate_d0(device_t dev) 375 { 376 u_int32_t iobase, membase, irq; 377 378 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 379 /* Save important PCI config data. */ 380 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 381 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 382 irq = pci_read_config(dev, PCIR_INTLINE, 4); 383 384 /* Reset the power state. */ 385 device_printf(dev, "chip is in D%d power mode " 386 "-- setting to D0\n", pci_get_powerstate(dev)); 387 388 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 389 390 /* Restore PCI config data. */ 391 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 392 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 393 pci_write_config(dev, PCIR_INTLINE, irq, 4); 394 } 395 } 396 397 static int 398 fxp_attach(device_t dev) 399 { 400 int error = 0; 401 struct fxp_softc *sc = device_get_softc(dev); 402 struct ifnet *ifp; 403 u_int32_t val; 404 u_int16_t data; 405 int i, rid, m1, m2, prefer_iomap; 406 407 callout_init(&sc->fxp_stat_timer); 408 sysctl_ctx_init(&sc->sysctl_ctx); 409 410 /* 411 * Enable bus mastering. Enable memory space too, in case 412 * BIOS/Prom forgot about it. 413 */ 414 pci_enable_busmaster(dev); 415 pci_enable_io(dev, SYS_RES_MEMORY); 416 val = pci_read_config(dev, PCIR_COMMAND, 2); 417 418 fxp_powerstate_d0(dev); 419 420 /* 421 * Figure out which we should try first - memory mapping or i/o mapping? 422 * We default to memory mapping. Then we accept an override from the 423 * command line. Then we check to see which one is enabled. 424 */ 425 m1 = PCIM_CMD_MEMEN; 426 m2 = PCIM_CMD_PORTEN; 427 prefer_iomap = 0; 428 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 429 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 430 m1 = PCIM_CMD_PORTEN; 431 m2 = PCIM_CMD_MEMEN; 432 } 433 434 if (val & m1) { 435 sc->rtp = 436 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 437 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 438 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 439 RF_ACTIVE); 440 } 441 if (sc->mem == NULL && (val & m2)) { 442 sc->rtp = 443 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 444 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 445 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 446 RF_ACTIVE); 447 } 448 449 if (!sc->mem) { 450 device_printf(dev, "could not map device registers\n"); 451 error = ENXIO; 452 goto fail; 453 } 454 if (bootverbose) { 455 device_printf(dev, "using %s space register mapping\n", 456 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 457 } 458 459 sc->sc_st = rman_get_bustag(sc->mem); 460 sc->sc_sh = rman_get_bushandle(sc->mem); 461 462 /* 463 * Allocate our interrupt. 464 */ 465 rid = 0; 466 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 467 RF_SHAREABLE | RF_ACTIVE); 468 if (sc->irq == NULL) { 469 device_printf(dev, "could not map interrupt\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 474 /* 475 * Reset to a stable state. 476 */ 477 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 478 DELAY(10); 479 480 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 481 M_DEVBUF, M_WAITOK | M_ZERO); 482 483 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 484 M_WAITOK | M_ZERO); 485 486 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 487 488 /* 489 * Pre-allocate our receive buffers. 490 */ 491 for (i = 0; i < FXP_NRFABUFS; i++) { 492 if (fxp_add_rfabuf(sc, NULL) != 0) { 493 goto failmem; 494 } 495 } 496 497 /* 498 * Find out how large of an SEEPROM we have. 499 */ 500 fxp_autosize_eeprom(sc); 501 502 /* 503 * Determine whether we must use the 503 serial interface. 504 */ 505 fxp_read_eeprom(sc, &data, 6, 1); 506 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 507 (data & FXP_PHY_SERIAL_ONLY)) 508 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 509 510 /* 511 * Create the sysctl tree 512 */ 513 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 514 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 515 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 516 if (sc->sysctl_tree == NULL) 517 goto fail; 518 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 519 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 520 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 521 "FXP driver receive interrupt microcode bundling delay"); 522 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 523 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 524 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 525 "FXP driver receive interrupt microcode bundle size limit"); 526 527 /* 528 * Pull in device tunables. 529 */ 530 sc->tunable_int_delay = TUNABLE_INT_DELAY; 531 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 532 resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "int_delay", &sc->tunable_int_delay); 534 resource_int_value(device_get_name(dev), device_get_unit(dev), 535 "bundle_max", &sc->tunable_bundle_max); 536 537 /* 538 * Find out the chip revision; lump all 82557 revs together. 539 */ 540 fxp_read_eeprom(sc, &data, 5, 1); 541 if ((data >> 8) == 1) 542 sc->revision = FXP_REV_82557; 543 else 544 sc->revision = pci_get_revid(dev); 545 546 /* 547 * Enable workarounds for certain chip revision deficiencies. 548 * 549 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 550 * some systems based a normal 82559 design, have a defect where 551 * the chip can cause a PCI protocol violation if it receives 552 * a CU_RESUME command when it is entering the IDLE state. The 553 * workaround is to disable Dynamic Standby Mode, so the chip never 554 * deasserts CLKRUN#, and always remains in an active state. 555 * 556 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 557 */ 558 i = pci_get_device(dev); 559 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 560 sc->revision >= FXP_REV_82559_A0) { 561 fxp_read_eeprom(sc, &data, 10, 1); 562 if (data & 0x02) { /* STB enable */ 563 u_int16_t cksum; 564 int i; 565 566 device_printf(dev, 567 "Disabling dynamic standby mode in EEPROM\n"); 568 data &= ~0x02; 569 fxp_write_eeprom(sc, &data, 10, 1); 570 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 571 cksum = 0; 572 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 573 fxp_read_eeprom(sc, &data, i, 1); 574 cksum += data; 575 } 576 i = (1 << sc->eeprom_size) - 1; 577 cksum = 0xBABA - cksum; 578 fxp_read_eeprom(sc, &data, i, 1); 579 fxp_write_eeprom(sc, &cksum, i, 1); 580 device_printf(dev, 581 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 582 i, data, cksum); 583 #if 1 584 /* 585 * If the user elects to continue, try the software 586 * workaround, as it is better than nothing. 587 */ 588 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 589 #endif 590 } 591 } 592 593 /* 594 * If we are not a 82557 chip, we can enable extended features. 595 */ 596 if (sc->revision != FXP_REV_82557) { 597 /* 598 * If MWI is enabled in the PCI configuration, and there 599 * is a valid cacheline size (8 or 16 dwords), then tell 600 * the board to turn on MWI. 601 */ 602 if (val & PCIM_CMD_MWRICEN && 603 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 604 sc->flags |= FXP_FLAG_MWI_ENABLE; 605 606 /* turn on the extended TxCB feature */ 607 sc->flags |= FXP_FLAG_EXT_TXCB; 608 609 /* enable reception of long frames for VLAN */ 610 sc->flags |= FXP_FLAG_LONG_PKT_EN; 611 } 612 613 /* 614 * Read MAC address. 615 */ 616 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 617 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 618 device_printf(dev, "10Mbps\n"); 619 if (bootverbose) { 620 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 621 pci_get_vendor(dev), pci_get_device(dev), 622 pci_get_subvendor(dev), pci_get_subdevice(dev), 623 pci_get_revid(dev)); 624 fxp_read_eeprom(sc, &data, 10, 1); 625 device_printf(dev, "Dynamic Standby mode is %s\n", 626 data & 0x02 ? "enabled" : "disabled"); 627 } 628 629 /* 630 * If this is only a 10Mbps device, then there is no MII, and 631 * the PHY will use a serial interface instead. 632 * 633 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 634 * doesn't have a programming interface of any sort. The 635 * media is sensed automatically based on how the link partner 636 * is configured. This is, in essence, manual configuration. 637 */ 638 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 639 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 640 fxp_serial_ifmedia_sts); 641 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 642 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 643 } else { 644 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 645 fxp_ifmedia_sts)) { 646 device_printf(dev, "MII without any PHY!\n"); 647 error = ENXIO; 648 goto fail; 649 } 650 } 651 652 ifp = &sc->arpcom.ac_if; 653 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 654 ifp->if_baudrate = 100000000; 655 ifp->if_init = fxp_init; 656 ifp->if_softc = sc; 657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658 ifp->if_ioctl = fxp_ioctl; 659 ifp->if_start = fxp_start; 660 #ifdef DEVICE_POLLING 661 ifp->if_poll = fxp_poll; 662 #endif 663 ifp->if_watchdog = fxp_watchdog; 664 665 /* 666 * Attach the interface. 667 */ 668 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 669 670 /* 671 * Tell the upper layer(s) we support long frames. 672 */ 673 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 674 675 /* 676 * Let the system queue as many packets as we have available 677 * TX descriptors. 678 */ 679 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 680 ifq_set_ready(&ifp->if_snd); 681 682 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 683 fxp_intr, sc, &sc->ih, 684 ifp->if_serializer); 685 if (error) { 686 ether_ifdetach(ifp); 687 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 688 ifmedia_removeall(&sc->sc_media); 689 device_printf(dev, "could not setup irq\n"); 690 goto fail; 691 } 692 693 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq)); 694 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 695 696 return (0); 697 698 failmem: 699 device_printf(dev, "Failed to malloc memory\n"); 700 error = ENOMEM; 701 fail: 702 fxp_release(dev); 703 return (error); 704 } 705 706 /* 707 * release all resources 708 */ 709 static void 710 fxp_release(device_t dev) 711 { 712 struct fxp_softc *sc = device_get_softc(dev); 713 714 if (sc->miibus) 715 device_delete_child(dev, sc->miibus); 716 bus_generic_detach(dev); 717 718 if (sc->cbl_base) 719 kfree(sc->cbl_base, M_DEVBUF); 720 if (sc->fxp_stats) 721 kfree(sc->fxp_stats, M_DEVBUF); 722 if (sc->mcsp) 723 kfree(sc->mcsp, M_DEVBUF); 724 if (sc->rfa_headm) 725 m_freem(sc->rfa_headm); 726 727 if (sc->irq) 728 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 729 if (sc->mem) 730 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 731 732 sysctl_ctx_free(&sc->sysctl_ctx); 733 } 734 735 /* 736 * Detach interface. 737 */ 738 static int 739 fxp_detach(device_t dev) 740 { 741 struct fxp_softc *sc = device_get_softc(dev); 742 743 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 744 745 /* 746 * Stop DMA and drop transmit queue. 747 */ 748 fxp_stop(sc); 749 750 /* 751 * Disable interrupts. 752 * 753 * NOTE: This should be done after fxp_stop(), because software 754 * resetting in fxp_stop() may leave interrupts turned on. 755 */ 756 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 757 758 /* 759 * Free all media structures. 760 */ 761 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 762 ifmedia_removeall(&sc->sc_media); 763 764 if (sc->ih) 765 bus_teardown_intr(dev, sc->irq, sc->ih); 766 767 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 768 769 /* 770 * Close down routes etc. 771 */ 772 ether_ifdetach(&sc->arpcom.ac_if); 773 774 /* Release our allocated resources. */ 775 fxp_release(dev); 776 777 return (0); 778 } 779 780 /* 781 * Device shutdown routine. Called at system shutdown after sync. The 782 * main purpose of this routine is to shut off receiver DMA so that 783 * kernel memory doesn't get clobbered during warmboot. 784 */ 785 static int 786 fxp_shutdown(device_t dev) 787 { 788 /* 789 * Make sure that DMA is disabled prior to reboot. Not doing 790 * do could allow DMA to corrupt kernel memory during the 791 * reboot before the driver initializes. 792 */ 793 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 794 return (0); 795 } 796 797 /* 798 * Device suspend routine. Stop the interface and save some PCI 799 * settings in case the BIOS doesn't restore them properly on 800 * resume. 801 */ 802 static int 803 fxp_suspend(device_t dev) 804 { 805 struct fxp_softc *sc = device_get_softc(dev); 806 int i; 807 808 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 809 810 fxp_stop(sc); 811 812 for (i = 0; i < 5; i++) 813 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 814 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 815 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 816 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 817 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 818 819 sc->suspended = 1; 820 821 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 822 return (0); 823 } 824 825 /* 826 * Device resume routine. Restore some PCI settings in case the BIOS 827 * doesn't, re-enable busmastering, and restart the interface if 828 * appropriate. 829 */ 830 static int 831 fxp_resume(device_t dev) 832 { 833 struct fxp_softc *sc = device_get_softc(dev); 834 struct ifnet *ifp = &sc->arpcom.ac_if; 835 int i; 836 837 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 838 839 fxp_powerstate_d0(dev); 840 841 /* better way to do this? */ 842 for (i = 0; i < 5; i++) 843 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 844 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 845 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 846 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 847 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 848 849 /* reenable busmastering and memory space */ 850 pci_enable_busmaster(dev); 851 pci_enable_io(dev, SYS_RES_MEMORY); 852 853 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 854 DELAY(10); 855 856 /* reinitialize interface if necessary */ 857 if (ifp->if_flags & IFF_UP) 858 fxp_init(sc); 859 860 sc->suspended = 0; 861 862 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 863 return (0); 864 } 865 866 static void 867 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 868 { 869 u_int16_t reg; 870 int x; 871 872 /* 873 * Shift in data. 874 */ 875 for (x = 1 << (length - 1); x; x >>= 1) { 876 if (data & x) 877 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 878 else 879 reg = FXP_EEPROM_EECS; 880 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 881 DELAY(1); 882 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 883 DELAY(1); 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 885 DELAY(1); 886 } 887 } 888 889 /* 890 * Read from the serial EEPROM. Basically, you manually shift in 891 * the read opcode (one bit at a time) and then shift in the address, 892 * and then you shift out the data (all of this one bit at a time). 893 * The word size is 16 bits, so you have to provide the address for 894 * every 16 bits of data. 895 */ 896 static u_int16_t 897 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 898 { 899 u_int16_t reg, data; 900 int x; 901 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 903 /* 904 * Shift in read opcode. 905 */ 906 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 907 /* 908 * Shift in address. 909 */ 910 data = 0; 911 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 912 if (offset & x) 913 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 914 else 915 reg = FXP_EEPROM_EECS; 916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 917 DELAY(1); 918 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 919 DELAY(1); 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 921 DELAY(1); 922 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 923 data++; 924 if (autosize && reg == 0) { 925 sc->eeprom_size = data; 926 break; 927 } 928 } 929 /* 930 * Shift out data. 931 */ 932 data = 0; 933 reg = FXP_EEPROM_EECS; 934 for (x = 1 << 15; x; x >>= 1) { 935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 936 DELAY(1); 937 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 938 data |= x; 939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 940 DELAY(1); 941 } 942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 943 DELAY(1); 944 945 return (data); 946 } 947 948 static void 949 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 950 { 951 int i; 952 953 /* 954 * Erase/write enable. 955 */ 956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 957 fxp_eeprom_shiftin(sc, 0x4, 3); 958 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 959 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 960 DELAY(1); 961 /* 962 * Shift in write opcode, address, data. 963 */ 964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 965 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 966 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 967 fxp_eeprom_shiftin(sc, data, 16); 968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 969 DELAY(1); 970 /* 971 * Wait for EEPROM to finish up. 972 */ 973 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 974 DELAY(1); 975 for (i = 0; i < 1000; i++) { 976 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 977 break; 978 DELAY(50); 979 } 980 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 981 DELAY(1); 982 /* 983 * Erase/write disable. 984 */ 985 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 986 fxp_eeprom_shiftin(sc, 0x4, 3); 987 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 988 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 989 DELAY(1); 990 } 991 992 /* 993 * From NetBSD: 994 * 995 * Figure out EEPROM size. 996 * 997 * 559's can have either 64-word or 256-word EEPROMs, the 558 998 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 999 * talks about the existance of 16 to 256 word EEPROMs. 1000 * 1001 * The only known sizes are 64 and 256, where the 256 version is used 1002 * by CardBus cards to store CIS information. 1003 * 1004 * The address is shifted in msb-to-lsb, and after the last 1005 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1006 * after which follows the actual data. We try to detect this zero, by 1007 * probing the data-out bit in the EEPROM control register just after 1008 * having shifted in a bit. If the bit is zero, we assume we've 1009 * shifted enough address bits. The data-out should be tri-state, 1010 * before this, which should translate to a logical one. 1011 */ 1012 static void 1013 fxp_autosize_eeprom(struct fxp_softc *sc) 1014 { 1015 1016 /* guess maximum size of 256 words */ 1017 sc->eeprom_size = 8; 1018 1019 /* autosize */ 1020 fxp_eeprom_getword(sc, 0, 1); 1021 } 1022 1023 static void 1024 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1025 { 1026 int i; 1027 1028 for (i = 0; i < words; i++) 1029 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1030 } 1031 1032 static void 1033 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1034 { 1035 int i; 1036 1037 for (i = 0; i < words; i++) 1038 fxp_eeprom_putword(sc, offset + i, data[i]); 1039 } 1040 1041 /* 1042 * Start packet transmission on the interface. 1043 */ 1044 static void 1045 fxp_start(struct ifnet *ifp) 1046 { 1047 struct fxp_softc *sc = ifp->if_softc; 1048 struct fxp_cb_tx *txp; 1049 1050 /* 1051 * See if we need to suspend xmit until the multicast filter 1052 * has been reprogrammed (which can only be done at the head 1053 * of the command chain). 1054 */ 1055 if (sc->need_mcsetup) { 1056 ifq_purge(&ifp->if_snd); 1057 return; 1058 } 1059 1060 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1061 return; 1062 1063 txp = NULL; 1064 1065 /* 1066 * We're finished if there is nothing more to add to the list or if 1067 * we're all filled up with buffers to transmit. 1068 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1069 * a NOP command when needed. 1070 */ 1071 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1072 struct mbuf *m, *mb_head; 1073 int segment, ntries = 0; 1074 1075 /* 1076 * Grab a packet to transmit. 1077 */ 1078 mb_head = ifq_dequeue(&ifp->if_snd, NULL); 1079 if (mb_head == NULL) 1080 break; 1081 tbdinit: 1082 /* 1083 * Make sure that the packet fits into one TX desc 1084 */ 1085 segment = 0; 1086 for (m = mb_head; m != NULL; m = m->m_next) { 1087 if (m->m_len != 0) { 1088 ++segment; 1089 if (segment >= FXP_NTXSEG) 1090 break; 1091 } 1092 } 1093 if (segment >= FXP_NTXSEG) { 1094 struct mbuf *mn; 1095 1096 if (ntries) { 1097 /* 1098 * Packet is excessively fragmented, 1099 * and will never fit into one TX 1100 * desc. Give it up. 1101 */ 1102 m_freem(mb_head); 1103 ifp->if_oerrors++; 1104 continue; 1105 } 1106 1107 mn = m_dup(mb_head, MB_DONTWAIT); 1108 if (mn == NULL) { 1109 m_freem(mb_head); 1110 ifp->if_oerrors++; 1111 continue; 1112 } 1113 1114 m_freem(mb_head); 1115 mb_head = mn; 1116 ntries = 1; 1117 goto tbdinit; 1118 } 1119 1120 /* 1121 * Get pointer to next available tx desc. 1122 */ 1123 txp = sc->cbl_last->next; 1124 1125 /* 1126 * Go through each of the mbufs in the chain and initialize 1127 * the transmit buffer descriptors with the physical address 1128 * and size of the mbuf. 1129 */ 1130 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1131 if (m->m_len != 0) { 1132 KKASSERT(segment < FXP_NTXSEG); 1133 1134 txp->tbd[segment].tb_addr = 1135 vtophys(mtod(m, vm_offset_t)); 1136 txp->tbd[segment].tb_size = m->m_len; 1137 segment++; 1138 } 1139 } 1140 KKASSERT(m == NULL); 1141 1142 txp->tbd_number = segment; 1143 txp->mb_head = mb_head; 1144 txp->cb_status = 0; 1145 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1146 txp->cb_command = 1147 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1148 FXP_CB_COMMAND_S; 1149 } else { 1150 txp->cb_command = 1151 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1152 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1153 } 1154 txp->tx_threshold = tx_threshold; 1155 1156 /* 1157 * Advance the end of list forward. 1158 */ 1159 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1160 sc->cbl_last = txp; 1161 1162 /* 1163 * Advance the beginning of the list forward if there are 1164 * no other packets queued (when nothing is queued, cbl_first 1165 * sits on the last TxCB that was sent out). 1166 */ 1167 if (sc->tx_queued == 0) 1168 sc->cbl_first = txp; 1169 1170 sc->tx_queued++; 1171 /* 1172 * Set a 5 second timer just in case we don't hear 1173 * from the card again. 1174 */ 1175 ifp->if_timer = 5; 1176 1177 BPF_MTAP(ifp, mb_head); 1178 } 1179 1180 if (sc->tx_queued >= FXP_NTXCB - 1) 1181 ifp->if_flags |= IFF_OACTIVE; 1182 1183 /* 1184 * We're finished. If we added to the list, issue a RESUME to get DMA 1185 * going again if suspended. 1186 */ 1187 if (txp != NULL) { 1188 fxp_scb_wait(sc); 1189 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1190 } 1191 } 1192 1193 #ifdef DEVICE_POLLING 1194 1195 static void 1196 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1197 { 1198 struct fxp_softc *sc = ifp->if_softc; 1199 u_int8_t statack; 1200 1201 switch(cmd) { 1202 case POLL_REGISTER: 1203 /* disable interrupts */ 1204 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1205 break; 1206 case POLL_DEREGISTER: 1207 /* enable interrupts */ 1208 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1209 break; 1210 default: 1211 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1212 FXP_SCB_STATACK_FR; 1213 if (cmd == POLL_AND_CHECK_STATUS) { 1214 u_int8_t tmp; 1215 1216 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1217 if (tmp == 0xff || tmp == 0) 1218 return; /* nothing to do */ 1219 tmp &= ~statack; 1220 /* ack what we can */ 1221 if (tmp != 0) 1222 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1223 statack |= tmp; 1224 } 1225 fxp_intr_body(sc, statack, count); 1226 break; 1227 } 1228 } 1229 1230 #endif /* DEVICE_POLLING */ 1231 1232 /* 1233 * Process interface interrupts. 1234 */ 1235 static void 1236 fxp_intr(void *xsc) 1237 { 1238 struct fxp_softc *sc = xsc; 1239 u_int8_t statack; 1240 1241 if (sc->suspended) { 1242 return; 1243 } 1244 1245 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1246 /* 1247 * It should not be possible to have all bits set; the 1248 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1249 * all bits are set, this may indicate that the card has 1250 * been physically ejected, so ignore it. 1251 */ 1252 if (statack == 0xff) 1253 return; 1254 1255 /* 1256 * First ACK all the interrupts in this pass. 1257 */ 1258 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1259 fxp_intr_body(sc, statack, -1); 1260 } 1261 } 1262 1263 static void 1264 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1265 { 1266 struct ifnet *ifp = &sc->arpcom.ac_if; 1267 struct mbuf *m; 1268 struct fxp_rfa *rfa; 1269 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1270 1271 if (rnr) 1272 fxp_rnr++; 1273 #ifdef DEVICE_POLLING 1274 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1275 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1276 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1277 rnr = 1; 1278 } 1279 #endif 1280 1281 /* 1282 * Free any finished transmit mbuf chains. 1283 * 1284 * Handle the CNA event likt a CXTNO event. It used to 1285 * be that this event (control unit not ready) was not 1286 * encountered, but it is now with the SMPng modifications. 1287 * The exact sequence of events that occur when the interface 1288 * is brought up are different now, and if this event 1289 * goes unhandled, the configuration/rxfilter setup sequence 1290 * can stall for several seconds. The result is that no 1291 * packets go out onto the wire for about 5 to 10 seconds 1292 * after the interface is ifconfig'ed for the first time. 1293 */ 1294 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1295 struct fxp_cb_tx *txp; 1296 int old_queued; 1297 1298 old_queued = sc->tx_queued; 1299 for (txp = sc->cbl_first; sc->tx_queued && 1300 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1301 txp = txp->next) { 1302 if ((m = txp->mb_head) != NULL) { 1303 txp->mb_head = NULL; 1304 sc->tx_queued--; 1305 m_freem(m); 1306 } else { 1307 sc->tx_queued--; 1308 } 1309 } 1310 sc->cbl_first = txp; 1311 1312 if (old_queued > sc->tx_queued) 1313 ifp->if_flags &= ~IFF_OACTIVE; 1314 1315 if (sc->tx_queued == 0) { 1316 ifp->if_timer = 0; 1317 if (sc->need_mcsetup) 1318 fxp_mc_setup(sc); 1319 } 1320 1321 /* 1322 * Try to start more packets transmitting. 1323 */ 1324 if (!ifq_is_empty(&ifp->if_snd)) 1325 if_devstart(ifp); 1326 } 1327 1328 /* 1329 * Just return if nothing happened on the receive side. 1330 */ 1331 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1332 return; 1333 1334 /* 1335 * Process receiver interrupts. If a no-resource (RNR) 1336 * condition exists, get whatever packets we can and 1337 * re-start the receiver. 1338 * 1339 * When using polling, we do not process the list to completion, 1340 * so when we get an RNR interrupt we must defer the restart 1341 * until we hit the last buffer with the C bit set. 1342 * If we run out of cycles and rfa_headm has the C bit set, 1343 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1344 * that the info will be used in the subsequent polling cycle. 1345 */ 1346 for (;;) { 1347 m = sc->rfa_headm; 1348 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1349 RFA_ALIGNMENT_FUDGE); 1350 1351 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1352 if (count >= 0 && count-- == 0) { 1353 if (rnr) { 1354 /* Defer RNR processing until the next time. */ 1355 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1356 rnr = 0; 1357 } 1358 break; 1359 } 1360 #endif /* DEVICE_POLLING */ 1361 1362 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1363 break; 1364 1365 /* 1366 * Remove first packet from the chain. 1367 */ 1368 sc->rfa_headm = m->m_next; 1369 m->m_next = NULL; 1370 1371 /* 1372 * Add a new buffer to the receive chain. 1373 * If this fails, the old buffer is recycled 1374 * instead. 1375 */ 1376 if (fxp_add_rfabuf(sc, m) == 0) { 1377 int total_len; 1378 1379 /* 1380 * Fetch packet length (the top 2 bits of 1381 * actual_size are flags set by the controller 1382 * upon completion), and drop the packet in case 1383 * of bogus length or CRC errors. 1384 */ 1385 total_len = rfa->actual_size & 0x3fff; 1386 if (total_len < sizeof(struct ether_header) || 1387 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1388 sizeof(struct fxp_rfa) || 1389 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1390 m_freem(m); 1391 continue; 1392 } 1393 m->m_pkthdr.len = m->m_len = total_len; 1394 ifp->if_input(ifp, m); 1395 } 1396 } 1397 if (rnr) { 1398 fxp_scb_wait(sc); 1399 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1400 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1401 RFA_ALIGNMENT_FUDGE); 1402 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1403 } 1404 } 1405 1406 /* 1407 * Update packet in/out/collision statistics. The i82557 doesn't 1408 * allow you to access these counters without doing a fairly 1409 * expensive DMA to get _all_ of the statistics it maintains, so 1410 * we do this operation here only once per second. The statistics 1411 * counters in the kernel are updated from the previous dump-stats 1412 * DMA and then a new dump-stats DMA is started. The on-chip 1413 * counters are zeroed when the DMA completes. If we can't start 1414 * the DMA immediately, we don't wait - we just prepare to read 1415 * them again next time. 1416 */ 1417 static void 1418 fxp_tick(void *xsc) 1419 { 1420 struct fxp_softc *sc = xsc; 1421 struct ifnet *ifp = &sc->arpcom.ac_if; 1422 struct fxp_stats *sp = sc->fxp_stats; 1423 struct fxp_cb_tx *txp; 1424 struct mbuf *m; 1425 int old_queued; 1426 1427 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1428 1429 ifp->if_opackets += sp->tx_good; 1430 ifp->if_collisions += sp->tx_total_collisions; 1431 if (sp->rx_good) { 1432 ifp->if_ipackets += sp->rx_good; 1433 sc->rx_idle_secs = 0; 1434 } else { 1435 /* 1436 * Receiver's been idle for another second. 1437 */ 1438 sc->rx_idle_secs++; 1439 } 1440 ifp->if_ierrors += 1441 sp->rx_crc_errors + 1442 sp->rx_alignment_errors + 1443 sp->rx_rnr_errors + 1444 sp->rx_overrun_errors; 1445 /* 1446 * If any transmit underruns occured, bump up the transmit 1447 * threshold by another 512 bytes (64 * 8). 1448 */ 1449 if (sp->tx_underruns) { 1450 ifp->if_oerrors += sp->tx_underruns; 1451 if (tx_threshold < 192) 1452 tx_threshold += 64; 1453 } 1454 1455 /* 1456 * Release any xmit buffers that have completed DMA. This isn't 1457 * strictly necessary to do here, but it's advantagous for mbufs 1458 * with external storage to be released in a timely manner rather 1459 * than being defered for a potentially long time. This limits 1460 * the delay to a maximum of one second. 1461 */ 1462 old_queued = sc->tx_queued; 1463 for (txp = sc->cbl_first; sc->tx_queued && 1464 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1465 txp = txp->next) { 1466 if ((m = txp->mb_head) != NULL) { 1467 txp->mb_head = NULL; 1468 sc->tx_queued--; 1469 m_freem(m); 1470 } else { 1471 sc->tx_queued--; 1472 } 1473 } 1474 sc->cbl_first = txp; 1475 1476 if (old_queued > sc->tx_queued) 1477 ifp->if_flags &= ~IFF_OACTIVE; 1478 if (sc->tx_queued == 0) 1479 ifp->if_timer = 0; 1480 1481 /* 1482 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1483 * then assume the receiver has locked up and attempt to clear 1484 * the condition by reprogramming the multicast filter. This is 1485 * a work-around for a bug in the 82557 where the receiver locks 1486 * up if it gets certain types of garbage in the syncronization 1487 * bits prior to the packet header. This bug is supposed to only 1488 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1489 * mode as well (perhaps due to a 10/100 speed transition). 1490 */ 1491 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1492 sc->rx_idle_secs = 0; 1493 fxp_mc_setup(sc); 1494 } 1495 /* 1496 * If there is no pending command, start another stats 1497 * dump. Otherwise punt for now. 1498 */ 1499 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1500 /* 1501 * Start another stats dump. 1502 */ 1503 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1504 } else { 1505 /* 1506 * A previous command is still waiting to be accepted. 1507 * Just zero our copy of the stats and wait for the 1508 * next timer event to update them. 1509 */ 1510 sp->tx_good = 0; 1511 sp->tx_underruns = 0; 1512 sp->tx_total_collisions = 0; 1513 1514 sp->rx_good = 0; 1515 sp->rx_crc_errors = 0; 1516 sp->rx_alignment_errors = 0; 1517 sp->rx_rnr_errors = 0; 1518 sp->rx_overrun_errors = 0; 1519 } 1520 if (sc->miibus != NULL) 1521 mii_tick(device_get_softc(sc->miibus)); 1522 /* 1523 * Schedule another timeout one second from now. 1524 */ 1525 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1526 1527 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1528 } 1529 1530 /* 1531 * Stop the interface. Cancels the statistics updater and resets 1532 * the interface. 1533 */ 1534 static void 1535 fxp_stop(struct fxp_softc *sc) 1536 { 1537 struct ifnet *ifp = &sc->arpcom.ac_if; 1538 struct fxp_cb_tx *txp; 1539 int i; 1540 1541 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1542 ifp->if_timer = 0; 1543 1544 /* 1545 * Cancel stats updater. 1546 */ 1547 callout_stop(&sc->fxp_stat_timer); 1548 1549 /* 1550 * Issue software reset, which also unloads the microcode. 1551 */ 1552 sc->flags &= ~FXP_FLAG_UCODE; 1553 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1554 DELAY(50); 1555 1556 /* 1557 * Release any xmit buffers. 1558 */ 1559 txp = sc->cbl_base; 1560 if (txp != NULL) { 1561 for (i = 0; i < FXP_NTXCB; i++) { 1562 if (txp[i].mb_head != NULL) { 1563 m_freem(txp[i].mb_head); 1564 txp[i].mb_head = NULL; 1565 } 1566 } 1567 } 1568 sc->tx_queued = 0; 1569 1570 /* 1571 * Free all the receive buffers then reallocate/reinitialize 1572 */ 1573 if (sc->rfa_headm != NULL) 1574 m_freem(sc->rfa_headm); 1575 sc->rfa_headm = NULL; 1576 sc->rfa_tailm = NULL; 1577 for (i = 0; i < FXP_NRFABUFS; i++) { 1578 if (fxp_add_rfabuf(sc, NULL) != 0) { 1579 /* 1580 * This "can't happen" - we're at splimp() 1581 * and we just freed all the buffers we need 1582 * above. 1583 */ 1584 panic("fxp_stop: no buffers!"); 1585 } 1586 } 1587 } 1588 1589 /* 1590 * Watchdog/transmission transmit timeout handler. Called when a 1591 * transmission is started on the interface, but no interrupt is 1592 * received before the timeout. This usually indicates that the 1593 * card has wedged for some reason. 1594 */ 1595 static void 1596 fxp_watchdog(struct ifnet *ifp) 1597 { 1598 if_printf(ifp, "device timeout\n"); 1599 ifp->if_oerrors++; 1600 fxp_init(ifp->if_softc); 1601 } 1602 1603 static void 1604 fxp_init(void *xsc) 1605 { 1606 struct fxp_softc *sc = xsc; 1607 struct ifnet *ifp = &sc->arpcom.ac_if; 1608 struct fxp_cb_config *cbp; 1609 struct fxp_cb_ias *cb_ias; 1610 struct fxp_cb_tx *txp; 1611 struct fxp_cb_mcs *mcsp; 1612 int i, prm; 1613 1614 /* 1615 * Cancel any pending I/O 1616 */ 1617 fxp_stop(sc); 1618 1619 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1620 1621 /* 1622 * Initialize base of CBL and RFA memory. Loading with zero 1623 * sets it up for regular linear addressing. 1624 */ 1625 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1626 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1627 1628 fxp_scb_wait(sc); 1629 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1630 1631 /* 1632 * Initialize base of dump-stats buffer. 1633 */ 1634 fxp_scb_wait(sc); 1635 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1636 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1637 1638 /* 1639 * Attempt to load microcode if requested. 1640 */ 1641 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1642 fxp_load_ucode(sc); 1643 1644 /* 1645 * Initialize the multicast address list. 1646 */ 1647 if (fxp_mc_addrs(sc)) { 1648 mcsp = sc->mcsp; 1649 mcsp->cb_status = 0; 1650 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1651 mcsp->link_addr = -1; 1652 /* 1653 * Start the multicast setup command. 1654 */ 1655 fxp_scb_wait(sc); 1656 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1657 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1658 /* ...and wait for it to complete. */ 1659 fxp_dma_wait(&mcsp->cb_status, sc); 1660 } 1661 1662 /* 1663 * We temporarily use memory that contains the TxCB list to 1664 * construct the config CB. The TxCB list memory is rebuilt 1665 * later. 1666 */ 1667 cbp = (struct fxp_cb_config *) sc->cbl_base; 1668 1669 /* 1670 * This bcopy is kind of disgusting, but there are a bunch of must be 1671 * zero and must be one bits in this structure and this is the easiest 1672 * way to initialize them all to proper values. 1673 */ 1674 bcopy(fxp_cb_config_template, 1675 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1676 sizeof(fxp_cb_config_template)); 1677 1678 cbp->cb_status = 0; 1679 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1680 cbp->link_addr = -1; /* (no) next command */ 1681 cbp->byte_count = 22; /* (22) bytes to config */ 1682 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1683 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1684 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1685 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1686 cbp->type_enable = 0; /* actually reserved */ 1687 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1688 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1689 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1690 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1691 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1692 cbp->late_scb = 0; /* (don't) defer SCB update */ 1693 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1694 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1695 cbp->ci_int = 1; /* interrupt on CU idle */ 1696 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1697 cbp->ext_stats_dis = 1; /* disable extended counters */ 1698 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1699 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1700 cbp->disc_short_rx = !prm; /* discard short packets */ 1701 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1702 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1703 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1704 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1705 cbp->csma_dis = 0; /* (don't) disable link */ 1706 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1707 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1708 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1709 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1710 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1711 cbp->nsai = 1; /* (don't) disable source addr insert */ 1712 cbp->preamble_length = 2; /* (7 byte) preamble */ 1713 cbp->loopback = 0; /* (don't) loopback */ 1714 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1715 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1716 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1717 cbp->promiscuous = prm; /* promiscuous mode */ 1718 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1719 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1720 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1721 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1722 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1723 1724 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1725 cbp->padding = 1; /* (do) pad short tx packets */ 1726 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1727 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1728 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1729 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1730 /* must set wake_en in PMCSR also */ 1731 cbp->force_fdx = 0; /* (don't) force full duplex */ 1732 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1733 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1734 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1735 1736 if (sc->revision == FXP_REV_82557) { 1737 /* 1738 * The 82557 has no hardware flow control, the values 1739 * below are the defaults for the chip. 1740 */ 1741 cbp->fc_delay_lsb = 0; 1742 cbp->fc_delay_msb = 0x40; 1743 cbp->pri_fc_thresh = 3; 1744 cbp->tx_fc_dis = 0; 1745 cbp->rx_fc_restop = 0; 1746 cbp->rx_fc_restart = 0; 1747 cbp->fc_filter = 0; 1748 cbp->pri_fc_loc = 1; 1749 } else { 1750 cbp->fc_delay_lsb = 0x1f; 1751 cbp->fc_delay_msb = 0x01; 1752 cbp->pri_fc_thresh = 3; 1753 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1754 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1755 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1756 cbp->fc_filter = !prm; /* drop FC frames to host */ 1757 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1758 } 1759 1760 /* 1761 * Start the config command/DMA. 1762 */ 1763 fxp_scb_wait(sc); 1764 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1765 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1766 /* ...and wait for it to complete. */ 1767 fxp_dma_wait(&cbp->cb_status, sc); 1768 1769 /* 1770 * Now initialize the station address. Temporarily use the TxCB 1771 * memory area like we did above for the config CB. 1772 */ 1773 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1774 cb_ias->cb_status = 0; 1775 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1776 cb_ias->link_addr = -1; 1777 bcopy(sc->arpcom.ac_enaddr, 1778 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1779 sizeof(sc->arpcom.ac_enaddr)); 1780 1781 /* 1782 * Start the IAS (Individual Address Setup) command/DMA. 1783 */ 1784 fxp_scb_wait(sc); 1785 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1786 /* ...and wait for it to complete. */ 1787 fxp_dma_wait(&cb_ias->cb_status, sc); 1788 1789 /* 1790 * Initialize transmit control block (TxCB) list. 1791 */ 1792 1793 txp = sc->cbl_base; 1794 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1795 for (i = 0; i < FXP_NTXCB; i++) { 1796 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1797 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1798 txp[i].link_addr = 1799 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1800 if (sc->flags & FXP_FLAG_EXT_TXCB) 1801 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1802 else 1803 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1804 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1805 } 1806 /* 1807 * Set the suspend flag on the first TxCB and start the control 1808 * unit. It will execute the NOP and then suspend. 1809 */ 1810 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1811 sc->cbl_first = sc->cbl_last = txp; 1812 sc->tx_queued = 1; 1813 /* XXX set if_timer? */ 1814 1815 fxp_scb_wait(sc); 1816 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1817 1818 /* 1819 * Initialize receiver buffer area - RFA. 1820 */ 1821 fxp_scb_wait(sc); 1822 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1823 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1824 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1825 1826 /* 1827 * Set current media. 1828 */ 1829 if (sc->miibus != NULL) 1830 mii_mediachg(device_get_softc(sc->miibus)); 1831 1832 ifp->if_flags |= IFF_RUNNING; 1833 ifp->if_flags &= ~IFF_OACTIVE; 1834 1835 /* 1836 * Enable interrupts. 1837 */ 1838 #ifdef DEVICE_POLLING 1839 /* 1840 * ... but only do that if we are not polling. And because (presumably) 1841 * the default is interrupts on, we need to disable them explicitly! 1842 */ 1843 if ( ifp->if_flags & IFF_POLLING ) 1844 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1845 else 1846 #endif /* DEVICE_POLLING */ 1847 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1848 1849 /* 1850 * Start stats updater. 1851 */ 1852 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1853 } 1854 1855 static int 1856 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1857 { 1858 1859 return (0); 1860 } 1861 1862 static void 1863 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1864 { 1865 1866 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1867 } 1868 1869 /* 1870 * Change media according to request. 1871 */ 1872 static int 1873 fxp_ifmedia_upd(struct ifnet *ifp) 1874 { 1875 struct fxp_softc *sc = ifp->if_softc; 1876 struct mii_data *mii; 1877 1878 mii = device_get_softc(sc->miibus); 1879 mii_mediachg(mii); 1880 return (0); 1881 } 1882 1883 /* 1884 * Notify the world which media we're using. 1885 */ 1886 static void 1887 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1888 { 1889 struct fxp_softc *sc = ifp->if_softc; 1890 struct mii_data *mii; 1891 1892 mii = device_get_softc(sc->miibus); 1893 mii_pollstat(mii); 1894 ifmr->ifm_active = mii->mii_media_active; 1895 ifmr->ifm_status = mii->mii_media_status; 1896 1897 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1898 sc->cu_resume_bug = 1; 1899 else 1900 sc->cu_resume_bug = 0; 1901 } 1902 1903 /* 1904 * Add a buffer to the end of the RFA buffer list. 1905 * Return 0 if successful, 1 for failure. A failure results in 1906 * adding the 'oldm' (if non-NULL) on to the end of the list - 1907 * tossing out its old contents and recycling it. 1908 * The RFA struct is stuck at the beginning of mbuf cluster and the 1909 * data pointer is fixed up to point just past it. 1910 */ 1911 static int 1912 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1913 { 1914 u_int32_t v; 1915 struct mbuf *m; 1916 struct fxp_rfa *rfa, *p_rfa; 1917 1918 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1919 if (m == NULL) { /* try to recycle the old mbuf instead */ 1920 if (oldm == NULL) 1921 return 1; 1922 m = oldm; 1923 m->m_data = m->m_ext.ext_buf; 1924 } 1925 1926 /* 1927 * Move the data pointer up so that the incoming data packet 1928 * will be 32-bit aligned. 1929 */ 1930 m->m_data += RFA_ALIGNMENT_FUDGE; 1931 1932 /* 1933 * Get a pointer to the base of the mbuf cluster and move 1934 * data start past it. 1935 */ 1936 rfa = mtod(m, struct fxp_rfa *); 1937 m->m_data += sizeof(struct fxp_rfa); 1938 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1939 1940 /* 1941 * Initialize the rest of the RFA. Note that since the RFA 1942 * is misaligned, we cannot store values directly. Instead, 1943 * we use an optimized, inline copy. 1944 */ 1945 1946 rfa->rfa_status = 0; 1947 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1948 rfa->actual_size = 0; 1949 1950 v = -1; 1951 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1952 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1953 1954 /* 1955 * If there are other buffers already on the list, attach this 1956 * one to the end by fixing up the tail to point to this one. 1957 */ 1958 if (sc->rfa_headm != NULL) { 1959 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1960 RFA_ALIGNMENT_FUDGE); 1961 sc->rfa_tailm->m_next = m; 1962 v = vtophys(rfa); 1963 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1964 p_rfa->rfa_control = 0; 1965 } else { 1966 sc->rfa_headm = m; 1967 } 1968 sc->rfa_tailm = m; 1969 1970 return (m == oldm); 1971 } 1972 1973 static int 1974 fxp_miibus_readreg(device_t dev, int phy, int reg) 1975 { 1976 struct fxp_softc *sc = device_get_softc(dev); 1977 int count = 10000; 1978 int value; 1979 1980 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1981 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1982 1983 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1984 && count--) 1985 DELAY(10); 1986 1987 if (count <= 0) 1988 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1989 1990 return (value & 0xffff); 1991 } 1992 1993 static void 1994 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1995 { 1996 struct fxp_softc *sc = device_get_softc(dev); 1997 int count = 10000; 1998 1999 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2000 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2001 (value & 0xffff)); 2002 2003 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2004 count--) 2005 DELAY(10); 2006 2007 if (count <= 0) 2008 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2009 } 2010 2011 static int 2012 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2013 { 2014 struct fxp_softc *sc = ifp->if_softc; 2015 struct ifreq *ifr = (struct ifreq *)data; 2016 struct mii_data *mii; 2017 int error = 0; 2018 2019 switch (command) { 2020 2021 case SIOCSIFFLAGS: 2022 if (ifp->if_flags & IFF_ALLMULTI) 2023 sc->flags |= FXP_FLAG_ALL_MCAST; 2024 else 2025 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2026 2027 /* 2028 * If interface is marked up and not running, then start it. 2029 * If it is marked down and running, stop it. 2030 * XXX If it's up then re-initialize it. This is so flags 2031 * such as IFF_PROMISC are handled. 2032 */ 2033 if (ifp->if_flags & IFF_UP) { 2034 fxp_init(sc); 2035 } else { 2036 if (ifp->if_flags & IFF_RUNNING) 2037 fxp_stop(sc); 2038 } 2039 break; 2040 2041 case SIOCADDMULTI: 2042 case SIOCDELMULTI: 2043 if (ifp->if_flags & IFF_ALLMULTI) 2044 sc->flags |= FXP_FLAG_ALL_MCAST; 2045 else 2046 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2047 /* 2048 * Multicast list has changed; set the hardware filter 2049 * accordingly. 2050 */ 2051 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2052 fxp_mc_setup(sc); 2053 /* 2054 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2055 * again rather than else {}. 2056 */ 2057 if (sc->flags & FXP_FLAG_ALL_MCAST) 2058 fxp_init(sc); 2059 error = 0; 2060 break; 2061 2062 case SIOCSIFMEDIA: 2063 case SIOCGIFMEDIA: 2064 if (sc->miibus != NULL) { 2065 mii = device_get_softc(sc->miibus); 2066 error = ifmedia_ioctl(ifp, ifr, 2067 &mii->mii_media, command); 2068 } else { 2069 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2070 } 2071 break; 2072 2073 default: 2074 error = ether_ioctl(ifp, command, data); 2075 break; 2076 } 2077 return (error); 2078 } 2079 2080 /* 2081 * Fill in the multicast address list and return number of entries. 2082 */ 2083 static int 2084 fxp_mc_addrs(struct fxp_softc *sc) 2085 { 2086 struct fxp_cb_mcs *mcsp = sc->mcsp; 2087 struct ifnet *ifp = &sc->arpcom.ac_if; 2088 struct ifmultiaddr *ifma; 2089 int nmcasts; 2090 2091 nmcasts = 0; 2092 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2093 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2094 if (ifma->ifma_addr->sa_family != AF_LINK) 2095 continue; 2096 if (nmcasts >= MAXMCADDR) { 2097 sc->flags |= FXP_FLAG_ALL_MCAST; 2098 nmcasts = 0; 2099 break; 2100 } 2101 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2102 (void *)(uintptr_t)(volatile void *) 2103 &sc->mcsp->mc_addr[nmcasts][0], 6); 2104 nmcasts++; 2105 } 2106 } 2107 mcsp->mc_cnt = nmcasts * 6; 2108 return (nmcasts); 2109 } 2110 2111 /* 2112 * Program the multicast filter. 2113 * 2114 * We have an artificial restriction that the multicast setup command 2115 * must be the first command in the chain, so we take steps to ensure 2116 * this. By requiring this, it allows us to keep up the performance of 2117 * the pre-initialized command ring (esp. link pointers) by not actually 2118 * inserting the mcsetup command in the ring - i.e. its link pointer 2119 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2120 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2121 * lead into the regular TxCB ring when it completes. 2122 * 2123 * This function must be called at splimp. 2124 */ 2125 static void 2126 fxp_mc_setup(struct fxp_softc *sc) 2127 { 2128 struct fxp_cb_mcs *mcsp = sc->mcsp; 2129 struct ifnet *ifp = &sc->arpcom.ac_if; 2130 int count; 2131 2132 /* 2133 * If there are queued commands, we must wait until they are all 2134 * completed. If we are already waiting, then add a NOP command 2135 * with interrupt option so that we're notified when all commands 2136 * have been completed - fxp_start() ensures that no additional 2137 * TX commands will be added when need_mcsetup is true. 2138 */ 2139 if (sc->tx_queued) { 2140 struct fxp_cb_tx *txp; 2141 2142 /* 2143 * need_mcsetup will be true if we are already waiting for the 2144 * NOP command to be completed (see below). In this case, bail. 2145 */ 2146 if (sc->need_mcsetup) 2147 return; 2148 sc->need_mcsetup = 1; 2149 2150 /* 2151 * Add a NOP command with interrupt so that we are notified 2152 * when all TX commands have been processed. 2153 */ 2154 txp = sc->cbl_last->next; 2155 txp->mb_head = NULL; 2156 txp->cb_status = 0; 2157 txp->cb_command = FXP_CB_COMMAND_NOP | 2158 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2159 /* 2160 * Advance the end of list forward. 2161 */ 2162 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2163 sc->cbl_last = txp; 2164 sc->tx_queued++; 2165 /* 2166 * Issue a resume in case the CU has just suspended. 2167 */ 2168 fxp_scb_wait(sc); 2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2170 /* 2171 * Set a 5 second timer just in case we don't hear from the 2172 * card again. 2173 */ 2174 ifp->if_timer = 5; 2175 2176 return; 2177 } 2178 sc->need_mcsetup = 0; 2179 2180 /* 2181 * Initialize multicast setup descriptor. 2182 */ 2183 mcsp->next = sc->cbl_base; 2184 mcsp->mb_head = NULL; 2185 mcsp->cb_status = 0; 2186 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2187 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2188 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2189 fxp_mc_addrs(sc); 2190 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2191 sc->tx_queued = 1; 2192 2193 /* 2194 * Wait until command unit is not active. This should never 2195 * be the case when nothing is queued, but make sure anyway. 2196 */ 2197 count = 100; 2198 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2199 FXP_SCB_CUS_ACTIVE && --count) 2200 DELAY(10); 2201 if (count == 0) { 2202 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2203 return; 2204 } 2205 2206 /* 2207 * Start the multicast setup command. 2208 */ 2209 fxp_scb_wait(sc); 2210 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2211 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2212 2213 ifp->if_timer = 2; 2214 return; 2215 } 2216 2217 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2218 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2219 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2220 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2221 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2222 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2223 2224 #define UCODE(x) x, sizeof(x) 2225 2226 struct ucode { 2227 u_int32_t revision; 2228 u_int32_t *ucode; 2229 int length; 2230 u_short int_delay_offset; 2231 u_short bundle_max_offset; 2232 } ucode_table[] = { 2233 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2234 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2235 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2236 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2237 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2238 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2239 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2240 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2241 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2242 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2243 { 0, NULL, 0, 0, 0 } 2244 }; 2245 2246 static void 2247 fxp_load_ucode(struct fxp_softc *sc) 2248 { 2249 struct ucode *uc; 2250 struct fxp_cb_ucode *cbp; 2251 2252 for (uc = ucode_table; uc->ucode != NULL; uc++) 2253 if (sc->revision == uc->revision) 2254 break; 2255 if (uc->ucode == NULL) 2256 return; 2257 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2258 cbp->cb_status = 0; 2259 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2260 cbp->link_addr = -1; /* (no) next command */ 2261 memcpy(cbp->ucode, uc->ucode, uc->length); 2262 if (uc->int_delay_offset) 2263 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2264 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2265 if (uc->bundle_max_offset) 2266 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2267 sc->tunable_bundle_max; 2268 /* 2269 * Download the ucode to the chip. 2270 */ 2271 fxp_scb_wait(sc); 2272 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2273 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2274 /* ...and wait for it to complete. */ 2275 fxp_dma_wait(&cbp->cb_status, sc); 2276 if_printf(&sc->arpcom.ac_if, 2277 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2278 sc->tunable_int_delay, 2279 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2280 sc->flags |= FXP_FLAG_UCODE; 2281 } 2282 2283 static int 2284 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2285 { 2286 int error, value; 2287 2288 value = *(int *)arg1; 2289 error = sysctl_handle_int(oidp, &value, 0, req); 2290 if (error || !req->newptr) 2291 return (error); 2292 if (value < low || value > high) 2293 return (EINVAL); 2294 *(int *)arg1 = value; 2295 return (0); 2296 } 2297 2298 /* 2299 * Interrupt delay is expressed in microseconds, a multiplier is used 2300 * to convert this to the appropriate clock ticks before using. 2301 */ 2302 static int 2303 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2304 { 2305 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2306 } 2307 2308 static int 2309 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2310 { 2311 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2312 } 2313