1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.33 2005/05/31 08:30:14 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 170 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 176 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 180 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 185 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 186 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 187 { 0, -1, NULL }, 188 }; 189 190 static int fxp_probe(device_t dev); 191 static int fxp_attach(device_t dev); 192 static int fxp_detach(device_t dev); 193 static int fxp_shutdown(device_t dev); 194 static int fxp_suspend(device_t dev); 195 static int fxp_resume(device_t dev); 196 197 static void fxp_intr(void *xsc); 198 static void fxp_intr_body(struct fxp_softc *sc, 199 u_int8_t statack, int count); 200 201 static void fxp_init(void *xsc); 202 static void fxp_tick(void *xsc); 203 static void fxp_powerstate_d0(device_t dev); 204 static void fxp_start(struct ifnet *ifp); 205 static void fxp_stop(struct fxp_softc *sc); 206 static void fxp_release(device_t dev); 207 static int fxp_ioctl(struct ifnet *ifp, u_long command, 208 caddr_t data, struct ucred *); 209 static void fxp_watchdog(struct ifnet *ifp); 210 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 211 static int fxp_mc_addrs(struct fxp_softc *sc); 212 static void fxp_mc_setup(struct fxp_softc *sc); 213 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 214 int autosize); 215 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 216 u_int16_t data); 217 static void fxp_autosize_eeprom(struct fxp_softc *sc); 218 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 219 int offset, int words); 220 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 221 int offset, int words); 222 static int fxp_ifmedia_upd(struct ifnet *ifp); 223 static void fxp_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 226 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 227 struct ifmediareq *ifmr); 228 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 229 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 230 int value); 231 static void fxp_load_ucode(struct fxp_softc *sc); 232 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 233 int low, int high); 234 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 235 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 236 #ifdef DEVICE_POLLING 237 static poll_handler_t fxp_poll; 238 #endif 239 240 static void fxp_lwcopy(volatile u_int32_t *src, 241 volatile u_int32_t *dst); 242 static void fxp_scb_wait(struct fxp_softc *sc); 243 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 244 static void fxp_dma_wait(volatile u_int16_t *status, 245 struct fxp_softc *sc); 246 247 static device_method_t fxp_methods[] = { 248 /* Device interface */ 249 DEVMETHOD(device_probe, fxp_probe), 250 DEVMETHOD(device_attach, fxp_attach), 251 DEVMETHOD(device_detach, fxp_detach), 252 DEVMETHOD(device_shutdown, fxp_shutdown), 253 DEVMETHOD(device_suspend, fxp_suspend), 254 DEVMETHOD(device_resume, fxp_resume), 255 256 /* MII interface */ 257 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 258 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 259 260 { 0, 0 } 261 }; 262 263 static driver_t fxp_driver = { 264 "fxp", 265 fxp_methods, 266 sizeof(struct fxp_softc), 267 }; 268 269 static devclass_t fxp_devclass; 270 271 DECLARE_DUMMY_MODULE(if_fxp); 272 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 273 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 274 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 275 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 276 277 static int fxp_rnr; 278 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 279 280 /* 281 * Copy a 16-bit aligned 32-bit quantity. 282 */ 283 static void 284 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 285 { 286 #ifdef __i386__ 287 *dst = *src; 288 #else 289 volatile u_int16_t *a = (volatile u_int16_t *)src; 290 volatile u_int16_t *b = (volatile u_int16_t *)dst; 291 292 b[0] = a[0]; 293 b[1] = a[1]; 294 #endif 295 } 296 297 /* 298 * Wait for the previous command to be accepted (but not necessarily 299 * completed). 300 */ 301 static void 302 fxp_scb_wait(struct fxp_softc *sc) 303 { 304 int i = 10000; 305 306 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 307 DELAY(2); 308 if (i == 0) { 309 if_printf(&sc->arpcom.ac_if, 310 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 311 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 312 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 313 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 314 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 315 } 316 } 317 318 static void 319 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 320 { 321 322 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 323 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 324 fxp_scb_wait(sc); 325 } 326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 327 } 328 329 static void 330 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 331 { 332 int i = 10000; 333 334 while (!(*status & FXP_CB_STATUS_C) && --i) 335 DELAY(2); 336 if (i == 0) 337 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 338 } 339 340 /* 341 * Return identification string if this is device is ours. 342 */ 343 static int 344 fxp_probe(device_t dev) 345 { 346 u_int16_t devid; 347 u_int8_t revid; 348 struct fxp_ident *ident; 349 350 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 351 devid = pci_get_device(dev); 352 revid = pci_get_revid(dev); 353 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 354 if (ident->devid == devid && 355 (ident->revid == revid || ident->revid == -1)) { 356 device_set_desc(dev, ident->name); 357 return (0); 358 } 359 } 360 } 361 return (ENXIO); 362 } 363 364 static void 365 fxp_powerstate_d0(device_t dev) 366 { 367 u_int32_t iobase, membase, irq; 368 369 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 370 /* Save important PCI config data. */ 371 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 372 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 373 irq = pci_read_config(dev, PCIR_INTLINE, 4); 374 375 /* Reset the power state. */ 376 device_printf(dev, "chip is in D%d power mode " 377 "-- setting to D0\n", pci_get_powerstate(dev)); 378 379 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 380 381 /* Restore PCI config data. */ 382 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 383 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 384 pci_write_config(dev, PCIR_INTLINE, irq, 4); 385 } 386 } 387 388 static int 389 fxp_attach(device_t dev) 390 { 391 int error = 0; 392 struct fxp_softc *sc = device_get_softc(dev); 393 struct ifnet *ifp; 394 u_int32_t val; 395 u_int16_t data; 396 int i, rid, m1, m2, prefer_iomap; 397 int s; 398 399 callout_init(&sc->fxp_stat_timer); 400 sysctl_ctx_init(&sc->sysctl_ctx); 401 402 s = splimp(); 403 404 /* 405 * Enable bus mastering. Enable memory space too, in case 406 * BIOS/Prom forgot about it. 407 */ 408 pci_enable_busmaster(dev); 409 pci_enable_io(dev, SYS_RES_MEMORY); 410 val = pci_read_config(dev, PCIR_COMMAND, 2); 411 412 fxp_powerstate_d0(dev); 413 414 /* 415 * Figure out which we should try first - memory mapping or i/o mapping? 416 * We default to memory mapping. Then we accept an override from the 417 * command line. Then we check to see which one is enabled. 418 */ 419 m1 = PCIM_CMD_MEMEN; 420 m2 = PCIM_CMD_PORTEN; 421 prefer_iomap = 0; 422 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 423 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 424 m1 = PCIM_CMD_PORTEN; 425 m2 = PCIM_CMD_MEMEN; 426 } 427 428 if (val & m1) { 429 sc->rtp = 430 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 431 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 432 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 433 RF_ACTIVE); 434 } 435 if (sc->mem == NULL && (val & m2)) { 436 sc->rtp = 437 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 438 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 439 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 440 RF_ACTIVE); 441 } 442 443 if (!sc->mem) { 444 device_printf(dev, "could not map device registers\n"); 445 error = ENXIO; 446 goto fail; 447 } 448 if (bootverbose) { 449 device_printf(dev, "using %s space register mapping\n", 450 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 451 } 452 453 sc->sc_st = rman_get_bustag(sc->mem); 454 sc->sc_sh = rman_get_bushandle(sc->mem); 455 456 /* 457 * Allocate our interrupt. 458 */ 459 rid = 0; 460 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 461 RF_SHAREABLE | RF_ACTIVE); 462 if (sc->irq == NULL) { 463 device_printf(dev, "could not map interrupt\n"); 464 error = ENXIO; 465 goto fail; 466 } 467 468 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 469 fxp_intr, sc, &sc->ih, NULL); 470 if (error) { 471 device_printf(dev, "could not setup irq\n"); 472 goto fail; 473 } 474 475 /* 476 * Reset to a stable state. 477 */ 478 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 479 DELAY(10); 480 481 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 482 M_DEVBUF, M_WAITOK | M_ZERO); 483 484 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 485 M_WAITOK | M_ZERO); 486 487 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 488 489 /* 490 * Pre-allocate our receive buffers. 491 */ 492 for (i = 0; i < FXP_NRFABUFS; i++) { 493 if (fxp_add_rfabuf(sc, NULL) != 0) { 494 goto failmem; 495 } 496 } 497 498 /* 499 * Find out how large of an SEEPROM we have. 500 */ 501 fxp_autosize_eeprom(sc); 502 503 /* 504 * Determine whether we must use the 503 serial interface. 505 */ 506 fxp_read_eeprom(sc, &data, 6, 1); 507 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 508 (data & FXP_PHY_SERIAL_ONLY)) 509 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 510 511 /* 512 * Create the sysctl tree 513 */ 514 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 515 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 516 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 517 if (sc->sysctl_tree == NULL) 518 goto fail; 519 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 520 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 521 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 522 "FXP driver receive interrupt microcode bundling delay"); 523 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 524 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 525 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 526 "FXP driver receive interrupt microcode bundle size limit"); 527 528 /* 529 * Pull in device tunables. 530 */ 531 sc->tunable_int_delay = TUNABLE_INT_DELAY; 532 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "int_delay", &sc->tunable_int_delay); 535 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 536 "bundle_max", &sc->tunable_bundle_max); 537 538 /* 539 * Find out the chip revision; lump all 82557 revs together. 540 */ 541 fxp_read_eeprom(sc, &data, 5, 1); 542 if ((data >> 8) == 1) 543 sc->revision = FXP_REV_82557; 544 else 545 sc->revision = pci_get_revid(dev); 546 547 /* 548 * Enable workarounds for certain chip revision deficiencies. 549 * 550 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 551 * some systems based a normal 82559 design, have a defect where 552 * the chip can cause a PCI protocol violation if it receives 553 * a CU_RESUME command when it is entering the IDLE state. The 554 * workaround is to disable Dynamic Standby Mode, so the chip never 555 * deasserts CLKRUN#, and always remains in an active state. 556 * 557 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 558 */ 559 i = pci_get_device(dev); 560 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 561 sc->revision >= FXP_REV_82559_A0) { 562 fxp_read_eeprom(sc, &data, 10, 1); 563 if (data & 0x02) { /* STB enable */ 564 u_int16_t cksum; 565 int i; 566 567 device_printf(dev, 568 "Disabling dynamic standby mode in EEPROM\n"); 569 data &= ~0x02; 570 fxp_write_eeprom(sc, &data, 10, 1); 571 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 572 cksum = 0; 573 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 574 fxp_read_eeprom(sc, &data, i, 1); 575 cksum += data; 576 } 577 i = (1 << sc->eeprom_size) - 1; 578 cksum = 0xBABA - cksum; 579 fxp_read_eeprom(sc, &data, i, 1); 580 fxp_write_eeprom(sc, &cksum, i, 1); 581 device_printf(dev, 582 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 583 i, data, cksum); 584 #if 1 585 /* 586 * If the user elects to continue, try the software 587 * workaround, as it is better than nothing. 588 */ 589 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 590 #endif 591 } 592 } 593 594 /* 595 * If we are not a 82557 chip, we can enable extended features. 596 */ 597 if (sc->revision != FXP_REV_82557) { 598 /* 599 * If MWI is enabled in the PCI configuration, and there 600 * is a valid cacheline size (8 or 16 dwords), then tell 601 * the board to turn on MWI. 602 */ 603 if (val & PCIM_CMD_MWRICEN && 604 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 605 sc->flags |= FXP_FLAG_MWI_ENABLE; 606 607 /* turn on the extended TxCB feature */ 608 sc->flags |= FXP_FLAG_EXT_TXCB; 609 610 /* enable reception of long frames for VLAN */ 611 sc->flags |= FXP_FLAG_LONG_PKT_EN; 612 } 613 614 /* 615 * Read MAC address. 616 */ 617 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 618 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 619 device_printf(dev, "10Mbps\n"); 620 if (bootverbose) { 621 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 622 pci_get_vendor(dev), pci_get_device(dev), 623 pci_get_subvendor(dev), pci_get_subdevice(dev), 624 pci_get_revid(dev)); 625 fxp_read_eeprom(sc, &data, 10, 1); 626 device_printf(dev, "Dynamic Standby mode is %s\n", 627 data & 0x02 ? "enabled" : "disabled"); 628 } 629 630 /* 631 * If this is only a 10Mbps device, then there is no MII, and 632 * the PHY will use a serial interface instead. 633 * 634 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 635 * doesn't have a programming interface of any sort. The 636 * media is sensed automatically based on how the link partner 637 * is configured. This is, in essence, manual configuration. 638 */ 639 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 640 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 641 fxp_serial_ifmedia_sts); 642 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 643 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 644 } else { 645 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 646 fxp_ifmedia_sts)) { 647 device_printf(dev, "MII without any PHY!\n"); 648 error = ENXIO; 649 goto fail; 650 } 651 } 652 653 ifp = &sc->arpcom.ac_if; 654 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 655 ifp->if_baudrate = 100000000; 656 ifp->if_init = fxp_init; 657 ifp->if_softc = sc; 658 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 659 ifp->if_ioctl = fxp_ioctl; 660 ifp->if_start = fxp_start; 661 #ifdef DEVICE_POLLING 662 ifp->if_poll = fxp_poll; 663 #endif 664 ifp->if_watchdog = fxp_watchdog; 665 666 /* 667 * Attach the interface. 668 */ 669 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 670 671 /* 672 * Tell the upper layer(s) we support long frames. 673 */ 674 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 675 676 /* 677 * Let the system queue as many packets as we have available 678 * TX descriptors. 679 */ 680 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 681 ifq_set_ready(&ifp->if_snd); 682 683 splx(s); 684 return (0); 685 686 failmem: 687 device_printf(dev, "Failed to malloc memory\n"); 688 error = ENOMEM; 689 fail: 690 splx(s); 691 fxp_release(dev); 692 return (error); 693 } 694 695 /* 696 * release all resources 697 */ 698 static void 699 fxp_release(device_t dev) 700 { 701 struct fxp_softc *sc; 702 703 sc = device_get_softc(dev); 704 bus_generic_detach(dev); 705 if (sc->miibus) 706 device_delete_child(dev, sc->miibus); 707 708 if (sc->cbl_base) 709 free(sc->cbl_base, M_DEVBUF); 710 if (sc->fxp_stats) 711 free(sc->fxp_stats, M_DEVBUF); 712 if (sc->mcsp) 713 free(sc->mcsp, M_DEVBUF); 714 if (sc->rfa_headm) 715 m_freem(sc->rfa_headm); 716 717 if (sc->ih) 718 bus_teardown_intr(dev, sc->irq, sc->ih); 719 if (sc->irq) 720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 721 if (sc->mem) 722 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 723 724 sysctl_ctx_free(&sc->sysctl_ctx); 725 } 726 727 /* 728 * Detach interface. 729 */ 730 static int 731 fxp_detach(device_t dev) 732 { 733 struct fxp_softc *sc = device_get_softc(dev); 734 int s; 735 736 /* disable interrupts */ 737 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 738 739 s = splimp(); 740 741 /* 742 * Stop DMA and drop transmit queue. 743 */ 744 fxp_stop(sc); 745 746 /* 747 * Close down routes etc. 748 */ 749 ether_ifdetach(&sc->arpcom.ac_if); 750 751 /* 752 * Free all media structures. 753 */ 754 ifmedia_removeall(&sc->sc_media); 755 756 splx(s); 757 758 /* Release our allocated resources. */ 759 fxp_release(dev); 760 761 return (0); 762 } 763 764 /* 765 * Device shutdown routine. Called at system shutdown after sync. The 766 * main purpose of this routine is to shut off receiver DMA so that 767 * kernel memory doesn't get clobbered during warmboot. 768 */ 769 static int 770 fxp_shutdown(device_t dev) 771 { 772 /* 773 * Make sure that DMA is disabled prior to reboot. Not doing 774 * do could allow DMA to corrupt kernel memory during the 775 * reboot before the driver initializes. 776 */ 777 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 778 return (0); 779 } 780 781 /* 782 * Device suspend routine. Stop the interface and save some PCI 783 * settings in case the BIOS doesn't restore them properly on 784 * resume. 785 */ 786 static int 787 fxp_suspend(device_t dev) 788 { 789 struct fxp_softc *sc = device_get_softc(dev); 790 int i, s; 791 792 s = splimp(); 793 794 fxp_stop(sc); 795 796 for (i = 0; i < 5; i++) 797 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 798 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 799 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 800 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 801 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 802 803 sc->suspended = 1; 804 805 splx(s); 806 return (0); 807 } 808 809 /* 810 * Device resume routine. Restore some PCI settings in case the BIOS 811 * doesn't, re-enable busmastering, and restart the interface if 812 * appropriate. 813 */ 814 static int 815 fxp_resume(device_t dev) 816 { 817 struct fxp_softc *sc = device_get_softc(dev); 818 struct ifnet *ifp = &sc->arpcom.ac_if; 819 int i, s; 820 821 s = splimp(); 822 823 fxp_powerstate_d0(dev); 824 825 /* better way to do this? */ 826 for (i = 0; i < 5; i++) 827 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 828 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 829 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 830 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 831 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 832 833 /* reenable busmastering and memory space */ 834 pci_enable_busmaster(dev); 835 pci_enable_io(dev, SYS_RES_MEMORY); 836 837 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 838 DELAY(10); 839 840 /* reinitialize interface if necessary */ 841 if (ifp->if_flags & IFF_UP) 842 fxp_init(sc); 843 844 sc->suspended = 0; 845 846 splx(s); 847 return (0); 848 } 849 850 static void 851 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 852 { 853 u_int16_t reg; 854 int x; 855 856 /* 857 * Shift in data. 858 */ 859 for (x = 1 << (length - 1); x; x >>= 1) { 860 if (data & x) 861 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 862 else 863 reg = FXP_EEPROM_EECS; 864 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 865 DELAY(1); 866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 867 DELAY(1); 868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 869 DELAY(1); 870 } 871 } 872 873 /* 874 * Read from the serial EEPROM. Basically, you manually shift in 875 * the read opcode (one bit at a time) and then shift in the address, 876 * and then you shift out the data (all of this one bit at a time). 877 * The word size is 16 bits, so you have to provide the address for 878 * every 16 bits of data. 879 */ 880 static u_int16_t 881 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 882 { 883 u_int16_t reg, data; 884 int x; 885 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 887 /* 888 * Shift in read opcode. 889 */ 890 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 891 /* 892 * Shift in address. 893 */ 894 data = 0; 895 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 896 if (offset & x) 897 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 898 else 899 reg = FXP_EEPROM_EECS; 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 901 DELAY(1); 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 903 DELAY(1); 904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 905 DELAY(1); 906 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 907 data++; 908 if (autosize && reg == 0) { 909 sc->eeprom_size = data; 910 break; 911 } 912 } 913 /* 914 * Shift out data. 915 */ 916 data = 0; 917 reg = FXP_EEPROM_EECS; 918 for (x = 1 << 15; x; x >>= 1) { 919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 920 DELAY(1); 921 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 922 data |= x; 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 924 DELAY(1); 925 } 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 927 DELAY(1); 928 929 return (data); 930 } 931 932 static void 933 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 934 { 935 int i; 936 937 /* 938 * Erase/write enable. 939 */ 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 941 fxp_eeprom_shiftin(sc, 0x4, 3); 942 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 944 DELAY(1); 945 /* 946 * Shift in write opcode, address, data. 947 */ 948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 949 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 950 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 951 fxp_eeprom_shiftin(sc, data, 16); 952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 953 DELAY(1); 954 /* 955 * Wait for EEPROM to finish up. 956 */ 957 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 958 DELAY(1); 959 for (i = 0; i < 1000; i++) { 960 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 961 break; 962 DELAY(50); 963 } 964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 965 DELAY(1); 966 /* 967 * Erase/write disable. 968 */ 969 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 970 fxp_eeprom_shiftin(sc, 0x4, 3); 971 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 973 DELAY(1); 974 } 975 976 /* 977 * From NetBSD: 978 * 979 * Figure out EEPROM size. 980 * 981 * 559's can have either 64-word or 256-word EEPROMs, the 558 982 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 983 * talks about the existance of 16 to 256 word EEPROMs. 984 * 985 * The only known sizes are 64 and 256, where the 256 version is used 986 * by CardBus cards to store CIS information. 987 * 988 * The address is shifted in msb-to-lsb, and after the last 989 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 990 * after which follows the actual data. We try to detect this zero, by 991 * probing the data-out bit in the EEPROM control register just after 992 * having shifted in a bit. If the bit is zero, we assume we've 993 * shifted enough address bits. The data-out should be tri-state, 994 * before this, which should translate to a logical one. 995 */ 996 static void 997 fxp_autosize_eeprom(struct fxp_softc *sc) 998 { 999 1000 /* guess maximum size of 256 words */ 1001 sc->eeprom_size = 8; 1002 1003 /* autosize */ 1004 (void) fxp_eeprom_getword(sc, 0, 1); 1005 } 1006 1007 static void 1008 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1009 { 1010 int i; 1011 1012 for (i = 0; i < words; i++) 1013 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1014 } 1015 1016 static void 1017 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1018 { 1019 int i; 1020 1021 for (i = 0; i < words; i++) 1022 fxp_eeprom_putword(sc, offset + i, data[i]); 1023 } 1024 1025 /* 1026 * Start packet transmission on the interface. 1027 */ 1028 static void 1029 fxp_start(struct ifnet *ifp) 1030 { 1031 struct fxp_softc *sc = ifp->if_softc; 1032 struct fxp_cb_tx *txp; 1033 1034 /* 1035 * See if we need to suspend xmit until the multicast filter 1036 * has been reprogrammed (which can only be done at the head 1037 * of the command chain). 1038 */ 1039 if (sc->need_mcsetup) { 1040 return; 1041 } 1042 1043 txp = NULL; 1044 1045 /* 1046 * We're finished if there is nothing more to add to the list or if 1047 * we're all filled up with buffers to transmit. 1048 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1049 * a NOP command when needed. 1050 */ 1051 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1052 struct mbuf *m, *mb_head; 1053 int segment, ntries = 0; 1054 1055 /* 1056 * Grab a packet to transmit. The packet is dequeued, 1057 * once we are sure that we have enough free descriptors. 1058 */ 1059 mb_head = ifq_poll(&ifp->if_snd); 1060 if (mb_head == NULL) 1061 break; 1062 1063 /* 1064 * Get pointer to next available tx desc. 1065 */ 1066 txp = sc->cbl_last->next; 1067 1068 /* 1069 * Go through each of the mbufs in the chain and initialize 1070 * the transmit buffer descriptors with the physical address 1071 * and size of the mbuf. 1072 */ 1073 tbdinit: 1074 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1075 if (m->m_len != 0) { 1076 if (segment == FXP_NTXSEG) 1077 break; 1078 txp->tbd[segment].tb_addr = 1079 vtophys(mtod(m, vm_offset_t)); 1080 txp->tbd[segment].tb_size = m->m_len; 1081 segment++; 1082 } 1083 } 1084 if (m != NULL) { 1085 struct mbuf *mn; 1086 1087 /* 1088 * We ran out of segments. We have to recopy this 1089 * mbuf chain first. Bail out if we can't get the 1090 * new buffers. 1091 */ 1092 if (ntries > 0) 1093 break; 1094 mn = m_dup(mb_head, MB_DONTWAIT); 1095 if (mn == NULL) 1096 break; 1097 /* We can transmit the packet, dequeue it. */ 1098 mb_head = ifq_dequeue(&ifp->if_snd); 1099 m_freem(mb_head); 1100 mb_head = mn; 1101 ntries = 1; 1102 goto tbdinit; 1103 } else { 1104 /* Nothing to worry about, just dequeue. */ 1105 mb_head = ifq_dequeue(&ifp->if_snd); 1106 } 1107 1108 txp->tbd_number = segment; 1109 txp->mb_head = mb_head; 1110 txp->cb_status = 0; 1111 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1112 txp->cb_command = 1113 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1114 FXP_CB_COMMAND_S; 1115 } else { 1116 txp->cb_command = 1117 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1118 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1119 /* 1120 * Set a 5 second timer just in case we don't hear 1121 * from the card again. 1122 */ 1123 ifp->if_timer = 5; 1124 } 1125 txp->tx_threshold = tx_threshold; 1126 1127 /* 1128 * Advance the end of list forward. 1129 */ 1130 1131 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1132 sc->cbl_last = txp; 1133 1134 /* 1135 * Advance the beginning of the list forward if there are 1136 * no other packets queued (when nothing is queued, cbl_first 1137 * sits on the last TxCB that was sent out). 1138 */ 1139 if (sc->tx_queued == 0) 1140 sc->cbl_first = txp; 1141 1142 sc->tx_queued++; 1143 1144 BPF_MTAP(ifp, mb_head); 1145 } 1146 1147 /* 1148 * We're finished. If we added to the list, issue a RESUME to get DMA 1149 * going again if suspended. 1150 */ 1151 if (txp != NULL) { 1152 fxp_scb_wait(sc); 1153 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1154 } 1155 } 1156 1157 #ifdef DEVICE_POLLING 1158 1159 static void 1160 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1161 { 1162 struct fxp_softc *sc = ifp->if_softc; 1163 u_int8_t statack; 1164 1165 switch(cmd) { 1166 case POLL_REGISTER: 1167 /* disable interrupts */ 1168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1169 break; 1170 case POLL_DEREGISTER: 1171 /* enable interrupts */ 1172 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1173 break; 1174 default: 1175 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1176 FXP_SCB_STATACK_FR; 1177 if (cmd == POLL_AND_CHECK_STATUS) { 1178 u_int8_t tmp; 1179 1180 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1181 if (tmp == 0xff || tmp == 0) 1182 return; /* nothing to do */ 1183 tmp &= ~statack; 1184 /* ack what we can */ 1185 if (tmp != 0) 1186 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1187 statack |= tmp; 1188 } 1189 fxp_intr_body(sc, statack, count); 1190 break; 1191 } 1192 } 1193 1194 #endif /* DEVICE_POLLING */ 1195 1196 /* 1197 * Process interface interrupts. 1198 */ 1199 static void 1200 fxp_intr(void *xsc) 1201 { 1202 struct fxp_softc *sc = xsc; 1203 u_int8_t statack; 1204 1205 if (sc->suspended) { 1206 return; 1207 } 1208 1209 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1210 /* 1211 * It should not be possible to have all bits set; the 1212 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1213 * all bits are set, this may indicate that the card has 1214 * been physically ejected, so ignore it. 1215 */ 1216 if (statack == 0xff) 1217 return; 1218 1219 /* 1220 * First ACK all the interrupts in this pass. 1221 */ 1222 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1223 fxp_intr_body(sc, statack, -1); 1224 } 1225 } 1226 1227 static void 1228 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1229 { 1230 struct ifnet *ifp = &sc->arpcom.ac_if; 1231 struct mbuf *m; 1232 struct fxp_rfa *rfa; 1233 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1234 1235 if (rnr) 1236 fxp_rnr++; 1237 #ifdef DEVICE_POLLING 1238 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1239 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1240 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1241 rnr = 1; 1242 } 1243 #endif 1244 1245 /* 1246 * Free any finished transmit mbuf chains. 1247 * 1248 * Handle the CNA event likt a CXTNO event. It used to 1249 * be that this event (control unit not ready) was not 1250 * encountered, but it is now with the SMPng modifications. 1251 * The exact sequence of events that occur when the interface 1252 * is brought up are different now, and if this event 1253 * goes unhandled, the configuration/rxfilter setup sequence 1254 * can stall for several seconds. The result is that no 1255 * packets go out onto the wire for about 5 to 10 seconds 1256 * after the interface is ifconfig'ed for the first time. 1257 */ 1258 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1259 struct fxp_cb_tx *txp; 1260 1261 for (txp = sc->cbl_first; sc->tx_queued && 1262 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1263 txp = txp->next) { 1264 if ((m = txp->mb_head) != NULL) { 1265 txp->mb_head = NULL; 1266 sc->tx_queued--; 1267 m_freem(m); 1268 } else { 1269 sc->tx_queued--; 1270 } 1271 } 1272 sc->cbl_first = txp; 1273 ifp->if_timer = 0; 1274 if (sc->tx_queued == 0) { 1275 if (sc->need_mcsetup) 1276 fxp_mc_setup(sc); 1277 } 1278 /* 1279 * Try to start more packets transmitting. 1280 */ 1281 if (!ifq_is_empty(&ifp->if_snd)) 1282 (*ifp->if_start)(ifp); 1283 } 1284 1285 /* 1286 * Just return if nothing happened on the receive side. 1287 */ 1288 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1289 return; 1290 1291 /* 1292 * Process receiver interrupts. If a no-resource (RNR) 1293 * condition exists, get whatever packets we can and 1294 * re-start the receiver. 1295 * 1296 * When using polling, we do not process the list to completion, 1297 * so when we get an RNR interrupt we must defer the restart 1298 * until we hit the last buffer with the C bit set. 1299 * If we run out of cycles and rfa_headm has the C bit set, 1300 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1301 * that the info will be used in the subsequent polling cycle. 1302 */ 1303 for (;;) { 1304 m = sc->rfa_headm; 1305 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1306 RFA_ALIGNMENT_FUDGE); 1307 1308 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1309 if (count >= 0 && count-- == 0) { 1310 if (rnr) { 1311 /* Defer RNR processing until the next time. */ 1312 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1313 rnr = 0; 1314 } 1315 break; 1316 } 1317 #endif /* DEVICE_POLLING */ 1318 1319 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1320 break; 1321 1322 /* 1323 * Remove first packet from the chain. 1324 */ 1325 sc->rfa_headm = m->m_next; 1326 m->m_next = NULL; 1327 1328 /* 1329 * Add a new buffer to the receive chain. 1330 * If this fails, the old buffer is recycled 1331 * instead. 1332 */ 1333 if (fxp_add_rfabuf(sc, m) == 0) { 1334 int total_len; 1335 1336 /* 1337 * Fetch packet length (the top 2 bits of 1338 * actual_size are flags set by the controller 1339 * upon completion), and drop the packet in case 1340 * of bogus length or CRC errors. 1341 */ 1342 total_len = rfa->actual_size & 0x3fff; 1343 if (total_len < sizeof(struct ether_header) || 1344 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1345 sizeof(struct fxp_rfa) || 1346 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1347 m_freem(m); 1348 continue; 1349 } 1350 m->m_pkthdr.len = m->m_len = total_len; 1351 (*ifp->if_input)(ifp, m); 1352 } 1353 } 1354 if (rnr) { 1355 fxp_scb_wait(sc); 1356 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1357 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1358 RFA_ALIGNMENT_FUDGE); 1359 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1360 } 1361 } 1362 1363 /* 1364 * Update packet in/out/collision statistics. The i82557 doesn't 1365 * allow you to access these counters without doing a fairly 1366 * expensive DMA to get _all_ of the statistics it maintains, so 1367 * we do this operation here only once per second. The statistics 1368 * counters in the kernel are updated from the previous dump-stats 1369 * DMA and then a new dump-stats DMA is started. The on-chip 1370 * counters are zeroed when the DMA completes. If we can't start 1371 * the DMA immediately, we don't wait - we just prepare to read 1372 * them again next time. 1373 */ 1374 static void 1375 fxp_tick(void *xsc) 1376 { 1377 struct fxp_softc *sc = xsc; 1378 struct ifnet *ifp = &sc->arpcom.ac_if; 1379 struct fxp_stats *sp = sc->fxp_stats; 1380 struct fxp_cb_tx *txp; 1381 struct mbuf *m; 1382 int s; 1383 1384 ifp->if_opackets += sp->tx_good; 1385 ifp->if_collisions += sp->tx_total_collisions; 1386 if (sp->rx_good) { 1387 ifp->if_ipackets += sp->rx_good; 1388 sc->rx_idle_secs = 0; 1389 } else { 1390 /* 1391 * Receiver's been idle for another second. 1392 */ 1393 sc->rx_idle_secs++; 1394 } 1395 ifp->if_ierrors += 1396 sp->rx_crc_errors + 1397 sp->rx_alignment_errors + 1398 sp->rx_rnr_errors + 1399 sp->rx_overrun_errors; 1400 /* 1401 * If any transmit underruns occured, bump up the transmit 1402 * threshold by another 512 bytes (64 * 8). 1403 */ 1404 if (sp->tx_underruns) { 1405 ifp->if_oerrors += sp->tx_underruns; 1406 if (tx_threshold < 192) 1407 tx_threshold += 64; 1408 } 1409 s = splimp(); 1410 /* 1411 * Release any xmit buffers that have completed DMA. This isn't 1412 * strictly necessary to do here, but it's advantagous for mbufs 1413 * with external storage to be released in a timely manner rather 1414 * than being defered for a potentially long time. This limits 1415 * the delay to a maximum of one second. 1416 */ 1417 for (txp = sc->cbl_first; sc->tx_queued && 1418 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1419 txp = txp->next) { 1420 if ((m = txp->mb_head) != NULL) { 1421 txp->mb_head = NULL; 1422 sc->tx_queued--; 1423 m_freem(m); 1424 } else { 1425 sc->tx_queued--; 1426 } 1427 } 1428 sc->cbl_first = txp; 1429 /* 1430 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1431 * then assume the receiver has locked up and attempt to clear 1432 * the condition by reprogramming the multicast filter. This is 1433 * a work-around for a bug in the 82557 where the receiver locks 1434 * up if it gets certain types of garbage in the syncronization 1435 * bits prior to the packet header. This bug is supposed to only 1436 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1437 * mode as well (perhaps due to a 10/100 speed transition). 1438 */ 1439 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1440 sc->rx_idle_secs = 0; 1441 fxp_mc_setup(sc); 1442 } 1443 /* 1444 * If there is no pending command, start another stats 1445 * dump. Otherwise punt for now. 1446 */ 1447 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1448 /* 1449 * Start another stats dump. 1450 */ 1451 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1452 } else { 1453 /* 1454 * A previous command is still waiting to be accepted. 1455 * Just zero our copy of the stats and wait for the 1456 * next timer event to update them. 1457 */ 1458 sp->tx_good = 0; 1459 sp->tx_underruns = 0; 1460 sp->tx_total_collisions = 0; 1461 1462 sp->rx_good = 0; 1463 sp->rx_crc_errors = 0; 1464 sp->rx_alignment_errors = 0; 1465 sp->rx_rnr_errors = 0; 1466 sp->rx_overrun_errors = 0; 1467 } 1468 if (sc->miibus != NULL) 1469 mii_tick(device_get_softc(sc->miibus)); 1470 splx(s); 1471 /* 1472 * Schedule another timeout one second from now. 1473 */ 1474 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1475 } 1476 1477 /* 1478 * Stop the interface. Cancels the statistics updater and resets 1479 * the interface. 1480 */ 1481 static void 1482 fxp_stop(struct fxp_softc *sc) 1483 { 1484 struct ifnet *ifp = &sc->arpcom.ac_if; 1485 struct fxp_cb_tx *txp; 1486 int i; 1487 1488 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1489 ifp->if_timer = 0; 1490 1491 /* 1492 * Cancel stats updater. 1493 */ 1494 callout_stop(&sc->fxp_stat_timer); 1495 1496 /* 1497 * Issue software reset, which also unloads the microcode. 1498 */ 1499 sc->flags &= ~FXP_FLAG_UCODE; 1500 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1501 DELAY(50); 1502 1503 /* 1504 * Release any xmit buffers. 1505 */ 1506 txp = sc->cbl_base; 1507 if (txp != NULL) { 1508 for (i = 0; i < FXP_NTXCB; i++) { 1509 if (txp[i].mb_head != NULL) { 1510 m_freem(txp[i].mb_head); 1511 txp[i].mb_head = NULL; 1512 } 1513 } 1514 } 1515 sc->tx_queued = 0; 1516 1517 /* 1518 * Free all the receive buffers then reallocate/reinitialize 1519 */ 1520 if (sc->rfa_headm != NULL) 1521 m_freem(sc->rfa_headm); 1522 sc->rfa_headm = NULL; 1523 sc->rfa_tailm = NULL; 1524 for (i = 0; i < FXP_NRFABUFS; i++) { 1525 if (fxp_add_rfabuf(sc, NULL) != 0) { 1526 /* 1527 * This "can't happen" - we're at splimp() 1528 * and we just freed all the buffers we need 1529 * above. 1530 */ 1531 panic("fxp_stop: no buffers!"); 1532 } 1533 } 1534 } 1535 1536 /* 1537 * Watchdog/transmission transmit timeout handler. Called when a 1538 * transmission is started on the interface, but no interrupt is 1539 * received before the timeout. This usually indicates that the 1540 * card has wedged for some reason. 1541 */ 1542 static void 1543 fxp_watchdog(struct ifnet *ifp) 1544 { 1545 if_printf(ifp, "device timeout\n"); 1546 ifp->if_oerrors++; 1547 fxp_init(ifp->if_softc); 1548 } 1549 1550 static void 1551 fxp_init(void *xsc) 1552 { 1553 struct fxp_softc *sc = xsc; 1554 struct ifnet *ifp = &sc->arpcom.ac_if; 1555 struct fxp_cb_config *cbp; 1556 struct fxp_cb_ias *cb_ias; 1557 struct fxp_cb_tx *txp; 1558 struct fxp_cb_mcs *mcsp; 1559 int i, prm, s; 1560 1561 s = splimp(); 1562 /* 1563 * Cancel any pending I/O 1564 */ 1565 fxp_stop(sc); 1566 1567 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1568 1569 /* 1570 * Initialize base of CBL and RFA memory. Loading with zero 1571 * sets it up for regular linear addressing. 1572 */ 1573 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1574 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1575 1576 fxp_scb_wait(sc); 1577 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1578 1579 /* 1580 * Initialize base of dump-stats buffer. 1581 */ 1582 fxp_scb_wait(sc); 1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1585 1586 /* 1587 * Attempt to load microcode if requested. 1588 */ 1589 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1590 fxp_load_ucode(sc); 1591 1592 /* 1593 * Initialize the multicast address list. 1594 */ 1595 if (fxp_mc_addrs(sc)) { 1596 mcsp = sc->mcsp; 1597 mcsp->cb_status = 0; 1598 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1599 mcsp->link_addr = -1; 1600 /* 1601 * Start the multicast setup command. 1602 */ 1603 fxp_scb_wait(sc); 1604 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1605 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1606 /* ...and wait for it to complete. */ 1607 fxp_dma_wait(&mcsp->cb_status, sc); 1608 } 1609 1610 /* 1611 * We temporarily use memory that contains the TxCB list to 1612 * construct the config CB. The TxCB list memory is rebuilt 1613 * later. 1614 */ 1615 cbp = (struct fxp_cb_config *) sc->cbl_base; 1616 1617 /* 1618 * This bcopy is kind of disgusting, but there are a bunch of must be 1619 * zero and must be one bits in this structure and this is the easiest 1620 * way to initialize them all to proper values. 1621 */ 1622 bcopy(fxp_cb_config_template, 1623 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1624 sizeof(fxp_cb_config_template)); 1625 1626 cbp->cb_status = 0; 1627 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1628 cbp->link_addr = -1; /* (no) next command */ 1629 cbp->byte_count = 22; /* (22) bytes to config */ 1630 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1631 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1632 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1633 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1634 cbp->type_enable = 0; /* actually reserved */ 1635 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1636 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1637 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1638 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1639 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1640 cbp->late_scb = 0; /* (don't) defer SCB update */ 1641 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1642 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1643 cbp->ci_int = 1; /* interrupt on CU idle */ 1644 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1645 cbp->ext_stats_dis = 1; /* disable extended counters */ 1646 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1647 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1648 cbp->disc_short_rx = !prm; /* discard short packets */ 1649 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1650 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1651 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1652 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1653 cbp->csma_dis = 0; /* (don't) disable link */ 1654 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1655 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1656 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1657 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1658 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1659 cbp->nsai = 1; /* (don't) disable source addr insert */ 1660 cbp->preamble_length = 2; /* (7 byte) preamble */ 1661 cbp->loopback = 0; /* (don't) loopback */ 1662 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1663 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1664 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1665 cbp->promiscuous = prm; /* promiscuous mode */ 1666 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1667 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1668 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1669 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1670 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1671 1672 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1673 cbp->padding = 1; /* (do) pad short tx packets */ 1674 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1675 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1676 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1677 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1678 /* must set wake_en in PMCSR also */ 1679 cbp->force_fdx = 0; /* (don't) force full duplex */ 1680 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1681 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1682 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1683 1684 if (sc->revision == FXP_REV_82557) { 1685 /* 1686 * The 82557 has no hardware flow control, the values 1687 * below are the defaults for the chip. 1688 */ 1689 cbp->fc_delay_lsb = 0; 1690 cbp->fc_delay_msb = 0x40; 1691 cbp->pri_fc_thresh = 3; 1692 cbp->tx_fc_dis = 0; 1693 cbp->rx_fc_restop = 0; 1694 cbp->rx_fc_restart = 0; 1695 cbp->fc_filter = 0; 1696 cbp->pri_fc_loc = 1; 1697 } else { 1698 cbp->fc_delay_lsb = 0x1f; 1699 cbp->fc_delay_msb = 0x01; 1700 cbp->pri_fc_thresh = 3; 1701 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1702 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1703 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1704 cbp->fc_filter = !prm; /* drop FC frames to host */ 1705 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1706 } 1707 1708 /* 1709 * Start the config command/DMA. 1710 */ 1711 fxp_scb_wait(sc); 1712 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1713 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1714 /* ...and wait for it to complete. */ 1715 fxp_dma_wait(&cbp->cb_status, sc); 1716 1717 /* 1718 * Now initialize the station address. Temporarily use the TxCB 1719 * memory area like we did above for the config CB. 1720 */ 1721 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1722 cb_ias->cb_status = 0; 1723 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1724 cb_ias->link_addr = -1; 1725 bcopy(sc->arpcom.ac_enaddr, 1726 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1727 sizeof(sc->arpcom.ac_enaddr)); 1728 1729 /* 1730 * Start the IAS (Individual Address Setup) command/DMA. 1731 */ 1732 fxp_scb_wait(sc); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1734 /* ...and wait for it to complete. */ 1735 fxp_dma_wait(&cb_ias->cb_status, sc); 1736 1737 /* 1738 * Initialize transmit control block (TxCB) list. 1739 */ 1740 1741 txp = sc->cbl_base; 1742 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1743 for (i = 0; i < FXP_NTXCB; i++) { 1744 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1745 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1746 txp[i].link_addr = 1747 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1748 if (sc->flags & FXP_FLAG_EXT_TXCB) 1749 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1750 else 1751 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1752 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1753 } 1754 /* 1755 * Set the suspend flag on the first TxCB and start the control 1756 * unit. It will execute the NOP and then suspend. 1757 */ 1758 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1759 sc->cbl_first = sc->cbl_last = txp; 1760 sc->tx_queued = 1; 1761 1762 fxp_scb_wait(sc); 1763 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1764 1765 /* 1766 * Initialize receiver buffer area - RFA. 1767 */ 1768 fxp_scb_wait(sc); 1769 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1770 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1771 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1772 1773 /* 1774 * Set current media. 1775 */ 1776 if (sc->miibus != NULL) 1777 mii_mediachg(device_get_softc(sc->miibus)); 1778 1779 ifp->if_flags |= IFF_RUNNING; 1780 ifp->if_flags &= ~IFF_OACTIVE; 1781 1782 /* 1783 * Enable interrupts. 1784 */ 1785 #ifdef DEVICE_POLLING 1786 /* 1787 * ... but only do that if we are not polling. And because (presumably) 1788 * the default is interrupts on, we need to disable them explicitly! 1789 */ 1790 if ( ifp->if_flags & IFF_POLLING ) 1791 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1792 else 1793 #endif /* DEVICE_POLLING */ 1794 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1795 splx(s); 1796 1797 /* 1798 * Start stats updater. 1799 */ 1800 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1801 } 1802 1803 static int 1804 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1805 { 1806 1807 return (0); 1808 } 1809 1810 static void 1811 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1812 { 1813 1814 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1815 } 1816 1817 /* 1818 * Change media according to request. 1819 */ 1820 static int 1821 fxp_ifmedia_upd(struct ifnet *ifp) 1822 { 1823 struct fxp_softc *sc = ifp->if_softc; 1824 struct mii_data *mii; 1825 1826 mii = device_get_softc(sc->miibus); 1827 mii_mediachg(mii); 1828 return (0); 1829 } 1830 1831 /* 1832 * Notify the world which media we're using. 1833 */ 1834 static void 1835 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1836 { 1837 struct fxp_softc *sc = ifp->if_softc; 1838 struct mii_data *mii; 1839 1840 mii = device_get_softc(sc->miibus); 1841 mii_pollstat(mii); 1842 ifmr->ifm_active = mii->mii_media_active; 1843 ifmr->ifm_status = mii->mii_media_status; 1844 1845 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1846 sc->cu_resume_bug = 1; 1847 else 1848 sc->cu_resume_bug = 0; 1849 } 1850 1851 /* 1852 * Add a buffer to the end of the RFA buffer list. 1853 * Return 0 if successful, 1 for failure. A failure results in 1854 * adding the 'oldm' (if non-NULL) on to the end of the list - 1855 * tossing out its old contents and recycling it. 1856 * The RFA struct is stuck at the beginning of mbuf cluster and the 1857 * data pointer is fixed up to point just past it. 1858 */ 1859 static int 1860 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1861 { 1862 u_int32_t v; 1863 struct mbuf *m; 1864 struct fxp_rfa *rfa, *p_rfa; 1865 1866 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1867 if (m == NULL) { /* try to recycle the old mbuf instead */ 1868 if (oldm == NULL) 1869 return 1; 1870 m = oldm; 1871 m->m_data = m->m_ext.ext_buf; 1872 } 1873 1874 /* 1875 * Move the data pointer up so that the incoming data packet 1876 * will be 32-bit aligned. 1877 */ 1878 m->m_data += RFA_ALIGNMENT_FUDGE; 1879 1880 /* 1881 * Get a pointer to the base of the mbuf cluster and move 1882 * data start past it. 1883 */ 1884 rfa = mtod(m, struct fxp_rfa *); 1885 m->m_data += sizeof(struct fxp_rfa); 1886 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1887 1888 /* 1889 * Initialize the rest of the RFA. Note that since the RFA 1890 * is misaligned, we cannot store values directly. Instead, 1891 * we use an optimized, inline copy. 1892 */ 1893 1894 rfa->rfa_status = 0; 1895 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1896 rfa->actual_size = 0; 1897 1898 v = -1; 1899 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1900 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1901 1902 /* 1903 * If there are other buffers already on the list, attach this 1904 * one to the end by fixing up the tail to point to this one. 1905 */ 1906 if (sc->rfa_headm != NULL) { 1907 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1908 RFA_ALIGNMENT_FUDGE); 1909 sc->rfa_tailm->m_next = m; 1910 v = vtophys(rfa); 1911 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1912 p_rfa->rfa_control = 0; 1913 } else { 1914 sc->rfa_headm = m; 1915 } 1916 sc->rfa_tailm = m; 1917 1918 return (m == oldm); 1919 } 1920 1921 static volatile int 1922 fxp_miibus_readreg(device_t dev, int phy, int reg) 1923 { 1924 struct fxp_softc *sc = device_get_softc(dev); 1925 int count = 10000; 1926 int value; 1927 1928 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1929 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1930 1931 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1932 && count--) 1933 DELAY(10); 1934 1935 if (count <= 0) 1936 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1937 1938 return (value & 0xffff); 1939 } 1940 1941 static void 1942 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1943 { 1944 struct fxp_softc *sc = device_get_softc(dev); 1945 int count = 10000; 1946 1947 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1948 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1949 (value & 0xffff)); 1950 1951 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1952 count--) 1953 DELAY(10); 1954 1955 if (count <= 0) 1956 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1957 } 1958 1959 static int 1960 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1961 { 1962 struct fxp_softc *sc = ifp->if_softc; 1963 struct ifreq *ifr = (struct ifreq *)data; 1964 struct mii_data *mii; 1965 int s, error = 0; 1966 1967 s = splimp(); 1968 1969 switch (command) { 1970 1971 case SIOCSIFFLAGS: 1972 if (ifp->if_flags & IFF_ALLMULTI) 1973 sc->flags |= FXP_FLAG_ALL_MCAST; 1974 else 1975 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1976 1977 /* 1978 * If interface is marked up and not running, then start it. 1979 * If it is marked down and running, stop it. 1980 * XXX If it's up then re-initialize it. This is so flags 1981 * such as IFF_PROMISC are handled. 1982 */ 1983 if (ifp->if_flags & IFF_UP) { 1984 fxp_init(sc); 1985 } else { 1986 if (ifp->if_flags & IFF_RUNNING) 1987 fxp_stop(sc); 1988 } 1989 break; 1990 1991 case SIOCADDMULTI: 1992 case SIOCDELMULTI: 1993 if (ifp->if_flags & IFF_ALLMULTI) 1994 sc->flags |= FXP_FLAG_ALL_MCAST; 1995 else 1996 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1997 /* 1998 * Multicast list has changed; set the hardware filter 1999 * accordingly. 2000 */ 2001 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2002 fxp_mc_setup(sc); 2003 /* 2004 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2005 * again rather than else {}. 2006 */ 2007 if (sc->flags & FXP_FLAG_ALL_MCAST) 2008 fxp_init(sc); 2009 error = 0; 2010 break; 2011 2012 case SIOCSIFMEDIA: 2013 case SIOCGIFMEDIA: 2014 if (sc->miibus != NULL) { 2015 mii = device_get_softc(sc->miibus); 2016 error = ifmedia_ioctl(ifp, ifr, 2017 &mii->mii_media, command); 2018 } else { 2019 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2020 } 2021 break; 2022 2023 default: 2024 error = ether_ioctl(ifp, command, data); 2025 break; 2026 } 2027 splx(s); 2028 return (error); 2029 } 2030 2031 /* 2032 * Fill in the multicast address list and return number of entries. 2033 */ 2034 static int 2035 fxp_mc_addrs(struct fxp_softc *sc) 2036 { 2037 struct fxp_cb_mcs *mcsp = sc->mcsp; 2038 struct ifnet *ifp = &sc->arpcom.ac_if; 2039 struct ifmultiaddr *ifma; 2040 int nmcasts; 2041 2042 nmcasts = 0; 2043 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2044 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2045 if (ifma->ifma_addr->sa_family != AF_LINK) 2046 continue; 2047 if (nmcasts >= MAXMCADDR) { 2048 sc->flags |= FXP_FLAG_ALL_MCAST; 2049 nmcasts = 0; 2050 break; 2051 } 2052 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2053 (void *)(uintptr_t)(volatile void *) 2054 &sc->mcsp->mc_addr[nmcasts][0], 6); 2055 nmcasts++; 2056 } 2057 } 2058 mcsp->mc_cnt = nmcasts * 6; 2059 return (nmcasts); 2060 } 2061 2062 /* 2063 * Program the multicast filter. 2064 * 2065 * We have an artificial restriction that the multicast setup command 2066 * must be the first command in the chain, so we take steps to ensure 2067 * this. By requiring this, it allows us to keep up the performance of 2068 * the pre-initialized command ring (esp. link pointers) by not actually 2069 * inserting the mcsetup command in the ring - i.e. its link pointer 2070 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2071 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2072 * lead into the regular TxCB ring when it completes. 2073 * 2074 * This function must be called at splimp. 2075 */ 2076 static void 2077 fxp_mc_setup(struct fxp_softc *sc) 2078 { 2079 struct fxp_cb_mcs *mcsp = sc->mcsp; 2080 struct ifnet *ifp = &sc->arpcom.ac_if; 2081 int count; 2082 2083 /* 2084 * If there are queued commands, we must wait until they are all 2085 * completed. If we are already waiting, then add a NOP command 2086 * with interrupt option so that we're notified when all commands 2087 * have been completed - fxp_start() ensures that no additional 2088 * TX commands will be added when need_mcsetup is true. 2089 */ 2090 if (sc->tx_queued) { 2091 struct fxp_cb_tx *txp; 2092 2093 /* 2094 * need_mcsetup will be true if we are already waiting for the 2095 * NOP command to be completed (see below). In this case, bail. 2096 */ 2097 if (sc->need_mcsetup) 2098 return; 2099 sc->need_mcsetup = 1; 2100 2101 /* 2102 * Add a NOP command with interrupt so that we are notified 2103 * when all TX commands have been processed. 2104 */ 2105 txp = sc->cbl_last->next; 2106 txp->mb_head = NULL; 2107 txp->cb_status = 0; 2108 txp->cb_command = FXP_CB_COMMAND_NOP | 2109 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2110 /* 2111 * Advance the end of list forward. 2112 */ 2113 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2114 sc->cbl_last = txp; 2115 sc->tx_queued++; 2116 /* 2117 * Issue a resume in case the CU has just suspended. 2118 */ 2119 fxp_scb_wait(sc); 2120 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2121 /* 2122 * Set a 5 second timer just in case we don't hear from the 2123 * card again. 2124 */ 2125 ifp->if_timer = 5; 2126 2127 return; 2128 } 2129 sc->need_mcsetup = 0; 2130 2131 /* 2132 * Initialize multicast setup descriptor. 2133 */ 2134 mcsp->next = sc->cbl_base; 2135 mcsp->mb_head = NULL; 2136 mcsp->cb_status = 0; 2137 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2138 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2139 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2140 (void) fxp_mc_addrs(sc); 2141 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2142 sc->tx_queued = 1; 2143 2144 /* 2145 * Wait until command unit is not active. This should never 2146 * be the case when nothing is queued, but make sure anyway. 2147 */ 2148 count = 100; 2149 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2150 FXP_SCB_CUS_ACTIVE && --count) 2151 DELAY(10); 2152 if (count == 0) { 2153 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2154 return; 2155 } 2156 2157 /* 2158 * Start the multicast setup command. 2159 */ 2160 fxp_scb_wait(sc); 2161 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2163 2164 ifp->if_timer = 2; 2165 return; 2166 } 2167 2168 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2169 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2170 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2171 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2172 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2173 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2174 2175 #define UCODE(x) x, sizeof(x) 2176 2177 struct ucode { 2178 u_int32_t revision; 2179 u_int32_t *ucode; 2180 int length; 2181 u_short int_delay_offset; 2182 u_short bundle_max_offset; 2183 } ucode_table[] = { 2184 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2185 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2186 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2187 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2188 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2189 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2190 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2191 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2192 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2193 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2194 { 0, NULL, 0, 0, 0 } 2195 }; 2196 2197 static void 2198 fxp_load_ucode(struct fxp_softc *sc) 2199 { 2200 struct ucode *uc; 2201 struct fxp_cb_ucode *cbp; 2202 2203 for (uc = ucode_table; uc->ucode != NULL; uc++) 2204 if (sc->revision == uc->revision) 2205 break; 2206 if (uc->ucode == NULL) 2207 return; 2208 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2209 cbp->cb_status = 0; 2210 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2211 cbp->link_addr = -1; /* (no) next command */ 2212 memcpy(cbp->ucode, uc->ucode, uc->length); 2213 if (uc->int_delay_offset) 2214 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2215 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2216 if (uc->bundle_max_offset) 2217 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2218 sc->tunable_bundle_max; 2219 /* 2220 * Download the ucode to the chip. 2221 */ 2222 fxp_scb_wait(sc); 2223 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2224 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2225 /* ...and wait for it to complete. */ 2226 fxp_dma_wait(&cbp->cb_status, sc); 2227 if_printf(&sc->arpcom.ac_if, 2228 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2229 sc->tunable_int_delay, 2230 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2231 sc->flags |= FXP_FLAG_UCODE; 2232 } 2233 2234 static int 2235 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2236 { 2237 int error, value; 2238 2239 value = *(int *)arg1; 2240 error = sysctl_handle_int(oidp, &value, 0, req); 2241 if (error || !req->newptr) 2242 return (error); 2243 if (value < low || value > high) 2244 return (EINVAL); 2245 *(int *)arg1 = value; 2246 return (0); 2247 } 2248 2249 /* 2250 * Interrupt delay is expressed in microseconds, a multiplier is used 2251 * to convert this to the appropriate clock ticks before using. 2252 */ 2253 static int 2254 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2255 { 2256 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2257 } 2258 2259 static int 2260 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2261 { 2262 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2263 } 2264