1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.30 2005/05/31 08:19:04 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 170 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 176 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 180 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 185 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 186 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 187 { 0, -1, NULL }, 188 }; 189 190 static int fxp_probe(device_t dev); 191 static int fxp_attach(device_t dev); 192 static int fxp_detach(device_t dev); 193 static int fxp_shutdown(device_t dev); 194 static int fxp_suspend(device_t dev); 195 static int fxp_resume(device_t dev); 196 197 static void fxp_intr(void *xsc); 198 static void fxp_intr_body(struct fxp_softc *sc, 199 u_int8_t statack, int count); 200 201 static void fxp_init(void *xsc); 202 static void fxp_tick(void *xsc); 203 static void fxp_powerstate_d0(device_t dev); 204 static void fxp_start(struct ifnet *ifp); 205 static void fxp_stop(struct fxp_softc *sc); 206 static void fxp_release(struct fxp_softc *sc); 207 static int fxp_ioctl(struct ifnet *ifp, u_long command, 208 caddr_t data, struct ucred *); 209 static void fxp_watchdog(struct ifnet *ifp); 210 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 211 static int fxp_mc_addrs(struct fxp_softc *sc); 212 static void fxp_mc_setup(struct fxp_softc *sc); 213 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 214 int autosize); 215 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 216 u_int16_t data); 217 static void fxp_autosize_eeprom(struct fxp_softc *sc); 218 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 219 int offset, int words); 220 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 221 int offset, int words); 222 static int fxp_ifmedia_upd(struct ifnet *ifp); 223 static void fxp_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 226 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 227 struct ifmediareq *ifmr); 228 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 229 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 230 int value); 231 static void fxp_load_ucode(struct fxp_softc *sc); 232 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 233 int low, int high); 234 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 235 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 236 #ifdef DEVICE_POLLING 237 static poll_handler_t fxp_poll; 238 #endif 239 240 static __inline void fxp_lwcopy(volatile u_int32_t *src, 241 volatile u_int32_t *dst); 242 static __inline void fxp_scb_wait(struct fxp_softc *sc); 243 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 244 static __inline void fxp_dma_wait(volatile u_int16_t *status, 245 struct fxp_softc *sc); 246 247 static device_method_t fxp_methods[] = { 248 /* Device interface */ 249 DEVMETHOD(device_probe, fxp_probe), 250 DEVMETHOD(device_attach, fxp_attach), 251 DEVMETHOD(device_detach, fxp_detach), 252 DEVMETHOD(device_shutdown, fxp_shutdown), 253 DEVMETHOD(device_suspend, fxp_suspend), 254 DEVMETHOD(device_resume, fxp_resume), 255 256 /* MII interface */ 257 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 258 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 259 260 { 0, 0 } 261 }; 262 263 static driver_t fxp_driver = { 264 "fxp", 265 fxp_methods, 266 sizeof(struct fxp_softc), 267 }; 268 269 static devclass_t fxp_devclass; 270 271 DECLARE_DUMMY_MODULE(if_fxp); 272 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 273 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 274 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 275 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 276 277 static int fxp_rnr; 278 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 279 280 /* 281 * Inline function to copy a 16-bit aligned 32-bit quantity. 282 */ 283 static __inline void 284 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 285 { 286 #ifdef __i386__ 287 *dst = *src; 288 #else 289 volatile u_int16_t *a = (volatile u_int16_t *)src; 290 volatile u_int16_t *b = (volatile u_int16_t *)dst; 291 292 b[0] = a[0]; 293 b[1] = a[1]; 294 #endif 295 } 296 297 /* 298 * Wait for the previous command to be accepted (but not necessarily 299 * completed). 300 */ 301 static __inline void 302 fxp_scb_wait(struct fxp_softc *sc) 303 { 304 int i = 10000; 305 306 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 307 DELAY(2); 308 if (i == 0) 309 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 310 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 311 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 312 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 313 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 314 } 315 316 static __inline void 317 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 318 { 319 320 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 322 fxp_scb_wait(sc); 323 } 324 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 325 } 326 327 static __inline void 328 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 329 { 330 int i = 10000; 331 332 while (!(*status & FXP_CB_STATUS_C) && --i) 333 DELAY(2); 334 if (i == 0) 335 device_printf(sc->dev, "DMA timeout\n"); 336 } 337 338 /* 339 * Return identification string if this is device is ours. 340 */ 341 static int 342 fxp_probe(device_t dev) 343 { 344 u_int16_t devid; 345 u_int8_t revid; 346 struct fxp_ident *ident; 347 348 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 349 devid = pci_get_device(dev); 350 revid = pci_get_revid(dev); 351 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 352 if (ident->devid == devid && 353 (ident->revid == revid || ident->revid == -1)) { 354 device_set_desc(dev, ident->name); 355 return (0); 356 } 357 } 358 } 359 return (ENXIO); 360 } 361 362 static void 363 fxp_powerstate_d0(device_t dev) 364 { 365 u_int32_t iobase, membase, irq; 366 367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 368 /* Save important PCI config data. */ 369 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 370 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 371 irq = pci_read_config(dev, PCIR_INTLINE, 4); 372 373 /* Reset the power state. */ 374 device_printf(dev, "chip is in D%d power mode " 375 "-- setting to D0\n", pci_get_powerstate(dev)); 376 377 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 378 379 /* Restore PCI config data. */ 380 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 381 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 382 pci_write_config(dev, PCIR_INTLINE, irq, 4); 383 } 384 } 385 386 static int 387 fxp_attach(device_t dev) 388 { 389 int error = 0; 390 struct fxp_softc *sc = device_get_softc(dev); 391 struct ifnet *ifp; 392 u_int32_t val; 393 u_int16_t data; 394 int i, rid, m1, m2, prefer_iomap; 395 int s; 396 397 bzero(sc, sizeof(*sc)); 398 sc->dev = dev; 399 callout_init(&sc->fxp_stat_timer); 400 sysctl_ctx_init(&sc->sysctl_ctx); 401 402 s = splimp(); 403 404 /* 405 * Enable bus mastering. Enable memory space too, in case 406 * BIOS/Prom forgot about it. 407 */ 408 pci_enable_busmaster(dev); 409 pci_enable_io(dev, SYS_RES_MEMORY); 410 val = pci_read_config(dev, PCIR_COMMAND, 2); 411 412 fxp_powerstate_d0(dev); 413 414 /* 415 * Figure out which we should try first - memory mapping or i/o mapping? 416 * We default to memory mapping. Then we accept an override from the 417 * command line. Then we check to see which one is enabled. 418 */ 419 m1 = PCIM_CMD_MEMEN; 420 m2 = PCIM_CMD_PORTEN; 421 prefer_iomap = 0; 422 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 423 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 424 m1 = PCIM_CMD_PORTEN; 425 m2 = PCIM_CMD_MEMEN; 426 } 427 428 if (val & m1) { 429 sc->rtp = 430 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 431 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 432 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 433 RF_ACTIVE); 434 } 435 if (sc->mem == NULL && (val & m2)) { 436 sc->rtp = 437 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 438 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 439 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 440 RF_ACTIVE); 441 } 442 443 if (!sc->mem) { 444 device_printf(dev, "could not map device registers\n"); 445 error = ENXIO; 446 goto fail; 447 } 448 if (bootverbose) { 449 device_printf(dev, "using %s space register mapping\n", 450 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 451 } 452 453 sc->sc_st = rman_get_bustag(sc->mem); 454 sc->sc_sh = rman_get_bushandle(sc->mem); 455 456 /* 457 * Allocate our interrupt. 458 */ 459 rid = 0; 460 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 461 RF_SHAREABLE | RF_ACTIVE); 462 if (sc->irq == NULL) { 463 device_printf(dev, "could not map interrupt\n"); 464 error = ENXIO; 465 goto fail; 466 } 467 468 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 469 fxp_intr, sc, &sc->ih, NULL); 470 if (error) { 471 device_printf(dev, "could not setup irq\n"); 472 goto fail; 473 } 474 475 /* 476 * Reset to a stable state. 477 */ 478 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 479 DELAY(10); 480 481 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 482 M_DEVBUF, M_WAITOK | M_ZERO); 483 484 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 485 M_WAITOK | M_ZERO); 486 487 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 488 489 /* 490 * Pre-allocate our receive buffers. 491 */ 492 for (i = 0; i < FXP_NRFABUFS; i++) { 493 if (fxp_add_rfabuf(sc, NULL) != 0) { 494 goto failmem; 495 } 496 } 497 498 /* 499 * Find out how large of an SEEPROM we have. 500 */ 501 fxp_autosize_eeprom(sc); 502 503 /* 504 * Determine whether we must use the 503 serial interface. 505 */ 506 fxp_read_eeprom(sc, &data, 6, 1); 507 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 508 (data & FXP_PHY_SERIAL_ONLY)) 509 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 510 511 /* 512 * Create the sysctl tree 513 */ 514 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 515 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 516 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 517 if (sc->sysctl_tree == NULL) 518 goto fail; 519 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 520 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 521 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 522 "FXP driver receive interrupt microcode bundling delay"); 523 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 524 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 525 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 526 "FXP driver receive interrupt microcode bundle size limit"); 527 528 /* 529 * Pull in device tunables. 530 */ 531 sc->tunable_int_delay = TUNABLE_INT_DELAY; 532 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "int_delay", &sc->tunable_int_delay); 535 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 536 "bundle_max", &sc->tunable_bundle_max); 537 538 /* 539 * Find out the chip revision; lump all 82557 revs together. 540 */ 541 fxp_read_eeprom(sc, &data, 5, 1); 542 if ((data >> 8) == 1) 543 sc->revision = FXP_REV_82557; 544 else 545 sc->revision = pci_get_revid(dev); 546 547 /* 548 * Enable workarounds for certain chip revision deficiencies. 549 * 550 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 551 * some systems based a normal 82559 design, have a defect where 552 * the chip can cause a PCI protocol violation if it receives 553 * a CU_RESUME command when it is entering the IDLE state. The 554 * workaround is to disable Dynamic Standby Mode, so the chip never 555 * deasserts CLKRUN#, and always remains in an active state. 556 * 557 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 558 */ 559 i = pci_get_device(dev); 560 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 561 sc->revision >= FXP_REV_82559_A0) { 562 fxp_read_eeprom(sc, &data, 10, 1); 563 if (data & 0x02) { /* STB enable */ 564 u_int16_t cksum; 565 int i; 566 567 device_printf(dev, 568 "Disabling dynamic standby mode in EEPROM\n"); 569 data &= ~0x02; 570 fxp_write_eeprom(sc, &data, 10, 1); 571 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 572 cksum = 0; 573 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 574 fxp_read_eeprom(sc, &data, i, 1); 575 cksum += data; 576 } 577 i = (1 << sc->eeprom_size) - 1; 578 cksum = 0xBABA - cksum; 579 fxp_read_eeprom(sc, &data, i, 1); 580 fxp_write_eeprom(sc, &cksum, i, 1); 581 device_printf(dev, 582 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 583 i, data, cksum); 584 #if 1 585 /* 586 * If the user elects to continue, try the software 587 * workaround, as it is better than nothing. 588 */ 589 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 590 #endif 591 } 592 } 593 594 /* 595 * If we are not a 82557 chip, we can enable extended features. 596 */ 597 if (sc->revision != FXP_REV_82557) { 598 /* 599 * If MWI is enabled in the PCI configuration, and there 600 * is a valid cacheline size (8 or 16 dwords), then tell 601 * the board to turn on MWI. 602 */ 603 if (val & PCIM_CMD_MWRICEN && 604 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 605 sc->flags |= FXP_FLAG_MWI_ENABLE; 606 607 /* turn on the extended TxCB feature */ 608 sc->flags |= FXP_FLAG_EXT_TXCB; 609 610 /* enable reception of long frames for VLAN */ 611 sc->flags |= FXP_FLAG_LONG_PKT_EN; 612 } 613 614 /* 615 * Read MAC address. 616 */ 617 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 618 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 619 device_printf(dev, "10Mbps"); 620 if (bootverbose) { 621 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 622 pci_get_vendor(dev), pci_get_device(dev), 623 pci_get_subvendor(dev), pci_get_subdevice(dev), 624 pci_get_revid(dev)); 625 fxp_read_eeprom(sc, &data, 10, 1); 626 device_printf(dev, "Dynamic Standby mode is %s\n", 627 data & 0x02 ? "enabled" : "disabled"); 628 } 629 630 /* 631 * If this is only a 10Mbps device, then there is no MII, and 632 * the PHY will use a serial interface instead. 633 * 634 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 635 * doesn't have a programming interface of any sort. The 636 * media is sensed automatically based on how the link partner 637 * is configured. This is, in essence, manual configuration. 638 */ 639 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 640 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 641 fxp_serial_ifmedia_sts); 642 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 643 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 644 } else { 645 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 646 fxp_ifmedia_sts)) { 647 device_printf(dev, "MII without any PHY!\n"); 648 error = ENXIO; 649 goto fail; 650 } 651 } 652 653 ifp = &sc->arpcom.ac_if; 654 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 655 ifp->if_baudrate = 100000000; 656 ifp->if_init = fxp_init; 657 ifp->if_softc = sc; 658 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 659 ifp->if_ioctl = fxp_ioctl; 660 ifp->if_start = fxp_start; 661 #ifdef DEVICE_POLLING 662 ifp->if_poll = fxp_poll; 663 #endif 664 ifp->if_watchdog = fxp_watchdog; 665 666 /* 667 * Attach the interface. 668 */ 669 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 670 671 /* 672 * Tell the upper layer(s) we support long frames. 673 */ 674 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 675 676 /* 677 * Let the system queue as many packets as we have available 678 * TX descriptors. 679 */ 680 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 681 ifq_set_ready(&ifp->if_snd); 682 683 splx(s); 684 return (0); 685 686 failmem: 687 device_printf(dev, "Failed to malloc memory\n"); 688 error = ENOMEM; 689 fail: 690 splx(s); 691 fxp_release(sc); 692 return (error); 693 } 694 695 /* 696 * release all resources 697 */ 698 static void 699 fxp_release(struct fxp_softc *sc) 700 { 701 702 bus_generic_detach(sc->dev); 703 if (sc->miibus) 704 device_delete_child(sc->dev, sc->miibus); 705 706 if (sc->cbl_base) 707 free(sc->cbl_base, M_DEVBUF); 708 if (sc->fxp_stats) 709 free(sc->fxp_stats, M_DEVBUF); 710 if (sc->mcsp) 711 free(sc->mcsp, M_DEVBUF); 712 if (sc->rfa_headm) 713 m_freem(sc->rfa_headm); 714 715 if (sc->ih) 716 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 717 if (sc->irq) 718 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 719 if (sc->mem) 720 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 721 722 sysctl_ctx_free(&sc->sysctl_ctx); 723 } 724 725 /* 726 * Detach interface. 727 */ 728 static int 729 fxp_detach(device_t dev) 730 { 731 struct fxp_softc *sc = device_get_softc(dev); 732 int s; 733 734 /* disable interrupts */ 735 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 736 737 s = splimp(); 738 739 /* 740 * Stop DMA and drop transmit queue. 741 */ 742 fxp_stop(sc); 743 744 /* 745 * Close down routes etc. 746 */ 747 ether_ifdetach(&sc->arpcom.ac_if); 748 749 /* 750 * Free all media structures. 751 */ 752 ifmedia_removeall(&sc->sc_media); 753 754 splx(s); 755 756 /* Release our allocated resources. */ 757 fxp_release(sc); 758 759 return (0); 760 } 761 762 /* 763 * Device shutdown routine. Called at system shutdown after sync. The 764 * main purpose of this routine is to shut off receiver DMA so that 765 * kernel memory doesn't get clobbered during warmboot. 766 */ 767 static int 768 fxp_shutdown(device_t dev) 769 { 770 /* 771 * Make sure that DMA is disabled prior to reboot. Not doing 772 * do could allow DMA to corrupt kernel memory during the 773 * reboot before the driver initializes. 774 */ 775 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 776 return (0); 777 } 778 779 /* 780 * Device suspend routine. Stop the interface and save some PCI 781 * settings in case the BIOS doesn't restore them properly on 782 * resume. 783 */ 784 static int 785 fxp_suspend(device_t dev) 786 { 787 struct fxp_softc *sc = device_get_softc(dev); 788 int i, s; 789 790 s = splimp(); 791 792 fxp_stop(sc); 793 794 for (i = 0; i < 5; i++) 795 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 796 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 797 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 798 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 799 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 800 801 sc->suspended = 1; 802 803 splx(s); 804 return (0); 805 } 806 807 /* 808 * Device resume routine. Restore some PCI settings in case the BIOS 809 * doesn't, re-enable busmastering, and restart the interface if 810 * appropriate. 811 */ 812 static int 813 fxp_resume(device_t dev) 814 { 815 struct fxp_softc *sc = device_get_softc(dev); 816 struct ifnet *ifp = &sc->arpcom.ac_if; 817 int i, s; 818 819 s = splimp(); 820 821 fxp_powerstate_d0(dev); 822 823 /* better way to do this? */ 824 for (i = 0; i < 5; i++) 825 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 826 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 827 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 828 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 829 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 830 831 /* reenable busmastering and memory space */ 832 pci_enable_busmaster(dev); 833 pci_enable_io(dev, SYS_RES_MEMORY); 834 835 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 836 DELAY(10); 837 838 /* reinitialize interface if necessary */ 839 if (ifp->if_flags & IFF_UP) 840 fxp_init(sc); 841 842 sc->suspended = 0; 843 844 splx(s); 845 return (0); 846 } 847 848 static void 849 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 850 { 851 u_int16_t reg; 852 int x; 853 854 /* 855 * Shift in data. 856 */ 857 for (x = 1 << (length - 1); x; x >>= 1) { 858 if (data & x) 859 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 860 else 861 reg = FXP_EEPROM_EECS; 862 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 863 DELAY(1); 864 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 865 DELAY(1); 866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 867 DELAY(1); 868 } 869 } 870 871 /* 872 * Read from the serial EEPROM. Basically, you manually shift in 873 * the read opcode (one bit at a time) and then shift in the address, 874 * and then you shift out the data (all of this one bit at a time). 875 * The word size is 16 bits, so you have to provide the address for 876 * every 16 bits of data. 877 */ 878 static u_int16_t 879 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 880 { 881 u_int16_t reg, data; 882 int x; 883 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 885 /* 886 * Shift in read opcode. 887 */ 888 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 889 /* 890 * Shift in address. 891 */ 892 data = 0; 893 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 894 if (offset & x) 895 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 896 else 897 reg = FXP_EEPROM_EECS; 898 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 899 DELAY(1); 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 901 DELAY(1); 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 903 DELAY(1); 904 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 905 data++; 906 if (autosize && reg == 0) { 907 sc->eeprom_size = data; 908 break; 909 } 910 } 911 /* 912 * Shift out data. 913 */ 914 data = 0; 915 reg = FXP_EEPROM_EECS; 916 for (x = 1 << 15; x; x >>= 1) { 917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 918 DELAY(1); 919 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 920 data |= x; 921 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 922 DELAY(1); 923 } 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 925 DELAY(1); 926 927 return (data); 928 } 929 930 static void 931 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 932 { 933 int i; 934 935 /* 936 * Erase/write enable. 937 */ 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 939 fxp_eeprom_shiftin(sc, 0x4, 3); 940 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 942 DELAY(1); 943 /* 944 * Shift in write opcode, address, data. 945 */ 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 947 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 948 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 949 fxp_eeprom_shiftin(sc, data, 16); 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 951 DELAY(1); 952 /* 953 * Wait for EEPROM to finish up. 954 */ 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 956 DELAY(1); 957 for (i = 0; i < 1000; i++) { 958 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 959 break; 960 DELAY(50); 961 } 962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 963 DELAY(1); 964 /* 965 * Erase/write disable. 966 */ 967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 968 fxp_eeprom_shiftin(sc, 0x4, 3); 969 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 970 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 971 DELAY(1); 972 } 973 974 /* 975 * From NetBSD: 976 * 977 * Figure out EEPROM size. 978 * 979 * 559's can have either 64-word or 256-word EEPROMs, the 558 980 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 981 * talks about the existance of 16 to 256 word EEPROMs. 982 * 983 * The only known sizes are 64 and 256, where the 256 version is used 984 * by CardBus cards to store CIS information. 985 * 986 * The address is shifted in msb-to-lsb, and after the last 987 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 988 * after which follows the actual data. We try to detect this zero, by 989 * probing the data-out bit in the EEPROM control register just after 990 * having shifted in a bit. If the bit is zero, we assume we've 991 * shifted enough address bits. The data-out should be tri-state, 992 * before this, which should translate to a logical one. 993 */ 994 static void 995 fxp_autosize_eeprom(struct fxp_softc *sc) 996 { 997 998 /* guess maximum size of 256 words */ 999 sc->eeprom_size = 8; 1000 1001 /* autosize */ 1002 (void) fxp_eeprom_getword(sc, 0, 1); 1003 } 1004 1005 static void 1006 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1007 { 1008 int i; 1009 1010 for (i = 0; i < words; i++) 1011 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1012 } 1013 1014 static void 1015 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1016 { 1017 int i; 1018 1019 for (i = 0; i < words; i++) 1020 fxp_eeprom_putword(sc, offset + i, data[i]); 1021 } 1022 1023 /* 1024 * Start packet transmission on the interface. 1025 */ 1026 static void 1027 fxp_start(struct ifnet *ifp) 1028 { 1029 struct fxp_softc *sc = ifp->if_softc; 1030 struct fxp_cb_tx *txp; 1031 1032 /* 1033 * See if we need to suspend xmit until the multicast filter 1034 * has been reprogrammed (which can only be done at the head 1035 * of the command chain). 1036 */ 1037 if (sc->need_mcsetup) { 1038 return; 1039 } 1040 1041 txp = NULL; 1042 1043 /* 1044 * We're finished if there is nothing more to add to the list or if 1045 * we're all filled up with buffers to transmit. 1046 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1047 * a NOP command when needed. 1048 */ 1049 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1050 struct mbuf *m, *mb_head; 1051 int segment, ntries = 0; 1052 1053 /* 1054 * Grab a packet to transmit. The packet is dequeued, 1055 * once we are sure that we have enough free descriptors. 1056 */ 1057 mb_head = ifq_poll(&ifp->if_snd); 1058 if (mb_head == NULL) 1059 break; 1060 1061 /* 1062 * Get pointer to next available tx desc. 1063 */ 1064 txp = sc->cbl_last->next; 1065 1066 /* 1067 * Go through each of the mbufs in the chain and initialize 1068 * the transmit buffer descriptors with the physical address 1069 * and size of the mbuf. 1070 */ 1071 tbdinit: 1072 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1073 if (m->m_len != 0) { 1074 if (segment == FXP_NTXSEG) 1075 break; 1076 txp->tbd[segment].tb_addr = 1077 vtophys(mtod(m, vm_offset_t)); 1078 txp->tbd[segment].tb_size = m->m_len; 1079 segment++; 1080 } 1081 } 1082 if (m != NULL) { 1083 struct mbuf *mn; 1084 1085 /* 1086 * We ran out of segments. We have to recopy this 1087 * mbuf chain first. Bail out if we can't get the 1088 * new buffers. 1089 */ 1090 if (ntries > 0) 1091 break; 1092 mn = m_dup(mb_head, MB_DONTWAIT); 1093 if (mn == NULL) 1094 break; 1095 /* We can transmit the packet, dequeue it. */ 1096 mb_head = ifq_dequeue(&ifp->if_snd); 1097 m_freem(mb_head); 1098 mb_head = mn; 1099 ntries = 1; 1100 goto tbdinit; 1101 } else { 1102 /* Nothing to worry about, just dequeue. */ 1103 mb_head = ifq_dequeue(&ifp->if_snd); 1104 } 1105 1106 txp->tbd_number = segment; 1107 txp->mb_head = mb_head; 1108 txp->cb_status = 0; 1109 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1110 txp->cb_command = 1111 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1112 FXP_CB_COMMAND_S; 1113 } else { 1114 txp->cb_command = 1115 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1116 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1117 /* 1118 * Set a 5 second timer just in case we don't hear 1119 * from the card again. 1120 */ 1121 ifp->if_timer = 5; 1122 } 1123 txp->tx_threshold = tx_threshold; 1124 1125 /* 1126 * Advance the end of list forward. 1127 */ 1128 1129 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1130 sc->cbl_last = txp; 1131 1132 /* 1133 * Advance the beginning of the list forward if there are 1134 * no other packets queued (when nothing is queued, cbl_first 1135 * sits on the last TxCB that was sent out). 1136 */ 1137 if (sc->tx_queued == 0) 1138 sc->cbl_first = txp; 1139 1140 sc->tx_queued++; 1141 1142 BPF_MTAP(ifp, mb_head); 1143 } 1144 1145 /* 1146 * We're finished. If we added to the list, issue a RESUME to get DMA 1147 * going again if suspended. 1148 */ 1149 if (txp != NULL) { 1150 fxp_scb_wait(sc); 1151 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1152 } 1153 } 1154 1155 #ifdef DEVICE_POLLING 1156 1157 static void 1158 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1159 { 1160 struct fxp_softc *sc = ifp->if_softc; 1161 u_int8_t statack; 1162 1163 switch(cmd) { 1164 case POLL_REGISTER: 1165 /* disable interrupts */ 1166 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1167 break; 1168 case POLL_DEREGISTER: 1169 /* enable interrupts */ 1170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1171 break; 1172 default: 1173 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1174 FXP_SCB_STATACK_FR; 1175 if (cmd == POLL_AND_CHECK_STATUS) { 1176 u_int8_t tmp; 1177 1178 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1179 if (tmp == 0xff || tmp == 0) 1180 return; /* nothing to do */ 1181 tmp &= ~statack; 1182 /* ack what we can */ 1183 if (tmp != 0) 1184 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1185 statack |= tmp; 1186 } 1187 fxp_intr_body(sc, statack, count); 1188 break; 1189 } 1190 } 1191 1192 #endif /* DEVICE_POLLING */ 1193 1194 /* 1195 * Process interface interrupts. 1196 */ 1197 static void 1198 fxp_intr(void *xsc) 1199 { 1200 struct fxp_softc *sc = xsc; 1201 u_int8_t statack; 1202 1203 if (sc->suspended) { 1204 return; 1205 } 1206 1207 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1208 /* 1209 * It should not be possible to have all bits set; the 1210 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1211 * all bits are set, this may indicate that the card has 1212 * been physically ejected, so ignore it. 1213 */ 1214 if (statack == 0xff) 1215 return; 1216 1217 /* 1218 * First ACK all the interrupts in this pass. 1219 */ 1220 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1221 fxp_intr_body(sc, statack, -1); 1222 } 1223 } 1224 1225 static void 1226 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1227 { 1228 struct ifnet *ifp = &sc->arpcom.ac_if; 1229 struct mbuf *m; 1230 struct fxp_rfa *rfa; 1231 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1232 1233 if (rnr) 1234 fxp_rnr++; 1235 #ifdef DEVICE_POLLING 1236 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1237 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1238 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1239 rnr = 1; 1240 } 1241 #endif 1242 1243 /* 1244 * Free any finished transmit mbuf chains. 1245 * 1246 * Handle the CNA event likt a CXTNO event. It used to 1247 * be that this event (control unit not ready) was not 1248 * encountered, but it is now with the SMPng modifications. 1249 * The exact sequence of events that occur when the interface 1250 * is brought up are different now, and if this event 1251 * goes unhandled, the configuration/rxfilter setup sequence 1252 * can stall for several seconds. The result is that no 1253 * packets go out onto the wire for about 5 to 10 seconds 1254 * after the interface is ifconfig'ed for the first time. 1255 */ 1256 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1257 struct fxp_cb_tx *txp; 1258 1259 for (txp = sc->cbl_first; sc->tx_queued && 1260 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1261 txp = txp->next) { 1262 if ((m = txp->mb_head) != NULL) { 1263 txp->mb_head = NULL; 1264 sc->tx_queued--; 1265 m_freem(m); 1266 } else { 1267 sc->tx_queued--; 1268 } 1269 } 1270 sc->cbl_first = txp; 1271 ifp->if_timer = 0; 1272 if (sc->tx_queued == 0) { 1273 if (sc->need_mcsetup) 1274 fxp_mc_setup(sc); 1275 } 1276 /* 1277 * Try to start more packets transmitting. 1278 */ 1279 if (!ifq_is_empty(&ifp->if_snd)) 1280 (*ifp->if_start)(ifp); 1281 } 1282 1283 /* 1284 * Just return if nothing happened on the receive side. 1285 */ 1286 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1287 return; 1288 1289 /* 1290 * Process receiver interrupts. If a no-resource (RNR) 1291 * condition exists, get whatever packets we can and 1292 * re-start the receiver. 1293 * 1294 * When using polling, we do not process the list to completion, 1295 * so when we get an RNR interrupt we must defer the restart 1296 * until we hit the last buffer with the C bit set. 1297 * If we run out of cycles and rfa_headm has the C bit set, 1298 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1299 * that the info will be used in the subsequent polling cycle. 1300 */ 1301 for (;;) { 1302 m = sc->rfa_headm; 1303 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1304 RFA_ALIGNMENT_FUDGE); 1305 1306 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1307 if (count >= 0 && count-- == 0) { 1308 if (rnr) { 1309 /* Defer RNR processing until the next time. */ 1310 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1311 rnr = 0; 1312 } 1313 break; 1314 } 1315 #endif /* DEVICE_POLLING */ 1316 1317 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1318 break; 1319 1320 /* 1321 * Remove first packet from the chain. 1322 */ 1323 sc->rfa_headm = m->m_next; 1324 m->m_next = NULL; 1325 1326 /* 1327 * Add a new buffer to the receive chain. 1328 * If this fails, the old buffer is recycled 1329 * instead. 1330 */ 1331 if (fxp_add_rfabuf(sc, m) == 0) { 1332 int total_len; 1333 1334 /* 1335 * Fetch packet length (the top 2 bits of 1336 * actual_size are flags set by the controller 1337 * upon completion), and drop the packet in case 1338 * of bogus length or CRC errors. 1339 */ 1340 total_len = rfa->actual_size & 0x3fff; 1341 if (total_len < sizeof(struct ether_header) || 1342 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1343 sizeof(struct fxp_rfa) || 1344 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1345 m_freem(m); 1346 continue; 1347 } 1348 m->m_pkthdr.len = m->m_len = total_len; 1349 (*ifp->if_input)(ifp, m); 1350 } 1351 } 1352 if (rnr) { 1353 fxp_scb_wait(sc); 1354 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1355 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1356 RFA_ALIGNMENT_FUDGE); 1357 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1358 } 1359 } 1360 1361 /* 1362 * Update packet in/out/collision statistics. The i82557 doesn't 1363 * allow you to access these counters without doing a fairly 1364 * expensive DMA to get _all_ of the statistics it maintains, so 1365 * we do this operation here only once per second. The statistics 1366 * counters in the kernel are updated from the previous dump-stats 1367 * DMA and then a new dump-stats DMA is started. The on-chip 1368 * counters are zeroed when the DMA completes. If we can't start 1369 * the DMA immediately, we don't wait - we just prepare to read 1370 * them again next time. 1371 */ 1372 static void 1373 fxp_tick(void *xsc) 1374 { 1375 struct fxp_softc *sc = xsc; 1376 struct ifnet *ifp = &sc->arpcom.ac_if; 1377 struct fxp_stats *sp = sc->fxp_stats; 1378 struct fxp_cb_tx *txp; 1379 struct mbuf *m; 1380 int s; 1381 1382 ifp->if_opackets += sp->tx_good; 1383 ifp->if_collisions += sp->tx_total_collisions; 1384 if (sp->rx_good) { 1385 ifp->if_ipackets += sp->rx_good; 1386 sc->rx_idle_secs = 0; 1387 } else { 1388 /* 1389 * Receiver's been idle for another second. 1390 */ 1391 sc->rx_idle_secs++; 1392 } 1393 ifp->if_ierrors += 1394 sp->rx_crc_errors + 1395 sp->rx_alignment_errors + 1396 sp->rx_rnr_errors + 1397 sp->rx_overrun_errors; 1398 /* 1399 * If any transmit underruns occured, bump up the transmit 1400 * threshold by another 512 bytes (64 * 8). 1401 */ 1402 if (sp->tx_underruns) { 1403 ifp->if_oerrors += sp->tx_underruns; 1404 if (tx_threshold < 192) 1405 tx_threshold += 64; 1406 } 1407 s = splimp(); 1408 /* 1409 * Release any xmit buffers that have completed DMA. This isn't 1410 * strictly necessary to do here, but it's advantagous for mbufs 1411 * with external storage to be released in a timely manner rather 1412 * than being defered for a potentially long time. This limits 1413 * the delay to a maximum of one second. 1414 */ 1415 for (txp = sc->cbl_first; sc->tx_queued && 1416 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1417 txp = txp->next) { 1418 if ((m = txp->mb_head) != NULL) { 1419 txp->mb_head = NULL; 1420 sc->tx_queued--; 1421 m_freem(m); 1422 } else { 1423 sc->tx_queued--; 1424 } 1425 } 1426 sc->cbl_first = txp; 1427 /* 1428 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1429 * then assume the receiver has locked up and attempt to clear 1430 * the condition by reprogramming the multicast filter. This is 1431 * a work-around for a bug in the 82557 where the receiver locks 1432 * up if it gets certain types of garbage in the syncronization 1433 * bits prior to the packet header. This bug is supposed to only 1434 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1435 * mode as well (perhaps due to a 10/100 speed transition). 1436 */ 1437 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1438 sc->rx_idle_secs = 0; 1439 fxp_mc_setup(sc); 1440 } 1441 /* 1442 * If there is no pending command, start another stats 1443 * dump. Otherwise punt for now. 1444 */ 1445 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1446 /* 1447 * Start another stats dump. 1448 */ 1449 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1450 } else { 1451 /* 1452 * A previous command is still waiting to be accepted. 1453 * Just zero our copy of the stats and wait for the 1454 * next timer event to update them. 1455 */ 1456 sp->tx_good = 0; 1457 sp->tx_underruns = 0; 1458 sp->tx_total_collisions = 0; 1459 1460 sp->rx_good = 0; 1461 sp->rx_crc_errors = 0; 1462 sp->rx_alignment_errors = 0; 1463 sp->rx_rnr_errors = 0; 1464 sp->rx_overrun_errors = 0; 1465 } 1466 if (sc->miibus != NULL) 1467 mii_tick(device_get_softc(sc->miibus)); 1468 splx(s); 1469 /* 1470 * Schedule another timeout one second from now. 1471 */ 1472 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1473 } 1474 1475 /* 1476 * Stop the interface. Cancels the statistics updater and resets 1477 * the interface. 1478 */ 1479 static void 1480 fxp_stop(struct fxp_softc *sc) 1481 { 1482 struct ifnet *ifp = &sc->arpcom.ac_if; 1483 struct fxp_cb_tx *txp; 1484 int i; 1485 1486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1487 ifp->if_timer = 0; 1488 1489 /* 1490 * Cancel stats updater. 1491 */ 1492 callout_stop(&sc->fxp_stat_timer); 1493 1494 /* 1495 * Issue software reset, which also unloads the microcode. 1496 */ 1497 sc->flags &= ~FXP_FLAG_UCODE; 1498 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1499 DELAY(50); 1500 1501 /* 1502 * Release any xmit buffers. 1503 */ 1504 txp = sc->cbl_base; 1505 if (txp != NULL) { 1506 for (i = 0; i < FXP_NTXCB; i++) { 1507 if (txp[i].mb_head != NULL) { 1508 m_freem(txp[i].mb_head); 1509 txp[i].mb_head = NULL; 1510 } 1511 } 1512 } 1513 sc->tx_queued = 0; 1514 1515 /* 1516 * Free all the receive buffers then reallocate/reinitialize 1517 */ 1518 if (sc->rfa_headm != NULL) 1519 m_freem(sc->rfa_headm); 1520 sc->rfa_headm = NULL; 1521 sc->rfa_tailm = NULL; 1522 for (i = 0; i < FXP_NRFABUFS; i++) { 1523 if (fxp_add_rfabuf(sc, NULL) != 0) { 1524 /* 1525 * This "can't happen" - we're at splimp() 1526 * and we just freed all the buffers we need 1527 * above. 1528 */ 1529 panic("fxp_stop: no buffers!"); 1530 } 1531 } 1532 } 1533 1534 /* 1535 * Watchdog/transmission transmit timeout handler. Called when a 1536 * transmission is started on the interface, but no interrupt is 1537 * received before the timeout. This usually indicates that the 1538 * card has wedged for some reason. 1539 */ 1540 static void 1541 fxp_watchdog(struct ifnet *ifp) 1542 { 1543 if_printf(ifp, "device timeout\n"); 1544 ifp->if_oerrors++; 1545 fxp_init(ifp->if_softc); 1546 } 1547 1548 static void 1549 fxp_init(void *xsc) 1550 { 1551 struct fxp_softc *sc = xsc; 1552 struct ifnet *ifp = &sc->arpcom.ac_if; 1553 struct fxp_cb_config *cbp; 1554 struct fxp_cb_ias *cb_ias; 1555 struct fxp_cb_tx *txp; 1556 struct fxp_cb_mcs *mcsp; 1557 int i, prm, s; 1558 1559 s = splimp(); 1560 /* 1561 * Cancel any pending I/O 1562 */ 1563 fxp_stop(sc); 1564 1565 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1566 1567 /* 1568 * Initialize base of CBL and RFA memory. Loading with zero 1569 * sets it up for regular linear addressing. 1570 */ 1571 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1572 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1573 1574 fxp_scb_wait(sc); 1575 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1576 1577 /* 1578 * Initialize base of dump-stats buffer. 1579 */ 1580 fxp_scb_wait(sc); 1581 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1582 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1583 1584 /* 1585 * Attempt to load microcode if requested. 1586 */ 1587 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1588 fxp_load_ucode(sc); 1589 1590 /* 1591 * Initialize the multicast address list. 1592 */ 1593 if (fxp_mc_addrs(sc)) { 1594 mcsp = sc->mcsp; 1595 mcsp->cb_status = 0; 1596 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1597 mcsp->link_addr = -1; 1598 /* 1599 * Start the multicast setup command. 1600 */ 1601 fxp_scb_wait(sc); 1602 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1603 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1604 /* ...and wait for it to complete. */ 1605 fxp_dma_wait(&mcsp->cb_status, sc); 1606 } 1607 1608 /* 1609 * We temporarily use memory that contains the TxCB list to 1610 * construct the config CB. The TxCB list memory is rebuilt 1611 * later. 1612 */ 1613 cbp = (struct fxp_cb_config *) sc->cbl_base; 1614 1615 /* 1616 * This bcopy is kind of disgusting, but there are a bunch of must be 1617 * zero and must be one bits in this structure and this is the easiest 1618 * way to initialize them all to proper values. 1619 */ 1620 bcopy(fxp_cb_config_template, 1621 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1622 sizeof(fxp_cb_config_template)); 1623 1624 cbp->cb_status = 0; 1625 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1626 cbp->link_addr = -1; /* (no) next command */ 1627 cbp->byte_count = 22; /* (22) bytes to config */ 1628 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1629 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1630 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1631 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1632 cbp->type_enable = 0; /* actually reserved */ 1633 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1634 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1635 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1636 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1637 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1638 cbp->late_scb = 0; /* (don't) defer SCB update */ 1639 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1640 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1641 cbp->ci_int = 1; /* interrupt on CU idle */ 1642 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1643 cbp->ext_stats_dis = 1; /* disable extended counters */ 1644 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1645 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1646 cbp->disc_short_rx = !prm; /* discard short packets */ 1647 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1648 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1649 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1650 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1651 cbp->csma_dis = 0; /* (don't) disable link */ 1652 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1653 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1654 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1655 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1656 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1657 cbp->nsai = 1; /* (don't) disable source addr insert */ 1658 cbp->preamble_length = 2; /* (7 byte) preamble */ 1659 cbp->loopback = 0; /* (don't) loopback */ 1660 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1661 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1662 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1663 cbp->promiscuous = prm; /* promiscuous mode */ 1664 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1665 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1666 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1667 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1668 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1669 1670 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1671 cbp->padding = 1; /* (do) pad short tx packets */ 1672 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1673 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1674 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1675 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1676 /* must set wake_en in PMCSR also */ 1677 cbp->force_fdx = 0; /* (don't) force full duplex */ 1678 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1679 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1680 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1681 1682 if (sc->revision == FXP_REV_82557) { 1683 /* 1684 * The 82557 has no hardware flow control, the values 1685 * below are the defaults for the chip. 1686 */ 1687 cbp->fc_delay_lsb = 0; 1688 cbp->fc_delay_msb = 0x40; 1689 cbp->pri_fc_thresh = 3; 1690 cbp->tx_fc_dis = 0; 1691 cbp->rx_fc_restop = 0; 1692 cbp->rx_fc_restart = 0; 1693 cbp->fc_filter = 0; 1694 cbp->pri_fc_loc = 1; 1695 } else { 1696 cbp->fc_delay_lsb = 0x1f; 1697 cbp->fc_delay_msb = 0x01; 1698 cbp->pri_fc_thresh = 3; 1699 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1700 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1701 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1702 cbp->fc_filter = !prm; /* drop FC frames to host */ 1703 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1704 } 1705 1706 /* 1707 * Start the config command/DMA. 1708 */ 1709 fxp_scb_wait(sc); 1710 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1711 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1712 /* ...and wait for it to complete. */ 1713 fxp_dma_wait(&cbp->cb_status, sc); 1714 1715 /* 1716 * Now initialize the station address. Temporarily use the TxCB 1717 * memory area like we did above for the config CB. 1718 */ 1719 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1720 cb_ias->cb_status = 0; 1721 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1722 cb_ias->link_addr = -1; 1723 bcopy(sc->arpcom.ac_enaddr, 1724 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1725 sizeof(sc->arpcom.ac_enaddr)); 1726 1727 /* 1728 * Start the IAS (Individual Address Setup) command/DMA. 1729 */ 1730 fxp_scb_wait(sc); 1731 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1732 /* ...and wait for it to complete. */ 1733 fxp_dma_wait(&cb_ias->cb_status, sc); 1734 1735 /* 1736 * Initialize transmit control block (TxCB) list. 1737 */ 1738 1739 txp = sc->cbl_base; 1740 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1741 for (i = 0; i < FXP_NTXCB; i++) { 1742 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1743 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1744 txp[i].link_addr = 1745 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1746 if (sc->flags & FXP_FLAG_EXT_TXCB) 1747 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1748 else 1749 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1750 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1751 } 1752 /* 1753 * Set the suspend flag on the first TxCB and start the control 1754 * unit. It will execute the NOP and then suspend. 1755 */ 1756 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1757 sc->cbl_first = sc->cbl_last = txp; 1758 sc->tx_queued = 1; 1759 1760 fxp_scb_wait(sc); 1761 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1762 1763 /* 1764 * Initialize receiver buffer area - RFA. 1765 */ 1766 fxp_scb_wait(sc); 1767 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1768 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1769 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1770 1771 /* 1772 * Set current media. 1773 */ 1774 if (sc->miibus != NULL) 1775 mii_mediachg(device_get_softc(sc->miibus)); 1776 1777 ifp->if_flags |= IFF_RUNNING; 1778 ifp->if_flags &= ~IFF_OACTIVE; 1779 1780 /* 1781 * Enable interrupts. 1782 */ 1783 #ifdef DEVICE_POLLING 1784 /* 1785 * ... but only do that if we are not polling. And because (presumably) 1786 * the default is interrupts on, we need to disable them explicitly! 1787 */ 1788 if ( ifp->if_flags & IFF_POLLING ) 1789 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1790 else 1791 #endif /* DEVICE_POLLING */ 1792 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1793 splx(s); 1794 1795 /* 1796 * Start stats updater. 1797 */ 1798 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1799 } 1800 1801 static int 1802 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1803 { 1804 1805 return (0); 1806 } 1807 1808 static void 1809 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1810 { 1811 1812 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1813 } 1814 1815 /* 1816 * Change media according to request. 1817 */ 1818 static int 1819 fxp_ifmedia_upd(struct ifnet *ifp) 1820 { 1821 struct fxp_softc *sc = ifp->if_softc; 1822 struct mii_data *mii; 1823 1824 mii = device_get_softc(sc->miibus); 1825 mii_mediachg(mii); 1826 return (0); 1827 } 1828 1829 /* 1830 * Notify the world which media we're using. 1831 */ 1832 static void 1833 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1834 { 1835 struct fxp_softc *sc = ifp->if_softc; 1836 struct mii_data *mii; 1837 1838 mii = device_get_softc(sc->miibus); 1839 mii_pollstat(mii); 1840 ifmr->ifm_active = mii->mii_media_active; 1841 ifmr->ifm_status = mii->mii_media_status; 1842 1843 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1844 sc->cu_resume_bug = 1; 1845 else 1846 sc->cu_resume_bug = 0; 1847 } 1848 1849 /* 1850 * Add a buffer to the end of the RFA buffer list. 1851 * Return 0 if successful, 1 for failure. A failure results in 1852 * adding the 'oldm' (if non-NULL) on to the end of the list - 1853 * tossing out its old contents and recycling it. 1854 * The RFA struct is stuck at the beginning of mbuf cluster and the 1855 * data pointer is fixed up to point just past it. 1856 */ 1857 static int 1858 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1859 { 1860 u_int32_t v; 1861 struct mbuf *m; 1862 struct fxp_rfa *rfa, *p_rfa; 1863 1864 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1865 if (m == NULL) { /* try to recycle the old mbuf instead */ 1866 if (oldm == NULL) 1867 return 1; 1868 m = oldm; 1869 m->m_data = m->m_ext.ext_buf; 1870 } 1871 1872 /* 1873 * Move the data pointer up so that the incoming data packet 1874 * will be 32-bit aligned. 1875 */ 1876 m->m_data += RFA_ALIGNMENT_FUDGE; 1877 1878 /* 1879 * Get a pointer to the base of the mbuf cluster and move 1880 * data start past it. 1881 */ 1882 rfa = mtod(m, struct fxp_rfa *); 1883 m->m_data += sizeof(struct fxp_rfa); 1884 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1885 1886 /* 1887 * Initialize the rest of the RFA. Note that since the RFA 1888 * is misaligned, we cannot store values directly. Instead, 1889 * we use an optimized, inline copy. 1890 */ 1891 1892 rfa->rfa_status = 0; 1893 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1894 rfa->actual_size = 0; 1895 1896 v = -1; 1897 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1898 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1899 1900 /* 1901 * If there are other buffers already on the list, attach this 1902 * one to the end by fixing up the tail to point to this one. 1903 */ 1904 if (sc->rfa_headm != NULL) { 1905 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1906 RFA_ALIGNMENT_FUDGE); 1907 sc->rfa_tailm->m_next = m; 1908 v = vtophys(rfa); 1909 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1910 p_rfa->rfa_control = 0; 1911 } else { 1912 sc->rfa_headm = m; 1913 } 1914 sc->rfa_tailm = m; 1915 1916 return (m == oldm); 1917 } 1918 1919 static volatile int 1920 fxp_miibus_readreg(device_t dev, int phy, int reg) 1921 { 1922 struct fxp_softc *sc = device_get_softc(dev); 1923 int count = 10000; 1924 int value; 1925 1926 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1927 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1928 1929 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1930 && count--) 1931 DELAY(10); 1932 1933 if (count <= 0) 1934 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1935 1936 return (value & 0xffff); 1937 } 1938 1939 static void 1940 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1941 { 1942 struct fxp_softc *sc = device_get_softc(dev); 1943 int count = 10000; 1944 1945 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1946 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1947 (value & 0xffff)); 1948 1949 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1950 count--) 1951 DELAY(10); 1952 1953 if (count <= 0) 1954 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1955 } 1956 1957 static int 1958 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1959 { 1960 struct fxp_softc *sc = ifp->if_softc; 1961 struct ifreq *ifr = (struct ifreq *)data; 1962 struct mii_data *mii; 1963 int s, error = 0; 1964 1965 s = splimp(); 1966 1967 switch (command) { 1968 1969 case SIOCSIFFLAGS: 1970 if (ifp->if_flags & IFF_ALLMULTI) 1971 sc->flags |= FXP_FLAG_ALL_MCAST; 1972 else 1973 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1974 1975 /* 1976 * If interface is marked up and not running, then start it. 1977 * If it is marked down and running, stop it. 1978 * XXX If it's up then re-initialize it. This is so flags 1979 * such as IFF_PROMISC are handled. 1980 */ 1981 if (ifp->if_flags & IFF_UP) { 1982 fxp_init(sc); 1983 } else { 1984 if (ifp->if_flags & IFF_RUNNING) 1985 fxp_stop(sc); 1986 } 1987 break; 1988 1989 case SIOCADDMULTI: 1990 case SIOCDELMULTI: 1991 if (ifp->if_flags & IFF_ALLMULTI) 1992 sc->flags |= FXP_FLAG_ALL_MCAST; 1993 else 1994 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1995 /* 1996 * Multicast list has changed; set the hardware filter 1997 * accordingly. 1998 */ 1999 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2000 fxp_mc_setup(sc); 2001 /* 2002 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2003 * again rather than else {}. 2004 */ 2005 if (sc->flags & FXP_FLAG_ALL_MCAST) 2006 fxp_init(sc); 2007 error = 0; 2008 break; 2009 2010 case SIOCSIFMEDIA: 2011 case SIOCGIFMEDIA: 2012 if (sc->miibus != NULL) { 2013 mii = device_get_softc(sc->miibus); 2014 error = ifmedia_ioctl(ifp, ifr, 2015 &mii->mii_media, command); 2016 } else { 2017 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2018 } 2019 break; 2020 2021 default: 2022 error = ether_ioctl(ifp, command, data); 2023 break; 2024 } 2025 splx(s); 2026 return (error); 2027 } 2028 2029 /* 2030 * Fill in the multicast address list and return number of entries. 2031 */ 2032 static int 2033 fxp_mc_addrs(struct fxp_softc *sc) 2034 { 2035 struct fxp_cb_mcs *mcsp = sc->mcsp; 2036 struct ifnet *ifp = &sc->arpcom.ac_if; 2037 struct ifmultiaddr *ifma; 2038 int nmcasts; 2039 2040 nmcasts = 0; 2041 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2042 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2043 if (ifma->ifma_addr->sa_family != AF_LINK) 2044 continue; 2045 if (nmcasts >= MAXMCADDR) { 2046 sc->flags |= FXP_FLAG_ALL_MCAST; 2047 nmcasts = 0; 2048 break; 2049 } 2050 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2051 (void *)(uintptr_t)(volatile void *) 2052 &sc->mcsp->mc_addr[nmcasts][0], 6); 2053 nmcasts++; 2054 } 2055 } 2056 mcsp->mc_cnt = nmcasts * 6; 2057 return (nmcasts); 2058 } 2059 2060 /* 2061 * Program the multicast filter. 2062 * 2063 * We have an artificial restriction that the multicast setup command 2064 * must be the first command in the chain, so we take steps to ensure 2065 * this. By requiring this, it allows us to keep up the performance of 2066 * the pre-initialized command ring (esp. link pointers) by not actually 2067 * inserting the mcsetup command in the ring - i.e. its link pointer 2068 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2069 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2070 * lead into the regular TxCB ring when it completes. 2071 * 2072 * This function must be called at splimp. 2073 */ 2074 static void 2075 fxp_mc_setup(struct fxp_softc *sc) 2076 { 2077 struct fxp_cb_mcs *mcsp = sc->mcsp; 2078 struct ifnet *ifp = &sc->arpcom.ac_if; 2079 int count; 2080 2081 /* 2082 * If there are queued commands, we must wait until they are all 2083 * completed. If we are already waiting, then add a NOP command 2084 * with interrupt option so that we're notified when all commands 2085 * have been completed - fxp_start() ensures that no additional 2086 * TX commands will be added when need_mcsetup is true. 2087 */ 2088 if (sc->tx_queued) { 2089 struct fxp_cb_tx *txp; 2090 2091 /* 2092 * need_mcsetup will be true if we are already waiting for the 2093 * NOP command to be completed (see below). In this case, bail. 2094 */ 2095 if (sc->need_mcsetup) 2096 return; 2097 sc->need_mcsetup = 1; 2098 2099 /* 2100 * Add a NOP command with interrupt so that we are notified 2101 * when all TX commands have been processed. 2102 */ 2103 txp = sc->cbl_last->next; 2104 txp->mb_head = NULL; 2105 txp->cb_status = 0; 2106 txp->cb_command = FXP_CB_COMMAND_NOP | 2107 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2108 /* 2109 * Advance the end of list forward. 2110 */ 2111 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2112 sc->cbl_last = txp; 2113 sc->tx_queued++; 2114 /* 2115 * Issue a resume in case the CU has just suspended. 2116 */ 2117 fxp_scb_wait(sc); 2118 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2119 /* 2120 * Set a 5 second timer just in case we don't hear from the 2121 * card again. 2122 */ 2123 ifp->if_timer = 5; 2124 2125 return; 2126 } 2127 sc->need_mcsetup = 0; 2128 2129 /* 2130 * Initialize multicast setup descriptor. 2131 */ 2132 mcsp->next = sc->cbl_base; 2133 mcsp->mb_head = NULL; 2134 mcsp->cb_status = 0; 2135 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2136 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2137 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2138 (void) fxp_mc_addrs(sc); 2139 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2140 sc->tx_queued = 1; 2141 2142 /* 2143 * Wait until command unit is not active. This should never 2144 * be the case when nothing is queued, but make sure anyway. 2145 */ 2146 count = 100; 2147 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2148 FXP_SCB_CUS_ACTIVE && --count) 2149 DELAY(10); 2150 if (count == 0) { 2151 device_printf(sc->dev, "command queue timeout\n"); 2152 return; 2153 } 2154 2155 /* 2156 * Start the multicast setup command. 2157 */ 2158 fxp_scb_wait(sc); 2159 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2160 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2161 2162 ifp->if_timer = 2; 2163 return; 2164 } 2165 2166 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2167 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2168 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2169 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2170 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2171 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2172 2173 #define UCODE(x) x, sizeof(x) 2174 2175 struct ucode { 2176 u_int32_t revision; 2177 u_int32_t *ucode; 2178 int length; 2179 u_short int_delay_offset; 2180 u_short bundle_max_offset; 2181 } ucode_table[] = { 2182 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2183 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2184 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2185 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2186 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2187 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2188 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2189 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2190 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2191 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2192 { 0, NULL, 0, 0, 0 } 2193 }; 2194 2195 static void 2196 fxp_load_ucode(struct fxp_softc *sc) 2197 { 2198 struct ucode *uc; 2199 struct fxp_cb_ucode *cbp; 2200 2201 for (uc = ucode_table; uc->ucode != NULL; uc++) 2202 if (sc->revision == uc->revision) 2203 break; 2204 if (uc->ucode == NULL) 2205 return; 2206 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2207 cbp->cb_status = 0; 2208 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2209 cbp->link_addr = -1; /* (no) next command */ 2210 memcpy(cbp->ucode, uc->ucode, uc->length); 2211 if (uc->int_delay_offset) 2212 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2213 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2214 if (uc->bundle_max_offset) 2215 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2216 sc->tunable_bundle_max; 2217 /* 2218 * Download the ucode to the chip. 2219 */ 2220 fxp_scb_wait(sc); 2221 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2222 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2223 /* ...and wait for it to complete. */ 2224 fxp_dma_wait(&cbp->cb_status, sc); 2225 device_printf(sc->dev, 2226 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2227 sc->tunable_int_delay, 2228 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2229 sc->flags |= FXP_FLAG_UCODE; 2230 } 2231 2232 static int 2233 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2234 { 2235 int error, value; 2236 2237 value = *(int *)arg1; 2238 error = sysctl_handle_int(oidp, &value, 0, req); 2239 if (error || !req->newptr) 2240 return (error); 2241 if (value < low || value > high) 2242 return (EINVAL); 2243 *(int *)arg1 = value; 2244 return (0); 2245 } 2246 2247 /* 2248 * Interrupt delay is expressed in microseconds, a multiplier is used 2249 * to convert this to the appropriate clock ticks before using. 2250 */ 2251 static int 2252 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2253 { 2254 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2255 } 2256 2257 static int 2258 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2259 { 2260 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2261 } 2262