1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.46 2006/09/23 01:59:16 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef NS 53 #include <netns/ns.h> 54 #include <netns/ns_if.h> 55 #endif 56 57 #include <net/bpf.h> 58 #include <sys/sockio.h> 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 64 #include <net/ethernet.h> 65 #include <net/if_arp.h> 66 67 #include <vm/vm.h> /* for vtophys */ 68 #include <vm/pmap.h> /* for vtophys */ 69 70 #include <net/if_types.h> 71 #include <net/vlan/if_vlan_var.h> 72 73 #include <bus/pci/pcivar.h> 74 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include "../mii_layer/mii.h" 77 #include "../mii_layer/miivar.h" 78 79 #include "if_fxpreg.h" 80 #include "if_fxpvar.h" 81 #include "rcvbundl.h" 82 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 int16_t revid; /* -1 matches anything */ 142 char *name; 143 }; 144 145 /* 146 * Claim various Intel PCI device identifiers for this driver. The 147 * sub-vendor and sub-device field are extensively used to identify 148 * particular variants, but we don't currently differentiate between 149 * them. 150 */ 151 static struct fxp_ident fxp_ident_table[] = { 152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 172 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 173 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 174 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 192 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 193 { 0, -1, NULL }, 194 }; 195 196 static int fxp_probe(device_t dev); 197 static int fxp_attach(device_t dev); 198 static int fxp_detach(device_t dev); 199 static int fxp_shutdown(device_t dev); 200 static int fxp_suspend(device_t dev); 201 static int fxp_resume(device_t dev); 202 203 static void fxp_intr(void *xsc); 204 static void fxp_intr_body(struct fxp_softc *sc, 205 u_int8_t statack, int count); 206 207 static void fxp_init(void *xsc); 208 static void fxp_tick(void *xsc); 209 static void fxp_powerstate_d0(device_t dev); 210 static void fxp_start(struct ifnet *ifp); 211 static void fxp_stop(struct fxp_softc *sc); 212 static void fxp_release(device_t dev); 213 static int fxp_ioctl(struct ifnet *ifp, u_long command, 214 caddr_t data, struct ucred *); 215 static void fxp_watchdog(struct ifnet *ifp); 216 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 217 static int fxp_mc_addrs(struct fxp_softc *sc); 218 static void fxp_mc_setup(struct fxp_softc *sc); 219 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 220 int autosize); 221 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 222 u_int16_t data); 223 static void fxp_autosize_eeprom(struct fxp_softc *sc); 224 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 225 int offset, int words); 226 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 227 int offset, int words); 228 static int fxp_ifmedia_upd(struct ifnet *ifp); 229 static void fxp_ifmedia_sts(struct ifnet *ifp, 230 struct ifmediareq *ifmr); 231 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 232 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 233 struct ifmediareq *ifmr); 234 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 235 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 236 int value); 237 static void fxp_load_ucode(struct fxp_softc *sc); 238 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 239 int low, int high); 240 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 241 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 242 #ifdef DEVICE_POLLING 243 static poll_handler_t fxp_poll; 244 #endif 245 246 static void fxp_lwcopy(volatile u_int32_t *src, 247 volatile u_int32_t *dst); 248 static void fxp_scb_wait(struct fxp_softc *sc); 249 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 250 static void fxp_dma_wait(volatile u_int16_t *status, 251 struct fxp_softc *sc); 252 253 static device_method_t fxp_methods[] = { 254 /* Device interface */ 255 DEVMETHOD(device_probe, fxp_probe), 256 DEVMETHOD(device_attach, fxp_attach), 257 DEVMETHOD(device_detach, fxp_detach), 258 DEVMETHOD(device_shutdown, fxp_shutdown), 259 DEVMETHOD(device_suspend, fxp_suspend), 260 DEVMETHOD(device_resume, fxp_resume), 261 262 /* MII interface */ 263 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 264 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 265 266 { 0, 0 } 267 }; 268 269 static driver_t fxp_driver = { 270 "fxp", 271 fxp_methods, 272 sizeof(struct fxp_softc), 273 }; 274 275 static devclass_t fxp_devclass; 276 277 DECLARE_DUMMY_MODULE(if_fxp); 278 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 279 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283 static int fxp_rnr; 284 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286 /* 287 * Copy a 16-bit aligned 32-bit quantity. 288 */ 289 static void 290 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 291 { 292 #ifdef __i386__ 293 *dst = *src; 294 #else 295 volatile u_int16_t *a = (volatile u_int16_t *)src; 296 volatile u_int16_t *b = (volatile u_int16_t *)dst; 297 298 b[0] = a[0]; 299 b[1] = a[1]; 300 #endif 301 } 302 303 /* 304 * Wait for the previous command to be accepted (but not necessarily 305 * completed). 306 */ 307 static void 308 fxp_scb_wait(struct fxp_softc *sc) 309 { 310 int i = 10000; 311 312 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 313 DELAY(2); 314 if (i == 0) { 315 if_printf(&sc->arpcom.ac_if, 316 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 317 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 318 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 319 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 320 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 321 } 322 } 323 324 static void 325 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 326 { 327 328 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 330 fxp_scb_wait(sc); 331 } 332 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 333 } 334 335 static void 336 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 337 { 338 int i = 10000; 339 340 while (!(*status & FXP_CB_STATUS_C) && --i) 341 DELAY(2); 342 if (i == 0) 343 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 344 } 345 346 /* 347 * Return identification string if this is device is ours. 348 */ 349 static int 350 fxp_probe(device_t dev) 351 { 352 u_int16_t devid; 353 u_int8_t revid; 354 struct fxp_ident *ident; 355 356 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 357 devid = pci_get_device(dev); 358 revid = pci_get_revid(dev); 359 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 360 if (ident->devid == devid && 361 (ident->revid == revid || ident->revid == -1)) { 362 device_set_desc(dev, ident->name); 363 return (0); 364 } 365 } 366 } 367 return (ENXIO); 368 } 369 370 static void 371 fxp_powerstate_d0(device_t dev) 372 { 373 u_int32_t iobase, membase, irq; 374 375 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 376 /* Save important PCI config data. */ 377 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 378 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 379 irq = pci_read_config(dev, PCIR_INTLINE, 4); 380 381 /* Reset the power state. */ 382 device_printf(dev, "chip is in D%d power mode " 383 "-- setting to D0\n", pci_get_powerstate(dev)); 384 385 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 386 387 /* Restore PCI config data. */ 388 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 389 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 390 pci_write_config(dev, PCIR_INTLINE, irq, 4); 391 } 392 } 393 394 static int 395 fxp_attach(device_t dev) 396 { 397 int error = 0; 398 struct fxp_softc *sc = device_get_softc(dev); 399 struct ifnet *ifp; 400 u_int32_t val; 401 u_int16_t data; 402 int i, rid, m1, m2, prefer_iomap; 403 404 callout_init(&sc->fxp_stat_timer); 405 sysctl_ctx_init(&sc->sysctl_ctx); 406 407 /* 408 * Enable bus mastering. Enable memory space too, in case 409 * BIOS/Prom forgot about it. 410 */ 411 pci_enable_busmaster(dev); 412 pci_enable_io(dev, SYS_RES_MEMORY); 413 val = pci_read_config(dev, PCIR_COMMAND, 2); 414 415 fxp_powerstate_d0(dev); 416 417 /* 418 * Figure out which we should try first - memory mapping or i/o mapping? 419 * We default to memory mapping. Then we accept an override from the 420 * command line. Then we check to see which one is enabled. 421 */ 422 m1 = PCIM_CMD_MEMEN; 423 m2 = PCIM_CMD_PORTEN; 424 prefer_iomap = 0; 425 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 426 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 427 m1 = PCIM_CMD_PORTEN; 428 m2 = PCIM_CMD_MEMEN; 429 } 430 431 if (val & m1) { 432 sc->rtp = 433 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 434 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 435 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 436 RF_ACTIVE); 437 } 438 if (sc->mem == NULL && (val & m2)) { 439 sc->rtp = 440 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 441 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 442 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 443 RF_ACTIVE); 444 } 445 446 if (!sc->mem) { 447 device_printf(dev, "could not map device registers\n"); 448 error = ENXIO; 449 goto fail; 450 } 451 if (bootverbose) { 452 device_printf(dev, "using %s space register mapping\n", 453 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 454 } 455 456 sc->sc_st = rman_get_bustag(sc->mem); 457 sc->sc_sh = rman_get_bushandle(sc->mem); 458 459 /* 460 * Allocate our interrupt. 461 */ 462 rid = 0; 463 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 464 RF_SHAREABLE | RF_ACTIVE); 465 if (sc->irq == NULL) { 466 device_printf(dev, "could not map interrupt\n"); 467 error = ENXIO; 468 goto fail; 469 } 470 471 /* 472 * Reset to a stable state. 473 */ 474 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 475 DELAY(10); 476 477 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 478 M_DEVBUF, M_WAITOK | M_ZERO); 479 480 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 481 M_WAITOK | M_ZERO); 482 483 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 484 485 /* 486 * Pre-allocate our receive buffers. 487 */ 488 for (i = 0; i < FXP_NRFABUFS; i++) { 489 if (fxp_add_rfabuf(sc, NULL) != 0) { 490 goto failmem; 491 } 492 } 493 494 /* 495 * Find out how large of an SEEPROM we have. 496 */ 497 fxp_autosize_eeprom(sc); 498 499 /* 500 * Determine whether we must use the 503 serial interface. 501 */ 502 fxp_read_eeprom(sc, &data, 6, 1); 503 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 504 (data & FXP_PHY_SERIAL_ONLY)) 505 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 506 507 /* 508 * Create the sysctl tree 509 */ 510 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 511 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 512 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 513 if (sc->sysctl_tree == NULL) 514 goto fail; 515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 516 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 517 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 518 "FXP driver receive interrupt microcode bundling delay"); 519 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 520 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 521 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 522 "FXP driver receive interrupt microcode bundle size limit"); 523 524 /* 525 * Pull in device tunables. 526 */ 527 sc->tunable_int_delay = TUNABLE_INT_DELAY; 528 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 529 resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "int_delay", &sc->tunable_int_delay); 531 resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "bundle_max", &sc->tunable_bundle_max); 533 534 /* 535 * Find out the chip revision; lump all 82557 revs together. 536 */ 537 fxp_read_eeprom(sc, &data, 5, 1); 538 if ((data >> 8) == 1) 539 sc->revision = FXP_REV_82557; 540 else 541 sc->revision = pci_get_revid(dev); 542 543 /* 544 * Enable workarounds for certain chip revision deficiencies. 545 * 546 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 547 * some systems based a normal 82559 design, have a defect where 548 * the chip can cause a PCI protocol violation if it receives 549 * a CU_RESUME command when it is entering the IDLE state. The 550 * workaround is to disable Dynamic Standby Mode, so the chip never 551 * deasserts CLKRUN#, and always remains in an active state. 552 * 553 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 554 */ 555 i = pci_get_device(dev); 556 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 557 sc->revision >= FXP_REV_82559_A0) { 558 fxp_read_eeprom(sc, &data, 10, 1); 559 if (data & 0x02) { /* STB enable */ 560 u_int16_t cksum; 561 int i; 562 563 device_printf(dev, 564 "Disabling dynamic standby mode in EEPROM\n"); 565 data &= ~0x02; 566 fxp_write_eeprom(sc, &data, 10, 1); 567 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 568 cksum = 0; 569 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 570 fxp_read_eeprom(sc, &data, i, 1); 571 cksum += data; 572 } 573 i = (1 << sc->eeprom_size) - 1; 574 cksum = 0xBABA - cksum; 575 fxp_read_eeprom(sc, &data, i, 1); 576 fxp_write_eeprom(sc, &cksum, i, 1); 577 device_printf(dev, 578 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 579 i, data, cksum); 580 #if 1 581 /* 582 * If the user elects to continue, try the software 583 * workaround, as it is better than nothing. 584 */ 585 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 586 #endif 587 } 588 } 589 590 /* 591 * If we are not a 82557 chip, we can enable extended features. 592 */ 593 if (sc->revision != FXP_REV_82557) { 594 /* 595 * If MWI is enabled in the PCI configuration, and there 596 * is a valid cacheline size (8 or 16 dwords), then tell 597 * the board to turn on MWI. 598 */ 599 if (val & PCIM_CMD_MWRICEN && 600 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 601 sc->flags |= FXP_FLAG_MWI_ENABLE; 602 603 /* turn on the extended TxCB feature */ 604 sc->flags |= FXP_FLAG_EXT_TXCB; 605 606 /* enable reception of long frames for VLAN */ 607 sc->flags |= FXP_FLAG_LONG_PKT_EN; 608 } 609 610 /* 611 * Read MAC address. 612 */ 613 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 614 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 615 device_printf(dev, "10Mbps\n"); 616 if (bootverbose) { 617 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 618 pci_get_vendor(dev), pci_get_device(dev), 619 pci_get_subvendor(dev), pci_get_subdevice(dev), 620 pci_get_revid(dev)); 621 fxp_read_eeprom(sc, &data, 10, 1); 622 device_printf(dev, "Dynamic Standby mode is %s\n", 623 data & 0x02 ? "enabled" : "disabled"); 624 } 625 626 /* 627 * If this is only a 10Mbps device, then there is no MII, and 628 * the PHY will use a serial interface instead. 629 * 630 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 631 * doesn't have a programming interface of any sort. The 632 * media is sensed automatically based on how the link partner 633 * is configured. This is, in essence, manual configuration. 634 */ 635 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 636 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 637 fxp_serial_ifmedia_sts); 638 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 639 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 640 } else { 641 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 642 fxp_ifmedia_sts)) { 643 device_printf(dev, "MII without any PHY!\n"); 644 error = ENXIO; 645 goto fail; 646 } 647 } 648 649 ifp = &sc->arpcom.ac_if; 650 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 651 ifp->if_baudrate = 100000000; 652 ifp->if_init = fxp_init; 653 ifp->if_softc = sc; 654 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 655 ifp->if_ioctl = fxp_ioctl; 656 ifp->if_start = fxp_start; 657 #ifdef DEVICE_POLLING 658 ifp->if_poll = fxp_poll; 659 #endif 660 ifp->if_watchdog = fxp_watchdog; 661 662 /* 663 * Attach the interface. 664 */ 665 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 666 667 /* 668 * Tell the upper layer(s) we support long frames. 669 */ 670 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 671 672 /* 673 * Let the system queue as many packets as we have available 674 * TX descriptors. 675 */ 676 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 677 ifq_set_ready(&ifp->if_snd); 678 679 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 680 fxp_intr, sc, &sc->ih, 681 ifp->if_serializer); 682 if (error) { 683 ether_ifdetach(ifp); 684 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 685 ifmedia_removeall(&sc->sc_media); 686 device_printf(dev, "could not setup irq\n"); 687 goto fail; 688 } 689 690 return (0); 691 692 failmem: 693 device_printf(dev, "Failed to malloc memory\n"); 694 error = ENOMEM; 695 fail: 696 fxp_release(dev); 697 return (error); 698 } 699 700 /* 701 * release all resources 702 */ 703 static void 704 fxp_release(device_t dev) 705 { 706 struct fxp_softc *sc = device_get_softc(dev); 707 708 if (sc->miibus) 709 device_delete_child(dev, sc->miibus); 710 bus_generic_detach(dev); 711 712 if (sc->cbl_base) 713 kfree(sc->cbl_base, M_DEVBUF); 714 if (sc->fxp_stats) 715 kfree(sc->fxp_stats, M_DEVBUF); 716 if (sc->mcsp) 717 kfree(sc->mcsp, M_DEVBUF); 718 if (sc->rfa_headm) 719 m_freem(sc->rfa_headm); 720 721 if (sc->irq) 722 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 723 if (sc->mem) 724 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 725 726 sysctl_ctx_free(&sc->sysctl_ctx); 727 } 728 729 /* 730 * Detach interface. 731 */ 732 static int 733 fxp_detach(device_t dev) 734 { 735 struct fxp_softc *sc = device_get_softc(dev); 736 737 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 738 739 /* 740 * Stop DMA and drop transmit queue. 741 */ 742 fxp_stop(sc); 743 744 /* 745 * Disable interrupts. 746 * 747 * NOTE: This should be done after fxp_stop(), because software 748 * resetting in fxp_stop() may leave interrupts turned on. 749 */ 750 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 751 752 /* 753 * Free all media structures. 754 */ 755 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 756 ifmedia_removeall(&sc->sc_media); 757 758 if (sc->ih) 759 bus_teardown_intr(dev, sc->irq, sc->ih); 760 761 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 762 763 /* 764 * Close down routes etc. 765 */ 766 ether_ifdetach(&sc->arpcom.ac_if); 767 768 /* Release our allocated resources. */ 769 fxp_release(dev); 770 771 return (0); 772 } 773 774 /* 775 * Device shutdown routine. Called at system shutdown after sync. The 776 * main purpose of this routine is to shut off receiver DMA so that 777 * kernel memory doesn't get clobbered during warmboot. 778 */ 779 static int 780 fxp_shutdown(device_t dev) 781 { 782 /* 783 * Make sure that DMA is disabled prior to reboot. Not doing 784 * do could allow DMA to corrupt kernel memory during the 785 * reboot before the driver initializes. 786 */ 787 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 788 return (0); 789 } 790 791 /* 792 * Device suspend routine. Stop the interface and save some PCI 793 * settings in case the BIOS doesn't restore them properly on 794 * resume. 795 */ 796 static int 797 fxp_suspend(device_t dev) 798 { 799 struct fxp_softc *sc = device_get_softc(dev); 800 int i; 801 802 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 803 804 fxp_stop(sc); 805 806 for (i = 0; i < 5; i++) 807 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 808 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 809 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 810 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 811 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 812 813 sc->suspended = 1; 814 815 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 816 return (0); 817 } 818 819 /* 820 * Device resume routine. Restore some PCI settings in case the BIOS 821 * doesn't, re-enable busmastering, and restart the interface if 822 * appropriate. 823 */ 824 static int 825 fxp_resume(device_t dev) 826 { 827 struct fxp_softc *sc = device_get_softc(dev); 828 struct ifnet *ifp = &sc->arpcom.ac_if; 829 int i; 830 831 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 832 833 fxp_powerstate_d0(dev); 834 835 /* better way to do this? */ 836 for (i = 0; i < 5; i++) 837 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 838 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 839 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 840 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 841 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 842 843 /* reenable busmastering and memory space */ 844 pci_enable_busmaster(dev); 845 pci_enable_io(dev, SYS_RES_MEMORY); 846 847 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 848 DELAY(10); 849 850 /* reinitialize interface if necessary */ 851 if (ifp->if_flags & IFF_UP) 852 fxp_init(sc); 853 854 sc->suspended = 0; 855 856 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 857 return (0); 858 } 859 860 static void 861 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 862 { 863 u_int16_t reg; 864 int x; 865 866 /* 867 * Shift in data. 868 */ 869 for (x = 1 << (length - 1); x; x >>= 1) { 870 if (data & x) 871 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 872 else 873 reg = FXP_EEPROM_EECS; 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 875 DELAY(1); 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 877 DELAY(1); 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 879 DELAY(1); 880 } 881 } 882 883 /* 884 * Read from the serial EEPROM. Basically, you manually shift in 885 * the read opcode (one bit at a time) and then shift in the address, 886 * and then you shift out the data (all of this one bit at a time). 887 * The word size is 16 bits, so you have to provide the address for 888 * every 16 bits of data. 889 */ 890 static u_int16_t 891 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 892 { 893 u_int16_t reg, data; 894 int x; 895 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 897 /* 898 * Shift in read opcode. 899 */ 900 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 901 /* 902 * Shift in address. 903 */ 904 data = 0; 905 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 906 if (offset & x) 907 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 908 else 909 reg = FXP_EEPROM_EECS; 910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 911 DELAY(1); 912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 913 DELAY(1); 914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 915 DELAY(1); 916 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 917 data++; 918 if (autosize && reg == 0) { 919 sc->eeprom_size = data; 920 break; 921 } 922 } 923 /* 924 * Shift out data. 925 */ 926 data = 0; 927 reg = FXP_EEPROM_EECS; 928 for (x = 1 << 15; x; x >>= 1) { 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 930 DELAY(1); 931 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 932 data |= x; 933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 934 DELAY(1); 935 } 936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 937 DELAY(1); 938 939 return (data); 940 } 941 942 static void 943 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 944 { 945 int i; 946 947 /* 948 * Erase/write enable. 949 */ 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 951 fxp_eeprom_shiftin(sc, 0x4, 3); 952 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 954 DELAY(1); 955 /* 956 * Shift in write opcode, address, data. 957 */ 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 959 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 960 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 961 fxp_eeprom_shiftin(sc, data, 16); 962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 963 DELAY(1); 964 /* 965 * Wait for EEPROM to finish up. 966 */ 967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 968 DELAY(1); 969 for (i = 0; i < 1000; i++) { 970 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 971 break; 972 DELAY(50); 973 } 974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 975 DELAY(1); 976 /* 977 * Erase/write disable. 978 */ 979 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 980 fxp_eeprom_shiftin(sc, 0x4, 3); 981 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 982 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 983 DELAY(1); 984 } 985 986 /* 987 * From NetBSD: 988 * 989 * Figure out EEPROM size. 990 * 991 * 559's can have either 64-word or 256-word EEPROMs, the 558 992 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 993 * talks about the existance of 16 to 256 word EEPROMs. 994 * 995 * The only known sizes are 64 and 256, where the 256 version is used 996 * by CardBus cards to store CIS information. 997 * 998 * The address is shifted in msb-to-lsb, and after the last 999 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1000 * after which follows the actual data. We try to detect this zero, by 1001 * probing the data-out bit in the EEPROM control register just after 1002 * having shifted in a bit. If the bit is zero, we assume we've 1003 * shifted enough address bits. The data-out should be tri-state, 1004 * before this, which should translate to a logical one. 1005 */ 1006 static void 1007 fxp_autosize_eeprom(struct fxp_softc *sc) 1008 { 1009 1010 /* guess maximum size of 256 words */ 1011 sc->eeprom_size = 8; 1012 1013 /* autosize */ 1014 fxp_eeprom_getword(sc, 0, 1); 1015 } 1016 1017 static void 1018 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1019 { 1020 int i; 1021 1022 for (i = 0; i < words; i++) 1023 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1024 } 1025 1026 static void 1027 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1028 { 1029 int i; 1030 1031 for (i = 0; i < words; i++) 1032 fxp_eeprom_putword(sc, offset + i, data[i]); 1033 } 1034 1035 /* 1036 * Start packet transmission on the interface. 1037 */ 1038 static void 1039 fxp_start(struct ifnet *ifp) 1040 { 1041 struct fxp_softc *sc = ifp->if_softc; 1042 struct fxp_cb_tx *txp; 1043 1044 /* 1045 * See if we need to suspend xmit until the multicast filter 1046 * has been reprogrammed (which can only be done at the head 1047 * of the command chain). 1048 */ 1049 if (sc->need_mcsetup) { 1050 return; 1051 } 1052 1053 txp = NULL; 1054 1055 /* 1056 * We're finished if there is nothing more to add to the list or if 1057 * we're all filled up with buffers to transmit. 1058 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1059 * a NOP command when needed. 1060 */ 1061 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1062 struct mbuf *m, *mb_head; 1063 int segment, ntries = 0; 1064 1065 /* 1066 * Grab a packet to transmit. The packet is dequeued, 1067 * once we are sure that we have enough free descriptors. 1068 */ 1069 mb_head = ifq_poll(&ifp->if_snd); 1070 if (mb_head == NULL) 1071 break; 1072 1073 /* 1074 * Get pointer to next available tx desc. 1075 */ 1076 txp = sc->cbl_last->next; 1077 1078 /* 1079 * Go through each of the mbufs in the chain and initialize 1080 * the transmit buffer descriptors with the physical address 1081 * and size of the mbuf. 1082 */ 1083 tbdinit: 1084 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1085 if (m->m_len != 0) { 1086 if (segment == FXP_NTXSEG) 1087 break; 1088 txp->tbd[segment].tb_addr = 1089 vtophys(mtod(m, vm_offset_t)); 1090 txp->tbd[segment].tb_size = m->m_len; 1091 segment++; 1092 } 1093 } 1094 if (m != NULL) { 1095 struct mbuf *mn; 1096 1097 /* 1098 * We ran out of segments. We have to recopy this 1099 * mbuf chain first. Bail out if we can't get the 1100 * new buffers. 1101 */ 1102 if (ntries > 0) 1103 break; 1104 mn = m_dup(mb_head, MB_DONTWAIT); 1105 if (mn == NULL) 1106 break; 1107 /* We can transmit the packet, dequeue it. */ 1108 ifq_dequeue(&ifp->if_snd, mb_head); 1109 m_freem(mb_head); 1110 mb_head = mn; 1111 ntries = 1; 1112 goto tbdinit; 1113 } else { 1114 /* Nothing to worry about, just dequeue. */ 1115 ifq_dequeue(&ifp->if_snd, mb_head); 1116 } 1117 1118 txp->tbd_number = segment; 1119 txp->mb_head = mb_head; 1120 txp->cb_status = 0; 1121 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1122 txp->cb_command = 1123 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1124 FXP_CB_COMMAND_S; 1125 } else { 1126 txp->cb_command = 1127 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1128 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1129 /* 1130 * Set a 5 second timer just in case we don't hear 1131 * from the card again. 1132 */ 1133 ifp->if_timer = 5; 1134 } 1135 txp->tx_threshold = tx_threshold; 1136 1137 /* 1138 * Advance the end of list forward. 1139 */ 1140 1141 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1142 sc->cbl_last = txp; 1143 1144 /* 1145 * Advance the beginning of the list forward if there are 1146 * no other packets queued (when nothing is queued, cbl_first 1147 * sits on the last TxCB that was sent out). 1148 */ 1149 if (sc->tx_queued == 0) 1150 sc->cbl_first = txp; 1151 1152 sc->tx_queued++; 1153 1154 BPF_MTAP(ifp, mb_head); 1155 } 1156 1157 /* 1158 * We're finished. If we added to the list, issue a RESUME to get DMA 1159 * going again if suspended. 1160 */ 1161 if (txp != NULL) { 1162 fxp_scb_wait(sc); 1163 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1164 } 1165 } 1166 1167 #ifdef DEVICE_POLLING 1168 1169 static void 1170 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1171 { 1172 struct fxp_softc *sc = ifp->if_softc; 1173 u_int8_t statack; 1174 1175 switch(cmd) { 1176 case POLL_REGISTER: 1177 /* disable interrupts */ 1178 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1179 break; 1180 case POLL_DEREGISTER: 1181 /* enable interrupts */ 1182 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1183 break; 1184 default: 1185 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1186 FXP_SCB_STATACK_FR; 1187 if (cmd == POLL_AND_CHECK_STATUS) { 1188 u_int8_t tmp; 1189 1190 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1191 if (tmp == 0xff || tmp == 0) 1192 return; /* nothing to do */ 1193 tmp &= ~statack; 1194 /* ack what we can */ 1195 if (tmp != 0) 1196 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1197 statack |= tmp; 1198 } 1199 fxp_intr_body(sc, statack, count); 1200 break; 1201 } 1202 } 1203 1204 #endif /* DEVICE_POLLING */ 1205 1206 /* 1207 * Process interface interrupts. 1208 */ 1209 static void 1210 fxp_intr(void *xsc) 1211 { 1212 struct fxp_softc *sc = xsc; 1213 u_int8_t statack; 1214 1215 if (sc->suspended) { 1216 return; 1217 } 1218 1219 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1220 /* 1221 * It should not be possible to have all bits set; the 1222 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1223 * all bits are set, this may indicate that the card has 1224 * been physically ejected, so ignore it. 1225 */ 1226 if (statack == 0xff) 1227 return; 1228 1229 /* 1230 * First ACK all the interrupts in this pass. 1231 */ 1232 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1233 fxp_intr_body(sc, statack, -1); 1234 } 1235 } 1236 1237 static void 1238 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1239 { 1240 struct ifnet *ifp = &sc->arpcom.ac_if; 1241 struct mbuf *m; 1242 struct fxp_rfa *rfa; 1243 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1244 1245 if (rnr) 1246 fxp_rnr++; 1247 #ifdef DEVICE_POLLING 1248 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1249 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1250 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1251 rnr = 1; 1252 } 1253 #endif 1254 1255 /* 1256 * Free any finished transmit mbuf chains. 1257 * 1258 * Handle the CNA event likt a CXTNO event. It used to 1259 * be that this event (control unit not ready) was not 1260 * encountered, but it is now with the SMPng modifications. 1261 * The exact sequence of events that occur when the interface 1262 * is brought up are different now, and if this event 1263 * goes unhandled, the configuration/rxfilter setup sequence 1264 * can stall for several seconds. The result is that no 1265 * packets go out onto the wire for about 5 to 10 seconds 1266 * after the interface is ifconfig'ed for the first time. 1267 */ 1268 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1269 struct fxp_cb_tx *txp; 1270 1271 for (txp = sc->cbl_first; sc->tx_queued && 1272 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1273 txp = txp->next) { 1274 if ((m = txp->mb_head) != NULL) { 1275 txp->mb_head = NULL; 1276 sc->tx_queued--; 1277 m_freem(m); 1278 } else { 1279 sc->tx_queued--; 1280 } 1281 } 1282 sc->cbl_first = txp; 1283 ifp->if_timer = 0; 1284 if (sc->tx_queued == 0) { 1285 if (sc->need_mcsetup) 1286 fxp_mc_setup(sc); 1287 } 1288 /* 1289 * Try to start more packets transmitting. 1290 */ 1291 if (!ifq_is_empty(&ifp->if_snd)) 1292 (*ifp->if_start)(ifp); 1293 } 1294 1295 /* 1296 * Just return if nothing happened on the receive side. 1297 */ 1298 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1299 return; 1300 1301 /* 1302 * Process receiver interrupts. If a no-resource (RNR) 1303 * condition exists, get whatever packets we can and 1304 * re-start the receiver. 1305 * 1306 * When using polling, we do not process the list to completion, 1307 * so when we get an RNR interrupt we must defer the restart 1308 * until we hit the last buffer with the C bit set. 1309 * If we run out of cycles and rfa_headm has the C bit set, 1310 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1311 * that the info will be used in the subsequent polling cycle. 1312 */ 1313 for (;;) { 1314 m = sc->rfa_headm; 1315 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1316 RFA_ALIGNMENT_FUDGE); 1317 1318 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1319 if (count >= 0 && count-- == 0) { 1320 if (rnr) { 1321 /* Defer RNR processing until the next time. */ 1322 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1323 rnr = 0; 1324 } 1325 break; 1326 } 1327 #endif /* DEVICE_POLLING */ 1328 1329 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1330 break; 1331 1332 /* 1333 * Remove first packet from the chain. 1334 */ 1335 sc->rfa_headm = m->m_next; 1336 m->m_next = NULL; 1337 1338 /* 1339 * Add a new buffer to the receive chain. 1340 * If this fails, the old buffer is recycled 1341 * instead. 1342 */ 1343 if (fxp_add_rfabuf(sc, m) == 0) { 1344 int total_len; 1345 1346 /* 1347 * Fetch packet length (the top 2 bits of 1348 * actual_size are flags set by the controller 1349 * upon completion), and drop the packet in case 1350 * of bogus length or CRC errors. 1351 */ 1352 total_len = rfa->actual_size & 0x3fff; 1353 if (total_len < sizeof(struct ether_header) || 1354 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1355 sizeof(struct fxp_rfa) || 1356 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1357 m_freem(m); 1358 continue; 1359 } 1360 m->m_pkthdr.len = m->m_len = total_len; 1361 ifp->if_input(ifp, m); 1362 } 1363 } 1364 if (rnr) { 1365 fxp_scb_wait(sc); 1366 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1367 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1368 RFA_ALIGNMENT_FUDGE); 1369 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1370 } 1371 } 1372 1373 /* 1374 * Update packet in/out/collision statistics. The i82557 doesn't 1375 * allow you to access these counters without doing a fairly 1376 * expensive DMA to get _all_ of the statistics it maintains, so 1377 * we do this operation here only once per second. The statistics 1378 * counters in the kernel are updated from the previous dump-stats 1379 * DMA and then a new dump-stats DMA is started. The on-chip 1380 * counters are zeroed when the DMA completes. If we can't start 1381 * the DMA immediately, we don't wait - we just prepare to read 1382 * them again next time. 1383 */ 1384 static void 1385 fxp_tick(void *xsc) 1386 { 1387 struct fxp_softc *sc = xsc; 1388 struct ifnet *ifp = &sc->arpcom.ac_if; 1389 struct fxp_stats *sp = sc->fxp_stats; 1390 struct fxp_cb_tx *txp; 1391 struct mbuf *m; 1392 1393 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1394 1395 ifp->if_opackets += sp->tx_good; 1396 ifp->if_collisions += sp->tx_total_collisions; 1397 if (sp->rx_good) { 1398 ifp->if_ipackets += sp->rx_good; 1399 sc->rx_idle_secs = 0; 1400 } else { 1401 /* 1402 * Receiver's been idle for another second. 1403 */ 1404 sc->rx_idle_secs++; 1405 } 1406 ifp->if_ierrors += 1407 sp->rx_crc_errors + 1408 sp->rx_alignment_errors + 1409 sp->rx_rnr_errors + 1410 sp->rx_overrun_errors; 1411 /* 1412 * If any transmit underruns occured, bump up the transmit 1413 * threshold by another 512 bytes (64 * 8). 1414 */ 1415 if (sp->tx_underruns) { 1416 ifp->if_oerrors += sp->tx_underruns; 1417 if (tx_threshold < 192) 1418 tx_threshold += 64; 1419 } 1420 1421 /* 1422 * Release any xmit buffers that have completed DMA. This isn't 1423 * strictly necessary to do here, but it's advantagous for mbufs 1424 * with external storage to be released in a timely manner rather 1425 * than being defered for a potentially long time. This limits 1426 * the delay to a maximum of one second. 1427 */ 1428 for (txp = sc->cbl_first; sc->tx_queued && 1429 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1430 txp = txp->next) { 1431 if ((m = txp->mb_head) != NULL) { 1432 txp->mb_head = NULL; 1433 sc->tx_queued--; 1434 m_freem(m); 1435 } else { 1436 sc->tx_queued--; 1437 } 1438 } 1439 sc->cbl_first = txp; 1440 /* 1441 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1442 * then assume the receiver has locked up and attempt to clear 1443 * the condition by reprogramming the multicast filter. This is 1444 * a work-around for a bug in the 82557 where the receiver locks 1445 * up if it gets certain types of garbage in the syncronization 1446 * bits prior to the packet header. This bug is supposed to only 1447 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1448 * mode as well (perhaps due to a 10/100 speed transition). 1449 */ 1450 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1451 sc->rx_idle_secs = 0; 1452 fxp_mc_setup(sc); 1453 } 1454 /* 1455 * If there is no pending command, start another stats 1456 * dump. Otherwise punt for now. 1457 */ 1458 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1459 /* 1460 * Start another stats dump. 1461 */ 1462 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1463 } else { 1464 /* 1465 * A previous command is still waiting to be accepted. 1466 * Just zero our copy of the stats and wait for the 1467 * next timer event to update them. 1468 */ 1469 sp->tx_good = 0; 1470 sp->tx_underruns = 0; 1471 sp->tx_total_collisions = 0; 1472 1473 sp->rx_good = 0; 1474 sp->rx_crc_errors = 0; 1475 sp->rx_alignment_errors = 0; 1476 sp->rx_rnr_errors = 0; 1477 sp->rx_overrun_errors = 0; 1478 } 1479 if (sc->miibus != NULL) 1480 mii_tick(device_get_softc(sc->miibus)); 1481 /* 1482 * Schedule another timeout one second from now. 1483 */ 1484 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1485 1486 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1487 } 1488 1489 /* 1490 * Stop the interface. Cancels the statistics updater and resets 1491 * the interface. 1492 */ 1493 static void 1494 fxp_stop(struct fxp_softc *sc) 1495 { 1496 struct ifnet *ifp = &sc->arpcom.ac_if; 1497 struct fxp_cb_tx *txp; 1498 int i; 1499 1500 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1501 ifp->if_timer = 0; 1502 1503 /* 1504 * Cancel stats updater. 1505 */ 1506 callout_stop(&sc->fxp_stat_timer); 1507 1508 /* 1509 * Issue software reset, which also unloads the microcode. 1510 */ 1511 sc->flags &= ~FXP_FLAG_UCODE; 1512 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1513 DELAY(50); 1514 1515 /* 1516 * Release any xmit buffers. 1517 */ 1518 txp = sc->cbl_base; 1519 if (txp != NULL) { 1520 for (i = 0; i < FXP_NTXCB; i++) { 1521 if (txp[i].mb_head != NULL) { 1522 m_freem(txp[i].mb_head); 1523 txp[i].mb_head = NULL; 1524 } 1525 } 1526 } 1527 sc->tx_queued = 0; 1528 1529 /* 1530 * Free all the receive buffers then reallocate/reinitialize 1531 */ 1532 if (sc->rfa_headm != NULL) 1533 m_freem(sc->rfa_headm); 1534 sc->rfa_headm = NULL; 1535 sc->rfa_tailm = NULL; 1536 for (i = 0; i < FXP_NRFABUFS; i++) { 1537 if (fxp_add_rfabuf(sc, NULL) != 0) { 1538 /* 1539 * This "can't happen" - we're at splimp() 1540 * and we just freed all the buffers we need 1541 * above. 1542 */ 1543 panic("fxp_stop: no buffers!"); 1544 } 1545 } 1546 } 1547 1548 /* 1549 * Watchdog/transmission transmit timeout handler. Called when a 1550 * transmission is started on the interface, but no interrupt is 1551 * received before the timeout. This usually indicates that the 1552 * card has wedged for some reason. 1553 */ 1554 static void 1555 fxp_watchdog(struct ifnet *ifp) 1556 { 1557 if_printf(ifp, "device timeout\n"); 1558 ifp->if_oerrors++; 1559 fxp_init(ifp->if_softc); 1560 } 1561 1562 static void 1563 fxp_init(void *xsc) 1564 { 1565 struct fxp_softc *sc = xsc; 1566 struct ifnet *ifp = &sc->arpcom.ac_if; 1567 struct fxp_cb_config *cbp; 1568 struct fxp_cb_ias *cb_ias; 1569 struct fxp_cb_tx *txp; 1570 struct fxp_cb_mcs *mcsp; 1571 int i, prm; 1572 1573 /* 1574 * Cancel any pending I/O 1575 */ 1576 fxp_stop(sc); 1577 1578 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1579 1580 /* 1581 * Initialize base of CBL and RFA memory. Loading with zero 1582 * sets it up for regular linear addressing. 1583 */ 1584 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1585 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1586 1587 fxp_scb_wait(sc); 1588 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1589 1590 /* 1591 * Initialize base of dump-stats buffer. 1592 */ 1593 fxp_scb_wait(sc); 1594 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1595 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1596 1597 /* 1598 * Attempt to load microcode if requested. 1599 */ 1600 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1601 fxp_load_ucode(sc); 1602 1603 /* 1604 * Initialize the multicast address list. 1605 */ 1606 if (fxp_mc_addrs(sc)) { 1607 mcsp = sc->mcsp; 1608 mcsp->cb_status = 0; 1609 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1610 mcsp->link_addr = -1; 1611 /* 1612 * Start the multicast setup command. 1613 */ 1614 fxp_scb_wait(sc); 1615 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1616 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1617 /* ...and wait for it to complete. */ 1618 fxp_dma_wait(&mcsp->cb_status, sc); 1619 } 1620 1621 /* 1622 * We temporarily use memory that contains the TxCB list to 1623 * construct the config CB. The TxCB list memory is rebuilt 1624 * later. 1625 */ 1626 cbp = (struct fxp_cb_config *) sc->cbl_base; 1627 1628 /* 1629 * This bcopy is kind of disgusting, but there are a bunch of must be 1630 * zero and must be one bits in this structure and this is the easiest 1631 * way to initialize them all to proper values. 1632 */ 1633 bcopy(fxp_cb_config_template, 1634 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1635 sizeof(fxp_cb_config_template)); 1636 1637 cbp->cb_status = 0; 1638 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1639 cbp->link_addr = -1; /* (no) next command */ 1640 cbp->byte_count = 22; /* (22) bytes to config */ 1641 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1642 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1643 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1644 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1645 cbp->type_enable = 0; /* actually reserved */ 1646 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1647 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1648 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1649 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1650 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1651 cbp->late_scb = 0; /* (don't) defer SCB update */ 1652 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1653 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1654 cbp->ci_int = 1; /* interrupt on CU idle */ 1655 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1656 cbp->ext_stats_dis = 1; /* disable extended counters */ 1657 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1658 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1659 cbp->disc_short_rx = !prm; /* discard short packets */ 1660 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1661 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1662 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1663 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1664 cbp->csma_dis = 0; /* (don't) disable link */ 1665 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1666 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1667 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1668 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1669 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1670 cbp->nsai = 1; /* (don't) disable source addr insert */ 1671 cbp->preamble_length = 2; /* (7 byte) preamble */ 1672 cbp->loopback = 0; /* (don't) loopback */ 1673 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1674 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1675 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1676 cbp->promiscuous = prm; /* promiscuous mode */ 1677 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1678 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1679 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1680 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1681 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1682 1683 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1684 cbp->padding = 1; /* (do) pad short tx packets */ 1685 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1686 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1687 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1688 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1689 /* must set wake_en in PMCSR also */ 1690 cbp->force_fdx = 0; /* (don't) force full duplex */ 1691 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1692 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1693 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1694 1695 if (sc->revision == FXP_REV_82557) { 1696 /* 1697 * The 82557 has no hardware flow control, the values 1698 * below are the defaults for the chip. 1699 */ 1700 cbp->fc_delay_lsb = 0; 1701 cbp->fc_delay_msb = 0x40; 1702 cbp->pri_fc_thresh = 3; 1703 cbp->tx_fc_dis = 0; 1704 cbp->rx_fc_restop = 0; 1705 cbp->rx_fc_restart = 0; 1706 cbp->fc_filter = 0; 1707 cbp->pri_fc_loc = 1; 1708 } else { 1709 cbp->fc_delay_lsb = 0x1f; 1710 cbp->fc_delay_msb = 0x01; 1711 cbp->pri_fc_thresh = 3; 1712 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1713 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1714 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1715 cbp->fc_filter = !prm; /* drop FC frames to host */ 1716 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1717 } 1718 1719 /* 1720 * Start the config command/DMA. 1721 */ 1722 fxp_scb_wait(sc); 1723 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1724 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1725 /* ...and wait for it to complete. */ 1726 fxp_dma_wait(&cbp->cb_status, sc); 1727 1728 /* 1729 * Now initialize the station address. Temporarily use the TxCB 1730 * memory area like we did above for the config CB. 1731 */ 1732 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1733 cb_ias->cb_status = 0; 1734 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1735 cb_ias->link_addr = -1; 1736 bcopy(sc->arpcom.ac_enaddr, 1737 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1738 sizeof(sc->arpcom.ac_enaddr)); 1739 1740 /* 1741 * Start the IAS (Individual Address Setup) command/DMA. 1742 */ 1743 fxp_scb_wait(sc); 1744 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1745 /* ...and wait for it to complete. */ 1746 fxp_dma_wait(&cb_ias->cb_status, sc); 1747 1748 /* 1749 * Initialize transmit control block (TxCB) list. 1750 */ 1751 1752 txp = sc->cbl_base; 1753 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1754 for (i = 0; i < FXP_NTXCB; i++) { 1755 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1756 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1757 txp[i].link_addr = 1758 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1759 if (sc->flags & FXP_FLAG_EXT_TXCB) 1760 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1761 else 1762 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1763 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1764 } 1765 /* 1766 * Set the suspend flag on the first TxCB and start the control 1767 * unit. It will execute the NOP and then suspend. 1768 */ 1769 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1770 sc->cbl_first = sc->cbl_last = txp; 1771 sc->tx_queued = 1; 1772 1773 fxp_scb_wait(sc); 1774 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1775 1776 /* 1777 * Initialize receiver buffer area - RFA. 1778 */ 1779 fxp_scb_wait(sc); 1780 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1781 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1782 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1783 1784 /* 1785 * Set current media. 1786 */ 1787 if (sc->miibus != NULL) 1788 mii_mediachg(device_get_softc(sc->miibus)); 1789 1790 ifp->if_flags |= IFF_RUNNING; 1791 ifp->if_flags &= ~IFF_OACTIVE; 1792 1793 /* 1794 * Enable interrupts. 1795 */ 1796 #ifdef DEVICE_POLLING 1797 /* 1798 * ... but only do that if we are not polling. And because (presumably) 1799 * the default is interrupts on, we need to disable them explicitly! 1800 */ 1801 if ( ifp->if_flags & IFF_POLLING ) 1802 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1803 else 1804 #endif /* DEVICE_POLLING */ 1805 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1806 1807 /* 1808 * Start stats updater. 1809 */ 1810 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1811 } 1812 1813 static int 1814 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1815 { 1816 1817 return (0); 1818 } 1819 1820 static void 1821 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1822 { 1823 1824 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1825 } 1826 1827 /* 1828 * Change media according to request. 1829 */ 1830 static int 1831 fxp_ifmedia_upd(struct ifnet *ifp) 1832 { 1833 struct fxp_softc *sc = ifp->if_softc; 1834 struct mii_data *mii; 1835 1836 mii = device_get_softc(sc->miibus); 1837 mii_mediachg(mii); 1838 return (0); 1839 } 1840 1841 /* 1842 * Notify the world which media we're using. 1843 */ 1844 static void 1845 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1846 { 1847 struct fxp_softc *sc = ifp->if_softc; 1848 struct mii_data *mii; 1849 1850 mii = device_get_softc(sc->miibus); 1851 mii_pollstat(mii); 1852 ifmr->ifm_active = mii->mii_media_active; 1853 ifmr->ifm_status = mii->mii_media_status; 1854 1855 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1856 sc->cu_resume_bug = 1; 1857 else 1858 sc->cu_resume_bug = 0; 1859 } 1860 1861 /* 1862 * Add a buffer to the end of the RFA buffer list. 1863 * Return 0 if successful, 1 for failure. A failure results in 1864 * adding the 'oldm' (if non-NULL) on to the end of the list - 1865 * tossing out its old contents and recycling it. 1866 * The RFA struct is stuck at the beginning of mbuf cluster and the 1867 * data pointer is fixed up to point just past it. 1868 */ 1869 static int 1870 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1871 { 1872 u_int32_t v; 1873 struct mbuf *m; 1874 struct fxp_rfa *rfa, *p_rfa; 1875 1876 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1877 if (m == NULL) { /* try to recycle the old mbuf instead */ 1878 if (oldm == NULL) 1879 return 1; 1880 m = oldm; 1881 m->m_data = m->m_ext.ext_buf; 1882 } 1883 1884 /* 1885 * Move the data pointer up so that the incoming data packet 1886 * will be 32-bit aligned. 1887 */ 1888 m->m_data += RFA_ALIGNMENT_FUDGE; 1889 1890 /* 1891 * Get a pointer to the base of the mbuf cluster and move 1892 * data start past it. 1893 */ 1894 rfa = mtod(m, struct fxp_rfa *); 1895 m->m_data += sizeof(struct fxp_rfa); 1896 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1897 1898 /* 1899 * Initialize the rest of the RFA. Note that since the RFA 1900 * is misaligned, we cannot store values directly. Instead, 1901 * we use an optimized, inline copy. 1902 */ 1903 1904 rfa->rfa_status = 0; 1905 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1906 rfa->actual_size = 0; 1907 1908 v = -1; 1909 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1910 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1911 1912 /* 1913 * If there are other buffers already on the list, attach this 1914 * one to the end by fixing up the tail to point to this one. 1915 */ 1916 if (sc->rfa_headm != NULL) { 1917 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1918 RFA_ALIGNMENT_FUDGE); 1919 sc->rfa_tailm->m_next = m; 1920 v = vtophys(rfa); 1921 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1922 p_rfa->rfa_control = 0; 1923 } else { 1924 sc->rfa_headm = m; 1925 } 1926 sc->rfa_tailm = m; 1927 1928 return (m == oldm); 1929 } 1930 1931 static volatile int 1932 fxp_miibus_readreg(device_t dev, int phy, int reg) 1933 { 1934 struct fxp_softc *sc = device_get_softc(dev); 1935 int count = 10000; 1936 int value; 1937 1938 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1939 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1940 1941 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1942 && count--) 1943 DELAY(10); 1944 1945 if (count <= 0) 1946 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1947 1948 return (value & 0xffff); 1949 } 1950 1951 static void 1952 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1953 { 1954 struct fxp_softc *sc = device_get_softc(dev); 1955 int count = 10000; 1956 1957 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1958 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1959 (value & 0xffff)); 1960 1961 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1962 count--) 1963 DELAY(10); 1964 1965 if (count <= 0) 1966 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1967 } 1968 1969 static int 1970 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1971 { 1972 struct fxp_softc *sc = ifp->if_softc; 1973 struct ifreq *ifr = (struct ifreq *)data; 1974 struct mii_data *mii; 1975 int error = 0; 1976 1977 switch (command) { 1978 1979 case SIOCSIFFLAGS: 1980 if (ifp->if_flags & IFF_ALLMULTI) 1981 sc->flags |= FXP_FLAG_ALL_MCAST; 1982 else 1983 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1984 1985 /* 1986 * If interface is marked up and not running, then start it. 1987 * If it is marked down and running, stop it. 1988 * XXX If it's up then re-initialize it. This is so flags 1989 * such as IFF_PROMISC are handled. 1990 */ 1991 if (ifp->if_flags & IFF_UP) { 1992 fxp_init(sc); 1993 } else { 1994 if (ifp->if_flags & IFF_RUNNING) 1995 fxp_stop(sc); 1996 } 1997 break; 1998 1999 case SIOCADDMULTI: 2000 case SIOCDELMULTI: 2001 if (ifp->if_flags & IFF_ALLMULTI) 2002 sc->flags |= FXP_FLAG_ALL_MCAST; 2003 else 2004 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2005 /* 2006 * Multicast list has changed; set the hardware filter 2007 * accordingly. 2008 */ 2009 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2010 fxp_mc_setup(sc); 2011 /* 2012 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2013 * again rather than else {}. 2014 */ 2015 if (sc->flags & FXP_FLAG_ALL_MCAST) 2016 fxp_init(sc); 2017 error = 0; 2018 break; 2019 2020 case SIOCSIFMEDIA: 2021 case SIOCGIFMEDIA: 2022 if (sc->miibus != NULL) { 2023 mii = device_get_softc(sc->miibus); 2024 error = ifmedia_ioctl(ifp, ifr, 2025 &mii->mii_media, command); 2026 } else { 2027 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2028 } 2029 break; 2030 2031 default: 2032 error = ether_ioctl(ifp, command, data); 2033 break; 2034 } 2035 return (error); 2036 } 2037 2038 /* 2039 * Fill in the multicast address list and return number of entries. 2040 */ 2041 static int 2042 fxp_mc_addrs(struct fxp_softc *sc) 2043 { 2044 struct fxp_cb_mcs *mcsp = sc->mcsp; 2045 struct ifnet *ifp = &sc->arpcom.ac_if; 2046 struct ifmultiaddr *ifma; 2047 int nmcasts; 2048 2049 nmcasts = 0; 2050 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2051 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2052 if (ifma->ifma_addr->sa_family != AF_LINK) 2053 continue; 2054 if (nmcasts >= MAXMCADDR) { 2055 sc->flags |= FXP_FLAG_ALL_MCAST; 2056 nmcasts = 0; 2057 break; 2058 } 2059 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2060 (void *)(uintptr_t)(volatile void *) 2061 &sc->mcsp->mc_addr[nmcasts][0], 6); 2062 nmcasts++; 2063 } 2064 } 2065 mcsp->mc_cnt = nmcasts * 6; 2066 return (nmcasts); 2067 } 2068 2069 /* 2070 * Program the multicast filter. 2071 * 2072 * We have an artificial restriction that the multicast setup command 2073 * must be the first command in the chain, so we take steps to ensure 2074 * this. By requiring this, it allows us to keep up the performance of 2075 * the pre-initialized command ring (esp. link pointers) by not actually 2076 * inserting the mcsetup command in the ring - i.e. its link pointer 2077 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2078 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2079 * lead into the regular TxCB ring when it completes. 2080 * 2081 * This function must be called at splimp. 2082 */ 2083 static void 2084 fxp_mc_setup(struct fxp_softc *sc) 2085 { 2086 struct fxp_cb_mcs *mcsp = sc->mcsp; 2087 struct ifnet *ifp = &sc->arpcom.ac_if; 2088 int count; 2089 2090 /* 2091 * If there are queued commands, we must wait until they are all 2092 * completed. If we are already waiting, then add a NOP command 2093 * with interrupt option so that we're notified when all commands 2094 * have been completed - fxp_start() ensures that no additional 2095 * TX commands will be added when need_mcsetup is true. 2096 */ 2097 if (sc->tx_queued) { 2098 struct fxp_cb_tx *txp; 2099 2100 /* 2101 * need_mcsetup will be true if we are already waiting for the 2102 * NOP command to be completed (see below). In this case, bail. 2103 */ 2104 if (sc->need_mcsetup) 2105 return; 2106 sc->need_mcsetup = 1; 2107 2108 /* 2109 * Add a NOP command with interrupt so that we are notified 2110 * when all TX commands have been processed. 2111 */ 2112 txp = sc->cbl_last->next; 2113 txp->mb_head = NULL; 2114 txp->cb_status = 0; 2115 txp->cb_command = FXP_CB_COMMAND_NOP | 2116 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2117 /* 2118 * Advance the end of list forward. 2119 */ 2120 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2121 sc->cbl_last = txp; 2122 sc->tx_queued++; 2123 /* 2124 * Issue a resume in case the CU has just suspended. 2125 */ 2126 fxp_scb_wait(sc); 2127 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2128 /* 2129 * Set a 5 second timer just in case we don't hear from the 2130 * card again. 2131 */ 2132 ifp->if_timer = 5; 2133 2134 return; 2135 } 2136 sc->need_mcsetup = 0; 2137 2138 /* 2139 * Initialize multicast setup descriptor. 2140 */ 2141 mcsp->next = sc->cbl_base; 2142 mcsp->mb_head = NULL; 2143 mcsp->cb_status = 0; 2144 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2145 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2146 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2147 fxp_mc_addrs(sc); 2148 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2149 sc->tx_queued = 1; 2150 2151 /* 2152 * Wait until command unit is not active. This should never 2153 * be the case when nothing is queued, but make sure anyway. 2154 */ 2155 count = 100; 2156 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2157 FXP_SCB_CUS_ACTIVE && --count) 2158 DELAY(10); 2159 if (count == 0) { 2160 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2161 return; 2162 } 2163 2164 /* 2165 * Start the multicast setup command. 2166 */ 2167 fxp_scb_wait(sc); 2168 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2170 2171 ifp->if_timer = 2; 2172 return; 2173 } 2174 2175 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2176 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2177 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2178 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2179 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2180 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2181 2182 #define UCODE(x) x, sizeof(x) 2183 2184 struct ucode { 2185 u_int32_t revision; 2186 u_int32_t *ucode; 2187 int length; 2188 u_short int_delay_offset; 2189 u_short bundle_max_offset; 2190 } ucode_table[] = { 2191 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2192 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2193 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2194 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2195 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2196 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2197 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2198 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2199 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2200 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2201 { 0, NULL, 0, 0, 0 } 2202 }; 2203 2204 static void 2205 fxp_load_ucode(struct fxp_softc *sc) 2206 { 2207 struct ucode *uc; 2208 struct fxp_cb_ucode *cbp; 2209 2210 for (uc = ucode_table; uc->ucode != NULL; uc++) 2211 if (sc->revision == uc->revision) 2212 break; 2213 if (uc->ucode == NULL) 2214 return; 2215 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2216 cbp->cb_status = 0; 2217 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2218 cbp->link_addr = -1; /* (no) next command */ 2219 memcpy(cbp->ucode, uc->ucode, uc->length); 2220 if (uc->int_delay_offset) 2221 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2222 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2223 if (uc->bundle_max_offset) 2224 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2225 sc->tunable_bundle_max; 2226 /* 2227 * Download the ucode to the chip. 2228 */ 2229 fxp_scb_wait(sc); 2230 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2231 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2232 /* ...and wait for it to complete. */ 2233 fxp_dma_wait(&cbp->cb_status, sc); 2234 if_printf(&sc->arpcom.ac_if, 2235 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2236 sc->tunable_int_delay, 2237 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2238 sc->flags |= FXP_FLAG_UCODE; 2239 } 2240 2241 static int 2242 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2243 { 2244 int error, value; 2245 2246 value = *(int *)arg1; 2247 error = sysctl_handle_int(oidp, &value, 0, req); 2248 if (error || !req->newptr) 2249 return (error); 2250 if (value < low || value > high) 2251 return (EINVAL); 2252 *(int *)arg1 = value; 2253 return (0); 2254 } 2255 2256 /* 2257 * Interrupt delay is expressed in microseconds, a multiplier is used 2258 * to convert this to the appropriate clock ticks before using. 2259 */ 2260 static int 2261 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2262 { 2263 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2264 } 2265 2266 static int 2267 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2268 { 2269 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2270 } 2271