1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.22 2005/02/12 04:18:05 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 #include <machine/clock.h> /* for DELAY */ 68 69 #include <net/if_types.h> 70 #include <net/vlan/if_vlan_var.h> 71 72 #include <bus/pci/pcivar.h> 73 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include "../mii_layer/mii.h" 76 #include "../mii_layer/miivar.h" 77 78 #include "if_fxpreg.h" 79 #include "if_fxpvar.h" 80 #include "rcvbundl.h" 81 82 #include "miibus_if.h" 83 84 /* 85 * NOTE! On the Alpha, we have an alignment constraint. The 86 * card DMAs the packet immediately following the RFA. However, 87 * the first thing in the packet is a 14-byte Ethernet header. 88 * This means that the packet is misaligned. To compensate, 89 * we actually offset the RFA 2 bytes into the cluster. This 90 * alignes the packet after the Ethernet header at a 32-bit 91 * boundary. HOWEVER! This means that the RFA is misaligned! 92 */ 93 #define RFA_ALIGNMENT_FUDGE 2 94 95 /* 96 * Set initial transmit threshold at 64 (512 bytes). This is 97 * increased by 64 (512 bytes) at a time, to maximum of 192 98 * (1536 bytes), if an underrun occurs. 99 */ 100 static int tx_threshold = 64; 101 102 /* 103 * The configuration byte map has several undefined fields which 104 * must be one or must be zero. Set up a template for these bits 105 * only, (assuming a 82557 chip) leaving the actual configuration 106 * to fxp_init. 107 * 108 * See struct fxp_cb_config for the bit definitions. 109 */ 110 static u_char fxp_cb_config_template[] = { 111 0x0, 0x0, /* cb_status */ 112 0x0, 0x0, /* cb_command */ 113 0x0, 0x0, 0x0, 0x0, /* link_addr */ 114 0x0, /* 0 */ 115 0x0, /* 1 */ 116 0x0, /* 2 */ 117 0x0, /* 3 */ 118 0x0, /* 4 */ 119 0x0, /* 5 */ 120 0x32, /* 6 */ 121 0x0, /* 7 */ 122 0x0, /* 8 */ 123 0x0, /* 9 */ 124 0x6, /* 10 */ 125 0x0, /* 11 */ 126 0x0, /* 12 */ 127 0x0, /* 13 */ 128 0xf2, /* 14 */ 129 0x48, /* 15 */ 130 0x0, /* 16 */ 131 0x40, /* 17 */ 132 0xf0, /* 18 */ 133 0x0, /* 19 */ 134 0x3f, /* 20 */ 135 0x5 /* 21 */ 136 }; 137 138 struct fxp_ident { 139 u_int16_t devid; 140 int16_t revid; /* -1 matches anything */ 141 char *name; 142 }; 143 144 /* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150 static struct fxp_ident fxp_ident_table[] = { 151 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 152 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 153 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 162 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 163 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 168 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 169 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 176 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 180 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 185 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 186 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 187 { 0, -1, NULL }, 188 }; 189 190 static int fxp_probe(device_t dev); 191 static int fxp_attach(device_t dev); 192 static int fxp_detach(device_t dev); 193 static int fxp_shutdown(device_t dev); 194 static int fxp_suspend(device_t dev); 195 static int fxp_resume(device_t dev); 196 197 static void fxp_intr(void *xsc); 198 static void fxp_intr_body(struct fxp_softc *sc, 199 u_int8_t statack, int count); 200 201 static void fxp_init(void *xsc); 202 static void fxp_tick(void *xsc); 203 static void fxp_powerstate_d0(device_t dev); 204 static void fxp_start(struct ifnet *ifp); 205 static void fxp_stop(struct fxp_softc *sc); 206 static void fxp_release(struct fxp_softc *sc); 207 static int fxp_ioctl(struct ifnet *ifp, u_long command, 208 caddr_t data, struct ucred *); 209 static void fxp_watchdog(struct ifnet *ifp); 210 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 211 static int fxp_mc_addrs(struct fxp_softc *sc); 212 static void fxp_mc_setup(struct fxp_softc *sc); 213 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 214 int autosize); 215 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 216 u_int16_t data); 217 static void fxp_autosize_eeprom(struct fxp_softc *sc); 218 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 219 int offset, int words); 220 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 221 int offset, int words); 222 static int fxp_ifmedia_upd(struct ifnet *ifp); 223 static void fxp_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 226 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 227 struct ifmediareq *ifmr); 228 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 229 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 230 int value); 231 static void fxp_load_ucode(struct fxp_softc *sc); 232 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 233 int low, int high); 234 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 235 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 236 static __inline void fxp_lwcopy(volatile u_int32_t *src, 237 volatile u_int32_t *dst); 238 static __inline void fxp_scb_wait(struct fxp_softc *sc); 239 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 240 static __inline void fxp_dma_wait(volatile u_int16_t *status, 241 struct fxp_softc *sc); 242 243 static device_method_t fxp_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, fxp_probe), 246 DEVMETHOD(device_attach, fxp_attach), 247 DEVMETHOD(device_detach, fxp_detach), 248 DEVMETHOD(device_shutdown, fxp_shutdown), 249 DEVMETHOD(device_suspend, fxp_suspend), 250 DEVMETHOD(device_resume, fxp_resume), 251 252 /* MII interface */ 253 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 254 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 255 256 { 0, 0 } 257 }; 258 259 static driver_t fxp_driver = { 260 "fxp", 261 fxp_methods, 262 sizeof(struct fxp_softc), 263 }; 264 265 static devclass_t fxp_devclass; 266 267 DECLARE_DUMMY_MODULE(if_fxp); 268 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 269 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 270 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 271 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 272 273 static int fxp_rnr; 274 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 275 276 /* 277 * Inline function to copy a 16-bit aligned 32-bit quantity. 278 */ 279 static __inline void 280 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 281 { 282 #ifdef __i386__ 283 *dst = *src; 284 #else 285 volatile u_int16_t *a = (volatile u_int16_t *)src; 286 volatile u_int16_t *b = (volatile u_int16_t *)dst; 287 288 b[0] = a[0]; 289 b[1] = a[1]; 290 #endif 291 } 292 293 /* 294 * Wait for the previous command to be accepted (but not necessarily 295 * completed). 296 */ 297 static __inline void 298 fxp_scb_wait(struct fxp_softc *sc) 299 { 300 int i = 10000; 301 302 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 303 DELAY(2); 304 if (i == 0) 305 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 306 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 307 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 308 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 309 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 310 } 311 312 static __inline void 313 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 314 { 315 316 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 318 fxp_scb_wait(sc); 319 } 320 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 321 } 322 323 static __inline void 324 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 325 { 326 int i = 10000; 327 328 while (!(*status & FXP_CB_STATUS_C) && --i) 329 DELAY(2); 330 if (i == 0) 331 device_printf(sc->dev, "DMA timeout\n"); 332 } 333 334 /* 335 * Return identification string if this is device is ours. 336 */ 337 static int 338 fxp_probe(device_t dev) 339 { 340 u_int16_t devid; 341 u_int8_t revid; 342 struct fxp_ident *ident; 343 344 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 345 devid = pci_get_device(dev); 346 revid = pci_get_revid(dev); 347 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 348 if (ident->devid == devid && 349 (ident->revid == revid || ident->revid == -1)) { 350 device_set_desc(dev, ident->name); 351 return (0); 352 } 353 } 354 } 355 return (ENXIO); 356 } 357 358 static void 359 fxp_powerstate_d0(device_t dev) 360 { 361 u_int32_t iobase, membase, irq; 362 363 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 364 /* Save important PCI config data. */ 365 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 366 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 367 irq = pci_read_config(dev, PCIR_INTLINE, 4); 368 369 /* Reset the power state. */ 370 device_printf(dev, "chip is in D%d power mode " 371 "-- setting to D0\n", pci_get_powerstate(dev)); 372 373 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 374 375 /* Restore PCI config data. */ 376 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 377 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 378 pci_write_config(dev, PCIR_INTLINE, irq, 4); 379 } 380 } 381 382 static int 383 fxp_attach(device_t dev) 384 { 385 int error = 0; 386 struct fxp_softc *sc = device_get_softc(dev); 387 struct ifnet *ifp; 388 u_int32_t val; 389 u_int16_t data; 390 int i, rid, m1, m2, prefer_iomap; 391 int s; 392 393 bzero(sc, sizeof(*sc)); 394 sc->dev = dev; 395 callout_init(&sc->fxp_stat_timer); 396 sysctl_ctx_init(&sc->sysctl_ctx); 397 398 s = splimp(); 399 400 /* 401 * Enable bus mastering. Enable memory space too, in case 402 * BIOS/Prom forgot about it. 403 */ 404 val = pci_read_config(dev, PCIR_COMMAND, 2); 405 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 406 pci_write_config(dev, PCIR_COMMAND, val, 2); 407 val = pci_read_config(dev, PCIR_COMMAND, 2); 408 409 fxp_powerstate_d0(dev); 410 411 /* 412 * Figure out which we should try first - memory mapping or i/o mapping? 413 * We default to memory mapping. Then we accept an override from the 414 * command line. Then we check to see which one is enabled. 415 */ 416 m1 = PCIM_CMD_MEMEN; 417 m2 = PCIM_CMD_PORTEN; 418 prefer_iomap = 0; 419 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 420 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 421 m1 = PCIM_CMD_PORTEN; 422 m2 = PCIM_CMD_MEMEN; 423 } 424 425 if (val & m1) { 426 sc->rtp = 427 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 428 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 429 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 430 0, ~0, 1, RF_ACTIVE); 431 } 432 if (sc->mem == NULL && (val & m2)) { 433 sc->rtp = 434 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 435 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 436 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 437 0, ~0, 1, RF_ACTIVE); 438 } 439 440 if (!sc->mem) { 441 device_printf(dev, "could not map device registers\n"); 442 error = ENXIO; 443 goto fail; 444 } 445 if (bootverbose) { 446 device_printf(dev, "using %s space register mapping\n", 447 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 448 } 449 450 sc->sc_st = rman_get_bustag(sc->mem); 451 sc->sc_sh = rman_get_bushandle(sc->mem); 452 453 /* 454 * Allocate our interrupt. 455 */ 456 rid = 0; 457 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 458 RF_SHAREABLE | RF_ACTIVE); 459 if (sc->irq == NULL) { 460 device_printf(dev, "could not map interrupt\n"); 461 error = ENXIO; 462 goto fail; 463 } 464 465 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 466 fxp_intr, sc, &sc->ih); 467 if (error) { 468 device_printf(dev, "could not setup irq\n"); 469 goto fail; 470 } 471 472 /* 473 * Reset to a stable state. 474 */ 475 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 476 DELAY(10); 477 478 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 479 M_DEVBUF, M_WAITOK | M_ZERO); 480 481 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 482 M_WAITOK | M_ZERO); 483 484 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 485 486 /* 487 * Pre-allocate our receive buffers. 488 */ 489 for (i = 0; i < FXP_NRFABUFS; i++) { 490 if (fxp_add_rfabuf(sc, NULL) != 0) { 491 goto failmem; 492 } 493 } 494 495 /* 496 * Find out how large of an SEEPROM we have. 497 */ 498 fxp_autosize_eeprom(sc); 499 500 /* 501 * Determine whether we must use the 503 serial interface. 502 */ 503 fxp_read_eeprom(sc, &data, 6, 1); 504 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 505 (data & FXP_PHY_SERIAL_ONLY)) 506 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 507 508 /* 509 * Create the sysctl tree 510 */ 511 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 512 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 513 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 514 if (sc->sysctl_tree == NULL) 515 goto fail; 516 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 517 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 518 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 519 "FXP driver receive interrupt microcode bundling delay"); 520 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 521 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 522 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 523 "FXP driver receive interrupt microcode bundle size limit"); 524 525 /* 526 * Pull in device tunables. 527 */ 528 sc->tunable_int_delay = TUNABLE_INT_DELAY; 529 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 530 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 531 "int_delay", &sc->tunable_int_delay); 532 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "bundle_max", &sc->tunable_bundle_max); 534 535 /* 536 * Find out the chip revision; lump all 82557 revs together. 537 */ 538 fxp_read_eeprom(sc, &data, 5, 1); 539 if ((data >> 8) == 1) 540 sc->revision = FXP_REV_82557; 541 else 542 sc->revision = pci_get_revid(dev); 543 544 /* 545 * Enable workarounds for certain chip revision deficiencies. 546 * 547 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 548 * some systems based a normal 82559 design, have a defect where 549 * the chip can cause a PCI protocol violation if it receives 550 * a CU_RESUME command when it is entering the IDLE state. The 551 * workaround is to disable Dynamic Standby Mode, so the chip never 552 * deasserts CLKRUN#, and always remains in an active state. 553 * 554 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 555 */ 556 i = pci_get_device(dev); 557 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 558 sc->revision >= FXP_REV_82559_A0) { 559 fxp_read_eeprom(sc, &data, 10, 1); 560 if (data & 0x02) { /* STB enable */ 561 u_int16_t cksum; 562 int i; 563 564 device_printf(dev, 565 "Disabling dynamic standby mode in EEPROM\n"); 566 data &= ~0x02; 567 fxp_write_eeprom(sc, &data, 10, 1); 568 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 569 cksum = 0; 570 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 571 fxp_read_eeprom(sc, &data, i, 1); 572 cksum += data; 573 } 574 i = (1 << sc->eeprom_size) - 1; 575 cksum = 0xBABA - cksum; 576 fxp_read_eeprom(sc, &data, i, 1); 577 fxp_write_eeprom(sc, &cksum, i, 1); 578 device_printf(dev, 579 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 580 i, data, cksum); 581 #if 1 582 /* 583 * If the user elects to continue, try the software 584 * workaround, as it is better than nothing. 585 */ 586 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 587 #endif 588 } 589 } 590 591 /* 592 * If we are not a 82557 chip, we can enable extended features. 593 */ 594 if (sc->revision != FXP_REV_82557) { 595 /* 596 * If MWI is enabled in the PCI configuration, and there 597 * is a valid cacheline size (8 or 16 dwords), then tell 598 * the board to turn on MWI. 599 */ 600 if (val & PCIM_CMD_MWRICEN && 601 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 602 sc->flags |= FXP_FLAG_MWI_ENABLE; 603 604 /* turn on the extended TxCB feature */ 605 sc->flags |= FXP_FLAG_EXT_TXCB; 606 607 /* enable reception of long frames for VLAN */ 608 sc->flags |= FXP_FLAG_LONG_PKT_EN; 609 } 610 611 /* 612 * Read MAC address. 613 */ 614 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 615 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 616 device_printf(dev, "10Mbps"); 617 if (bootverbose) { 618 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 619 pci_get_vendor(dev), pci_get_device(dev), 620 pci_get_subvendor(dev), pci_get_subdevice(dev), 621 pci_get_revid(dev)); 622 fxp_read_eeprom(sc, &data, 10, 1); 623 device_printf(dev, "Dynamic Standby mode is %s\n", 624 data & 0x02 ? "enabled" : "disabled"); 625 } 626 627 /* 628 * If this is only a 10Mbps device, then there is no MII, and 629 * the PHY will use a serial interface instead. 630 * 631 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 632 * doesn't have a programming interface of any sort. The 633 * media is sensed automatically based on how the link partner 634 * is configured. This is, in essence, manual configuration. 635 */ 636 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 637 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 638 fxp_serial_ifmedia_sts); 639 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 640 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 641 } else { 642 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 643 fxp_ifmedia_sts)) { 644 device_printf(dev, "MII without any PHY!\n"); 645 error = ENXIO; 646 goto fail; 647 } 648 } 649 650 ifp = &sc->arpcom.ac_if; 651 if_initname(ifp, "fxp", device_get_unit(dev)); 652 ifp->if_baudrate = 100000000; 653 ifp->if_init = fxp_init; 654 ifp->if_softc = sc; 655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 656 ifp->if_ioctl = fxp_ioctl; 657 ifp->if_start = fxp_start; 658 ifp->if_watchdog = fxp_watchdog; 659 660 /* 661 * Attach the interface. 662 */ 663 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 664 665 /* 666 * Tell the upper layer(s) we support long frames. 667 */ 668 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 669 670 /* 671 * Let the system queue as many packets as we have available 672 * TX descriptors. 673 */ 674 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 675 ifq_set_ready(&ifp->if_snd); 676 677 splx(s); 678 return (0); 679 680 failmem: 681 device_printf(dev, "Failed to malloc memory\n"); 682 error = ENOMEM; 683 fail: 684 splx(s); 685 fxp_release(sc); 686 return (error); 687 } 688 689 /* 690 * release all resources 691 */ 692 static void 693 fxp_release(struct fxp_softc *sc) 694 { 695 696 bus_generic_detach(sc->dev); 697 if (sc->miibus) 698 device_delete_child(sc->dev, sc->miibus); 699 700 if (sc->cbl_base) 701 free(sc->cbl_base, M_DEVBUF); 702 if (sc->fxp_stats) 703 free(sc->fxp_stats, M_DEVBUF); 704 if (sc->mcsp) 705 free(sc->mcsp, M_DEVBUF); 706 if (sc->rfa_headm) 707 m_freem(sc->rfa_headm); 708 709 if (sc->ih) 710 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 711 if (sc->irq) 712 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 713 if (sc->mem) 714 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 715 716 sysctl_ctx_free(&sc->sysctl_ctx); 717 } 718 719 /* 720 * Detach interface. 721 */ 722 static int 723 fxp_detach(device_t dev) 724 { 725 struct fxp_softc *sc = device_get_softc(dev); 726 int s; 727 728 /* disable interrupts */ 729 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 730 731 s = splimp(); 732 733 /* 734 * Stop DMA and drop transmit queue. 735 */ 736 fxp_stop(sc); 737 738 /* 739 * Close down routes etc. 740 */ 741 ether_ifdetach(&sc->arpcom.ac_if); 742 743 /* 744 * Free all media structures. 745 */ 746 ifmedia_removeall(&sc->sc_media); 747 748 splx(s); 749 750 /* Release our allocated resources. */ 751 fxp_release(sc); 752 753 return (0); 754 } 755 756 /* 757 * Device shutdown routine. Called at system shutdown after sync. The 758 * main purpose of this routine is to shut off receiver DMA so that 759 * kernel memory doesn't get clobbered during warmboot. 760 */ 761 static int 762 fxp_shutdown(device_t dev) 763 { 764 /* 765 * Make sure that DMA is disabled prior to reboot. Not doing 766 * do could allow DMA to corrupt kernel memory during the 767 * reboot before the driver initializes. 768 */ 769 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 770 return (0); 771 } 772 773 /* 774 * Device suspend routine. Stop the interface and save some PCI 775 * settings in case the BIOS doesn't restore them properly on 776 * resume. 777 */ 778 static int 779 fxp_suspend(device_t dev) 780 { 781 struct fxp_softc *sc = device_get_softc(dev); 782 int i, s; 783 784 s = splimp(); 785 786 fxp_stop(sc); 787 788 for (i = 0; i < 5; i++) 789 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 790 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 791 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 792 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 793 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 794 795 sc->suspended = 1; 796 797 splx(s); 798 return (0); 799 } 800 801 /* 802 * Device resume routine. Restore some PCI settings in case the BIOS 803 * doesn't, re-enable busmastering, and restart the interface if 804 * appropriate. 805 */ 806 static int 807 fxp_resume(device_t dev) 808 { 809 struct fxp_softc *sc = device_get_softc(dev); 810 struct ifnet *ifp = &sc->arpcom.ac_if; 811 u_int16_t pci_command; 812 int i, s; 813 814 s = splimp(); 815 816 fxp_powerstate_d0(dev); 817 818 /* better way to do this? */ 819 for (i = 0; i < 5; i++) 820 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 821 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 822 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 823 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 824 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 825 826 /* reenable busmastering */ 827 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 828 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 829 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 830 831 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 832 DELAY(10); 833 834 /* reinitialize interface if necessary */ 835 if (ifp->if_flags & IFF_UP) 836 fxp_init(sc); 837 838 sc->suspended = 0; 839 840 splx(s); 841 return (0); 842 } 843 844 static void 845 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 846 { 847 u_int16_t reg; 848 int x; 849 850 /* 851 * Shift in data. 852 */ 853 for (x = 1 << (length - 1); x; x >>= 1) { 854 if (data & x) 855 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 856 else 857 reg = FXP_EEPROM_EECS; 858 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 859 DELAY(1); 860 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 861 DELAY(1); 862 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 863 DELAY(1); 864 } 865 } 866 867 /* 868 * Read from the serial EEPROM. Basically, you manually shift in 869 * the read opcode (one bit at a time) and then shift in the address, 870 * and then you shift out the data (all of this one bit at a time). 871 * The word size is 16 bits, so you have to provide the address for 872 * every 16 bits of data. 873 */ 874 static u_int16_t 875 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 876 { 877 u_int16_t reg, data; 878 int x; 879 880 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 881 /* 882 * Shift in read opcode. 883 */ 884 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 885 /* 886 * Shift in address. 887 */ 888 data = 0; 889 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 890 if (offset & x) 891 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 892 else 893 reg = FXP_EEPROM_EECS; 894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 895 DELAY(1); 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 897 DELAY(1); 898 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 899 DELAY(1); 900 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 901 data++; 902 if (autosize && reg == 0) { 903 sc->eeprom_size = data; 904 break; 905 } 906 } 907 /* 908 * Shift out data. 909 */ 910 data = 0; 911 reg = FXP_EEPROM_EECS; 912 for (x = 1 << 15; x; x >>= 1) { 913 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 914 DELAY(1); 915 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 916 data |= x; 917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 918 DELAY(1); 919 } 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 921 DELAY(1); 922 923 return (data); 924 } 925 926 static void 927 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 928 { 929 int i; 930 931 /* 932 * Erase/write enable. 933 */ 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 935 fxp_eeprom_shiftin(sc, 0x4, 3); 936 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 938 DELAY(1); 939 /* 940 * Shift in write opcode, address, data. 941 */ 942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 943 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 944 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 945 fxp_eeprom_shiftin(sc, data, 16); 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 947 DELAY(1); 948 /* 949 * Wait for EEPROM to finish up. 950 */ 951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 952 DELAY(1); 953 for (i = 0; i < 1000; i++) { 954 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 955 break; 956 DELAY(50); 957 } 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 959 DELAY(1); 960 /* 961 * Erase/write disable. 962 */ 963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 964 fxp_eeprom_shiftin(sc, 0x4, 3); 965 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 967 DELAY(1); 968 } 969 970 /* 971 * From NetBSD: 972 * 973 * Figure out EEPROM size. 974 * 975 * 559's can have either 64-word or 256-word EEPROMs, the 558 976 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 977 * talks about the existance of 16 to 256 word EEPROMs. 978 * 979 * The only known sizes are 64 and 256, where the 256 version is used 980 * by CardBus cards to store CIS information. 981 * 982 * The address is shifted in msb-to-lsb, and after the last 983 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 984 * after which follows the actual data. We try to detect this zero, by 985 * probing the data-out bit in the EEPROM control register just after 986 * having shifted in a bit. If the bit is zero, we assume we've 987 * shifted enough address bits. The data-out should be tri-state, 988 * before this, which should translate to a logical one. 989 */ 990 static void 991 fxp_autosize_eeprom(struct fxp_softc *sc) 992 { 993 994 /* guess maximum size of 256 words */ 995 sc->eeprom_size = 8; 996 997 /* autosize */ 998 (void) fxp_eeprom_getword(sc, 0, 1); 999 } 1000 1001 static void 1002 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1003 { 1004 int i; 1005 1006 for (i = 0; i < words; i++) 1007 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1008 } 1009 1010 static void 1011 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1012 { 1013 int i; 1014 1015 for (i = 0; i < words; i++) 1016 fxp_eeprom_putword(sc, offset + i, data[i]); 1017 } 1018 1019 /* 1020 * Start packet transmission on the interface. 1021 */ 1022 static void 1023 fxp_start(struct ifnet *ifp) 1024 { 1025 struct fxp_softc *sc = ifp->if_softc; 1026 struct fxp_cb_tx *txp; 1027 1028 /* 1029 * See if we need to suspend xmit until the multicast filter 1030 * has been reprogrammed (which can only be done at the head 1031 * of the command chain). 1032 */ 1033 if (sc->need_mcsetup) { 1034 return; 1035 } 1036 1037 txp = NULL; 1038 1039 /* 1040 * We're finished if there is nothing more to add to the list or if 1041 * we're all filled up with buffers to transmit. 1042 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1043 * a NOP command when needed. 1044 */ 1045 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1046 struct mbuf *m, *mb_head; 1047 int segment; 1048 1049 /* 1050 * Grab a packet to transmit. The packet is dequeued, 1051 * once we are sure that we have enough free descriptors. 1052 */ 1053 mb_head = ifq_poll(&ifp->if_snd); 1054 if (mb_head == NULL) 1055 break; 1056 1057 /* 1058 * Get pointer to next available tx desc. 1059 */ 1060 txp = sc->cbl_last->next; 1061 1062 /* 1063 * Go through each of the mbufs in the chain and initialize 1064 * the transmit buffer descriptors with the physical address 1065 * and size of the mbuf. 1066 */ 1067 tbdinit: 1068 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1069 if (m->m_len != 0) { 1070 if (segment == FXP_NTXSEG) 1071 break; 1072 txp->tbd[segment].tb_addr = 1073 vtophys(mtod(m, vm_offset_t)); 1074 txp->tbd[segment].tb_size = m->m_len; 1075 segment++; 1076 } 1077 } 1078 if (m != NULL) { 1079 struct mbuf *mn; 1080 1081 /* 1082 * We ran out of segments. We have to recopy this 1083 * mbuf chain first. Bail out if we can't get the 1084 * new buffers. 1085 */ 1086 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1087 if (mn == NULL) 1088 break; 1089 if (mb_head->m_pkthdr.len > MHLEN) { 1090 MCLGET(mn, MB_DONTWAIT); 1091 if ((mn->m_flags & M_EXT) == 0) { 1092 m_freem(mn); 1093 break; 1094 } 1095 } 1096 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1097 mtod(mn, caddr_t)); 1098 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1099 /* We can transmit the packet, dequeue it. */ 1100 mb_head = ifq_dequeue(&ifp->if_snd); 1101 m_freem(mb_head); 1102 mb_head = mn; 1103 goto tbdinit; 1104 } else { 1105 /* Nothing to worry about, just dequeue. */ 1106 mb_head = ifq_dequeue(&ifp->if_snd); 1107 } 1108 1109 txp->tbd_number = segment; 1110 txp->mb_head = mb_head; 1111 txp->cb_status = 0; 1112 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1113 txp->cb_command = 1114 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1115 FXP_CB_COMMAND_S; 1116 } else { 1117 txp->cb_command = 1118 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1119 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1120 /* 1121 * Set a 5 second timer just in case we don't hear 1122 * from the card again. 1123 */ 1124 ifp->if_timer = 5; 1125 } 1126 txp->tx_threshold = tx_threshold; 1127 1128 /* 1129 * Advance the end of list forward. 1130 */ 1131 1132 #ifdef __alpha__ 1133 /* 1134 * On platforms which can't access memory in 16-bit 1135 * granularities, we must prevent the card from DMA'ing 1136 * up the status while we update the command field. 1137 * This could cause us to overwrite the completion status. 1138 */ 1139 atomic_clear_short(&sc->cbl_last->cb_command, 1140 FXP_CB_COMMAND_S); 1141 #else 1142 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1143 #endif /*__alpha__*/ 1144 sc->cbl_last = txp; 1145 1146 /* 1147 * Advance the beginning of the list forward if there are 1148 * no other packets queued (when nothing is queued, cbl_first 1149 * sits on the last TxCB that was sent out). 1150 */ 1151 if (sc->tx_queued == 0) 1152 sc->cbl_first = txp; 1153 1154 sc->tx_queued++; 1155 1156 BPF_MTAP(ifp, mb_head); 1157 } 1158 1159 /* 1160 * We're finished. If we added to the list, issue a RESUME to get DMA 1161 * going again if suspended. 1162 */ 1163 if (txp != NULL) { 1164 fxp_scb_wait(sc); 1165 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1166 } 1167 } 1168 1169 #ifdef DEVICE_POLLING 1170 static poll_handler_t fxp_poll; 1171 1172 static void 1173 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1174 { 1175 struct fxp_softc *sc = ifp->if_softc; 1176 u_int8_t statack; 1177 1178 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1179 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1180 return; 1181 } 1182 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1183 FXP_SCB_STATACK_FR; 1184 if (cmd == POLL_AND_CHECK_STATUS) { 1185 u_int8_t tmp; 1186 1187 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1188 if (tmp == 0xff || tmp == 0) 1189 return; /* nothing to do */ 1190 tmp &= ~statack; 1191 /* ack what we can */ 1192 if (tmp != 0) 1193 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1194 statack |= tmp; 1195 } 1196 fxp_intr_body(sc, statack, count); 1197 } 1198 #endif /* DEVICE_POLLING */ 1199 1200 /* 1201 * Process interface interrupts. 1202 */ 1203 static void 1204 fxp_intr(void *xsc) 1205 { 1206 struct fxp_softc *sc = xsc; 1207 u_int8_t statack; 1208 1209 #ifdef DEVICE_POLLING 1210 struct ifnet *ifp = &sc->arpcom.ac_if; 1211 1212 if (ifp->if_flags & IFF_POLLING) 1213 return; 1214 if (ether_poll_register(fxp_poll, ifp)) { 1215 /* disable interrupts */ 1216 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1217 fxp_poll(ifp, 0, 1); 1218 return; 1219 } 1220 #endif 1221 1222 if (sc->suspended) { 1223 return; 1224 } 1225 1226 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1227 /* 1228 * It should not be possible to have all bits set; the 1229 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1230 * all bits are set, this may indicate that the card has 1231 * been physically ejected, so ignore it. 1232 */ 1233 if (statack == 0xff) 1234 return; 1235 1236 /* 1237 * First ACK all the interrupts in this pass. 1238 */ 1239 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1240 fxp_intr_body(sc, statack, -1); 1241 } 1242 } 1243 1244 static void 1245 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1246 { 1247 struct ifnet *ifp = &sc->arpcom.ac_if; 1248 struct mbuf *m; 1249 struct fxp_rfa *rfa; 1250 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1251 1252 if (rnr) 1253 fxp_rnr++; 1254 #ifdef DEVICE_POLLING 1255 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1256 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1257 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1258 rnr = 1; 1259 } 1260 #endif 1261 1262 /* 1263 * Free any finished transmit mbuf chains. 1264 * 1265 * Handle the CNA event likt a CXTNO event. It used to 1266 * be that this event (control unit not ready) was not 1267 * encountered, but it is now with the SMPng modifications. 1268 * The exact sequence of events that occur when the interface 1269 * is brought up are different now, and if this event 1270 * goes unhandled, the configuration/rxfilter setup sequence 1271 * can stall for several seconds. The result is that no 1272 * packets go out onto the wire for about 5 to 10 seconds 1273 * after the interface is ifconfig'ed for the first time. 1274 */ 1275 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1276 struct fxp_cb_tx *txp; 1277 1278 for (txp = sc->cbl_first; sc->tx_queued && 1279 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1280 txp = txp->next) { 1281 if ((m = txp->mb_head) != NULL) { 1282 txp->mb_head = NULL; 1283 sc->tx_queued--; 1284 m_freem(m); 1285 } else { 1286 sc->tx_queued--; 1287 } 1288 } 1289 sc->cbl_first = txp; 1290 ifp->if_timer = 0; 1291 if (sc->tx_queued == 0) { 1292 if (sc->need_mcsetup) 1293 fxp_mc_setup(sc); 1294 } 1295 /* 1296 * Try to start more packets transmitting. 1297 */ 1298 if (!ifq_is_empty(&ifp->if_snd)) 1299 (*ifp->if_start)(ifp); 1300 } 1301 1302 /* 1303 * Just return if nothing happened on the receive side. 1304 */ 1305 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1306 return; 1307 1308 /* 1309 * Process receiver interrupts. If a no-resource (RNR) 1310 * condition exists, get whatever packets we can and 1311 * re-start the receiver. 1312 * 1313 * When using polling, we do not process the list to completion, 1314 * so when we get an RNR interrupt we must defer the restart 1315 * until we hit the last buffer with the C bit set. 1316 * If we run out of cycles and rfa_headm has the C bit set, 1317 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1318 * that the info will be used in the subsequent polling cycle. 1319 */ 1320 for (;;) { 1321 m = sc->rfa_headm; 1322 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1323 RFA_ALIGNMENT_FUDGE); 1324 1325 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1326 if (count >= 0 && count-- == 0) { 1327 if (rnr) { 1328 /* Defer RNR processing until the next time. */ 1329 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1330 rnr = 0; 1331 } 1332 break; 1333 } 1334 #endif /* DEVICE_POLLING */ 1335 1336 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1337 break; 1338 1339 /* 1340 * Remove first packet from the chain. 1341 */ 1342 sc->rfa_headm = m->m_next; 1343 m->m_next = NULL; 1344 1345 /* 1346 * Add a new buffer to the receive chain. 1347 * If this fails, the old buffer is recycled 1348 * instead. 1349 */ 1350 if (fxp_add_rfabuf(sc, m) == 0) { 1351 int total_len; 1352 1353 /* 1354 * Fetch packet length (the top 2 bits of 1355 * actual_size are flags set by the controller 1356 * upon completion), and drop the packet in case 1357 * of bogus length or CRC errors. 1358 */ 1359 total_len = rfa->actual_size & 0x3fff; 1360 if (total_len < sizeof(struct ether_header) || 1361 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1362 sizeof(struct fxp_rfa) || 1363 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1364 m_freem(m); 1365 continue; 1366 } 1367 m->m_pkthdr.len = m->m_len = total_len; 1368 (*ifp->if_input)(ifp, m); 1369 } 1370 } 1371 if (rnr) { 1372 fxp_scb_wait(sc); 1373 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1374 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1375 RFA_ALIGNMENT_FUDGE); 1376 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1377 } 1378 } 1379 1380 /* 1381 * Update packet in/out/collision statistics. The i82557 doesn't 1382 * allow you to access these counters without doing a fairly 1383 * expensive DMA to get _all_ of the statistics it maintains, so 1384 * we do this operation here only once per second. The statistics 1385 * counters in the kernel are updated from the previous dump-stats 1386 * DMA and then a new dump-stats DMA is started. The on-chip 1387 * counters are zeroed when the DMA completes. If we can't start 1388 * the DMA immediately, we don't wait - we just prepare to read 1389 * them again next time. 1390 */ 1391 static void 1392 fxp_tick(void *xsc) 1393 { 1394 struct fxp_softc *sc = xsc; 1395 struct ifnet *ifp = &sc->arpcom.ac_if; 1396 struct fxp_stats *sp = sc->fxp_stats; 1397 struct fxp_cb_tx *txp; 1398 struct mbuf *m; 1399 int s; 1400 1401 ifp->if_opackets += sp->tx_good; 1402 ifp->if_collisions += sp->tx_total_collisions; 1403 if (sp->rx_good) { 1404 ifp->if_ipackets += sp->rx_good; 1405 sc->rx_idle_secs = 0; 1406 } else { 1407 /* 1408 * Receiver's been idle for another second. 1409 */ 1410 sc->rx_idle_secs++; 1411 } 1412 ifp->if_ierrors += 1413 sp->rx_crc_errors + 1414 sp->rx_alignment_errors + 1415 sp->rx_rnr_errors + 1416 sp->rx_overrun_errors; 1417 /* 1418 * If any transmit underruns occured, bump up the transmit 1419 * threshold by another 512 bytes (64 * 8). 1420 */ 1421 if (sp->tx_underruns) { 1422 ifp->if_oerrors += sp->tx_underruns; 1423 if (tx_threshold < 192) 1424 tx_threshold += 64; 1425 } 1426 s = splimp(); 1427 /* 1428 * Release any xmit buffers that have completed DMA. This isn't 1429 * strictly necessary to do here, but it's advantagous for mbufs 1430 * with external storage to be released in a timely manner rather 1431 * than being defered for a potentially long time. This limits 1432 * the delay to a maximum of one second. 1433 */ 1434 for (txp = sc->cbl_first; sc->tx_queued && 1435 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1436 txp = txp->next) { 1437 if ((m = txp->mb_head) != NULL) { 1438 txp->mb_head = NULL; 1439 sc->tx_queued--; 1440 m_freem(m); 1441 } else { 1442 sc->tx_queued--; 1443 } 1444 } 1445 sc->cbl_first = txp; 1446 /* 1447 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1448 * then assume the receiver has locked up and attempt to clear 1449 * the condition by reprogramming the multicast filter. This is 1450 * a work-around for a bug in the 82557 where the receiver locks 1451 * up if it gets certain types of garbage in the syncronization 1452 * bits prior to the packet header. This bug is supposed to only 1453 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1454 * mode as well (perhaps due to a 10/100 speed transition). 1455 */ 1456 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1457 sc->rx_idle_secs = 0; 1458 fxp_mc_setup(sc); 1459 } 1460 /* 1461 * If there is no pending command, start another stats 1462 * dump. Otherwise punt for now. 1463 */ 1464 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1465 /* 1466 * Start another stats dump. 1467 */ 1468 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1469 } else { 1470 /* 1471 * A previous command is still waiting to be accepted. 1472 * Just zero our copy of the stats and wait for the 1473 * next timer event to update them. 1474 */ 1475 sp->tx_good = 0; 1476 sp->tx_underruns = 0; 1477 sp->tx_total_collisions = 0; 1478 1479 sp->rx_good = 0; 1480 sp->rx_crc_errors = 0; 1481 sp->rx_alignment_errors = 0; 1482 sp->rx_rnr_errors = 0; 1483 sp->rx_overrun_errors = 0; 1484 } 1485 if (sc->miibus != NULL) 1486 mii_tick(device_get_softc(sc->miibus)); 1487 splx(s); 1488 /* 1489 * Schedule another timeout one second from now. 1490 */ 1491 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1492 } 1493 1494 /* 1495 * Stop the interface. Cancels the statistics updater and resets 1496 * the interface. 1497 */ 1498 static void 1499 fxp_stop(struct fxp_softc *sc) 1500 { 1501 struct ifnet *ifp = &sc->arpcom.ac_if; 1502 struct fxp_cb_tx *txp; 1503 int i; 1504 1505 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1506 ifp->if_timer = 0; 1507 1508 #ifdef DEVICE_POLLING 1509 ether_poll_deregister(ifp); 1510 #endif 1511 /* 1512 * Cancel stats updater. 1513 */ 1514 callout_stop(&sc->fxp_stat_timer); 1515 1516 /* 1517 * Issue software reset, which also unloads the microcode. 1518 */ 1519 sc->flags &= ~FXP_FLAG_UCODE; 1520 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1521 DELAY(50); 1522 1523 /* 1524 * Release any xmit buffers. 1525 */ 1526 txp = sc->cbl_base; 1527 if (txp != NULL) { 1528 for (i = 0; i < FXP_NTXCB; i++) { 1529 if (txp[i].mb_head != NULL) { 1530 m_freem(txp[i].mb_head); 1531 txp[i].mb_head = NULL; 1532 } 1533 } 1534 } 1535 sc->tx_queued = 0; 1536 1537 /* 1538 * Free all the receive buffers then reallocate/reinitialize 1539 */ 1540 if (sc->rfa_headm != NULL) 1541 m_freem(sc->rfa_headm); 1542 sc->rfa_headm = NULL; 1543 sc->rfa_tailm = NULL; 1544 for (i = 0; i < FXP_NRFABUFS; i++) { 1545 if (fxp_add_rfabuf(sc, NULL) != 0) { 1546 /* 1547 * This "can't happen" - we're at splimp() 1548 * and we just freed all the buffers we need 1549 * above. 1550 */ 1551 panic("fxp_stop: no buffers!"); 1552 } 1553 } 1554 } 1555 1556 /* 1557 * Watchdog/transmission transmit timeout handler. Called when a 1558 * transmission is started on the interface, but no interrupt is 1559 * received before the timeout. This usually indicates that the 1560 * card has wedged for some reason. 1561 */ 1562 static void 1563 fxp_watchdog(struct ifnet *ifp) 1564 { 1565 struct fxp_softc *sc = ifp->if_softc; 1566 1567 device_printf(sc->dev, "device timeout\n"); 1568 ifp->if_oerrors++; 1569 1570 fxp_init(sc); 1571 } 1572 1573 static void 1574 fxp_init(void *xsc) 1575 { 1576 struct fxp_softc *sc = xsc; 1577 struct ifnet *ifp = &sc->arpcom.ac_if; 1578 struct fxp_cb_config *cbp; 1579 struct fxp_cb_ias *cb_ias; 1580 struct fxp_cb_tx *txp; 1581 struct fxp_cb_mcs *mcsp; 1582 int i, prm, s; 1583 1584 s = splimp(); 1585 /* 1586 * Cancel any pending I/O 1587 */ 1588 fxp_stop(sc); 1589 1590 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1591 1592 /* 1593 * Initialize base of CBL and RFA memory. Loading with zero 1594 * sets it up for regular linear addressing. 1595 */ 1596 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1597 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1598 1599 fxp_scb_wait(sc); 1600 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1601 1602 /* 1603 * Initialize base of dump-stats buffer. 1604 */ 1605 fxp_scb_wait(sc); 1606 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1607 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1608 1609 /* 1610 * Attempt to load microcode if requested. 1611 */ 1612 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1613 fxp_load_ucode(sc); 1614 1615 /* 1616 * Initialize the multicast address list. 1617 */ 1618 if (fxp_mc_addrs(sc)) { 1619 mcsp = sc->mcsp; 1620 mcsp->cb_status = 0; 1621 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1622 mcsp->link_addr = -1; 1623 /* 1624 * Start the multicast setup command. 1625 */ 1626 fxp_scb_wait(sc); 1627 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1628 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1629 /* ...and wait for it to complete. */ 1630 fxp_dma_wait(&mcsp->cb_status, sc); 1631 } 1632 1633 /* 1634 * We temporarily use memory that contains the TxCB list to 1635 * construct the config CB. The TxCB list memory is rebuilt 1636 * later. 1637 */ 1638 cbp = (struct fxp_cb_config *) sc->cbl_base; 1639 1640 /* 1641 * This bcopy is kind of disgusting, but there are a bunch of must be 1642 * zero and must be one bits in this structure and this is the easiest 1643 * way to initialize them all to proper values. 1644 */ 1645 bcopy(fxp_cb_config_template, 1646 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1647 sizeof(fxp_cb_config_template)); 1648 1649 cbp->cb_status = 0; 1650 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1651 cbp->link_addr = -1; /* (no) next command */ 1652 cbp->byte_count = 22; /* (22) bytes to config */ 1653 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1654 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1655 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1656 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1657 cbp->type_enable = 0; /* actually reserved */ 1658 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1659 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1660 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1661 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1662 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1663 cbp->late_scb = 0; /* (don't) defer SCB update */ 1664 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1665 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1666 cbp->ci_int = 1; /* interrupt on CU idle */ 1667 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1668 cbp->ext_stats_dis = 1; /* disable extended counters */ 1669 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1670 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1671 cbp->disc_short_rx = !prm; /* discard short packets */ 1672 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1673 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1674 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1675 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1676 cbp->csma_dis = 0; /* (don't) disable link */ 1677 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1678 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1679 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1680 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1681 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1682 cbp->nsai = 1; /* (don't) disable source addr insert */ 1683 cbp->preamble_length = 2; /* (7 byte) preamble */ 1684 cbp->loopback = 0; /* (don't) loopback */ 1685 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1686 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1687 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1688 cbp->promiscuous = prm; /* promiscuous mode */ 1689 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1690 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1691 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1692 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1693 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1694 1695 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1696 cbp->padding = 1; /* (do) pad short tx packets */ 1697 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1698 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1699 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1700 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1701 /* must set wake_en in PMCSR also */ 1702 cbp->force_fdx = 0; /* (don't) force full duplex */ 1703 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1704 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1705 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1706 1707 if (sc->revision == FXP_REV_82557) { 1708 /* 1709 * The 82557 has no hardware flow control, the values 1710 * below are the defaults for the chip. 1711 */ 1712 cbp->fc_delay_lsb = 0; 1713 cbp->fc_delay_msb = 0x40; 1714 cbp->pri_fc_thresh = 3; 1715 cbp->tx_fc_dis = 0; 1716 cbp->rx_fc_restop = 0; 1717 cbp->rx_fc_restart = 0; 1718 cbp->fc_filter = 0; 1719 cbp->pri_fc_loc = 1; 1720 } else { 1721 cbp->fc_delay_lsb = 0x1f; 1722 cbp->fc_delay_msb = 0x01; 1723 cbp->pri_fc_thresh = 3; 1724 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1725 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1726 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1727 cbp->fc_filter = !prm; /* drop FC frames to host */ 1728 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1729 } 1730 1731 /* 1732 * Start the config command/DMA. 1733 */ 1734 fxp_scb_wait(sc); 1735 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1736 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1737 /* ...and wait for it to complete. */ 1738 fxp_dma_wait(&cbp->cb_status, sc); 1739 1740 /* 1741 * Now initialize the station address. Temporarily use the TxCB 1742 * memory area like we did above for the config CB. 1743 */ 1744 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1745 cb_ias->cb_status = 0; 1746 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1747 cb_ias->link_addr = -1; 1748 bcopy(sc->arpcom.ac_enaddr, 1749 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1750 sizeof(sc->arpcom.ac_enaddr)); 1751 1752 /* 1753 * Start the IAS (Individual Address Setup) command/DMA. 1754 */ 1755 fxp_scb_wait(sc); 1756 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1757 /* ...and wait for it to complete. */ 1758 fxp_dma_wait(&cb_ias->cb_status, sc); 1759 1760 /* 1761 * Initialize transmit control block (TxCB) list. 1762 */ 1763 1764 txp = sc->cbl_base; 1765 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1766 for (i = 0; i < FXP_NTXCB; i++) { 1767 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1768 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1769 txp[i].link_addr = 1770 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1771 if (sc->flags & FXP_FLAG_EXT_TXCB) 1772 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1773 else 1774 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1775 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1776 } 1777 /* 1778 * Set the suspend flag on the first TxCB and start the control 1779 * unit. It will execute the NOP and then suspend. 1780 */ 1781 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1782 sc->cbl_first = sc->cbl_last = txp; 1783 sc->tx_queued = 1; 1784 1785 fxp_scb_wait(sc); 1786 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1787 1788 /* 1789 * Initialize receiver buffer area - RFA. 1790 */ 1791 fxp_scb_wait(sc); 1792 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1793 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1794 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1795 1796 /* 1797 * Set current media. 1798 */ 1799 if (sc->miibus != NULL) 1800 mii_mediachg(device_get_softc(sc->miibus)); 1801 1802 ifp->if_flags |= IFF_RUNNING; 1803 ifp->if_flags &= ~IFF_OACTIVE; 1804 1805 /* 1806 * Enable interrupts. 1807 */ 1808 #ifdef DEVICE_POLLING 1809 /* 1810 * ... but only do that if we are not polling. And because (presumably) 1811 * the default is interrupts on, we need to disable them explicitly! 1812 */ 1813 if ( ifp->if_flags & IFF_POLLING ) 1814 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1815 else 1816 #endif /* DEVICE_POLLING */ 1817 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1818 splx(s); 1819 1820 /* 1821 * Start stats updater. 1822 */ 1823 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1824 } 1825 1826 static int 1827 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1828 { 1829 1830 return (0); 1831 } 1832 1833 static void 1834 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1835 { 1836 1837 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1838 } 1839 1840 /* 1841 * Change media according to request. 1842 */ 1843 static int 1844 fxp_ifmedia_upd(struct ifnet *ifp) 1845 { 1846 struct fxp_softc *sc = ifp->if_softc; 1847 struct mii_data *mii; 1848 1849 mii = device_get_softc(sc->miibus); 1850 mii_mediachg(mii); 1851 return (0); 1852 } 1853 1854 /* 1855 * Notify the world which media we're using. 1856 */ 1857 static void 1858 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1859 { 1860 struct fxp_softc *sc = ifp->if_softc; 1861 struct mii_data *mii; 1862 1863 mii = device_get_softc(sc->miibus); 1864 mii_pollstat(mii); 1865 ifmr->ifm_active = mii->mii_media_active; 1866 ifmr->ifm_status = mii->mii_media_status; 1867 1868 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1869 sc->cu_resume_bug = 1; 1870 else 1871 sc->cu_resume_bug = 0; 1872 } 1873 1874 /* 1875 * Add a buffer to the end of the RFA buffer list. 1876 * Return 0 if successful, 1 for failure. A failure results in 1877 * adding the 'oldm' (if non-NULL) on to the end of the list - 1878 * tossing out its old contents and recycling it. 1879 * The RFA struct is stuck at the beginning of mbuf cluster and the 1880 * data pointer is fixed up to point just past it. 1881 */ 1882 static int 1883 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1884 { 1885 u_int32_t v; 1886 struct mbuf *m; 1887 struct fxp_rfa *rfa, *p_rfa; 1888 1889 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1890 if (m == NULL) { /* try to recycle the old mbuf instead */ 1891 if (oldm == NULL) 1892 return 1; 1893 m = oldm; 1894 m->m_data = m->m_ext.ext_buf; 1895 } 1896 1897 /* 1898 * Move the data pointer up so that the incoming data packet 1899 * will be 32-bit aligned. 1900 */ 1901 m->m_data += RFA_ALIGNMENT_FUDGE; 1902 1903 /* 1904 * Get a pointer to the base of the mbuf cluster and move 1905 * data start past it. 1906 */ 1907 rfa = mtod(m, struct fxp_rfa *); 1908 m->m_data += sizeof(struct fxp_rfa); 1909 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1910 1911 /* 1912 * Initialize the rest of the RFA. Note that since the RFA 1913 * is misaligned, we cannot store values directly. Instead, 1914 * we use an optimized, inline copy. 1915 */ 1916 1917 rfa->rfa_status = 0; 1918 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1919 rfa->actual_size = 0; 1920 1921 v = -1; 1922 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1923 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1924 1925 /* 1926 * If there are other buffers already on the list, attach this 1927 * one to the end by fixing up the tail to point to this one. 1928 */ 1929 if (sc->rfa_headm != NULL) { 1930 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1931 RFA_ALIGNMENT_FUDGE); 1932 sc->rfa_tailm->m_next = m; 1933 v = vtophys(rfa); 1934 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1935 p_rfa->rfa_control = 0; 1936 } else { 1937 sc->rfa_headm = m; 1938 } 1939 sc->rfa_tailm = m; 1940 1941 return (m == oldm); 1942 } 1943 1944 static volatile int 1945 fxp_miibus_readreg(device_t dev, int phy, int reg) 1946 { 1947 struct fxp_softc *sc = device_get_softc(dev); 1948 int count = 10000; 1949 int value; 1950 1951 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1952 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1953 1954 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1955 && count--) 1956 DELAY(10); 1957 1958 if (count <= 0) 1959 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1960 1961 return (value & 0xffff); 1962 } 1963 1964 static void 1965 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1966 { 1967 struct fxp_softc *sc = device_get_softc(dev); 1968 int count = 10000; 1969 1970 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1971 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1972 (value & 0xffff)); 1973 1974 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1975 count--) 1976 DELAY(10); 1977 1978 if (count <= 0) 1979 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1980 } 1981 1982 static int 1983 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1984 { 1985 struct fxp_softc *sc = ifp->if_softc; 1986 struct ifreq *ifr = (struct ifreq *)data; 1987 struct mii_data *mii; 1988 int s, error = 0; 1989 1990 s = splimp(); 1991 1992 switch (command) { 1993 case SIOCSIFADDR: 1994 case SIOCGIFADDR: 1995 case SIOCSIFMTU: 1996 error = ether_ioctl(ifp, command, data); 1997 break; 1998 1999 case SIOCSIFFLAGS: 2000 if (ifp->if_flags & IFF_ALLMULTI) 2001 sc->flags |= FXP_FLAG_ALL_MCAST; 2002 else 2003 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2004 2005 /* 2006 * If interface is marked up and not running, then start it. 2007 * If it is marked down and running, stop it. 2008 * XXX If it's up then re-initialize it. This is so flags 2009 * such as IFF_PROMISC are handled. 2010 */ 2011 if (ifp->if_flags & IFF_UP) { 2012 fxp_init(sc); 2013 } else { 2014 if (ifp->if_flags & IFF_RUNNING) 2015 fxp_stop(sc); 2016 } 2017 break; 2018 2019 case SIOCADDMULTI: 2020 case SIOCDELMULTI: 2021 if (ifp->if_flags & IFF_ALLMULTI) 2022 sc->flags |= FXP_FLAG_ALL_MCAST; 2023 else 2024 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2025 /* 2026 * Multicast list has changed; set the hardware filter 2027 * accordingly. 2028 */ 2029 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2030 fxp_mc_setup(sc); 2031 /* 2032 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2033 * again rather than else {}. 2034 */ 2035 if (sc->flags & FXP_FLAG_ALL_MCAST) 2036 fxp_init(sc); 2037 error = 0; 2038 break; 2039 2040 case SIOCSIFMEDIA: 2041 case SIOCGIFMEDIA: 2042 if (sc->miibus != NULL) { 2043 mii = device_get_softc(sc->miibus); 2044 error = ifmedia_ioctl(ifp, ifr, 2045 &mii->mii_media, command); 2046 } else { 2047 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2048 } 2049 break; 2050 2051 default: 2052 error = EINVAL; 2053 } 2054 splx(s); 2055 return (error); 2056 } 2057 2058 /* 2059 * Fill in the multicast address list and return number of entries. 2060 */ 2061 static int 2062 fxp_mc_addrs(struct fxp_softc *sc) 2063 { 2064 struct fxp_cb_mcs *mcsp = sc->mcsp; 2065 struct ifnet *ifp = &sc->arpcom.ac_if; 2066 struct ifmultiaddr *ifma; 2067 int nmcasts; 2068 2069 nmcasts = 0; 2070 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2071 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2072 if (ifma->ifma_addr->sa_family != AF_LINK) 2073 continue; 2074 if (nmcasts >= MAXMCADDR) { 2075 sc->flags |= FXP_FLAG_ALL_MCAST; 2076 nmcasts = 0; 2077 break; 2078 } 2079 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2080 (void *)(uintptr_t)(volatile void *) 2081 &sc->mcsp->mc_addr[nmcasts][0], 6); 2082 nmcasts++; 2083 } 2084 } 2085 mcsp->mc_cnt = nmcasts * 6; 2086 return (nmcasts); 2087 } 2088 2089 /* 2090 * Program the multicast filter. 2091 * 2092 * We have an artificial restriction that the multicast setup command 2093 * must be the first command in the chain, so we take steps to ensure 2094 * this. By requiring this, it allows us to keep up the performance of 2095 * the pre-initialized command ring (esp. link pointers) by not actually 2096 * inserting the mcsetup command in the ring - i.e. its link pointer 2097 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2098 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2099 * lead into the regular TxCB ring when it completes. 2100 * 2101 * This function must be called at splimp. 2102 */ 2103 static void 2104 fxp_mc_setup(struct fxp_softc *sc) 2105 { 2106 struct fxp_cb_mcs *mcsp = sc->mcsp; 2107 struct ifnet *ifp = &sc->arpcom.ac_if; 2108 int count; 2109 2110 /* 2111 * If there are queued commands, we must wait until they are all 2112 * completed. If we are already waiting, then add a NOP command 2113 * with interrupt option so that we're notified when all commands 2114 * have been completed - fxp_start() ensures that no additional 2115 * TX commands will be added when need_mcsetup is true. 2116 */ 2117 if (sc->tx_queued) { 2118 struct fxp_cb_tx *txp; 2119 2120 /* 2121 * need_mcsetup will be true if we are already waiting for the 2122 * NOP command to be completed (see below). In this case, bail. 2123 */ 2124 if (sc->need_mcsetup) 2125 return; 2126 sc->need_mcsetup = 1; 2127 2128 /* 2129 * Add a NOP command with interrupt so that we are notified 2130 * when all TX commands have been processed. 2131 */ 2132 txp = sc->cbl_last->next; 2133 txp->mb_head = NULL; 2134 txp->cb_status = 0; 2135 txp->cb_command = FXP_CB_COMMAND_NOP | 2136 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2137 /* 2138 * Advance the end of list forward. 2139 */ 2140 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2141 sc->cbl_last = txp; 2142 sc->tx_queued++; 2143 /* 2144 * Issue a resume in case the CU has just suspended. 2145 */ 2146 fxp_scb_wait(sc); 2147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2148 /* 2149 * Set a 5 second timer just in case we don't hear from the 2150 * card again. 2151 */ 2152 ifp->if_timer = 5; 2153 2154 return; 2155 } 2156 sc->need_mcsetup = 0; 2157 2158 /* 2159 * Initialize multicast setup descriptor. 2160 */ 2161 mcsp->next = sc->cbl_base; 2162 mcsp->mb_head = NULL; 2163 mcsp->cb_status = 0; 2164 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2165 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2166 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2167 (void) fxp_mc_addrs(sc); 2168 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2169 sc->tx_queued = 1; 2170 2171 /* 2172 * Wait until command unit is not active. This should never 2173 * be the case when nothing is queued, but make sure anyway. 2174 */ 2175 count = 100; 2176 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2177 FXP_SCB_CUS_ACTIVE && --count) 2178 DELAY(10); 2179 if (count == 0) { 2180 device_printf(sc->dev, "command queue timeout\n"); 2181 return; 2182 } 2183 2184 /* 2185 * Start the multicast setup command. 2186 */ 2187 fxp_scb_wait(sc); 2188 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2189 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2190 2191 ifp->if_timer = 2; 2192 return; 2193 } 2194 2195 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2196 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2197 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2198 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2199 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2200 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2201 2202 #define UCODE(x) x, sizeof(x) 2203 2204 struct ucode { 2205 u_int32_t revision; 2206 u_int32_t *ucode; 2207 int length; 2208 u_short int_delay_offset; 2209 u_short bundle_max_offset; 2210 } ucode_table[] = { 2211 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2212 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2213 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2214 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2215 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2216 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2217 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2218 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2219 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2220 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2221 { 0, NULL, 0, 0, 0 } 2222 }; 2223 2224 static void 2225 fxp_load_ucode(struct fxp_softc *sc) 2226 { 2227 struct ucode *uc; 2228 struct fxp_cb_ucode *cbp; 2229 2230 for (uc = ucode_table; uc->ucode != NULL; uc++) 2231 if (sc->revision == uc->revision) 2232 break; 2233 if (uc->ucode == NULL) 2234 return; 2235 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2236 cbp->cb_status = 0; 2237 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2238 cbp->link_addr = -1; /* (no) next command */ 2239 memcpy(cbp->ucode, uc->ucode, uc->length); 2240 if (uc->int_delay_offset) 2241 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2242 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2243 if (uc->bundle_max_offset) 2244 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2245 sc->tunable_bundle_max; 2246 /* 2247 * Download the ucode to the chip. 2248 */ 2249 fxp_scb_wait(sc); 2250 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2251 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2252 /* ...and wait for it to complete. */ 2253 fxp_dma_wait(&cbp->cb_status, sc); 2254 device_printf(sc->dev, 2255 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2256 sc->tunable_int_delay, 2257 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2258 sc->flags |= FXP_FLAG_UCODE; 2259 } 2260 2261 static int 2262 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2263 { 2264 int error, value; 2265 2266 value = *(int *)arg1; 2267 error = sysctl_handle_int(oidp, &value, 0, req); 2268 if (error || !req->newptr) 2269 return (error); 2270 if (value < low || value > high) 2271 return (EINVAL); 2272 *(int *)arg1 = value; 2273 return (0); 2274 } 2275 2276 /* 2277 * Interrupt delay is expressed in microseconds, a multiplier is used 2278 * to convert this to the appropriate clock ticks before using. 2279 */ 2280 static int 2281 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2282 { 2283 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2284 } 2285 2286 static int 2287 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2288 { 2289 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2290 } 2291