1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.37 2005/10/24 08:06:15 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef NS 53 #include <netns/ns.h> 54 #include <netns/ns_if.h> 55 #endif 56 57 #include <net/bpf.h> 58 #include <sys/sockio.h> 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 64 #include <net/ethernet.h> 65 #include <net/if_arp.h> 66 67 #include <vm/vm.h> /* for vtophys */ 68 #include <vm/pmap.h> /* for vtophys */ 69 70 #include <net/if_types.h> 71 #include <net/vlan/if_vlan_var.h> 72 73 #include <bus/pci/pcivar.h> 74 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include "../mii_layer/mii.h" 77 #include "../mii_layer/miivar.h" 78 79 #include "if_fxpreg.h" 80 #include "if_fxpvar.h" 81 #include "rcvbundl.h" 82 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 int16_t revid; /* -1 matches anything */ 142 char *name; 143 }; 144 145 /* 146 * Claim various Intel PCI device identifiers for this driver. The 147 * sub-vendor and sub-device field are extensively used to identify 148 * particular variants, but we don't currently differentiate between 149 * them. 150 */ 151 static struct fxp_ident fxp_ident_table[] = { 152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 172 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 173 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 177 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 182 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 186 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 188 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 189 { 0, -1, NULL }, 190 }; 191 192 static int fxp_probe(device_t dev); 193 static int fxp_attach(device_t dev); 194 static int fxp_detach(device_t dev); 195 static int fxp_shutdown(device_t dev); 196 static int fxp_suspend(device_t dev); 197 static int fxp_resume(device_t dev); 198 199 static void fxp_intr(void *xsc); 200 static void fxp_intr_body(struct fxp_softc *sc, 201 u_int8_t statack, int count); 202 203 static void fxp_init(void *xsc); 204 static void fxp_tick(void *xsc); 205 static void fxp_powerstate_d0(device_t dev); 206 static void fxp_start(struct ifnet *ifp); 207 static void fxp_stop(struct fxp_softc *sc); 208 static void fxp_release(device_t dev); 209 static int fxp_ioctl(struct ifnet *ifp, u_long command, 210 caddr_t data, struct ucred *); 211 static void fxp_watchdog(struct ifnet *ifp); 212 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 213 static int fxp_mc_addrs(struct fxp_softc *sc); 214 static void fxp_mc_setup(struct fxp_softc *sc); 215 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 216 int autosize); 217 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 218 u_int16_t data); 219 static void fxp_autosize_eeprom(struct fxp_softc *sc); 220 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 221 int offset, int words); 222 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 223 int offset, int words); 224 static int fxp_ifmedia_upd(struct ifnet *ifp); 225 static void fxp_ifmedia_sts(struct ifnet *ifp, 226 struct ifmediareq *ifmr); 227 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 228 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 229 struct ifmediareq *ifmr); 230 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 231 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 232 int value); 233 static void fxp_load_ucode(struct fxp_softc *sc); 234 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 235 int low, int high); 236 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 237 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 238 #ifdef DEVICE_POLLING 239 static poll_handler_t fxp_poll; 240 #endif 241 242 static void fxp_lwcopy(volatile u_int32_t *src, 243 volatile u_int32_t *dst); 244 static void fxp_scb_wait(struct fxp_softc *sc); 245 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 246 static void fxp_dma_wait(volatile u_int16_t *status, 247 struct fxp_softc *sc); 248 249 static device_method_t fxp_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, fxp_probe), 252 DEVMETHOD(device_attach, fxp_attach), 253 DEVMETHOD(device_detach, fxp_detach), 254 DEVMETHOD(device_shutdown, fxp_shutdown), 255 DEVMETHOD(device_suspend, fxp_suspend), 256 DEVMETHOD(device_resume, fxp_resume), 257 258 /* MII interface */ 259 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 260 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 261 262 { 0, 0 } 263 }; 264 265 static driver_t fxp_driver = { 266 "fxp", 267 fxp_methods, 268 sizeof(struct fxp_softc), 269 }; 270 271 static devclass_t fxp_devclass; 272 273 DECLARE_DUMMY_MODULE(if_fxp); 274 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 275 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 276 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 277 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 278 279 static int fxp_rnr; 280 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 281 282 /* 283 * Copy a 16-bit aligned 32-bit quantity. 284 */ 285 static void 286 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 287 { 288 #ifdef __i386__ 289 *dst = *src; 290 #else 291 volatile u_int16_t *a = (volatile u_int16_t *)src; 292 volatile u_int16_t *b = (volatile u_int16_t *)dst; 293 294 b[0] = a[0]; 295 b[1] = a[1]; 296 #endif 297 } 298 299 /* 300 * Wait for the previous command to be accepted (but not necessarily 301 * completed). 302 */ 303 static void 304 fxp_scb_wait(struct fxp_softc *sc) 305 { 306 int i = 10000; 307 308 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 309 DELAY(2); 310 if (i == 0) { 311 if_printf(&sc->arpcom.ac_if, 312 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 313 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 314 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 315 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 316 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 317 } 318 } 319 320 static void 321 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 322 { 323 324 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 325 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 326 fxp_scb_wait(sc); 327 } 328 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 329 } 330 331 static void 332 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 333 { 334 int i = 10000; 335 336 while (!(*status & FXP_CB_STATUS_C) && --i) 337 DELAY(2); 338 if (i == 0) 339 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 340 } 341 342 /* 343 * Return identification string if this is device is ours. 344 */ 345 static int 346 fxp_probe(device_t dev) 347 { 348 u_int16_t devid; 349 u_int8_t revid; 350 struct fxp_ident *ident; 351 352 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 353 devid = pci_get_device(dev); 354 revid = pci_get_revid(dev); 355 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 356 if (ident->devid == devid && 357 (ident->revid == revid || ident->revid == -1)) { 358 device_set_desc(dev, ident->name); 359 return (0); 360 } 361 } 362 } 363 return (ENXIO); 364 } 365 366 static void 367 fxp_powerstate_d0(device_t dev) 368 { 369 u_int32_t iobase, membase, irq; 370 371 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 372 /* Save important PCI config data. */ 373 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 374 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 375 irq = pci_read_config(dev, PCIR_INTLINE, 4); 376 377 /* Reset the power state. */ 378 device_printf(dev, "chip is in D%d power mode " 379 "-- setting to D0\n", pci_get_powerstate(dev)); 380 381 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 382 383 /* Restore PCI config data. */ 384 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 385 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 386 pci_write_config(dev, PCIR_INTLINE, irq, 4); 387 } 388 } 389 390 static int 391 fxp_attach(device_t dev) 392 { 393 int error = 0; 394 struct fxp_softc *sc = device_get_softc(dev); 395 struct ifnet *ifp; 396 u_int32_t val; 397 u_int16_t data; 398 int i, rid, m1, m2, prefer_iomap; 399 400 callout_init(&sc->fxp_stat_timer); 401 sysctl_ctx_init(&sc->sysctl_ctx); 402 403 /* 404 * Enable bus mastering. Enable memory space too, in case 405 * BIOS/Prom forgot about it. 406 */ 407 pci_enable_busmaster(dev); 408 pci_enable_io(dev, SYS_RES_MEMORY); 409 val = pci_read_config(dev, PCIR_COMMAND, 2); 410 411 fxp_powerstate_d0(dev); 412 413 /* 414 * Figure out which we should try first - memory mapping or i/o mapping? 415 * We default to memory mapping. Then we accept an override from the 416 * command line. Then we check to see which one is enabled. 417 */ 418 m1 = PCIM_CMD_MEMEN; 419 m2 = PCIM_CMD_PORTEN; 420 prefer_iomap = 0; 421 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 422 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 423 m1 = PCIM_CMD_PORTEN; 424 m2 = PCIM_CMD_MEMEN; 425 } 426 427 if (val & m1) { 428 sc->rtp = 429 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 430 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 431 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 432 RF_ACTIVE); 433 } 434 if (sc->mem == NULL && (val & m2)) { 435 sc->rtp = 436 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 437 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 438 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 439 RF_ACTIVE); 440 } 441 442 if (!sc->mem) { 443 device_printf(dev, "could not map device registers\n"); 444 error = ENXIO; 445 goto fail; 446 } 447 if (bootverbose) { 448 device_printf(dev, "using %s space register mapping\n", 449 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 450 } 451 452 sc->sc_st = rman_get_bustag(sc->mem); 453 sc->sc_sh = rman_get_bushandle(sc->mem); 454 455 /* 456 * Allocate our interrupt. 457 */ 458 rid = 0; 459 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 460 RF_SHAREABLE | RF_ACTIVE); 461 if (sc->irq == NULL) { 462 device_printf(dev, "could not map interrupt\n"); 463 error = ENXIO; 464 goto fail; 465 } 466 467 /* 468 * Reset to a stable state. 469 */ 470 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 471 DELAY(10); 472 473 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 474 M_DEVBUF, M_WAITOK | M_ZERO); 475 476 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 477 M_WAITOK | M_ZERO); 478 479 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 480 481 /* 482 * Pre-allocate our receive buffers. 483 */ 484 for (i = 0; i < FXP_NRFABUFS; i++) { 485 if (fxp_add_rfabuf(sc, NULL) != 0) { 486 goto failmem; 487 } 488 } 489 490 /* 491 * Find out how large of an SEEPROM we have. 492 */ 493 fxp_autosize_eeprom(sc); 494 495 /* 496 * Determine whether we must use the 503 serial interface. 497 */ 498 fxp_read_eeprom(sc, &data, 6, 1); 499 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 500 (data & FXP_PHY_SERIAL_ONLY)) 501 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 502 503 /* 504 * Create the sysctl tree 505 */ 506 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 507 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 508 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 509 if (sc->sysctl_tree == NULL) 510 goto fail; 511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 512 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 513 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 514 "FXP driver receive interrupt microcode bundling delay"); 515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 516 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 517 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 518 "FXP driver receive interrupt microcode bundle size limit"); 519 520 /* 521 * Pull in device tunables. 522 */ 523 sc->tunable_int_delay = TUNABLE_INT_DELAY; 524 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 525 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 526 "int_delay", &sc->tunable_int_delay); 527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "bundle_max", &sc->tunable_bundle_max); 529 530 /* 531 * Find out the chip revision; lump all 82557 revs together. 532 */ 533 fxp_read_eeprom(sc, &data, 5, 1); 534 if ((data >> 8) == 1) 535 sc->revision = FXP_REV_82557; 536 else 537 sc->revision = pci_get_revid(dev); 538 539 /* 540 * Enable workarounds for certain chip revision deficiencies. 541 * 542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 543 * some systems based a normal 82559 design, have a defect where 544 * the chip can cause a PCI protocol violation if it receives 545 * a CU_RESUME command when it is entering the IDLE state. The 546 * workaround is to disable Dynamic Standby Mode, so the chip never 547 * deasserts CLKRUN#, and always remains in an active state. 548 * 549 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 550 */ 551 i = pci_get_device(dev); 552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 553 sc->revision >= FXP_REV_82559_A0) { 554 fxp_read_eeprom(sc, &data, 10, 1); 555 if (data & 0x02) { /* STB enable */ 556 u_int16_t cksum; 557 int i; 558 559 device_printf(dev, 560 "Disabling dynamic standby mode in EEPROM\n"); 561 data &= ~0x02; 562 fxp_write_eeprom(sc, &data, 10, 1); 563 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 564 cksum = 0; 565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 566 fxp_read_eeprom(sc, &data, i, 1); 567 cksum += data; 568 } 569 i = (1 << sc->eeprom_size) - 1; 570 cksum = 0xBABA - cksum; 571 fxp_read_eeprom(sc, &data, i, 1); 572 fxp_write_eeprom(sc, &cksum, i, 1); 573 device_printf(dev, 574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 575 i, data, cksum); 576 #if 1 577 /* 578 * If the user elects to continue, try the software 579 * workaround, as it is better than nothing. 580 */ 581 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 582 #endif 583 } 584 } 585 586 /* 587 * If we are not a 82557 chip, we can enable extended features. 588 */ 589 if (sc->revision != FXP_REV_82557) { 590 /* 591 * If MWI is enabled in the PCI configuration, and there 592 * is a valid cacheline size (8 or 16 dwords), then tell 593 * the board to turn on MWI. 594 */ 595 if (val & PCIM_CMD_MWRICEN && 596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 597 sc->flags |= FXP_FLAG_MWI_ENABLE; 598 599 /* turn on the extended TxCB feature */ 600 sc->flags |= FXP_FLAG_EXT_TXCB; 601 602 /* enable reception of long frames for VLAN */ 603 sc->flags |= FXP_FLAG_LONG_PKT_EN; 604 } 605 606 /* 607 * Read MAC address. 608 */ 609 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 610 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 611 device_printf(dev, "10Mbps\n"); 612 if (bootverbose) { 613 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 614 pci_get_vendor(dev), pci_get_device(dev), 615 pci_get_subvendor(dev), pci_get_subdevice(dev), 616 pci_get_revid(dev)); 617 fxp_read_eeprom(sc, &data, 10, 1); 618 device_printf(dev, "Dynamic Standby mode is %s\n", 619 data & 0x02 ? "enabled" : "disabled"); 620 } 621 622 /* 623 * If this is only a 10Mbps device, then there is no MII, and 624 * the PHY will use a serial interface instead. 625 * 626 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 627 * doesn't have a programming interface of any sort. The 628 * media is sensed automatically based on how the link partner 629 * is configured. This is, in essence, manual configuration. 630 */ 631 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 632 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 633 fxp_serial_ifmedia_sts); 634 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 635 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 636 } else { 637 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 638 fxp_ifmedia_sts)) { 639 device_printf(dev, "MII without any PHY!\n"); 640 error = ENXIO; 641 goto fail; 642 } 643 } 644 645 ifp = &sc->arpcom.ac_if; 646 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 647 ifp->if_baudrate = 100000000; 648 ifp->if_init = fxp_init; 649 ifp->if_softc = sc; 650 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 651 ifp->if_ioctl = fxp_ioctl; 652 ifp->if_start = fxp_start; 653 #ifdef DEVICE_POLLING 654 ifp->if_poll = fxp_poll; 655 #endif 656 ifp->if_watchdog = fxp_watchdog; 657 658 /* 659 * Attach the interface. 660 */ 661 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 662 663 /* 664 * Tell the upper layer(s) we support long frames. 665 */ 666 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 667 668 /* 669 * Let the system queue as many packets as we have available 670 * TX descriptors. 671 */ 672 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 673 ifq_set_ready(&ifp->if_snd); 674 675 error = bus_setup_intr(dev, sc->irq, 0, 676 fxp_intr, sc, &sc->ih, NULL); 677 if (error) { 678 ether_ifdetach(ifp); 679 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 680 ifmedia_removeall(&sc->sc_media); 681 device_printf(dev, "could not setup irq\n"); 682 goto fail; 683 } 684 685 return (0); 686 687 failmem: 688 device_printf(dev, "Failed to malloc memory\n"); 689 error = ENOMEM; 690 fail: 691 fxp_release(dev); 692 return (error); 693 } 694 695 /* 696 * release all resources 697 */ 698 static void 699 fxp_release(device_t dev) 700 { 701 struct fxp_softc *sc = device_get_softc(dev); 702 703 if (sc->miibus) 704 device_delete_child(dev, sc->miibus); 705 bus_generic_detach(dev); 706 707 if (sc->cbl_base) 708 free(sc->cbl_base, M_DEVBUF); 709 if (sc->fxp_stats) 710 free(sc->fxp_stats, M_DEVBUF); 711 if (sc->mcsp) 712 free(sc->mcsp, M_DEVBUF); 713 if (sc->rfa_headm) 714 m_freem(sc->rfa_headm); 715 716 if (sc->irq) 717 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 718 if (sc->mem) 719 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 720 721 sysctl_ctx_free(&sc->sysctl_ctx); 722 } 723 724 /* 725 * Detach interface. 726 */ 727 static int 728 fxp_detach(device_t dev) 729 { 730 struct fxp_softc *sc = device_get_softc(dev); 731 732 /* disable interrupts */ 733 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 734 735 crit_enter(); 736 737 /* 738 * Stop DMA and drop transmit queue. 739 */ 740 fxp_stop(sc); 741 742 /* 743 * Close down routes etc. 744 */ 745 ether_ifdetach(&sc->arpcom.ac_if); 746 747 /* 748 * Free all media structures. 749 */ 750 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 751 ifmedia_removeall(&sc->sc_media); 752 753 if (sc->ih) 754 bus_teardown_intr(dev, sc->irq, sc->ih); 755 756 crit_exit(); 757 758 /* Release our allocated resources. */ 759 fxp_release(dev); 760 761 return (0); 762 } 763 764 /* 765 * Device shutdown routine. Called at system shutdown after sync. The 766 * main purpose of this routine is to shut off receiver DMA so that 767 * kernel memory doesn't get clobbered during warmboot. 768 */ 769 static int 770 fxp_shutdown(device_t dev) 771 { 772 /* 773 * Make sure that DMA is disabled prior to reboot. Not doing 774 * do could allow DMA to corrupt kernel memory during the 775 * reboot before the driver initializes. 776 */ 777 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 778 return (0); 779 } 780 781 /* 782 * Device suspend routine. Stop the interface and save some PCI 783 * settings in case the BIOS doesn't restore them properly on 784 * resume. 785 */ 786 static int 787 fxp_suspend(device_t dev) 788 { 789 struct fxp_softc *sc = device_get_softc(dev); 790 int i; 791 792 crit_enter(); 793 794 fxp_stop(sc); 795 796 for (i = 0; i < 5; i++) 797 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 798 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 799 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 800 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 801 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 802 803 sc->suspended = 1; 804 805 crit_exit(); 806 return (0); 807 } 808 809 /* 810 * Device resume routine. Restore some PCI settings in case the BIOS 811 * doesn't, re-enable busmastering, and restart the interface if 812 * appropriate. 813 */ 814 static int 815 fxp_resume(device_t dev) 816 { 817 struct fxp_softc *sc = device_get_softc(dev); 818 struct ifnet *ifp = &sc->arpcom.ac_if; 819 int i; 820 821 crit_enter(); 822 823 fxp_powerstate_d0(dev); 824 825 /* better way to do this? */ 826 for (i = 0; i < 5; i++) 827 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 828 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 829 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 830 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 831 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 832 833 /* reenable busmastering and memory space */ 834 pci_enable_busmaster(dev); 835 pci_enable_io(dev, SYS_RES_MEMORY); 836 837 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 838 DELAY(10); 839 840 /* reinitialize interface if necessary */ 841 if (ifp->if_flags & IFF_UP) 842 fxp_init(sc); 843 844 sc->suspended = 0; 845 846 crit_exit(); 847 return (0); 848 } 849 850 static void 851 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 852 { 853 u_int16_t reg; 854 int x; 855 856 /* 857 * Shift in data. 858 */ 859 for (x = 1 << (length - 1); x; x >>= 1) { 860 if (data & x) 861 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 862 else 863 reg = FXP_EEPROM_EECS; 864 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 865 DELAY(1); 866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 867 DELAY(1); 868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 869 DELAY(1); 870 } 871 } 872 873 /* 874 * Read from the serial EEPROM. Basically, you manually shift in 875 * the read opcode (one bit at a time) and then shift in the address, 876 * and then you shift out the data (all of this one bit at a time). 877 * The word size is 16 bits, so you have to provide the address for 878 * every 16 bits of data. 879 */ 880 static u_int16_t 881 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 882 { 883 u_int16_t reg, data; 884 int x; 885 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 887 /* 888 * Shift in read opcode. 889 */ 890 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 891 /* 892 * Shift in address. 893 */ 894 data = 0; 895 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 896 if (offset & x) 897 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 898 else 899 reg = FXP_EEPROM_EECS; 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 901 DELAY(1); 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 903 DELAY(1); 904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 905 DELAY(1); 906 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 907 data++; 908 if (autosize && reg == 0) { 909 sc->eeprom_size = data; 910 break; 911 } 912 } 913 /* 914 * Shift out data. 915 */ 916 data = 0; 917 reg = FXP_EEPROM_EECS; 918 for (x = 1 << 15; x; x >>= 1) { 919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 920 DELAY(1); 921 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 922 data |= x; 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 924 DELAY(1); 925 } 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 927 DELAY(1); 928 929 return (data); 930 } 931 932 static void 933 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 934 { 935 int i; 936 937 /* 938 * Erase/write enable. 939 */ 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 941 fxp_eeprom_shiftin(sc, 0x4, 3); 942 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 944 DELAY(1); 945 /* 946 * Shift in write opcode, address, data. 947 */ 948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 949 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 950 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 951 fxp_eeprom_shiftin(sc, data, 16); 952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 953 DELAY(1); 954 /* 955 * Wait for EEPROM to finish up. 956 */ 957 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 958 DELAY(1); 959 for (i = 0; i < 1000; i++) { 960 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 961 break; 962 DELAY(50); 963 } 964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 965 DELAY(1); 966 /* 967 * Erase/write disable. 968 */ 969 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 970 fxp_eeprom_shiftin(sc, 0x4, 3); 971 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 973 DELAY(1); 974 } 975 976 /* 977 * From NetBSD: 978 * 979 * Figure out EEPROM size. 980 * 981 * 559's can have either 64-word or 256-word EEPROMs, the 558 982 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 983 * talks about the existance of 16 to 256 word EEPROMs. 984 * 985 * The only known sizes are 64 and 256, where the 256 version is used 986 * by CardBus cards to store CIS information. 987 * 988 * The address is shifted in msb-to-lsb, and after the last 989 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 990 * after which follows the actual data. We try to detect this zero, by 991 * probing the data-out bit in the EEPROM control register just after 992 * having shifted in a bit. If the bit is zero, we assume we've 993 * shifted enough address bits. The data-out should be tri-state, 994 * before this, which should translate to a logical one. 995 */ 996 static void 997 fxp_autosize_eeprom(struct fxp_softc *sc) 998 { 999 1000 /* guess maximum size of 256 words */ 1001 sc->eeprom_size = 8; 1002 1003 /* autosize */ 1004 (void) fxp_eeprom_getword(sc, 0, 1); 1005 } 1006 1007 static void 1008 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1009 { 1010 int i; 1011 1012 for (i = 0; i < words; i++) 1013 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1014 } 1015 1016 static void 1017 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1018 { 1019 int i; 1020 1021 for (i = 0; i < words; i++) 1022 fxp_eeprom_putword(sc, offset + i, data[i]); 1023 } 1024 1025 /* 1026 * Start packet transmission on the interface. 1027 */ 1028 static void 1029 fxp_start(struct ifnet *ifp) 1030 { 1031 struct fxp_softc *sc = ifp->if_softc; 1032 struct fxp_cb_tx *txp; 1033 1034 /* 1035 * See if we need to suspend xmit until the multicast filter 1036 * has been reprogrammed (which can only be done at the head 1037 * of the command chain). 1038 */ 1039 if (sc->need_mcsetup) { 1040 return; 1041 } 1042 1043 txp = NULL; 1044 1045 /* 1046 * We're finished if there is nothing more to add to the list or if 1047 * we're all filled up with buffers to transmit. 1048 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1049 * a NOP command when needed. 1050 */ 1051 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1052 struct mbuf *m, *mb_head; 1053 int segment, ntries = 0; 1054 1055 /* 1056 * Grab a packet to transmit. The packet is dequeued, 1057 * once we are sure that we have enough free descriptors. 1058 */ 1059 mb_head = ifq_poll(&ifp->if_snd); 1060 if (mb_head == NULL) 1061 break; 1062 1063 /* 1064 * Get pointer to next available tx desc. 1065 */ 1066 txp = sc->cbl_last->next; 1067 1068 /* 1069 * Go through each of the mbufs in the chain and initialize 1070 * the transmit buffer descriptors with the physical address 1071 * and size of the mbuf. 1072 */ 1073 tbdinit: 1074 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1075 if (m->m_len != 0) { 1076 if (segment == FXP_NTXSEG) 1077 break; 1078 txp->tbd[segment].tb_addr = 1079 vtophys(mtod(m, vm_offset_t)); 1080 txp->tbd[segment].tb_size = m->m_len; 1081 segment++; 1082 } 1083 } 1084 if (m != NULL) { 1085 struct mbuf *mn; 1086 1087 /* 1088 * We ran out of segments. We have to recopy this 1089 * mbuf chain first. Bail out if we can't get the 1090 * new buffers. 1091 */ 1092 if (ntries > 0) 1093 break; 1094 mn = m_dup(mb_head, MB_DONTWAIT); 1095 if (mn == NULL) 1096 break; 1097 /* We can transmit the packet, dequeue it. */ 1098 mb_head = ifq_dequeue(&ifp->if_snd); 1099 m_freem(mb_head); 1100 mb_head = mn; 1101 ntries = 1; 1102 goto tbdinit; 1103 } else { 1104 /* Nothing to worry about, just dequeue. */ 1105 mb_head = ifq_dequeue(&ifp->if_snd); 1106 } 1107 1108 txp->tbd_number = segment; 1109 txp->mb_head = mb_head; 1110 txp->cb_status = 0; 1111 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1112 txp->cb_command = 1113 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1114 FXP_CB_COMMAND_S; 1115 } else { 1116 txp->cb_command = 1117 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1118 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1119 /* 1120 * Set a 5 second timer just in case we don't hear 1121 * from the card again. 1122 */ 1123 ifp->if_timer = 5; 1124 } 1125 txp->tx_threshold = tx_threshold; 1126 1127 /* 1128 * Advance the end of list forward. 1129 */ 1130 1131 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1132 sc->cbl_last = txp; 1133 1134 /* 1135 * Advance the beginning of the list forward if there are 1136 * no other packets queued (when nothing is queued, cbl_first 1137 * sits on the last TxCB that was sent out). 1138 */ 1139 if (sc->tx_queued == 0) 1140 sc->cbl_first = txp; 1141 1142 sc->tx_queued++; 1143 1144 BPF_MTAP(ifp, mb_head); 1145 } 1146 1147 /* 1148 * We're finished. If we added to the list, issue a RESUME to get DMA 1149 * going again if suspended. 1150 */ 1151 if (txp != NULL) { 1152 fxp_scb_wait(sc); 1153 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1154 } 1155 } 1156 1157 #ifdef DEVICE_POLLING 1158 1159 static void 1160 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1161 { 1162 struct fxp_softc *sc = ifp->if_softc; 1163 u_int8_t statack; 1164 1165 switch(cmd) { 1166 case POLL_REGISTER: 1167 /* disable interrupts */ 1168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1169 break; 1170 case POLL_DEREGISTER: 1171 /* enable interrupts */ 1172 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1173 break; 1174 default: 1175 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1176 FXP_SCB_STATACK_FR; 1177 if (cmd == POLL_AND_CHECK_STATUS) { 1178 u_int8_t tmp; 1179 1180 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1181 if (tmp == 0xff || tmp == 0) 1182 return; /* nothing to do */ 1183 tmp &= ~statack; 1184 /* ack what we can */ 1185 if (tmp != 0) 1186 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1187 statack |= tmp; 1188 } 1189 fxp_intr_body(sc, statack, count); 1190 break; 1191 } 1192 } 1193 1194 #endif /* DEVICE_POLLING */ 1195 1196 /* 1197 * Process interface interrupts. 1198 */ 1199 static void 1200 fxp_intr(void *xsc) 1201 { 1202 struct fxp_softc *sc = xsc; 1203 u_int8_t statack; 1204 1205 if (sc->suspended) { 1206 return; 1207 } 1208 1209 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1210 /* 1211 * It should not be possible to have all bits set; the 1212 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1213 * all bits are set, this may indicate that the card has 1214 * been physically ejected, so ignore it. 1215 */ 1216 if (statack == 0xff) 1217 return; 1218 1219 /* 1220 * First ACK all the interrupts in this pass. 1221 */ 1222 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1223 fxp_intr_body(sc, statack, -1); 1224 } 1225 } 1226 1227 static void 1228 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1229 { 1230 struct ifnet *ifp = &sc->arpcom.ac_if; 1231 struct mbuf *m; 1232 struct fxp_rfa *rfa; 1233 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1234 1235 if (rnr) 1236 fxp_rnr++; 1237 #ifdef DEVICE_POLLING 1238 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1239 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1240 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1241 rnr = 1; 1242 } 1243 #endif 1244 1245 /* 1246 * Free any finished transmit mbuf chains. 1247 * 1248 * Handle the CNA event likt a CXTNO event. It used to 1249 * be that this event (control unit not ready) was not 1250 * encountered, but it is now with the SMPng modifications. 1251 * The exact sequence of events that occur when the interface 1252 * is brought up are different now, and if this event 1253 * goes unhandled, the configuration/rxfilter setup sequence 1254 * can stall for several seconds. The result is that no 1255 * packets go out onto the wire for about 5 to 10 seconds 1256 * after the interface is ifconfig'ed for the first time. 1257 */ 1258 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1259 struct fxp_cb_tx *txp; 1260 1261 for (txp = sc->cbl_first; sc->tx_queued && 1262 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1263 txp = txp->next) { 1264 if ((m = txp->mb_head) != NULL) { 1265 txp->mb_head = NULL; 1266 sc->tx_queued--; 1267 m_freem(m); 1268 } else { 1269 sc->tx_queued--; 1270 } 1271 } 1272 sc->cbl_first = txp; 1273 ifp->if_timer = 0; 1274 if (sc->tx_queued == 0) { 1275 if (sc->need_mcsetup) 1276 fxp_mc_setup(sc); 1277 } 1278 /* 1279 * Try to start more packets transmitting. 1280 */ 1281 if (!ifq_is_empty(&ifp->if_snd)) 1282 (*ifp->if_start)(ifp); 1283 } 1284 1285 /* 1286 * Just return if nothing happened on the receive side. 1287 */ 1288 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1289 return; 1290 1291 /* 1292 * Process receiver interrupts. If a no-resource (RNR) 1293 * condition exists, get whatever packets we can and 1294 * re-start the receiver. 1295 * 1296 * When using polling, we do not process the list to completion, 1297 * so when we get an RNR interrupt we must defer the restart 1298 * until we hit the last buffer with the C bit set. 1299 * If we run out of cycles and rfa_headm has the C bit set, 1300 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1301 * that the info will be used in the subsequent polling cycle. 1302 */ 1303 for (;;) { 1304 m = sc->rfa_headm; 1305 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1306 RFA_ALIGNMENT_FUDGE); 1307 1308 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1309 if (count >= 0 && count-- == 0) { 1310 if (rnr) { 1311 /* Defer RNR processing until the next time. */ 1312 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1313 rnr = 0; 1314 } 1315 break; 1316 } 1317 #endif /* DEVICE_POLLING */ 1318 1319 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1320 break; 1321 1322 /* 1323 * Remove first packet from the chain. 1324 */ 1325 sc->rfa_headm = m->m_next; 1326 m->m_next = NULL; 1327 1328 /* 1329 * Add a new buffer to the receive chain. 1330 * If this fails, the old buffer is recycled 1331 * instead. 1332 */ 1333 if (fxp_add_rfabuf(sc, m) == 0) { 1334 int total_len; 1335 1336 /* 1337 * Fetch packet length (the top 2 bits of 1338 * actual_size are flags set by the controller 1339 * upon completion), and drop the packet in case 1340 * of bogus length or CRC errors. 1341 */ 1342 total_len = rfa->actual_size & 0x3fff; 1343 if (total_len < sizeof(struct ether_header) || 1344 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1345 sizeof(struct fxp_rfa) || 1346 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1347 m_freem(m); 1348 continue; 1349 } 1350 m->m_pkthdr.len = m->m_len = total_len; 1351 (*ifp->if_input)(ifp, m); 1352 } 1353 } 1354 if (rnr) { 1355 fxp_scb_wait(sc); 1356 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1357 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1358 RFA_ALIGNMENT_FUDGE); 1359 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1360 } 1361 } 1362 1363 /* 1364 * Update packet in/out/collision statistics. The i82557 doesn't 1365 * allow you to access these counters without doing a fairly 1366 * expensive DMA to get _all_ of the statistics it maintains, so 1367 * we do this operation here only once per second. The statistics 1368 * counters in the kernel are updated from the previous dump-stats 1369 * DMA and then a new dump-stats DMA is started. The on-chip 1370 * counters are zeroed when the DMA completes. If we can't start 1371 * the DMA immediately, we don't wait - we just prepare to read 1372 * them again next time. 1373 */ 1374 static void 1375 fxp_tick(void *xsc) 1376 { 1377 struct fxp_softc *sc = xsc; 1378 struct ifnet *ifp = &sc->arpcom.ac_if; 1379 struct fxp_stats *sp = sc->fxp_stats; 1380 struct fxp_cb_tx *txp; 1381 struct mbuf *m; 1382 1383 ifp->if_opackets += sp->tx_good; 1384 ifp->if_collisions += sp->tx_total_collisions; 1385 if (sp->rx_good) { 1386 ifp->if_ipackets += sp->rx_good; 1387 sc->rx_idle_secs = 0; 1388 } else { 1389 /* 1390 * Receiver's been idle for another second. 1391 */ 1392 sc->rx_idle_secs++; 1393 } 1394 ifp->if_ierrors += 1395 sp->rx_crc_errors + 1396 sp->rx_alignment_errors + 1397 sp->rx_rnr_errors + 1398 sp->rx_overrun_errors; 1399 /* 1400 * If any transmit underruns occured, bump up the transmit 1401 * threshold by another 512 bytes (64 * 8). 1402 */ 1403 if (sp->tx_underruns) { 1404 ifp->if_oerrors += sp->tx_underruns; 1405 if (tx_threshold < 192) 1406 tx_threshold += 64; 1407 } 1408 1409 crit_enter(); 1410 1411 /* 1412 * Release any xmit buffers that have completed DMA. This isn't 1413 * strictly necessary to do here, but it's advantagous for mbufs 1414 * with external storage to be released in a timely manner rather 1415 * than being defered for a potentially long time. This limits 1416 * the delay to a maximum of one second. 1417 */ 1418 for (txp = sc->cbl_first; sc->tx_queued && 1419 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1420 txp = txp->next) { 1421 if ((m = txp->mb_head) != NULL) { 1422 txp->mb_head = NULL; 1423 sc->tx_queued--; 1424 m_freem(m); 1425 } else { 1426 sc->tx_queued--; 1427 } 1428 } 1429 sc->cbl_first = txp; 1430 /* 1431 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1432 * then assume the receiver has locked up and attempt to clear 1433 * the condition by reprogramming the multicast filter. This is 1434 * a work-around for a bug in the 82557 where the receiver locks 1435 * up if it gets certain types of garbage in the syncronization 1436 * bits prior to the packet header. This bug is supposed to only 1437 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1438 * mode as well (perhaps due to a 10/100 speed transition). 1439 */ 1440 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1441 sc->rx_idle_secs = 0; 1442 fxp_mc_setup(sc); 1443 } 1444 /* 1445 * If there is no pending command, start another stats 1446 * dump. Otherwise punt for now. 1447 */ 1448 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1449 /* 1450 * Start another stats dump. 1451 */ 1452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1453 } else { 1454 /* 1455 * A previous command is still waiting to be accepted. 1456 * Just zero our copy of the stats and wait for the 1457 * next timer event to update them. 1458 */ 1459 sp->tx_good = 0; 1460 sp->tx_underruns = 0; 1461 sp->tx_total_collisions = 0; 1462 1463 sp->rx_good = 0; 1464 sp->rx_crc_errors = 0; 1465 sp->rx_alignment_errors = 0; 1466 sp->rx_rnr_errors = 0; 1467 sp->rx_overrun_errors = 0; 1468 } 1469 if (sc->miibus != NULL) 1470 mii_tick(device_get_softc(sc->miibus)); 1471 /* 1472 * Schedule another timeout one second from now. 1473 */ 1474 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1475 1476 crit_exit(); 1477 } 1478 1479 /* 1480 * Stop the interface. Cancels the statistics updater and resets 1481 * the interface. 1482 */ 1483 static void 1484 fxp_stop(struct fxp_softc *sc) 1485 { 1486 struct ifnet *ifp = &sc->arpcom.ac_if; 1487 struct fxp_cb_tx *txp; 1488 int i; 1489 1490 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1491 ifp->if_timer = 0; 1492 1493 /* 1494 * Cancel stats updater. 1495 */ 1496 callout_stop(&sc->fxp_stat_timer); 1497 1498 /* 1499 * Issue software reset, which also unloads the microcode. 1500 */ 1501 sc->flags &= ~FXP_FLAG_UCODE; 1502 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1503 DELAY(50); 1504 1505 /* 1506 * Release any xmit buffers. 1507 */ 1508 txp = sc->cbl_base; 1509 if (txp != NULL) { 1510 for (i = 0; i < FXP_NTXCB; i++) { 1511 if (txp[i].mb_head != NULL) { 1512 m_freem(txp[i].mb_head); 1513 txp[i].mb_head = NULL; 1514 } 1515 } 1516 } 1517 sc->tx_queued = 0; 1518 1519 /* 1520 * Free all the receive buffers then reallocate/reinitialize 1521 */ 1522 if (sc->rfa_headm != NULL) 1523 m_freem(sc->rfa_headm); 1524 sc->rfa_headm = NULL; 1525 sc->rfa_tailm = NULL; 1526 for (i = 0; i < FXP_NRFABUFS; i++) { 1527 if (fxp_add_rfabuf(sc, NULL) != 0) { 1528 /* 1529 * This "can't happen" - we're at splimp() 1530 * and we just freed all the buffers we need 1531 * above. 1532 */ 1533 panic("fxp_stop: no buffers!"); 1534 } 1535 } 1536 } 1537 1538 /* 1539 * Watchdog/transmission transmit timeout handler. Called when a 1540 * transmission is started on the interface, but no interrupt is 1541 * received before the timeout. This usually indicates that the 1542 * card has wedged for some reason. 1543 */ 1544 static void 1545 fxp_watchdog(struct ifnet *ifp) 1546 { 1547 if_printf(ifp, "device timeout\n"); 1548 ifp->if_oerrors++; 1549 fxp_init(ifp->if_softc); 1550 } 1551 1552 static void 1553 fxp_init(void *xsc) 1554 { 1555 struct fxp_softc *sc = xsc; 1556 struct ifnet *ifp = &sc->arpcom.ac_if; 1557 struct fxp_cb_config *cbp; 1558 struct fxp_cb_ias *cb_ias; 1559 struct fxp_cb_tx *txp; 1560 struct fxp_cb_mcs *mcsp; 1561 int i, prm; 1562 1563 crit_enter(); 1564 1565 /* 1566 * Cancel any pending I/O 1567 */ 1568 fxp_stop(sc); 1569 1570 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1571 1572 /* 1573 * Initialize base of CBL and RFA memory. Loading with zero 1574 * sets it up for regular linear addressing. 1575 */ 1576 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1577 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1578 1579 fxp_scb_wait(sc); 1580 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1581 1582 /* 1583 * Initialize base of dump-stats buffer. 1584 */ 1585 fxp_scb_wait(sc); 1586 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1588 1589 /* 1590 * Attempt to load microcode if requested. 1591 */ 1592 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1593 fxp_load_ucode(sc); 1594 1595 /* 1596 * Initialize the multicast address list. 1597 */ 1598 if (fxp_mc_addrs(sc)) { 1599 mcsp = sc->mcsp; 1600 mcsp->cb_status = 0; 1601 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1602 mcsp->link_addr = -1; 1603 /* 1604 * Start the multicast setup command. 1605 */ 1606 fxp_scb_wait(sc); 1607 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1608 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1609 /* ...and wait for it to complete. */ 1610 fxp_dma_wait(&mcsp->cb_status, sc); 1611 } 1612 1613 /* 1614 * We temporarily use memory that contains the TxCB list to 1615 * construct the config CB. The TxCB list memory is rebuilt 1616 * later. 1617 */ 1618 cbp = (struct fxp_cb_config *) sc->cbl_base; 1619 1620 /* 1621 * This bcopy is kind of disgusting, but there are a bunch of must be 1622 * zero and must be one bits in this structure and this is the easiest 1623 * way to initialize them all to proper values. 1624 */ 1625 bcopy(fxp_cb_config_template, 1626 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1627 sizeof(fxp_cb_config_template)); 1628 1629 cbp->cb_status = 0; 1630 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1631 cbp->link_addr = -1; /* (no) next command */ 1632 cbp->byte_count = 22; /* (22) bytes to config */ 1633 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1634 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1635 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1636 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1637 cbp->type_enable = 0; /* actually reserved */ 1638 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1639 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1640 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1641 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1642 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1643 cbp->late_scb = 0; /* (don't) defer SCB update */ 1644 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1645 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1646 cbp->ci_int = 1; /* interrupt on CU idle */ 1647 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1648 cbp->ext_stats_dis = 1; /* disable extended counters */ 1649 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1650 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1651 cbp->disc_short_rx = !prm; /* discard short packets */ 1652 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1653 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1654 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1655 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1656 cbp->csma_dis = 0; /* (don't) disable link */ 1657 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1658 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1659 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1660 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1661 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1662 cbp->nsai = 1; /* (don't) disable source addr insert */ 1663 cbp->preamble_length = 2; /* (7 byte) preamble */ 1664 cbp->loopback = 0; /* (don't) loopback */ 1665 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1666 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1667 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1668 cbp->promiscuous = prm; /* promiscuous mode */ 1669 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1670 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1671 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1672 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1673 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1674 1675 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1676 cbp->padding = 1; /* (do) pad short tx packets */ 1677 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1678 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1679 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1680 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1681 /* must set wake_en in PMCSR also */ 1682 cbp->force_fdx = 0; /* (don't) force full duplex */ 1683 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1684 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1685 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1686 1687 if (sc->revision == FXP_REV_82557) { 1688 /* 1689 * The 82557 has no hardware flow control, the values 1690 * below are the defaults for the chip. 1691 */ 1692 cbp->fc_delay_lsb = 0; 1693 cbp->fc_delay_msb = 0x40; 1694 cbp->pri_fc_thresh = 3; 1695 cbp->tx_fc_dis = 0; 1696 cbp->rx_fc_restop = 0; 1697 cbp->rx_fc_restart = 0; 1698 cbp->fc_filter = 0; 1699 cbp->pri_fc_loc = 1; 1700 } else { 1701 cbp->fc_delay_lsb = 0x1f; 1702 cbp->fc_delay_msb = 0x01; 1703 cbp->pri_fc_thresh = 3; 1704 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1705 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1706 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1707 cbp->fc_filter = !prm; /* drop FC frames to host */ 1708 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1709 } 1710 1711 /* 1712 * Start the config command/DMA. 1713 */ 1714 fxp_scb_wait(sc); 1715 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1716 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1717 /* ...and wait for it to complete. */ 1718 fxp_dma_wait(&cbp->cb_status, sc); 1719 1720 /* 1721 * Now initialize the station address. Temporarily use the TxCB 1722 * memory area like we did above for the config CB. 1723 */ 1724 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1725 cb_ias->cb_status = 0; 1726 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1727 cb_ias->link_addr = -1; 1728 bcopy(sc->arpcom.ac_enaddr, 1729 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1730 sizeof(sc->arpcom.ac_enaddr)); 1731 1732 /* 1733 * Start the IAS (Individual Address Setup) command/DMA. 1734 */ 1735 fxp_scb_wait(sc); 1736 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1737 /* ...and wait for it to complete. */ 1738 fxp_dma_wait(&cb_ias->cb_status, sc); 1739 1740 /* 1741 * Initialize transmit control block (TxCB) list. 1742 */ 1743 1744 txp = sc->cbl_base; 1745 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1746 for (i = 0; i < FXP_NTXCB; i++) { 1747 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1748 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1749 txp[i].link_addr = 1750 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1751 if (sc->flags & FXP_FLAG_EXT_TXCB) 1752 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1753 else 1754 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1755 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1756 } 1757 /* 1758 * Set the suspend flag on the first TxCB and start the control 1759 * unit. It will execute the NOP and then suspend. 1760 */ 1761 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1762 sc->cbl_first = sc->cbl_last = txp; 1763 sc->tx_queued = 1; 1764 1765 fxp_scb_wait(sc); 1766 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1767 1768 /* 1769 * Initialize receiver buffer area - RFA. 1770 */ 1771 fxp_scb_wait(sc); 1772 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1773 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1774 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1775 1776 /* 1777 * Set current media. 1778 */ 1779 if (sc->miibus != NULL) 1780 mii_mediachg(device_get_softc(sc->miibus)); 1781 1782 ifp->if_flags |= IFF_RUNNING; 1783 ifp->if_flags &= ~IFF_OACTIVE; 1784 1785 /* 1786 * Enable interrupts. 1787 */ 1788 #ifdef DEVICE_POLLING 1789 /* 1790 * ... but only do that if we are not polling. And because (presumably) 1791 * the default is interrupts on, we need to disable them explicitly! 1792 */ 1793 if ( ifp->if_flags & IFF_POLLING ) 1794 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1795 else 1796 #endif /* DEVICE_POLLING */ 1797 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1798 1799 /* 1800 * Start stats updater. 1801 */ 1802 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1803 1804 crit_exit(); 1805 } 1806 1807 static int 1808 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1809 { 1810 1811 return (0); 1812 } 1813 1814 static void 1815 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1816 { 1817 1818 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1819 } 1820 1821 /* 1822 * Change media according to request. 1823 */ 1824 static int 1825 fxp_ifmedia_upd(struct ifnet *ifp) 1826 { 1827 struct fxp_softc *sc = ifp->if_softc; 1828 struct mii_data *mii; 1829 1830 mii = device_get_softc(sc->miibus); 1831 mii_mediachg(mii); 1832 return (0); 1833 } 1834 1835 /* 1836 * Notify the world which media we're using. 1837 */ 1838 static void 1839 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1840 { 1841 struct fxp_softc *sc = ifp->if_softc; 1842 struct mii_data *mii; 1843 1844 mii = device_get_softc(sc->miibus); 1845 mii_pollstat(mii); 1846 ifmr->ifm_active = mii->mii_media_active; 1847 ifmr->ifm_status = mii->mii_media_status; 1848 1849 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1850 sc->cu_resume_bug = 1; 1851 else 1852 sc->cu_resume_bug = 0; 1853 } 1854 1855 /* 1856 * Add a buffer to the end of the RFA buffer list. 1857 * Return 0 if successful, 1 for failure. A failure results in 1858 * adding the 'oldm' (if non-NULL) on to the end of the list - 1859 * tossing out its old contents and recycling it. 1860 * The RFA struct is stuck at the beginning of mbuf cluster and the 1861 * data pointer is fixed up to point just past it. 1862 */ 1863 static int 1864 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1865 { 1866 u_int32_t v; 1867 struct mbuf *m; 1868 struct fxp_rfa *rfa, *p_rfa; 1869 1870 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1871 if (m == NULL) { /* try to recycle the old mbuf instead */ 1872 if (oldm == NULL) 1873 return 1; 1874 m = oldm; 1875 m->m_data = m->m_ext.ext_buf; 1876 } 1877 1878 /* 1879 * Move the data pointer up so that the incoming data packet 1880 * will be 32-bit aligned. 1881 */ 1882 m->m_data += RFA_ALIGNMENT_FUDGE; 1883 1884 /* 1885 * Get a pointer to the base of the mbuf cluster and move 1886 * data start past it. 1887 */ 1888 rfa = mtod(m, struct fxp_rfa *); 1889 m->m_data += sizeof(struct fxp_rfa); 1890 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1891 1892 /* 1893 * Initialize the rest of the RFA. Note that since the RFA 1894 * is misaligned, we cannot store values directly. Instead, 1895 * we use an optimized, inline copy. 1896 */ 1897 1898 rfa->rfa_status = 0; 1899 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1900 rfa->actual_size = 0; 1901 1902 v = -1; 1903 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1904 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1905 1906 /* 1907 * If there are other buffers already on the list, attach this 1908 * one to the end by fixing up the tail to point to this one. 1909 */ 1910 if (sc->rfa_headm != NULL) { 1911 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1912 RFA_ALIGNMENT_FUDGE); 1913 sc->rfa_tailm->m_next = m; 1914 v = vtophys(rfa); 1915 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1916 p_rfa->rfa_control = 0; 1917 } else { 1918 sc->rfa_headm = m; 1919 } 1920 sc->rfa_tailm = m; 1921 1922 return (m == oldm); 1923 } 1924 1925 static volatile int 1926 fxp_miibus_readreg(device_t dev, int phy, int reg) 1927 { 1928 struct fxp_softc *sc = device_get_softc(dev); 1929 int count = 10000; 1930 int value; 1931 1932 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1933 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1934 1935 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1936 && count--) 1937 DELAY(10); 1938 1939 if (count <= 0) 1940 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1941 1942 return (value & 0xffff); 1943 } 1944 1945 static void 1946 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1947 { 1948 struct fxp_softc *sc = device_get_softc(dev); 1949 int count = 10000; 1950 1951 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1952 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1953 (value & 0xffff)); 1954 1955 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1956 count--) 1957 DELAY(10); 1958 1959 if (count <= 0) 1960 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1961 } 1962 1963 static int 1964 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1965 { 1966 struct fxp_softc *sc = ifp->if_softc; 1967 struct ifreq *ifr = (struct ifreq *)data; 1968 struct mii_data *mii; 1969 int error = 0; 1970 1971 crit_enter(); 1972 1973 switch (command) { 1974 1975 case SIOCSIFFLAGS: 1976 if (ifp->if_flags & IFF_ALLMULTI) 1977 sc->flags |= FXP_FLAG_ALL_MCAST; 1978 else 1979 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1980 1981 /* 1982 * If interface is marked up and not running, then start it. 1983 * If it is marked down and running, stop it. 1984 * XXX If it's up then re-initialize it. This is so flags 1985 * such as IFF_PROMISC are handled. 1986 */ 1987 if (ifp->if_flags & IFF_UP) { 1988 fxp_init(sc); 1989 } else { 1990 if (ifp->if_flags & IFF_RUNNING) 1991 fxp_stop(sc); 1992 } 1993 break; 1994 1995 case SIOCADDMULTI: 1996 case SIOCDELMULTI: 1997 if (ifp->if_flags & IFF_ALLMULTI) 1998 sc->flags |= FXP_FLAG_ALL_MCAST; 1999 else 2000 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2001 /* 2002 * Multicast list has changed; set the hardware filter 2003 * accordingly. 2004 */ 2005 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2006 fxp_mc_setup(sc); 2007 /* 2008 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2009 * again rather than else {}. 2010 */ 2011 if (sc->flags & FXP_FLAG_ALL_MCAST) 2012 fxp_init(sc); 2013 error = 0; 2014 break; 2015 2016 case SIOCSIFMEDIA: 2017 case SIOCGIFMEDIA: 2018 if (sc->miibus != NULL) { 2019 mii = device_get_softc(sc->miibus); 2020 error = ifmedia_ioctl(ifp, ifr, 2021 &mii->mii_media, command); 2022 } else { 2023 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2024 } 2025 break; 2026 2027 default: 2028 error = ether_ioctl(ifp, command, data); 2029 break; 2030 } 2031 2032 crit_exit(); 2033 2034 return (error); 2035 } 2036 2037 /* 2038 * Fill in the multicast address list and return number of entries. 2039 */ 2040 static int 2041 fxp_mc_addrs(struct fxp_softc *sc) 2042 { 2043 struct fxp_cb_mcs *mcsp = sc->mcsp; 2044 struct ifnet *ifp = &sc->arpcom.ac_if; 2045 struct ifmultiaddr *ifma; 2046 int nmcasts; 2047 2048 nmcasts = 0; 2049 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2050 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2051 if (ifma->ifma_addr->sa_family != AF_LINK) 2052 continue; 2053 if (nmcasts >= MAXMCADDR) { 2054 sc->flags |= FXP_FLAG_ALL_MCAST; 2055 nmcasts = 0; 2056 break; 2057 } 2058 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2059 (void *)(uintptr_t)(volatile void *) 2060 &sc->mcsp->mc_addr[nmcasts][0], 6); 2061 nmcasts++; 2062 } 2063 } 2064 mcsp->mc_cnt = nmcasts * 6; 2065 return (nmcasts); 2066 } 2067 2068 /* 2069 * Program the multicast filter. 2070 * 2071 * We have an artificial restriction that the multicast setup command 2072 * must be the first command in the chain, so we take steps to ensure 2073 * this. By requiring this, it allows us to keep up the performance of 2074 * the pre-initialized command ring (esp. link pointers) by not actually 2075 * inserting the mcsetup command in the ring - i.e. its link pointer 2076 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2077 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2078 * lead into the regular TxCB ring when it completes. 2079 * 2080 * This function must be called at splimp. 2081 */ 2082 static void 2083 fxp_mc_setup(struct fxp_softc *sc) 2084 { 2085 struct fxp_cb_mcs *mcsp = sc->mcsp; 2086 struct ifnet *ifp = &sc->arpcom.ac_if; 2087 int count; 2088 2089 /* 2090 * If there are queued commands, we must wait until they are all 2091 * completed. If we are already waiting, then add a NOP command 2092 * with interrupt option so that we're notified when all commands 2093 * have been completed - fxp_start() ensures that no additional 2094 * TX commands will be added when need_mcsetup is true. 2095 */ 2096 if (sc->tx_queued) { 2097 struct fxp_cb_tx *txp; 2098 2099 /* 2100 * need_mcsetup will be true if we are already waiting for the 2101 * NOP command to be completed (see below). In this case, bail. 2102 */ 2103 if (sc->need_mcsetup) 2104 return; 2105 sc->need_mcsetup = 1; 2106 2107 /* 2108 * Add a NOP command with interrupt so that we are notified 2109 * when all TX commands have been processed. 2110 */ 2111 txp = sc->cbl_last->next; 2112 txp->mb_head = NULL; 2113 txp->cb_status = 0; 2114 txp->cb_command = FXP_CB_COMMAND_NOP | 2115 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2116 /* 2117 * Advance the end of list forward. 2118 */ 2119 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2120 sc->cbl_last = txp; 2121 sc->tx_queued++; 2122 /* 2123 * Issue a resume in case the CU has just suspended. 2124 */ 2125 fxp_scb_wait(sc); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2127 /* 2128 * Set a 5 second timer just in case we don't hear from the 2129 * card again. 2130 */ 2131 ifp->if_timer = 5; 2132 2133 return; 2134 } 2135 sc->need_mcsetup = 0; 2136 2137 /* 2138 * Initialize multicast setup descriptor. 2139 */ 2140 mcsp->next = sc->cbl_base; 2141 mcsp->mb_head = NULL; 2142 mcsp->cb_status = 0; 2143 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2144 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2145 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2146 (void) fxp_mc_addrs(sc); 2147 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2148 sc->tx_queued = 1; 2149 2150 /* 2151 * Wait until command unit is not active. This should never 2152 * be the case when nothing is queued, but make sure anyway. 2153 */ 2154 count = 100; 2155 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2156 FXP_SCB_CUS_ACTIVE && --count) 2157 DELAY(10); 2158 if (count == 0) { 2159 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2160 return; 2161 } 2162 2163 /* 2164 * Start the multicast setup command. 2165 */ 2166 fxp_scb_wait(sc); 2167 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2169 2170 ifp->if_timer = 2; 2171 return; 2172 } 2173 2174 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2175 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2176 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2177 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2178 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2179 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2180 2181 #define UCODE(x) x, sizeof(x) 2182 2183 struct ucode { 2184 u_int32_t revision; 2185 u_int32_t *ucode; 2186 int length; 2187 u_short int_delay_offset; 2188 u_short bundle_max_offset; 2189 } ucode_table[] = { 2190 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2191 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2192 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2193 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2194 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2195 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2196 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2197 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2198 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2199 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { 0, NULL, 0, 0, 0 } 2201 }; 2202 2203 static void 2204 fxp_load_ucode(struct fxp_softc *sc) 2205 { 2206 struct ucode *uc; 2207 struct fxp_cb_ucode *cbp; 2208 2209 for (uc = ucode_table; uc->ucode != NULL; uc++) 2210 if (sc->revision == uc->revision) 2211 break; 2212 if (uc->ucode == NULL) 2213 return; 2214 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2215 cbp->cb_status = 0; 2216 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2217 cbp->link_addr = -1; /* (no) next command */ 2218 memcpy(cbp->ucode, uc->ucode, uc->length); 2219 if (uc->int_delay_offset) 2220 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2221 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2222 if (uc->bundle_max_offset) 2223 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2224 sc->tunable_bundle_max; 2225 /* 2226 * Download the ucode to the chip. 2227 */ 2228 fxp_scb_wait(sc); 2229 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2230 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2231 /* ...and wait for it to complete. */ 2232 fxp_dma_wait(&cbp->cb_status, sc); 2233 if_printf(&sc->arpcom.ac_if, 2234 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2235 sc->tunable_int_delay, 2236 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2237 sc->flags |= FXP_FLAG_UCODE; 2238 } 2239 2240 static int 2241 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2242 { 2243 int error, value; 2244 2245 value = *(int *)arg1; 2246 error = sysctl_handle_int(oidp, &value, 0, req); 2247 if (error || !req->newptr) 2248 return (error); 2249 if (value < low || value > high) 2250 return (EINVAL); 2251 *(int *)arg1 = value; 2252 return (0); 2253 } 2254 2255 /* 2256 * Interrupt delay is expressed in microseconds, a multiplier is used 2257 * to convert this to the appropriate clock ticks before using. 2258 */ 2259 static int 2260 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2261 { 2262 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2263 } 2264 2265 static int 2266 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2267 { 2268 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2269 } 2270