1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.13 2004/07/02 17:42:17 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 168 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 169 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 170 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 171 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 173 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 174 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 175 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 176 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 178 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 179 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 180 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 182 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 183 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 184 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 185 { 0, -1, NULL }, 186 }; 187 188 static int fxp_probe(device_t dev); 189 static int fxp_attach(device_t dev); 190 static int fxp_detach(device_t dev); 191 static int fxp_shutdown(device_t dev); 192 static int fxp_suspend(device_t dev); 193 static int fxp_resume(device_t dev); 194 195 static void fxp_intr(void *xsc); 196 static void fxp_intr_body(struct fxp_softc *sc, 197 u_int8_t statack, int count); 198 199 static void fxp_init(void *xsc); 200 static void fxp_tick(void *xsc); 201 static void fxp_powerstate_d0(device_t dev); 202 static void fxp_start(struct ifnet *ifp); 203 static void fxp_stop(struct fxp_softc *sc); 204 static void fxp_release(struct fxp_softc *sc); 205 static int fxp_ioctl(struct ifnet *ifp, u_long command, 206 caddr_t data, struct ucred *); 207 static void fxp_watchdog(struct ifnet *ifp); 208 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 209 static int fxp_mc_addrs(struct fxp_softc *sc); 210 static void fxp_mc_setup(struct fxp_softc *sc); 211 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 212 int autosize); 213 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 214 u_int16_t data); 215 static void fxp_autosize_eeprom(struct fxp_softc *sc); 216 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 217 int offset, int words); 218 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 219 int offset, int words); 220 static int fxp_ifmedia_upd(struct ifnet *ifp); 221 static void fxp_ifmedia_sts(struct ifnet *ifp, 222 struct ifmediareq *ifmr); 223 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 224 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 225 struct ifmediareq *ifmr); 226 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 227 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 228 int value); 229 static void fxp_load_ucode(struct fxp_softc *sc); 230 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 231 int low, int high); 232 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 233 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 234 static __inline void fxp_lwcopy(volatile u_int32_t *src, 235 volatile u_int32_t *dst); 236 static __inline void fxp_scb_wait(struct fxp_softc *sc); 237 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 238 static __inline void fxp_dma_wait(volatile u_int16_t *status, 239 struct fxp_softc *sc); 240 241 static device_method_t fxp_methods[] = { 242 /* Device interface */ 243 DEVMETHOD(device_probe, fxp_probe), 244 DEVMETHOD(device_attach, fxp_attach), 245 DEVMETHOD(device_detach, fxp_detach), 246 DEVMETHOD(device_shutdown, fxp_shutdown), 247 DEVMETHOD(device_suspend, fxp_suspend), 248 DEVMETHOD(device_resume, fxp_resume), 249 250 /* MII interface */ 251 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 252 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 253 254 { 0, 0 } 255 }; 256 257 static driver_t fxp_driver = { 258 "fxp", 259 fxp_methods, 260 sizeof(struct fxp_softc), 261 }; 262 263 static devclass_t fxp_devclass; 264 265 DECLARE_DUMMY_MODULE(if_fxp); 266 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 267 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 268 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 269 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 270 271 static int fxp_rnr; 272 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 273 274 /* 275 * Inline function to copy a 16-bit aligned 32-bit quantity. 276 */ 277 static __inline void 278 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 279 { 280 #ifdef __i386__ 281 *dst = *src; 282 #else 283 volatile u_int16_t *a = (volatile u_int16_t *)src; 284 volatile u_int16_t *b = (volatile u_int16_t *)dst; 285 286 b[0] = a[0]; 287 b[1] = a[1]; 288 #endif 289 } 290 291 /* 292 * Wait for the previous command to be accepted (but not necessarily 293 * completed). 294 */ 295 static __inline void 296 fxp_scb_wait(struct fxp_softc *sc) 297 { 298 int i = 10000; 299 300 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 301 DELAY(2); 302 if (i == 0) 303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 307 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 308 } 309 310 static __inline void 311 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 312 { 313 314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 316 fxp_scb_wait(sc); 317 } 318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 319 } 320 321 static __inline void 322 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 323 { 324 int i = 10000; 325 326 while (!(*status & FXP_CB_STATUS_C) && --i) 327 DELAY(2); 328 if (i == 0) 329 device_printf(sc->dev, "DMA timeout\n"); 330 } 331 332 /* 333 * Return identification string if this is device is ours. 334 */ 335 static int 336 fxp_probe(device_t dev) 337 { 338 u_int16_t devid; 339 u_int8_t revid; 340 struct fxp_ident *ident; 341 342 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 343 devid = pci_get_device(dev); 344 revid = pci_get_revid(dev); 345 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 346 if (ident->devid == devid && 347 (ident->revid == revid || ident->revid == -1)) { 348 device_set_desc(dev, ident->name); 349 return (0); 350 } 351 } 352 } 353 return (ENXIO); 354 } 355 356 static void 357 fxp_powerstate_d0(device_t dev) 358 { 359 #if defined(__DragonFly__) || __FreeBSD_version >= 430002 360 u_int32_t iobase, membase, irq; 361 362 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 363 /* Save important PCI config data. */ 364 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 365 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 366 irq = pci_read_config(dev, PCIR_INTLINE, 4); 367 368 /* Reset the power state. */ 369 device_printf(dev, "chip is in D%d power mode " 370 "-- setting to D0\n", pci_get_powerstate(dev)); 371 372 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 373 374 /* Restore PCI config data. */ 375 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 376 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 377 pci_write_config(dev, PCIR_INTLINE, irq, 4); 378 } 379 #endif 380 } 381 382 static int 383 fxp_attach(device_t dev) 384 { 385 int error = 0; 386 struct fxp_softc *sc = device_get_softc(dev); 387 struct ifnet *ifp; 388 u_int32_t val; 389 u_int16_t data; 390 int i, rid, m1, m2, prefer_iomap; 391 int s; 392 393 bzero(sc, sizeof(*sc)); 394 sc->dev = dev; 395 callout_handle_init(&sc->stat_ch); 396 sysctl_ctx_init(&sc->sysctl_ctx); 397 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 398 399 s = splimp(); 400 401 /* 402 * Enable bus mastering. Enable memory space too, in case 403 * BIOS/Prom forgot about it. 404 */ 405 val = pci_read_config(dev, PCIR_COMMAND, 2); 406 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 407 pci_write_config(dev, PCIR_COMMAND, val, 2); 408 val = pci_read_config(dev, PCIR_COMMAND, 2); 409 410 fxp_powerstate_d0(dev); 411 412 /* 413 * Figure out which we should try first - memory mapping or i/o mapping? 414 * We default to memory mapping. Then we accept an override from the 415 * command line. Then we check to see which one is enabled. 416 */ 417 m1 = PCIM_CMD_MEMEN; 418 m2 = PCIM_CMD_PORTEN; 419 prefer_iomap = 0; 420 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 421 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 422 m1 = PCIM_CMD_PORTEN; 423 m2 = PCIM_CMD_MEMEN; 424 } 425 426 if (val & m1) { 427 sc->rtp = 428 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 429 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 430 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 431 0, ~0, 1, RF_ACTIVE); 432 } 433 if (sc->mem == NULL && (val & m2)) { 434 sc->rtp = 435 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 436 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 437 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 438 0, ~0, 1, RF_ACTIVE); 439 } 440 441 if (!sc->mem) { 442 device_printf(dev, "could not map device registers\n"); 443 error = ENXIO; 444 goto fail; 445 } 446 if (bootverbose) { 447 device_printf(dev, "using %s space register mapping\n", 448 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 449 } 450 451 sc->sc_st = rman_get_bustag(sc->mem); 452 sc->sc_sh = rman_get_bushandle(sc->mem); 453 454 /* 455 * Allocate our interrupt. 456 */ 457 rid = 0; 458 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 459 RF_SHAREABLE | RF_ACTIVE); 460 if (sc->irq == NULL) { 461 device_printf(dev, "could not map interrupt\n"); 462 error = ENXIO; 463 goto fail; 464 } 465 466 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 467 fxp_intr, sc, &sc->ih); 468 if (error) { 469 device_printf(dev, "could not setup irq\n"); 470 goto fail; 471 } 472 473 /* 474 * Reset to a stable state. 475 */ 476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 477 DELAY(10); 478 479 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 480 M_DEVBUF, M_WAITOK | M_ZERO); 481 482 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 483 M_WAITOK | M_ZERO); 484 485 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 486 487 /* 488 * Pre-allocate our receive buffers. 489 */ 490 for (i = 0; i < FXP_NRFABUFS; i++) { 491 if (fxp_add_rfabuf(sc, NULL) != 0) { 492 goto failmem; 493 } 494 } 495 496 /* 497 * Find out how large of an SEEPROM we have. 498 */ 499 fxp_autosize_eeprom(sc); 500 501 /* 502 * Determine whether we must use the 503 serial interface. 503 */ 504 fxp_read_eeprom(sc, &data, 6, 1); 505 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 506 (data & FXP_PHY_SERIAL_ONLY)) 507 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 508 509 /* 510 * Create the sysctl tree 511 */ 512 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 513 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 514 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 515 if (sc->sysctl_tree == NULL) 516 goto fail; 517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 518 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 519 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 520 "FXP driver receive interrupt microcode bundling delay"); 521 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 522 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 523 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 524 "FXP driver receive interrupt microcode bundle size limit"); 525 526 /* 527 * Pull in device tunables. 528 */ 529 sc->tunable_int_delay = TUNABLE_INT_DELAY; 530 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "int_delay", &sc->tunable_int_delay); 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "bundle_max", &sc->tunable_bundle_max); 535 536 /* 537 * Find out the chip revision; lump all 82557 revs together. 538 */ 539 fxp_read_eeprom(sc, &data, 5, 1); 540 if ((data >> 8) == 1) 541 sc->revision = FXP_REV_82557; 542 else 543 sc->revision = pci_get_revid(dev); 544 545 /* 546 * Enable workarounds for certain chip revision deficiencies. 547 * 548 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 549 * some systems based a normal 82559 design, have a defect where 550 * the chip can cause a PCI protocol violation if it receives 551 * a CU_RESUME command when it is entering the IDLE state. The 552 * workaround is to disable Dynamic Standby Mode, so the chip never 553 * deasserts CLKRUN#, and always remains in an active state. 554 * 555 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 556 */ 557 i = pci_get_device(dev); 558 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 559 sc->revision >= FXP_REV_82559_A0) { 560 fxp_read_eeprom(sc, &data, 10, 1); 561 if (data & 0x02) { /* STB enable */ 562 u_int16_t cksum; 563 int i; 564 565 device_printf(dev, 566 "Disabling dynamic standby mode in EEPROM\n"); 567 data &= ~0x02; 568 fxp_write_eeprom(sc, &data, 10, 1); 569 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 570 cksum = 0; 571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 572 fxp_read_eeprom(sc, &data, i, 1); 573 cksum += data; 574 } 575 i = (1 << sc->eeprom_size) - 1; 576 cksum = 0xBABA - cksum; 577 fxp_read_eeprom(sc, &data, i, 1); 578 fxp_write_eeprom(sc, &cksum, i, 1); 579 device_printf(dev, 580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 581 i, data, cksum); 582 #if 1 583 /* 584 * If the user elects to continue, try the software 585 * workaround, as it is better than nothing. 586 */ 587 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 588 #endif 589 } 590 } 591 592 /* 593 * If we are not a 82557 chip, we can enable extended features. 594 */ 595 if (sc->revision != FXP_REV_82557) { 596 /* 597 * If MWI is enabled in the PCI configuration, and there 598 * is a valid cacheline size (8 or 16 dwords), then tell 599 * the board to turn on MWI. 600 */ 601 if (val & PCIM_CMD_MWRICEN && 602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 603 sc->flags |= FXP_FLAG_MWI_ENABLE; 604 605 /* turn on the extended TxCB feature */ 606 sc->flags |= FXP_FLAG_EXT_TXCB; 607 608 /* enable reception of long frames for VLAN */ 609 sc->flags |= FXP_FLAG_LONG_PKT_EN; 610 } 611 612 /* 613 * Read MAC address. 614 */ 615 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 616 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 617 device_printf(dev, "10Mbps"); 618 if (bootverbose) { 619 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 620 pci_get_vendor(dev), pci_get_device(dev), 621 pci_get_subvendor(dev), pci_get_subdevice(dev), 622 pci_get_revid(dev)); 623 fxp_read_eeprom(sc, &data, 10, 1); 624 device_printf(dev, "Dynamic Standby mode is %s\n", 625 data & 0x02 ? "enabled" : "disabled"); 626 } 627 628 /* 629 * If this is only a 10Mbps device, then there is no MII, and 630 * the PHY will use a serial interface instead. 631 * 632 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 633 * doesn't have a programming interface of any sort. The 634 * media is sensed automatically based on how the link partner 635 * is configured. This is, in essence, manual configuration. 636 */ 637 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 638 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 639 fxp_serial_ifmedia_sts); 640 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 641 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 642 } else { 643 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 644 fxp_ifmedia_sts)) { 645 device_printf(dev, "MII without any PHY!\n"); 646 error = ENXIO; 647 goto fail; 648 } 649 } 650 651 ifp = &sc->arpcom.ac_if; 652 if_initname(ifp, "fxp", device_get_unit(dev)); 653 ifp->if_output = ether_output; 654 ifp->if_baudrate = 100000000; 655 ifp->if_init = fxp_init; 656 ifp->if_softc = sc; 657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658 ifp->if_ioctl = fxp_ioctl; 659 ifp->if_start = fxp_start; 660 ifp->if_watchdog = fxp_watchdog; 661 662 /* 663 * Attach the interface. 664 */ 665 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 666 667 /* 668 * Tell the upper layer(s) we support long frames. 669 */ 670 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 671 672 /* 673 * Let the system queue as many packets as we have available 674 * TX descriptors. 675 */ 676 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 677 678 splx(s); 679 return (0); 680 681 failmem: 682 device_printf(dev, "Failed to malloc memory\n"); 683 error = ENOMEM; 684 fail: 685 splx(s); 686 fxp_release(sc); 687 return (error); 688 } 689 690 /* 691 * release all resources 692 */ 693 static void 694 fxp_release(struct fxp_softc *sc) 695 { 696 697 bus_generic_detach(sc->dev); 698 if (sc->miibus) 699 device_delete_child(sc->dev, sc->miibus); 700 701 if (sc->cbl_base) 702 free(sc->cbl_base, M_DEVBUF); 703 if (sc->fxp_stats) 704 free(sc->fxp_stats, M_DEVBUF); 705 if (sc->mcsp) 706 free(sc->mcsp, M_DEVBUF); 707 if (sc->rfa_headm) 708 m_freem(sc->rfa_headm); 709 710 if (sc->ih) 711 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 712 if (sc->irq) 713 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 714 if (sc->mem) 715 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 716 717 sysctl_ctx_free(&sc->sysctl_ctx); 718 719 mtx_destroy(&sc->sc_mtx); 720 } 721 722 /* 723 * Detach interface. 724 */ 725 static int 726 fxp_detach(device_t dev) 727 { 728 struct fxp_softc *sc = device_get_softc(dev); 729 int s; 730 731 /* disable interrupts */ 732 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 733 734 s = splimp(); 735 736 /* 737 * Stop DMA and drop transmit queue. 738 */ 739 fxp_stop(sc); 740 741 /* 742 * Close down routes etc. 743 */ 744 ether_ifdetach(&sc->arpcom.ac_if); 745 746 /* 747 * Free all media structures. 748 */ 749 ifmedia_removeall(&sc->sc_media); 750 751 splx(s); 752 753 /* Release our allocated resources. */ 754 fxp_release(sc); 755 756 return (0); 757 } 758 759 /* 760 * Device shutdown routine. Called at system shutdown after sync. The 761 * main purpose of this routine is to shut off receiver DMA so that 762 * kernel memory doesn't get clobbered during warmboot. 763 */ 764 static int 765 fxp_shutdown(device_t dev) 766 { 767 /* 768 * Make sure that DMA is disabled prior to reboot. Not doing 769 * do could allow DMA to corrupt kernel memory during the 770 * reboot before the driver initializes. 771 */ 772 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 773 return (0); 774 } 775 776 /* 777 * Device suspend routine. Stop the interface and save some PCI 778 * settings in case the BIOS doesn't restore them properly on 779 * resume. 780 */ 781 static int 782 fxp_suspend(device_t dev) 783 { 784 struct fxp_softc *sc = device_get_softc(dev); 785 int i, s; 786 787 s = splimp(); 788 789 fxp_stop(sc); 790 791 for (i = 0; i < 5; i++) 792 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 793 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 794 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 795 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 796 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 797 798 sc->suspended = 1; 799 800 splx(s); 801 return (0); 802 } 803 804 /* 805 * Device resume routine. Restore some PCI settings in case the BIOS 806 * doesn't, re-enable busmastering, and restart the interface if 807 * appropriate. 808 */ 809 static int 810 fxp_resume(device_t dev) 811 { 812 struct fxp_softc *sc = device_get_softc(dev); 813 struct ifnet *ifp = &sc->sc_if; 814 u_int16_t pci_command; 815 int i, s; 816 817 s = splimp(); 818 819 fxp_powerstate_d0(dev); 820 821 /* better way to do this? */ 822 for (i = 0; i < 5; i++) 823 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 824 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 825 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 826 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 827 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 828 829 /* reenable busmastering */ 830 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 831 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 832 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 833 834 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 835 DELAY(10); 836 837 /* reinitialize interface if necessary */ 838 if (ifp->if_flags & IFF_UP) 839 fxp_init(sc); 840 841 sc->suspended = 0; 842 843 splx(s); 844 return (0); 845 } 846 847 static void 848 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 849 { 850 u_int16_t reg; 851 int x; 852 853 /* 854 * Shift in data. 855 */ 856 for (x = 1 << (length - 1); x; x >>= 1) { 857 if (data & x) 858 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 859 else 860 reg = FXP_EEPROM_EECS; 861 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 862 DELAY(1); 863 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 864 DELAY(1); 865 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 866 DELAY(1); 867 } 868 } 869 870 /* 871 * Read from the serial EEPROM. Basically, you manually shift in 872 * the read opcode (one bit at a time) and then shift in the address, 873 * and then you shift out the data (all of this one bit at a time). 874 * The word size is 16 bits, so you have to provide the address for 875 * every 16 bits of data. 876 */ 877 static u_int16_t 878 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 879 { 880 u_int16_t reg, data; 881 int x; 882 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 884 /* 885 * Shift in read opcode. 886 */ 887 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 888 /* 889 * Shift in address. 890 */ 891 data = 0; 892 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 893 if (offset & x) 894 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 895 else 896 reg = FXP_EEPROM_EECS; 897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 898 DELAY(1); 899 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 900 DELAY(1); 901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 902 DELAY(1); 903 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 904 data++; 905 if (autosize && reg == 0) { 906 sc->eeprom_size = data; 907 break; 908 } 909 } 910 /* 911 * Shift out data. 912 */ 913 data = 0; 914 reg = FXP_EEPROM_EECS; 915 for (x = 1 << 15; x; x >>= 1) { 916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 917 DELAY(1); 918 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 919 data |= x; 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 921 DELAY(1); 922 } 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 924 DELAY(1); 925 926 return (data); 927 } 928 929 static void 930 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 931 { 932 int i; 933 934 /* 935 * Erase/write enable. 936 */ 937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 938 fxp_eeprom_shiftin(sc, 0x4, 3); 939 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 941 DELAY(1); 942 /* 943 * Shift in write opcode, address, data. 944 */ 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 946 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 947 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 948 fxp_eeprom_shiftin(sc, data, 16); 949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 950 DELAY(1); 951 /* 952 * Wait for EEPROM to finish up. 953 */ 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 955 DELAY(1); 956 for (i = 0; i < 1000; i++) { 957 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 958 break; 959 DELAY(50); 960 } 961 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 962 DELAY(1); 963 /* 964 * Erase/write disable. 965 */ 966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 967 fxp_eeprom_shiftin(sc, 0x4, 3); 968 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 969 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 970 DELAY(1); 971 } 972 973 /* 974 * From NetBSD: 975 * 976 * Figure out EEPROM size. 977 * 978 * 559's can have either 64-word or 256-word EEPROMs, the 558 979 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 980 * talks about the existance of 16 to 256 word EEPROMs. 981 * 982 * The only known sizes are 64 and 256, where the 256 version is used 983 * by CardBus cards to store CIS information. 984 * 985 * The address is shifted in msb-to-lsb, and after the last 986 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 987 * after which follows the actual data. We try to detect this zero, by 988 * probing the data-out bit in the EEPROM control register just after 989 * having shifted in a bit. If the bit is zero, we assume we've 990 * shifted enough address bits. The data-out should be tri-state, 991 * before this, which should translate to a logical one. 992 */ 993 static void 994 fxp_autosize_eeprom(struct fxp_softc *sc) 995 { 996 997 /* guess maximum size of 256 words */ 998 sc->eeprom_size = 8; 999 1000 /* autosize */ 1001 (void) fxp_eeprom_getword(sc, 0, 1); 1002 } 1003 1004 static void 1005 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1006 { 1007 int i; 1008 1009 for (i = 0; i < words; i++) 1010 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1011 } 1012 1013 static void 1014 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1015 { 1016 int i; 1017 1018 for (i = 0; i < words; i++) 1019 fxp_eeprom_putword(sc, offset + i, data[i]); 1020 } 1021 1022 /* 1023 * Start packet transmission on the interface. 1024 */ 1025 static void 1026 fxp_start(struct ifnet *ifp) 1027 { 1028 struct fxp_softc *sc = ifp->if_softc; 1029 struct fxp_cb_tx *txp; 1030 1031 /* 1032 * See if we need to suspend xmit until the multicast filter 1033 * has been reprogrammed (which can only be done at the head 1034 * of the command chain). 1035 */ 1036 if (sc->need_mcsetup) { 1037 return; 1038 } 1039 1040 txp = NULL; 1041 1042 /* 1043 * We're finished if there is nothing more to add to the list or if 1044 * we're all filled up with buffers to transmit. 1045 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1046 * a NOP command when needed. 1047 */ 1048 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1049 struct mbuf *m, *mb_head; 1050 int segment; 1051 1052 /* 1053 * Grab a packet to transmit. 1054 */ 1055 IF_DEQUEUE(&ifp->if_snd, mb_head); 1056 1057 /* 1058 * Get pointer to next available tx desc. 1059 */ 1060 txp = sc->cbl_last->next; 1061 1062 /* 1063 * Go through each of the mbufs in the chain and initialize 1064 * the transmit buffer descriptors with the physical address 1065 * and size of the mbuf. 1066 */ 1067 tbdinit: 1068 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1069 if (m->m_len != 0) { 1070 if (segment == FXP_NTXSEG) 1071 break; 1072 txp->tbd[segment].tb_addr = 1073 vtophys(mtod(m, vm_offset_t)); 1074 txp->tbd[segment].tb_size = m->m_len; 1075 segment++; 1076 } 1077 } 1078 if (m != NULL) { 1079 struct mbuf *mn; 1080 1081 /* 1082 * We ran out of segments. We have to recopy this 1083 * mbuf chain first. Bail out if we can't get the 1084 * new buffers. 1085 */ 1086 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1087 if (mn == NULL) { 1088 m_freem(mb_head); 1089 break; 1090 } 1091 if (mb_head->m_pkthdr.len > MHLEN) { 1092 MCLGET(mn, MB_DONTWAIT); 1093 if ((mn->m_flags & M_EXT) == 0) { 1094 m_freem(mn); 1095 m_freem(mb_head); 1096 break; 1097 } 1098 } 1099 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1100 mtod(mn, caddr_t)); 1101 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1102 m_freem(mb_head); 1103 mb_head = mn; 1104 goto tbdinit; 1105 } 1106 1107 txp->tbd_number = segment; 1108 txp->mb_head = mb_head; 1109 txp->cb_status = 0; 1110 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1111 txp->cb_command = 1112 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1113 FXP_CB_COMMAND_S; 1114 } else { 1115 txp->cb_command = 1116 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1117 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1118 /* 1119 * Set a 5 second timer just in case we don't hear 1120 * from the card again. 1121 */ 1122 ifp->if_timer = 5; 1123 } 1124 txp->tx_threshold = tx_threshold; 1125 1126 /* 1127 * Advance the end of list forward. 1128 */ 1129 1130 #ifdef __alpha__ 1131 /* 1132 * On platforms which can't access memory in 16-bit 1133 * granularities, we must prevent the card from DMA'ing 1134 * up the status while we update the command field. 1135 * This could cause us to overwrite the completion status. 1136 */ 1137 atomic_clear_short(&sc->cbl_last->cb_command, 1138 FXP_CB_COMMAND_S); 1139 #else 1140 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1141 #endif /*__alpha__*/ 1142 sc->cbl_last = txp; 1143 1144 /* 1145 * Advance the beginning of the list forward if there are 1146 * no other packets queued (when nothing is queued, cbl_first 1147 * sits on the last TxCB that was sent out). 1148 */ 1149 if (sc->tx_queued == 0) 1150 sc->cbl_first = txp; 1151 1152 sc->tx_queued++; 1153 1154 /* 1155 * Pass packet to bpf if there is a listener. 1156 */ 1157 if (ifp->if_bpf) 1158 bpf_mtap(ifp, mb_head); 1159 } 1160 1161 /* 1162 * We're finished. If we added to the list, issue a RESUME to get DMA 1163 * going again if suspended. 1164 */ 1165 if (txp != NULL) { 1166 fxp_scb_wait(sc); 1167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1168 } 1169 } 1170 1171 #ifdef DEVICE_POLLING 1172 static poll_handler_t fxp_poll; 1173 1174 static void 1175 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1176 { 1177 struct fxp_softc *sc = ifp->if_softc; 1178 u_int8_t statack; 1179 1180 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1182 return; 1183 } 1184 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1185 FXP_SCB_STATACK_FR; 1186 if (cmd == POLL_AND_CHECK_STATUS) { 1187 u_int8_t tmp; 1188 1189 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1190 if (tmp == 0xff || tmp == 0) 1191 return; /* nothing to do */ 1192 tmp &= ~statack; 1193 /* ack what we can */ 1194 if (tmp != 0) 1195 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1196 statack |= tmp; 1197 } 1198 fxp_intr_body(sc, statack, count); 1199 } 1200 #endif /* DEVICE_POLLING */ 1201 1202 /* 1203 * Process interface interrupts. 1204 */ 1205 static void 1206 fxp_intr(void *xsc) 1207 { 1208 struct fxp_softc *sc = xsc; 1209 u_int8_t statack; 1210 1211 #ifdef DEVICE_POLLING 1212 struct ifnet *ifp = &sc->sc_if; 1213 1214 if (ifp->if_flags & IFF_POLLING) 1215 return; 1216 if (ether_poll_register(fxp_poll, ifp)) { 1217 /* disable interrupts */ 1218 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1219 fxp_poll(ifp, 0, 1); 1220 return; 1221 } 1222 #endif 1223 1224 if (sc->suspended) { 1225 return; 1226 } 1227 1228 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1229 /* 1230 * It should not be possible to have all bits set; the 1231 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1232 * all bits are set, this may indicate that the card has 1233 * been physically ejected, so ignore it. 1234 */ 1235 if (statack == 0xff) 1236 return; 1237 1238 /* 1239 * First ACK all the interrupts in this pass. 1240 */ 1241 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1242 fxp_intr_body(sc, statack, -1); 1243 } 1244 } 1245 1246 static void 1247 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1248 { 1249 struct ifnet *ifp = &sc->sc_if; 1250 struct mbuf *m; 1251 struct fxp_rfa *rfa; 1252 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1253 1254 if (rnr) 1255 fxp_rnr++; 1256 #ifdef DEVICE_POLLING 1257 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1258 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1259 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1260 rnr = 1; 1261 } 1262 #endif 1263 1264 /* 1265 * Free any finished transmit mbuf chains. 1266 * 1267 * Handle the CNA event likt a CXTNO event. It used to 1268 * be that this event (control unit not ready) was not 1269 * encountered, but it is now with the SMPng modifications. 1270 * The exact sequence of events that occur when the interface 1271 * is brought up are different now, and if this event 1272 * goes unhandled, the configuration/rxfilter setup sequence 1273 * can stall for several seconds. The result is that no 1274 * packets go out onto the wire for about 5 to 10 seconds 1275 * after the interface is ifconfig'ed for the first time. 1276 */ 1277 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1278 struct fxp_cb_tx *txp; 1279 1280 for (txp = sc->cbl_first; sc->tx_queued && 1281 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1282 txp = txp->next) { 1283 if (txp->mb_head != NULL) { 1284 m_freem(txp->mb_head); 1285 txp->mb_head = NULL; 1286 } 1287 sc->tx_queued--; 1288 } 1289 sc->cbl_first = txp; 1290 ifp->if_timer = 0; 1291 if (sc->tx_queued == 0) { 1292 if (sc->need_mcsetup) 1293 fxp_mc_setup(sc); 1294 } 1295 /* 1296 * Try to start more packets transmitting. 1297 */ 1298 if (ifp->if_snd.ifq_head != NULL) 1299 fxp_start(ifp); 1300 } 1301 1302 /* 1303 * Just return if nothing happened on the receive side. 1304 */ 1305 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1306 return; 1307 1308 /* 1309 * Process receiver interrupts. If a no-resource (RNR) 1310 * condition exists, get whatever packets we can and 1311 * re-start the receiver. 1312 * 1313 * When using polling, we do not process the list to completion, 1314 * so when we get an RNR interrupt we must defer the restart 1315 * until we hit the last buffer with the C bit set. 1316 * If we run out of cycles and rfa_headm has the C bit set, 1317 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1318 * that the info will be used in the subsequent polling cycle. 1319 */ 1320 for (;;) { 1321 m = sc->rfa_headm; 1322 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1323 RFA_ALIGNMENT_FUDGE); 1324 1325 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1326 if (count >= 0 && count-- == 0) { 1327 if (rnr) { 1328 /* Defer RNR processing until the next time. */ 1329 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1330 rnr = 0; 1331 } 1332 break; 1333 } 1334 #endif /* DEVICE_POLLING */ 1335 1336 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1337 break; 1338 1339 /* 1340 * Remove first packet from the chain. 1341 */ 1342 sc->rfa_headm = m->m_next; 1343 m->m_next = NULL; 1344 1345 /* 1346 * Add a new buffer to the receive chain. 1347 * If this fails, the old buffer is recycled 1348 * instead. 1349 */ 1350 if (fxp_add_rfabuf(sc, m) == 0) { 1351 int total_len; 1352 1353 /* 1354 * Fetch packet length (the top 2 bits of 1355 * actual_size are flags set by the controller 1356 * upon completion), and drop the packet in case 1357 * of bogus length or CRC errors. 1358 */ 1359 total_len = rfa->actual_size & 0x3fff; 1360 if (total_len < sizeof(struct ether_header) || 1361 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1362 sizeof(struct fxp_rfa) || 1363 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1364 m_freem(m); 1365 continue; 1366 } 1367 m->m_pkthdr.len = m->m_len = total_len; 1368 ether_input(ifp, NULL, m); 1369 } 1370 } 1371 if (rnr) { 1372 fxp_scb_wait(sc); 1373 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1374 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1375 RFA_ALIGNMENT_FUDGE); 1376 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1377 } 1378 } 1379 1380 /* 1381 * Update packet in/out/collision statistics. The i82557 doesn't 1382 * allow you to access these counters without doing a fairly 1383 * expensive DMA to get _all_ of the statistics it maintains, so 1384 * we do this operation here only once per second. The statistics 1385 * counters in the kernel are updated from the previous dump-stats 1386 * DMA and then a new dump-stats DMA is started. The on-chip 1387 * counters are zeroed when the DMA completes. If we can't start 1388 * the DMA immediately, we don't wait - we just prepare to read 1389 * them again next time. 1390 */ 1391 static void 1392 fxp_tick(void *xsc) 1393 { 1394 struct fxp_softc *sc = xsc; 1395 struct ifnet *ifp = &sc->sc_if; 1396 struct fxp_stats *sp = sc->fxp_stats; 1397 struct fxp_cb_tx *txp; 1398 int s; 1399 1400 ifp->if_opackets += sp->tx_good; 1401 ifp->if_collisions += sp->tx_total_collisions; 1402 if (sp->rx_good) { 1403 ifp->if_ipackets += sp->rx_good; 1404 sc->rx_idle_secs = 0; 1405 } else { 1406 /* 1407 * Receiver's been idle for another second. 1408 */ 1409 sc->rx_idle_secs++; 1410 } 1411 ifp->if_ierrors += 1412 sp->rx_crc_errors + 1413 sp->rx_alignment_errors + 1414 sp->rx_rnr_errors + 1415 sp->rx_overrun_errors; 1416 /* 1417 * If any transmit underruns occured, bump up the transmit 1418 * threshold by another 512 bytes (64 * 8). 1419 */ 1420 if (sp->tx_underruns) { 1421 ifp->if_oerrors += sp->tx_underruns; 1422 if (tx_threshold < 192) 1423 tx_threshold += 64; 1424 } 1425 s = splimp(); 1426 /* 1427 * Release any xmit buffers that have completed DMA. This isn't 1428 * strictly necessary to do here, but it's advantagous for mbufs 1429 * with external storage to be released in a timely manner rather 1430 * than being defered for a potentially long time. This limits 1431 * the delay to a maximum of one second. 1432 */ 1433 for (txp = sc->cbl_first; sc->tx_queued && 1434 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1435 txp = txp->next) { 1436 if (txp->mb_head != NULL) { 1437 m_freem(txp->mb_head); 1438 txp->mb_head = NULL; 1439 } 1440 sc->tx_queued--; 1441 } 1442 sc->cbl_first = txp; 1443 /* 1444 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1445 * then assume the receiver has locked up and attempt to clear 1446 * the condition by reprogramming the multicast filter. This is 1447 * a work-around for a bug in the 82557 where the receiver locks 1448 * up if it gets certain types of garbage in the syncronization 1449 * bits prior to the packet header. This bug is supposed to only 1450 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1451 * mode as well (perhaps due to a 10/100 speed transition). 1452 */ 1453 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1454 sc->rx_idle_secs = 0; 1455 fxp_mc_setup(sc); 1456 } 1457 /* 1458 * If there is no pending command, start another stats 1459 * dump. Otherwise punt for now. 1460 */ 1461 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1462 /* 1463 * Start another stats dump. 1464 */ 1465 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1466 } else { 1467 /* 1468 * A previous command is still waiting to be accepted. 1469 * Just zero our copy of the stats and wait for the 1470 * next timer event to update them. 1471 */ 1472 sp->tx_good = 0; 1473 sp->tx_underruns = 0; 1474 sp->tx_total_collisions = 0; 1475 1476 sp->rx_good = 0; 1477 sp->rx_crc_errors = 0; 1478 sp->rx_alignment_errors = 0; 1479 sp->rx_rnr_errors = 0; 1480 sp->rx_overrun_errors = 0; 1481 } 1482 if (sc->miibus != NULL) 1483 mii_tick(device_get_softc(sc->miibus)); 1484 splx(s); 1485 /* 1486 * Schedule another timeout one second from now. 1487 */ 1488 sc->stat_ch = timeout(fxp_tick, sc, hz); 1489 } 1490 1491 /* 1492 * Stop the interface. Cancels the statistics updater and resets 1493 * the interface. 1494 */ 1495 static void 1496 fxp_stop(struct fxp_softc *sc) 1497 { 1498 struct ifnet *ifp = &sc->sc_if; 1499 struct fxp_cb_tx *txp; 1500 int i; 1501 1502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1503 ifp->if_timer = 0; 1504 1505 #ifdef DEVICE_POLLING 1506 ether_poll_deregister(ifp); 1507 #endif 1508 /* 1509 * Cancel stats updater. 1510 */ 1511 untimeout(fxp_tick, sc, sc->stat_ch); 1512 1513 /* 1514 * Issue software reset, which also unloads the microcode. 1515 */ 1516 sc->flags &= ~FXP_FLAG_UCODE; 1517 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1518 DELAY(50); 1519 1520 /* 1521 * Release any xmit buffers. 1522 */ 1523 txp = sc->cbl_base; 1524 if (txp != NULL) { 1525 for (i = 0; i < FXP_NTXCB; i++) { 1526 if (txp[i].mb_head != NULL) { 1527 m_freem(txp[i].mb_head); 1528 txp[i].mb_head = NULL; 1529 } 1530 } 1531 } 1532 sc->tx_queued = 0; 1533 1534 /* 1535 * Free all the receive buffers then reallocate/reinitialize 1536 */ 1537 if (sc->rfa_headm != NULL) 1538 m_freem(sc->rfa_headm); 1539 sc->rfa_headm = NULL; 1540 sc->rfa_tailm = NULL; 1541 for (i = 0; i < FXP_NRFABUFS; i++) { 1542 if (fxp_add_rfabuf(sc, NULL) != 0) { 1543 /* 1544 * This "can't happen" - we're at splimp() 1545 * and we just freed all the buffers we need 1546 * above. 1547 */ 1548 panic("fxp_stop: no buffers!"); 1549 } 1550 } 1551 } 1552 1553 /* 1554 * Watchdog/transmission transmit timeout handler. Called when a 1555 * transmission is started on the interface, but no interrupt is 1556 * received before the timeout. This usually indicates that the 1557 * card has wedged for some reason. 1558 */ 1559 static void 1560 fxp_watchdog(struct ifnet *ifp) 1561 { 1562 struct fxp_softc *sc = ifp->if_softc; 1563 1564 device_printf(sc->dev, "device timeout\n"); 1565 ifp->if_oerrors++; 1566 1567 fxp_init(sc); 1568 } 1569 1570 static void 1571 fxp_init(void *xsc) 1572 { 1573 struct fxp_softc *sc = xsc; 1574 struct ifnet *ifp = &sc->sc_if; 1575 struct fxp_cb_config *cbp; 1576 struct fxp_cb_ias *cb_ias; 1577 struct fxp_cb_tx *txp; 1578 struct fxp_cb_mcs *mcsp; 1579 int i, prm, s; 1580 1581 s = splimp(); 1582 /* 1583 * Cancel any pending I/O 1584 */ 1585 fxp_stop(sc); 1586 1587 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1588 1589 /* 1590 * Initialize base of CBL and RFA memory. Loading with zero 1591 * sets it up for regular linear addressing. 1592 */ 1593 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1594 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1595 1596 fxp_scb_wait(sc); 1597 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1598 1599 /* 1600 * Initialize base of dump-stats buffer. 1601 */ 1602 fxp_scb_wait(sc); 1603 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1604 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1605 1606 /* 1607 * Attempt to load microcode if requested. 1608 */ 1609 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1610 fxp_load_ucode(sc); 1611 1612 /* 1613 * Initialize the multicast address list. 1614 */ 1615 if (fxp_mc_addrs(sc)) { 1616 mcsp = sc->mcsp; 1617 mcsp->cb_status = 0; 1618 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1619 mcsp->link_addr = -1; 1620 /* 1621 * Start the multicast setup command. 1622 */ 1623 fxp_scb_wait(sc); 1624 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1625 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1626 /* ...and wait for it to complete. */ 1627 fxp_dma_wait(&mcsp->cb_status, sc); 1628 } 1629 1630 /* 1631 * We temporarily use memory that contains the TxCB list to 1632 * construct the config CB. The TxCB list memory is rebuilt 1633 * later. 1634 */ 1635 cbp = (struct fxp_cb_config *) sc->cbl_base; 1636 1637 /* 1638 * This bcopy is kind of disgusting, but there are a bunch of must be 1639 * zero and must be one bits in this structure and this is the easiest 1640 * way to initialize them all to proper values. 1641 */ 1642 bcopy(fxp_cb_config_template, 1643 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1644 sizeof(fxp_cb_config_template)); 1645 1646 cbp->cb_status = 0; 1647 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1648 cbp->link_addr = -1; /* (no) next command */ 1649 cbp->byte_count = 22; /* (22) bytes to config */ 1650 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1651 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1652 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1653 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1654 cbp->type_enable = 0; /* actually reserved */ 1655 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1656 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1657 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1658 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1659 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1660 cbp->late_scb = 0; /* (don't) defer SCB update */ 1661 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1662 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1663 cbp->ci_int = 1; /* interrupt on CU idle */ 1664 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1665 cbp->ext_stats_dis = 1; /* disable extended counters */ 1666 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1667 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1668 cbp->disc_short_rx = !prm; /* discard short packets */ 1669 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1670 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1671 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1672 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1673 cbp->csma_dis = 0; /* (don't) disable link */ 1674 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1675 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1676 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1677 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1678 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1679 cbp->nsai = 1; /* (don't) disable source addr insert */ 1680 cbp->preamble_length = 2; /* (7 byte) preamble */ 1681 cbp->loopback = 0; /* (don't) loopback */ 1682 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1683 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1684 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1685 cbp->promiscuous = prm; /* promiscuous mode */ 1686 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1687 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1688 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1689 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1690 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1691 1692 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1693 cbp->padding = 1; /* (do) pad short tx packets */ 1694 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1695 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1696 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1697 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1698 /* must set wake_en in PMCSR also */ 1699 cbp->force_fdx = 0; /* (don't) force full duplex */ 1700 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1701 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1702 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1703 1704 if (sc->revision == FXP_REV_82557) { 1705 /* 1706 * The 82557 has no hardware flow control, the values 1707 * below are the defaults for the chip. 1708 */ 1709 cbp->fc_delay_lsb = 0; 1710 cbp->fc_delay_msb = 0x40; 1711 cbp->pri_fc_thresh = 3; 1712 cbp->tx_fc_dis = 0; 1713 cbp->rx_fc_restop = 0; 1714 cbp->rx_fc_restart = 0; 1715 cbp->fc_filter = 0; 1716 cbp->pri_fc_loc = 1; 1717 } else { 1718 cbp->fc_delay_lsb = 0x1f; 1719 cbp->fc_delay_msb = 0x01; 1720 cbp->pri_fc_thresh = 3; 1721 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1722 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1723 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1724 cbp->fc_filter = !prm; /* drop FC frames to host */ 1725 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1726 } 1727 1728 /* 1729 * Start the config command/DMA. 1730 */ 1731 fxp_scb_wait(sc); 1732 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1734 /* ...and wait for it to complete. */ 1735 fxp_dma_wait(&cbp->cb_status, sc); 1736 1737 /* 1738 * Now initialize the station address. Temporarily use the TxCB 1739 * memory area like we did above for the config CB. 1740 */ 1741 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1742 cb_ias->cb_status = 0; 1743 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1744 cb_ias->link_addr = -1; 1745 bcopy(sc->arpcom.ac_enaddr, 1746 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1747 sizeof(sc->arpcom.ac_enaddr)); 1748 1749 /* 1750 * Start the IAS (Individual Address Setup) command/DMA. 1751 */ 1752 fxp_scb_wait(sc); 1753 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1754 /* ...and wait for it to complete. */ 1755 fxp_dma_wait(&cb_ias->cb_status, sc); 1756 1757 /* 1758 * Initialize transmit control block (TxCB) list. 1759 */ 1760 1761 txp = sc->cbl_base; 1762 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1763 for (i = 0; i < FXP_NTXCB; i++) { 1764 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1765 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1766 txp[i].link_addr = 1767 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1768 if (sc->flags & FXP_FLAG_EXT_TXCB) 1769 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1770 else 1771 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1772 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1773 } 1774 /* 1775 * Set the suspend flag on the first TxCB and start the control 1776 * unit. It will execute the NOP and then suspend. 1777 */ 1778 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1779 sc->cbl_first = sc->cbl_last = txp; 1780 sc->tx_queued = 1; 1781 1782 fxp_scb_wait(sc); 1783 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1784 1785 /* 1786 * Initialize receiver buffer area - RFA. 1787 */ 1788 fxp_scb_wait(sc); 1789 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1790 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1791 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1792 1793 /* 1794 * Set current media. 1795 */ 1796 if (sc->miibus != NULL) 1797 mii_mediachg(device_get_softc(sc->miibus)); 1798 1799 ifp->if_flags |= IFF_RUNNING; 1800 ifp->if_flags &= ~IFF_OACTIVE; 1801 1802 /* 1803 * Enable interrupts. 1804 */ 1805 #ifdef DEVICE_POLLING 1806 /* 1807 * ... but only do that if we are not polling. And because (presumably) 1808 * the default is interrupts on, we need to disable them explicitly! 1809 */ 1810 if ( ifp->if_flags & IFF_POLLING ) 1811 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1812 else 1813 #endif /* DEVICE_POLLING */ 1814 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1815 splx(s); 1816 1817 /* 1818 * Start stats updater. 1819 */ 1820 sc->stat_ch = timeout(fxp_tick, sc, hz); 1821 } 1822 1823 static int 1824 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1825 { 1826 1827 return (0); 1828 } 1829 1830 static void 1831 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1832 { 1833 1834 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1835 } 1836 1837 /* 1838 * Change media according to request. 1839 */ 1840 static int 1841 fxp_ifmedia_upd(struct ifnet *ifp) 1842 { 1843 struct fxp_softc *sc = ifp->if_softc; 1844 struct mii_data *mii; 1845 1846 mii = device_get_softc(sc->miibus); 1847 mii_mediachg(mii); 1848 return (0); 1849 } 1850 1851 /* 1852 * Notify the world which media we're using. 1853 */ 1854 static void 1855 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1856 { 1857 struct fxp_softc *sc = ifp->if_softc; 1858 struct mii_data *mii; 1859 1860 mii = device_get_softc(sc->miibus); 1861 mii_pollstat(mii); 1862 ifmr->ifm_active = mii->mii_media_active; 1863 ifmr->ifm_status = mii->mii_media_status; 1864 1865 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1866 sc->cu_resume_bug = 1; 1867 else 1868 sc->cu_resume_bug = 0; 1869 } 1870 1871 /* 1872 * Add a buffer to the end of the RFA buffer list. 1873 * Return 0 if successful, 1 for failure. A failure results in 1874 * adding the 'oldm' (if non-NULL) on to the end of the list - 1875 * tossing out its old contents and recycling it. 1876 * The RFA struct is stuck at the beginning of mbuf cluster and the 1877 * data pointer is fixed up to point just past it. 1878 */ 1879 static int 1880 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1881 { 1882 u_int32_t v; 1883 struct mbuf *m; 1884 struct fxp_rfa *rfa, *p_rfa; 1885 1886 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1887 if (m == NULL) { /* try to recycle the old mbuf instead */ 1888 if (oldm == NULL) 1889 return 1; 1890 m = oldm; 1891 m->m_data = m->m_ext.ext_buf; 1892 } 1893 1894 /* 1895 * Move the data pointer up so that the incoming data packet 1896 * will be 32-bit aligned. 1897 */ 1898 m->m_data += RFA_ALIGNMENT_FUDGE; 1899 1900 /* 1901 * Get a pointer to the base of the mbuf cluster and move 1902 * data start past it. 1903 */ 1904 rfa = mtod(m, struct fxp_rfa *); 1905 m->m_data += sizeof(struct fxp_rfa); 1906 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1907 1908 /* 1909 * Initialize the rest of the RFA. Note that since the RFA 1910 * is misaligned, we cannot store values directly. Instead, 1911 * we use an optimized, inline copy. 1912 */ 1913 1914 rfa->rfa_status = 0; 1915 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1916 rfa->actual_size = 0; 1917 1918 v = -1; 1919 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1920 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1921 1922 /* 1923 * If there are other buffers already on the list, attach this 1924 * one to the end by fixing up the tail to point to this one. 1925 */ 1926 if (sc->rfa_headm != NULL) { 1927 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1928 RFA_ALIGNMENT_FUDGE); 1929 sc->rfa_tailm->m_next = m; 1930 v = vtophys(rfa); 1931 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1932 p_rfa->rfa_control = 0; 1933 } else { 1934 sc->rfa_headm = m; 1935 } 1936 sc->rfa_tailm = m; 1937 1938 return (m == oldm); 1939 } 1940 1941 static volatile int 1942 fxp_miibus_readreg(device_t dev, int phy, int reg) 1943 { 1944 struct fxp_softc *sc = device_get_softc(dev); 1945 int count = 10000; 1946 int value; 1947 1948 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1949 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1950 1951 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1952 && count--) 1953 DELAY(10); 1954 1955 if (count <= 0) 1956 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1957 1958 return (value & 0xffff); 1959 } 1960 1961 static void 1962 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1963 { 1964 struct fxp_softc *sc = device_get_softc(dev); 1965 int count = 10000; 1966 1967 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1968 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1969 (value & 0xffff)); 1970 1971 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1972 count--) 1973 DELAY(10); 1974 1975 if (count <= 0) 1976 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1977 } 1978 1979 static int 1980 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1981 { 1982 struct fxp_softc *sc = ifp->if_softc; 1983 struct ifreq *ifr = (struct ifreq *)data; 1984 struct mii_data *mii; 1985 int s, error = 0; 1986 1987 s = splimp(); 1988 1989 switch (command) { 1990 case SIOCSIFADDR: 1991 case SIOCGIFADDR: 1992 case SIOCSIFMTU: 1993 error = ether_ioctl(ifp, command, data); 1994 break; 1995 1996 case SIOCSIFFLAGS: 1997 if (ifp->if_flags & IFF_ALLMULTI) 1998 sc->flags |= FXP_FLAG_ALL_MCAST; 1999 else 2000 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2001 2002 /* 2003 * If interface is marked up and not running, then start it. 2004 * If it is marked down and running, stop it. 2005 * XXX If it's up then re-initialize it. This is so flags 2006 * such as IFF_PROMISC are handled. 2007 */ 2008 if (ifp->if_flags & IFF_UP) { 2009 fxp_init(sc); 2010 } else { 2011 if (ifp->if_flags & IFF_RUNNING) 2012 fxp_stop(sc); 2013 } 2014 break; 2015 2016 case SIOCADDMULTI: 2017 case SIOCDELMULTI: 2018 if (ifp->if_flags & IFF_ALLMULTI) 2019 sc->flags |= FXP_FLAG_ALL_MCAST; 2020 else 2021 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2022 /* 2023 * Multicast list has changed; set the hardware filter 2024 * accordingly. 2025 */ 2026 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2027 fxp_mc_setup(sc); 2028 /* 2029 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2030 * again rather than else {}. 2031 */ 2032 if (sc->flags & FXP_FLAG_ALL_MCAST) 2033 fxp_init(sc); 2034 error = 0; 2035 break; 2036 2037 case SIOCSIFMEDIA: 2038 case SIOCGIFMEDIA: 2039 if (sc->miibus != NULL) { 2040 mii = device_get_softc(sc->miibus); 2041 error = ifmedia_ioctl(ifp, ifr, 2042 &mii->mii_media, command); 2043 } else { 2044 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2045 } 2046 break; 2047 2048 default: 2049 error = EINVAL; 2050 } 2051 splx(s); 2052 return (error); 2053 } 2054 2055 /* 2056 * Fill in the multicast address list and return number of entries. 2057 */ 2058 static int 2059 fxp_mc_addrs(struct fxp_softc *sc) 2060 { 2061 struct fxp_cb_mcs *mcsp = sc->mcsp; 2062 struct ifnet *ifp = &sc->sc_if; 2063 struct ifmultiaddr *ifma; 2064 int nmcasts; 2065 2066 nmcasts = 0; 2067 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2068 #if defined(__DragonFly__) || __FreeBSD_version < 500000 2069 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2070 #else 2071 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2072 #endif 2073 if (ifma->ifma_addr->sa_family != AF_LINK) 2074 continue; 2075 if (nmcasts >= MAXMCADDR) { 2076 sc->flags |= FXP_FLAG_ALL_MCAST; 2077 nmcasts = 0; 2078 break; 2079 } 2080 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2081 (void *)(uintptr_t)(volatile void *) 2082 &sc->mcsp->mc_addr[nmcasts][0], 6); 2083 nmcasts++; 2084 } 2085 } 2086 mcsp->mc_cnt = nmcasts * 6; 2087 return (nmcasts); 2088 } 2089 2090 /* 2091 * Program the multicast filter. 2092 * 2093 * We have an artificial restriction that the multicast setup command 2094 * must be the first command in the chain, so we take steps to ensure 2095 * this. By requiring this, it allows us to keep up the performance of 2096 * the pre-initialized command ring (esp. link pointers) by not actually 2097 * inserting the mcsetup command in the ring - i.e. its link pointer 2098 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2099 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2100 * lead into the regular TxCB ring when it completes. 2101 * 2102 * This function must be called at splimp. 2103 */ 2104 static void 2105 fxp_mc_setup(struct fxp_softc *sc) 2106 { 2107 struct fxp_cb_mcs *mcsp = sc->mcsp; 2108 struct ifnet *ifp = &sc->sc_if; 2109 int count; 2110 2111 /* 2112 * If there are queued commands, we must wait until they are all 2113 * completed. If we are already waiting, then add a NOP command 2114 * with interrupt option so that we're notified when all commands 2115 * have been completed - fxp_start() ensures that no additional 2116 * TX commands will be added when need_mcsetup is true. 2117 */ 2118 if (sc->tx_queued) { 2119 struct fxp_cb_tx *txp; 2120 2121 /* 2122 * need_mcsetup will be true if we are already waiting for the 2123 * NOP command to be completed (see below). In this case, bail. 2124 */ 2125 if (sc->need_mcsetup) 2126 return; 2127 sc->need_mcsetup = 1; 2128 2129 /* 2130 * Add a NOP command with interrupt so that we are notified 2131 * when all TX commands have been processed. 2132 */ 2133 txp = sc->cbl_last->next; 2134 txp->mb_head = NULL; 2135 txp->cb_status = 0; 2136 txp->cb_command = FXP_CB_COMMAND_NOP | 2137 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2138 /* 2139 * Advance the end of list forward. 2140 */ 2141 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2142 sc->cbl_last = txp; 2143 sc->tx_queued++; 2144 /* 2145 * Issue a resume in case the CU has just suspended. 2146 */ 2147 fxp_scb_wait(sc); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2149 /* 2150 * Set a 5 second timer just in case we don't hear from the 2151 * card again. 2152 */ 2153 ifp->if_timer = 5; 2154 2155 return; 2156 } 2157 sc->need_mcsetup = 0; 2158 2159 /* 2160 * Initialize multicast setup descriptor. 2161 */ 2162 mcsp->next = sc->cbl_base; 2163 mcsp->mb_head = NULL; 2164 mcsp->cb_status = 0; 2165 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2166 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2167 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2168 (void) fxp_mc_addrs(sc); 2169 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2170 sc->tx_queued = 1; 2171 2172 /* 2173 * Wait until command unit is not active. This should never 2174 * be the case when nothing is queued, but make sure anyway. 2175 */ 2176 count = 100; 2177 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2178 FXP_SCB_CUS_ACTIVE && --count) 2179 DELAY(10); 2180 if (count == 0) { 2181 device_printf(sc->dev, "command queue timeout\n"); 2182 return; 2183 } 2184 2185 /* 2186 * Start the multicast setup command. 2187 */ 2188 fxp_scb_wait(sc); 2189 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2190 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2191 2192 ifp->if_timer = 2; 2193 return; 2194 } 2195 2196 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2197 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2198 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2199 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2200 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2201 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2202 2203 #define UCODE(x) x, sizeof(x) 2204 2205 struct ucode { 2206 u_int32_t revision; 2207 u_int32_t *ucode; 2208 int length; 2209 u_short int_delay_offset; 2210 u_short bundle_max_offset; 2211 } ucode_table[] = { 2212 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2213 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2214 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2215 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2216 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2217 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2218 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2219 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2220 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2221 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2222 { 0, NULL, 0, 0, 0 } 2223 }; 2224 2225 static void 2226 fxp_load_ucode(struct fxp_softc *sc) 2227 { 2228 struct ucode *uc; 2229 struct fxp_cb_ucode *cbp; 2230 2231 for (uc = ucode_table; uc->ucode != NULL; uc++) 2232 if (sc->revision == uc->revision) 2233 break; 2234 if (uc->ucode == NULL) 2235 return; 2236 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2237 cbp->cb_status = 0; 2238 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2239 cbp->link_addr = -1; /* (no) next command */ 2240 memcpy(cbp->ucode, uc->ucode, uc->length); 2241 if (uc->int_delay_offset) 2242 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2243 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2244 if (uc->bundle_max_offset) 2245 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2246 sc->tunable_bundle_max; 2247 /* 2248 * Download the ucode to the chip. 2249 */ 2250 fxp_scb_wait(sc); 2251 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2252 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2253 /* ...and wait for it to complete. */ 2254 fxp_dma_wait(&cbp->cb_status, sc); 2255 device_printf(sc->dev, 2256 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2257 sc->tunable_int_delay, 2258 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2259 sc->flags |= FXP_FLAG_UCODE; 2260 } 2261 2262 static int 2263 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2264 { 2265 int error, value; 2266 2267 value = *(int *)arg1; 2268 error = sysctl_handle_int(oidp, &value, 0, req); 2269 if (error || !req->newptr) 2270 return (error); 2271 if (value < low || value > high) 2272 return (EINVAL); 2273 *(int *)arg1 = value; 2274 return (0); 2275 } 2276 2277 /* 2278 * Interrupt delay is expressed in microseconds, a multiplier is used 2279 * to convert this to the appropriate clock ticks before using. 2280 */ 2281 static int 2282 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2283 { 2284 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2285 } 2286 2287 static int 2288 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2289 { 2290 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2291 } 2292