1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.28 2005/05/27 15:03:12 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 #include <machine/clock.h> /* for DELAY */ 68 69 #include <net/if_types.h> 70 #include <net/vlan/if_vlan_var.h> 71 72 #include <bus/pci/pcivar.h> 73 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include "../mii_layer/mii.h" 76 #include "../mii_layer/miivar.h" 77 78 #include "if_fxpreg.h" 79 #include "if_fxpvar.h" 80 #include "rcvbundl.h" 81 82 #include "miibus_if.h" 83 84 /* 85 * NOTE! On the Alpha, we have an alignment constraint. The 86 * card DMAs the packet immediately following the RFA. However, 87 * the first thing in the packet is a 14-byte Ethernet header. 88 * This means that the packet is misaligned. To compensate, 89 * we actually offset the RFA 2 bytes into the cluster. This 90 * alignes the packet after the Ethernet header at a 32-bit 91 * boundary. HOWEVER! This means that the RFA is misaligned! 92 */ 93 #define RFA_ALIGNMENT_FUDGE 2 94 95 /* 96 * Set initial transmit threshold at 64 (512 bytes). This is 97 * increased by 64 (512 bytes) at a time, to maximum of 192 98 * (1536 bytes), if an underrun occurs. 99 */ 100 static int tx_threshold = 64; 101 102 /* 103 * The configuration byte map has several undefined fields which 104 * must be one or must be zero. Set up a template for these bits 105 * only, (assuming a 82557 chip) leaving the actual configuration 106 * to fxp_init. 107 * 108 * See struct fxp_cb_config for the bit definitions. 109 */ 110 static u_char fxp_cb_config_template[] = { 111 0x0, 0x0, /* cb_status */ 112 0x0, 0x0, /* cb_command */ 113 0x0, 0x0, 0x0, 0x0, /* link_addr */ 114 0x0, /* 0 */ 115 0x0, /* 1 */ 116 0x0, /* 2 */ 117 0x0, /* 3 */ 118 0x0, /* 4 */ 119 0x0, /* 5 */ 120 0x32, /* 6 */ 121 0x0, /* 7 */ 122 0x0, /* 8 */ 123 0x0, /* 9 */ 124 0x6, /* 10 */ 125 0x0, /* 11 */ 126 0x0, /* 12 */ 127 0x0, /* 13 */ 128 0xf2, /* 14 */ 129 0x48, /* 15 */ 130 0x0, /* 16 */ 131 0x40, /* 17 */ 132 0xf0, /* 18 */ 133 0x0, /* 19 */ 134 0x3f, /* 20 */ 135 0x5 /* 21 */ 136 }; 137 138 struct fxp_ident { 139 u_int16_t devid; 140 int16_t revid; /* -1 matches anything */ 141 char *name; 142 }; 143 144 /* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150 static struct fxp_ident fxp_ident_table[] = { 151 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 152 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 153 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 162 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 163 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 168 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 169 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 171 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 172 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 176 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 177 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 181 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 185 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 186 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 187 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 188 { 0, -1, NULL }, 189 }; 190 191 static int fxp_probe(device_t dev); 192 static int fxp_attach(device_t dev); 193 static int fxp_detach(device_t dev); 194 static int fxp_shutdown(device_t dev); 195 static int fxp_suspend(device_t dev); 196 static int fxp_resume(device_t dev); 197 198 static void fxp_intr(void *xsc); 199 static void fxp_intr_body(struct fxp_softc *sc, 200 u_int8_t statack, int count); 201 202 static void fxp_init(void *xsc); 203 static void fxp_tick(void *xsc); 204 static void fxp_powerstate_d0(device_t dev); 205 static void fxp_start(struct ifnet *ifp); 206 static void fxp_stop(struct fxp_softc *sc); 207 static void fxp_release(struct fxp_softc *sc); 208 static int fxp_ioctl(struct ifnet *ifp, u_long command, 209 caddr_t data, struct ucred *); 210 static void fxp_watchdog(struct ifnet *ifp); 211 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 212 static int fxp_mc_addrs(struct fxp_softc *sc); 213 static void fxp_mc_setup(struct fxp_softc *sc); 214 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 215 int autosize); 216 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 217 u_int16_t data); 218 static void fxp_autosize_eeprom(struct fxp_softc *sc); 219 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 220 int offset, int words); 221 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 222 int offset, int words); 223 static int fxp_ifmedia_upd(struct ifnet *ifp); 224 static void fxp_ifmedia_sts(struct ifnet *ifp, 225 struct ifmediareq *ifmr); 226 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 227 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 228 struct ifmediareq *ifmr); 229 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 230 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 231 int value); 232 static void fxp_load_ucode(struct fxp_softc *sc); 233 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 234 int low, int high); 235 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 236 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 237 #ifdef DEVICE_POLLING 238 static poll_handler_t fxp_poll; 239 #endif 240 241 static __inline void fxp_lwcopy(volatile u_int32_t *src, 242 volatile u_int32_t *dst); 243 static __inline void fxp_scb_wait(struct fxp_softc *sc); 244 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 245 static __inline void fxp_dma_wait(volatile u_int16_t *status, 246 struct fxp_softc *sc); 247 248 static device_method_t fxp_methods[] = { 249 /* Device interface */ 250 DEVMETHOD(device_probe, fxp_probe), 251 DEVMETHOD(device_attach, fxp_attach), 252 DEVMETHOD(device_detach, fxp_detach), 253 DEVMETHOD(device_shutdown, fxp_shutdown), 254 DEVMETHOD(device_suspend, fxp_suspend), 255 DEVMETHOD(device_resume, fxp_resume), 256 257 /* MII interface */ 258 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 259 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 260 261 { 0, 0 } 262 }; 263 264 static driver_t fxp_driver = { 265 "fxp", 266 fxp_methods, 267 sizeof(struct fxp_softc), 268 }; 269 270 static devclass_t fxp_devclass; 271 272 DECLARE_DUMMY_MODULE(if_fxp); 273 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 274 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 275 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 276 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 277 278 static int fxp_rnr; 279 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 280 281 /* 282 * Inline function to copy a 16-bit aligned 32-bit quantity. 283 */ 284 static __inline void 285 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 286 { 287 #ifdef __i386__ 288 *dst = *src; 289 #else 290 volatile u_int16_t *a = (volatile u_int16_t *)src; 291 volatile u_int16_t *b = (volatile u_int16_t *)dst; 292 293 b[0] = a[0]; 294 b[1] = a[1]; 295 #endif 296 } 297 298 /* 299 * Wait for the previous command to be accepted (but not necessarily 300 * completed). 301 */ 302 static __inline void 303 fxp_scb_wait(struct fxp_softc *sc) 304 { 305 int i = 10000; 306 307 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 308 DELAY(2); 309 if (i == 0) 310 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 311 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 312 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 313 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 314 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 315 } 316 317 static __inline void 318 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 319 { 320 321 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 322 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 323 fxp_scb_wait(sc); 324 } 325 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 326 } 327 328 static __inline void 329 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 330 { 331 int i = 10000; 332 333 while (!(*status & FXP_CB_STATUS_C) && --i) 334 DELAY(2); 335 if (i == 0) 336 device_printf(sc->dev, "DMA timeout\n"); 337 } 338 339 /* 340 * Return identification string if this is device is ours. 341 */ 342 static int 343 fxp_probe(device_t dev) 344 { 345 u_int16_t devid; 346 u_int8_t revid; 347 struct fxp_ident *ident; 348 349 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 350 devid = pci_get_device(dev); 351 revid = pci_get_revid(dev); 352 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 353 if (ident->devid == devid && 354 (ident->revid == revid || ident->revid == -1)) { 355 device_set_desc(dev, ident->name); 356 return (0); 357 } 358 } 359 } 360 return (ENXIO); 361 } 362 363 static void 364 fxp_powerstate_d0(device_t dev) 365 { 366 u_int32_t iobase, membase, irq; 367 368 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 369 /* Save important PCI config data. */ 370 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 371 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 372 irq = pci_read_config(dev, PCIR_INTLINE, 4); 373 374 /* Reset the power state. */ 375 device_printf(dev, "chip is in D%d power mode " 376 "-- setting to D0\n", pci_get_powerstate(dev)); 377 378 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 379 380 /* Restore PCI config data. */ 381 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 382 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 383 pci_write_config(dev, PCIR_INTLINE, irq, 4); 384 } 385 } 386 387 static int 388 fxp_attach(device_t dev) 389 { 390 int error = 0; 391 struct fxp_softc *sc = device_get_softc(dev); 392 struct ifnet *ifp; 393 u_int32_t val; 394 u_int16_t data; 395 int i, rid, m1, m2, prefer_iomap; 396 int s; 397 398 bzero(sc, sizeof(*sc)); 399 sc->dev = dev; 400 callout_init(&sc->fxp_stat_timer); 401 sysctl_ctx_init(&sc->sysctl_ctx); 402 403 s = splimp(); 404 405 /* 406 * Enable bus mastering. Enable memory space too, in case 407 * BIOS/Prom forgot about it. 408 */ 409 val = pci_read_config(dev, PCIR_COMMAND, 2); 410 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 411 pci_write_config(dev, PCIR_COMMAND, val, 2); 412 val = pci_read_config(dev, PCIR_COMMAND, 2); 413 414 fxp_powerstate_d0(dev); 415 416 /* 417 * Figure out which we should try first - memory mapping or i/o mapping? 418 * We default to memory mapping. Then we accept an override from the 419 * command line. Then we check to see which one is enabled. 420 */ 421 m1 = PCIM_CMD_MEMEN; 422 m2 = PCIM_CMD_PORTEN; 423 prefer_iomap = 0; 424 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 425 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 426 m1 = PCIM_CMD_PORTEN; 427 m2 = PCIM_CMD_MEMEN; 428 } 429 430 if (val & m1) { 431 sc->rtp = 432 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 433 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 434 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 435 RF_ACTIVE); 436 } 437 if (sc->mem == NULL && (val & m2)) { 438 sc->rtp = 439 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 440 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 441 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 442 RF_ACTIVE); 443 } 444 445 if (!sc->mem) { 446 device_printf(dev, "could not map device registers\n"); 447 error = ENXIO; 448 goto fail; 449 } 450 if (bootverbose) { 451 device_printf(dev, "using %s space register mapping\n", 452 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 453 } 454 455 sc->sc_st = rman_get_bustag(sc->mem); 456 sc->sc_sh = rman_get_bushandle(sc->mem); 457 458 /* 459 * Allocate our interrupt. 460 */ 461 rid = 0; 462 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 463 RF_SHAREABLE | RF_ACTIVE); 464 if (sc->irq == NULL) { 465 device_printf(dev, "could not map interrupt\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 471 fxp_intr, sc, &sc->ih, NULL); 472 if (error) { 473 device_printf(dev, "could not setup irq\n"); 474 goto fail; 475 } 476 477 /* 478 * Reset to a stable state. 479 */ 480 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 481 DELAY(10); 482 483 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 484 M_DEVBUF, M_WAITOK | M_ZERO); 485 486 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 487 M_WAITOK | M_ZERO); 488 489 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 490 491 /* 492 * Pre-allocate our receive buffers. 493 */ 494 for (i = 0; i < FXP_NRFABUFS; i++) { 495 if (fxp_add_rfabuf(sc, NULL) != 0) { 496 goto failmem; 497 } 498 } 499 500 /* 501 * Find out how large of an SEEPROM we have. 502 */ 503 fxp_autosize_eeprom(sc); 504 505 /* 506 * Determine whether we must use the 503 serial interface. 507 */ 508 fxp_read_eeprom(sc, &data, 6, 1); 509 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 510 (data & FXP_PHY_SERIAL_ONLY)) 511 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 512 513 /* 514 * Create the sysctl tree 515 */ 516 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 517 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 518 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 519 if (sc->sysctl_tree == NULL) 520 goto fail; 521 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 522 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 523 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 524 "FXP driver receive interrupt microcode bundling delay"); 525 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 526 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 527 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 528 "FXP driver receive interrupt microcode bundle size limit"); 529 530 /* 531 * Pull in device tunables. 532 */ 533 sc->tunable_int_delay = TUNABLE_INT_DELAY; 534 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 535 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 536 "int_delay", &sc->tunable_int_delay); 537 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 538 "bundle_max", &sc->tunable_bundle_max); 539 540 /* 541 * Find out the chip revision; lump all 82557 revs together. 542 */ 543 fxp_read_eeprom(sc, &data, 5, 1); 544 if ((data >> 8) == 1) 545 sc->revision = FXP_REV_82557; 546 else 547 sc->revision = pci_get_revid(dev); 548 549 /* 550 * Enable workarounds for certain chip revision deficiencies. 551 * 552 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 553 * some systems based a normal 82559 design, have a defect where 554 * the chip can cause a PCI protocol violation if it receives 555 * a CU_RESUME command when it is entering the IDLE state. The 556 * workaround is to disable Dynamic Standby Mode, so the chip never 557 * deasserts CLKRUN#, and always remains in an active state. 558 * 559 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 560 */ 561 i = pci_get_device(dev); 562 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 563 sc->revision >= FXP_REV_82559_A0) { 564 fxp_read_eeprom(sc, &data, 10, 1); 565 if (data & 0x02) { /* STB enable */ 566 u_int16_t cksum; 567 int i; 568 569 device_printf(dev, 570 "Disabling dynamic standby mode in EEPROM\n"); 571 data &= ~0x02; 572 fxp_write_eeprom(sc, &data, 10, 1); 573 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 574 cksum = 0; 575 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 576 fxp_read_eeprom(sc, &data, i, 1); 577 cksum += data; 578 } 579 i = (1 << sc->eeprom_size) - 1; 580 cksum = 0xBABA - cksum; 581 fxp_read_eeprom(sc, &data, i, 1); 582 fxp_write_eeprom(sc, &cksum, i, 1); 583 device_printf(dev, 584 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 585 i, data, cksum); 586 #if 1 587 /* 588 * If the user elects to continue, try the software 589 * workaround, as it is better than nothing. 590 */ 591 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 592 #endif 593 } 594 } 595 596 /* 597 * If we are not a 82557 chip, we can enable extended features. 598 */ 599 if (sc->revision != FXP_REV_82557) { 600 /* 601 * If MWI is enabled in the PCI configuration, and there 602 * is a valid cacheline size (8 or 16 dwords), then tell 603 * the board to turn on MWI. 604 */ 605 if (val & PCIM_CMD_MWRICEN && 606 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 607 sc->flags |= FXP_FLAG_MWI_ENABLE; 608 609 /* turn on the extended TxCB feature */ 610 sc->flags |= FXP_FLAG_EXT_TXCB; 611 612 /* enable reception of long frames for VLAN */ 613 sc->flags |= FXP_FLAG_LONG_PKT_EN; 614 } 615 616 /* 617 * Read MAC address. 618 */ 619 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 620 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 621 device_printf(dev, "10Mbps"); 622 if (bootverbose) { 623 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 624 pci_get_vendor(dev), pci_get_device(dev), 625 pci_get_subvendor(dev), pci_get_subdevice(dev), 626 pci_get_revid(dev)); 627 fxp_read_eeprom(sc, &data, 10, 1); 628 device_printf(dev, "Dynamic Standby mode is %s\n", 629 data & 0x02 ? "enabled" : "disabled"); 630 } 631 632 /* 633 * If this is only a 10Mbps device, then there is no MII, and 634 * the PHY will use a serial interface instead. 635 * 636 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 637 * doesn't have a programming interface of any sort. The 638 * media is sensed automatically based on how the link partner 639 * is configured. This is, in essence, manual configuration. 640 */ 641 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 642 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 643 fxp_serial_ifmedia_sts); 644 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 645 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 646 } else { 647 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 648 fxp_ifmedia_sts)) { 649 device_printf(dev, "MII without any PHY!\n"); 650 error = ENXIO; 651 goto fail; 652 } 653 } 654 655 ifp = &sc->arpcom.ac_if; 656 if_initname(ifp, "fxp", device_get_unit(dev)); 657 ifp->if_baudrate = 100000000; 658 ifp->if_init = fxp_init; 659 ifp->if_softc = sc; 660 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 661 ifp->if_ioctl = fxp_ioctl; 662 ifp->if_start = fxp_start; 663 #ifdef DEVICE_POLLING 664 ifp->if_poll = fxp_poll; 665 #endif 666 ifp->if_watchdog = fxp_watchdog; 667 668 /* 669 * Attach the interface. 670 */ 671 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 672 673 /* 674 * Tell the upper layer(s) we support long frames. 675 */ 676 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 677 678 /* 679 * Let the system queue as many packets as we have available 680 * TX descriptors. 681 */ 682 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 683 ifq_set_ready(&ifp->if_snd); 684 685 splx(s); 686 return (0); 687 688 failmem: 689 device_printf(dev, "Failed to malloc memory\n"); 690 error = ENOMEM; 691 fail: 692 splx(s); 693 fxp_release(sc); 694 return (error); 695 } 696 697 /* 698 * release all resources 699 */ 700 static void 701 fxp_release(struct fxp_softc *sc) 702 { 703 704 bus_generic_detach(sc->dev); 705 if (sc->miibus) 706 device_delete_child(sc->dev, sc->miibus); 707 708 if (sc->cbl_base) 709 free(sc->cbl_base, M_DEVBUF); 710 if (sc->fxp_stats) 711 free(sc->fxp_stats, M_DEVBUF); 712 if (sc->mcsp) 713 free(sc->mcsp, M_DEVBUF); 714 if (sc->rfa_headm) 715 m_freem(sc->rfa_headm); 716 717 if (sc->ih) 718 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 719 if (sc->irq) 720 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 721 if (sc->mem) 722 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 723 724 sysctl_ctx_free(&sc->sysctl_ctx); 725 } 726 727 /* 728 * Detach interface. 729 */ 730 static int 731 fxp_detach(device_t dev) 732 { 733 struct fxp_softc *sc = device_get_softc(dev); 734 int s; 735 736 /* disable interrupts */ 737 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 738 739 s = splimp(); 740 741 /* 742 * Stop DMA and drop transmit queue. 743 */ 744 fxp_stop(sc); 745 746 /* 747 * Close down routes etc. 748 */ 749 ether_ifdetach(&sc->arpcom.ac_if); 750 751 /* 752 * Free all media structures. 753 */ 754 ifmedia_removeall(&sc->sc_media); 755 756 splx(s); 757 758 /* Release our allocated resources. */ 759 fxp_release(sc); 760 761 return (0); 762 } 763 764 /* 765 * Device shutdown routine. Called at system shutdown after sync. The 766 * main purpose of this routine is to shut off receiver DMA so that 767 * kernel memory doesn't get clobbered during warmboot. 768 */ 769 static int 770 fxp_shutdown(device_t dev) 771 { 772 /* 773 * Make sure that DMA is disabled prior to reboot. Not doing 774 * do could allow DMA to corrupt kernel memory during the 775 * reboot before the driver initializes. 776 */ 777 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 778 return (0); 779 } 780 781 /* 782 * Device suspend routine. Stop the interface and save some PCI 783 * settings in case the BIOS doesn't restore them properly on 784 * resume. 785 */ 786 static int 787 fxp_suspend(device_t dev) 788 { 789 struct fxp_softc *sc = device_get_softc(dev); 790 int i, s; 791 792 s = splimp(); 793 794 fxp_stop(sc); 795 796 for (i = 0; i < 5; i++) 797 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 798 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 799 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 800 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 801 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 802 803 sc->suspended = 1; 804 805 splx(s); 806 return (0); 807 } 808 809 /* 810 * Device resume routine. Restore some PCI settings in case the BIOS 811 * doesn't, re-enable busmastering, and restart the interface if 812 * appropriate. 813 */ 814 static int 815 fxp_resume(device_t dev) 816 { 817 struct fxp_softc *sc = device_get_softc(dev); 818 struct ifnet *ifp = &sc->arpcom.ac_if; 819 u_int16_t pci_command; 820 int i, s; 821 822 s = splimp(); 823 824 fxp_powerstate_d0(dev); 825 826 /* better way to do this? */ 827 for (i = 0; i < 5; i++) 828 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 829 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 830 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 831 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 832 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 833 834 /* reenable busmastering */ 835 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 836 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 837 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 838 839 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 840 DELAY(10); 841 842 /* reinitialize interface if necessary */ 843 if (ifp->if_flags & IFF_UP) 844 fxp_init(sc); 845 846 sc->suspended = 0; 847 848 splx(s); 849 return (0); 850 } 851 852 static void 853 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 854 { 855 u_int16_t reg; 856 int x; 857 858 /* 859 * Shift in data. 860 */ 861 for (x = 1 << (length - 1); x; x >>= 1) { 862 if (data & x) 863 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 864 else 865 reg = FXP_EEPROM_EECS; 866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 867 DELAY(1); 868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 869 DELAY(1); 870 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 871 DELAY(1); 872 } 873 } 874 875 /* 876 * Read from the serial EEPROM. Basically, you manually shift in 877 * the read opcode (one bit at a time) and then shift in the address, 878 * and then you shift out the data (all of this one bit at a time). 879 * The word size is 16 bits, so you have to provide the address for 880 * every 16 bits of data. 881 */ 882 static u_int16_t 883 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 884 { 885 u_int16_t reg, data; 886 int x; 887 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 889 /* 890 * Shift in read opcode. 891 */ 892 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 893 /* 894 * Shift in address. 895 */ 896 data = 0; 897 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 898 if (offset & x) 899 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 900 else 901 reg = FXP_EEPROM_EECS; 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 903 DELAY(1); 904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 905 DELAY(1); 906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 907 DELAY(1); 908 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 909 data++; 910 if (autosize && reg == 0) { 911 sc->eeprom_size = data; 912 break; 913 } 914 } 915 /* 916 * Shift out data. 917 */ 918 data = 0; 919 reg = FXP_EEPROM_EECS; 920 for (x = 1 << 15; x; x >>= 1) { 921 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 922 DELAY(1); 923 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 924 data |= x; 925 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 926 DELAY(1); 927 } 928 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 929 DELAY(1); 930 931 return (data); 932 } 933 934 static void 935 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 936 { 937 int i; 938 939 /* 940 * Erase/write enable. 941 */ 942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 943 fxp_eeprom_shiftin(sc, 0x4, 3); 944 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 946 DELAY(1); 947 /* 948 * Shift in write opcode, address, data. 949 */ 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 951 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 952 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 953 fxp_eeprom_shiftin(sc, data, 16); 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 955 DELAY(1); 956 /* 957 * Wait for EEPROM to finish up. 958 */ 959 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 960 DELAY(1); 961 for (i = 0; i < 1000; i++) { 962 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 963 break; 964 DELAY(50); 965 } 966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 967 DELAY(1); 968 /* 969 * Erase/write disable. 970 */ 971 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 972 fxp_eeprom_shiftin(sc, 0x4, 3); 973 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 975 DELAY(1); 976 } 977 978 /* 979 * From NetBSD: 980 * 981 * Figure out EEPROM size. 982 * 983 * 559's can have either 64-word or 256-word EEPROMs, the 558 984 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 985 * talks about the existance of 16 to 256 word EEPROMs. 986 * 987 * The only known sizes are 64 and 256, where the 256 version is used 988 * by CardBus cards to store CIS information. 989 * 990 * The address is shifted in msb-to-lsb, and after the last 991 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 992 * after which follows the actual data. We try to detect this zero, by 993 * probing the data-out bit in the EEPROM control register just after 994 * having shifted in a bit. If the bit is zero, we assume we've 995 * shifted enough address bits. The data-out should be tri-state, 996 * before this, which should translate to a logical one. 997 */ 998 static void 999 fxp_autosize_eeprom(struct fxp_softc *sc) 1000 { 1001 1002 /* guess maximum size of 256 words */ 1003 sc->eeprom_size = 8; 1004 1005 /* autosize */ 1006 (void) fxp_eeprom_getword(sc, 0, 1); 1007 } 1008 1009 static void 1010 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1011 { 1012 int i; 1013 1014 for (i = 0; i < words; i++) 1015 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1016 } 1017 1018 static void 1019 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1020 { 1021 int i; 1022 1023 for (i = 0; i < words; i++) 1024 fxp_eeprom_putword(sc, offset + i, data[i]); 1025 } 1026 1027 /* 1028 * Start packet transmission on the interface. 1029 */ 1030 static void 1031 fxp_start(struct ifnet *ifp) 1032 { 1033 struct fxp_softc *sc = ifp->if_softc; 1034 struct fxp_cb_tx *txp; 1035 1036 /* 1037 * See if we need to suspend xmit until the multicast filter 1038 * has been reprogrammed (which can only be done at the head 1039 * of the command chain). 1040 */ 1041 if (sc->need_mcsetup) { 1042 return; 1043 } 1044 1045 txp = NULL; 1046 1047 /* 1048 * We're finished if there is nothing more to add to the list or if 1049 * we're all filled up with buffers to transmit. 1050 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1051 * a NOP command when needed. 1052 */ 1053 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1054 struct mbuf *m, *mb_head; 1055 int segment; 1056 1057 /* 1058 * Grab a packet to transmit. The packet is dequeued, 1059 * once we are sure that we have enough free descriptors. 1060 */ 1061 mb_head = ifq_poll(&ifp->if_snd); 1062 if (mb_head == NULL) 1063 break; 1064 1065 /* 1066 * Get pointer to next available tx desc. 1067 */ 1068 txp = sc->cbl_last->next; 1069 1070 /* 1071 * Go through each of the mbufs in the chain and initialize 1072 * the transmit buffer descriptors with the physical address 1073 * and size of the mbuf. 1074 */ 1075 tbdinit: 1076 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1077 if (m->m_len != 0) { 1078 if (segment == FXP_NTXSEG) 1079 break; 1080 txp->tbd[segment].tb_addr = 1081 vtophys(mtod(m, vm_offset_t)); 1082 txp->tbd[segment].tb_size = m->m_len; 1083 segment++; 1084 } 1085 } 1086 if (m != NULL) { 1087 struct mbuf *mn; 1088 1089 /* 1090 * We ran out of segments. We have to recopy this 1091 * mbuf chain first. Bail out if we can't get the 1092 * new buffers. 1093 */ 1094 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1095 if (mn == NULL) 1096 break; 1097 if (mb_head->m_pkthdr.len > MHLEN) { 1098 MCLGET(mn, MB_DONTWAIT); 1099 if ((mn->m_flags & M_EXT) == 0) { 1100 m_freem(mn); 1101 break; 1102 } 1103 } 1104 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1105 mtod(mn, caddr_t)); 1106 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1107 /* We can transmit the packet, dequeue it. */ 1108 mb_head = ifq_dequeue(&ifp->if_snd); 1109 m_freem(mb_head); 1110 mb_head = mn; 1111 goto tbdinit; 1112 } else { 1113 /* Nothing to worry about, just dequeue. */ 1114 mb_head = ifq_dequeue(&ifp->if_snd); 1115 } 1116 1117 txp->tbd_number = segment; 1118 txp->mb_head = mb_head; 1119 txp->cb_status = 0; 1120 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1121 txp->cb_command = 1122 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1123 FXP_CB_COMMAND_S; 1124 } else { 1125 txp->cb_command = 1126 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1127 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1128 /* 1129 * Set a 5 second timer just in case we don't hear 1130 * from the card again. 1131 */ 1132 ifp->if_timer = 5; 1133 } 1134 txp->tx_threshold = tx_threshold; 1135 1136 /* 1137 * Advance the end of list forward. 1138 */ 1139 1140 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1141 sc->cbl_last = txp; 1142 1143 /* 1144 * Advance the beginning of the list forward if there are 1145 * no other packets queued (when nothing is queued, cbl_first 1146 * sits on the last TxCB that was sent out). 1147 */ 1148 if (sc->tx_queued == 0) 1149 sc->cbl_first = txp; 1150 1151 sc->tx_queued++; 1152 1153 BPF_MTAP(ifp, mb_head); 1154 } 1155 1156 /* 1157 * We're finished. If we added to the list, issue a RESUME to get DMA 1158 * going again if suspended. 1159 */ 1160 if (txp != NULL) { 1161 fxp_scb_wait(sc); 1162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1163 } 1164 } 1165 1166 #ifdef DEVICE_POLLING 1167 1168 static void 1169 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1170 { 1171 struct fxp_softc *sc = ifp->if_softc; 1172 u_int8_t statack; 1173 1174 switch(cmd) { 1175 case POLL_REGISTER: 1176 /* disable interrupts */ 1177 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1178 break; 1179 case POLL_DEREGISTER: 1180 /* enable interrupts */ 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1182 break; 1183 default: 1184 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1185 FXP_SCB_STATACK_FR; 1186 if (cmd == POLL_AND_CHECK_STATUS) { 1187 u_int8_t tmp; 1188 1189 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1190 if (tmp == 0xff || tmp == 0) 1191 return; /* nothing to do */ 1192 tmp &= ~statack; 1193 /* ack what we can */ 1194 if (tmp != 0) 1195 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1196 statack |= tmp; 1197 } 1198 fxp_intr_body(sc, statack, count); 1199 break; 1200 } 1201 } 1202 1203 #endif /* DEVICE_POLLING */ 1204 1205 /* 1206 * Process interface interrupts. 1207 */ 1208 static void 1209 fxp_intr(void *xsc) 1210 { 1211 struct fxp_softc *sc = xsc; 1212 u_int8_t statack; 1213 1214 if (sc->suspended) { 1215 return; 1216 } 1217 1218 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1219 /* 1220 * It should not be possible to have all bits set; the 1221 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1222 * all bits are set, this may indicate that the card has 1223 * been physically ejected, so ignore it. 1224 */ 1225 if (statack == 0xff) 1226 return; 1227 1228 /* 1229 * First ACK all the interrupts in this pass. 1230 */ 1231 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1232 fxp_intr_body(sc, statack, -1); 1233 } 1234 } 1235 1236 static void 1237 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1238 { 1239 struct ifnet *ifp = &sc->arpcom.ac_if; 1240 struct mbuf *m; 1241 struct fxp_rfa *rfa; 1242 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1243 1244 if (rnr) 1245 fxp_rnr++; 1246 #ifdef DEVICE_POLLING 1247 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1248 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1249 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1250 rnr = 1; 1251 } 1252 #endif 1253 1254 /* 1255 * Free any finished transmit mbuf chains. 1256 * 1257 * Handle the CNA event likt a CXTNO event. It used to 1258 * be that this event (control unit not ready) was not 1259 * encountered, but it is now with the SMPng modifications. 1260 * The exact sequence of events that occur when the interface 1261 * is brought up are different now, and if this event 1262 * goes unhandled, the configuration/rxfilter setup sequence 1263 * can stall for several seconds. The result is that no 1264 * packets go out onto the wire for about 5 to 10 seconds 1265 * after the interface is ifconfig'ed for the first time. 1266 */ 1267 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1268 struct fxp_cb_tx *txp; 1269 1270 for (txp = sc->cbl_first; sc->tx_queued && 1271 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1272 txp = txp->next) { 1273 if ((m = txp->mb_head) != NULL) { 1274 txp->mb_head = NULL; 1275 sc->tx_queued--; 1276 m_freem(m); 1277 } else { 1278 sc->tx_queued--; 1279 } 1280 } 1281 sc->cbl_first = txp; 1282 ifp->if_timer = 0; 1283 if (sc->tx_queued == 0) { 1284 if (sc->need_mcsetup) 1285 fxp_mc_setup(sc); 1286 } 1287 /* 1288 * Try to start more packets transmitting. 1289 */ 1290 if (!ifq_is_empty(&ifp->if_snd)) 1291 (*ifp->if_start)(ifp); 1292 } 1293 1294 /* 1295 * Just return if nothing happened on the receive side. 1296 */ 1297 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1298 return; 1299 1300 /* 1301 * Process receiver interrupts. If a no-resource (RNR) 1302 * condition exists, get whatever packets we can and 1303 * re-start the receiver. 1304 * 1305 * When using polling, we do not process the list to completion, 1306 * so when we get an RNR interrupt we must defer the restart 1307 * until we hit the last buffer with the C bit set. 1308 * If we run out of cycles and rfa_headm has the C bit set, 1309 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1310 * that the info will be used in the subsequent polling cycle. 1311 */ 1312 for (;;) { 1313 m = sc->rfa_headm; 1314 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1315 RFA_ALIGNMENT_FUDGE); 1316 1317 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1318 if (count >= 0 && count-- == 0) { 1319 if (rnr) { 1320 /* Defer RNR processing until the next time. */ 1321 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1322 rnr = 0; 1323 } 1324 break; 1325 } 1326 #endif /* DEVICE_POLLING */ 1327 1328 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1329 break; 1330 1331 /* 1332 * Remove first packet from the chain. 1333 */ 1334 sc->rfa_headm = m->m_next; 1335 m->m_next = NULL; 1336 1337 /* 1338 * Add a new buffer to the receive chain. 1339 * If this fails, the old buffer is recycled 1340 * instead. 1341 */ 1342 if (fxp_add_rfabuf(sc, m) == 0) { 1343 int total_len; 1344 1345 /* 1346 * Fetch packet length (the top 2 bits of 1347 * actual_size are flags set by the controller 1348 * upon completion), and drop the packet in case 1349 * of bogus length or CRC errors. 1350 */ 1351 total_len = rfa->actual_size & 0x3fff; 1352 if (total_len < sizeof(struct ether_header) || 1353 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1354 sizeof(struct fxp_rfa) || 1355 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1356 m_freem(m); 1357 continue; 1358 } 1359 m->m_pkthdr.len = m->m_len = total_len; 1360 (*ifp->if_input)(ifp, m); 1361 } 1362 } 1363 if (rnr) { 1364 fxp_scb_wait(sc); 1365 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1366 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1367 RFA_ALIGNMENT_FUDGE); 1368 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1369 } 1370 } 1371 1372 /* 1373 * Update packet in/out/collision statistics. The i82557 doesn't 1374 * allow you to access these counters without doing a fairly 1375 * expensive DMA to get _all_ of the statistics it maintains, so 1376 * we do this operation here only once per second. The statistics 1377 * counters in the kernel are updated from the previous dump-stats 1378 * DMA and then a new dump-stats DMA is started. The on-chip 1379 * counters are zeroed when the DMA completes. If we can't start 1380 * the DMA immediately, we don't wait - we just prepare to read 1381 * them again next time. 1382 */ 1383 static void 1384 fxp_tick(void *xsc) 1385 { 1386 struct fxp_softc *sc = xsc; 1387 struct ifnet *ifp = &sc->arpcom.ac_if; 1388 struct fxp_stats *sp = sc->fxp_stats; 1389 struct fxp_cb_tx *txp; 1390 struct mbuf *m; 1391 int s; 1392 1393 ifp->if_opackets += sp->tx_good; 1394 ifp->if_collisions += sp->tx_total_collisions; 1395 if (sp->rx_good) { 1396 ifp->if_ipackets += sp->rx_good; 1397 sc->rx_idle_secs = 0; 1398 } else { 1399 /* 1400 * Receiver's been idle for another second. 1401 */ 1402 sc->rx_idle_secs++; 1403 } 1404 ifp->if_ierrors += 1405 sp->rx_crc_errors + 1406 sp->rx_alignment_errors + 1407 sp->rx_rnr_errors + 1408 sp->rx_overrun_errors; 1409 /* 1410 * If any transmit underruns occured, bump up the transmit 1411 * threshold by another 512 bytes (64 * 8). 1412 */ 1413 if (sp->tx_underruns) { 1414 ifp->if_oerrors += sp->tx_underruns; 1415 if (tx_threshold < 192) 1416 tx_threshold += 64; 1417 } 1418 s = splimp(); 1419 /* 1420 * Release any xmit buffers that have completed DMA. This isn't 1421 * strictly necessary to do here, but it's advantagous for mbufs 1422 * with external storage to be released in a timely manner rather 1423 * than being defered for a potentially long time. This limits 1424 * the delay to a maximum of one second. 1425 */ 1426 for (txp = sc->cbl_first; sc->tx_queued && 1427 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1428 txp = txp->next) { 1429 if ((m = txp->mb_head) != NULL) { 1430 txp->mb_head = NULL; 1431 sc->tx_queued--; 1432 m_freem(m); 1433 } else { 1434 sc->tx_queued--; 1435 } 1436 } 1437 sc->cbl_first = txp; 1438 /* 1439 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1440 * then assume the receiver has locked up and attempt to clear 1441 * the condition by reprogramming the multicast filter. This is 1442 * a work-around for a bug in the 82557 where the receiver locks 1443 * up if it gets certain types of garbage in the syncronization 1444 * bits prior to the packet header. This bug is supposed to only 1445 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1446 * mode as well (perhaps due to a 10/100 speed transition). 1447 */ 1448 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1449 sc->rx_idle_secs = 0; 1450 fxp_mc_setup(sc); 1451 } 1452 /* 1453 * If there is no pending command, start another stats 1454 * dump. Otherwise punt for now. 1455 */ 1456 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1457 /* 1458 * Start another stats dump. 1459 */ 1460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1461 } else { 1462 /* 1463 * A previous command is still waiting to be accepted. 1464 * Just zero our copy of the stats and wait for the 1465 * next timer event to update them. 1466 */ 1467 sp->tx_good = 0; 1468 sp->tx_underruns = 0; 1469 sp->tx_total_collisions = 0; 1470 1471 sp->rx_good = 0; 1472 sp->rx_crc_errors = 0; 1473 sp->rx_alignment_errors = 0; 1474 sp->rx_rnr_errors = 0; 1475 sp->rx_overrun_errors = 0; 1476 } 1477 if (sc->miibus != NULL) 1478 mii_tick(device_get_softc(sc->miibus)); 1479 splx(s); 1480 /* 1481 * Schedule another timeout one second from now. 1482 */ 1483 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1484 } 1485 1486 /* 1487 * Stop the interface. Cancels the statistics updater and resets 1488 * the interface. 1489 */ 1490 static void 1491 fxp_stop(struct fxp_softc *sc) 1492 { 1493 struct ifnet *ifp = &sc->arpcom.ac_if; 1494 struct fxp_cb_tx *txp; 1495 int i; 1496 1497 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1498 ifp->if_timer = 0; 1499 1500 /* 1501 * Cancel stats updater. 1502 */ 1503 callout_stop(&sc->fxp_stat_timer); 1504 1505 /* 1506 * Issue software reset, which also unloads the microcode. 1507 */ 1508 sc->flags &= ~FXP_FLAG_UCODE; 1509 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1510 DELAY(50); 1511 1512 /* 1513 * Release any xmit buffers. 1514 */ 1515 txp = sc->cbl_base; 1516 if (txp != NULL) { 1517 for (i = 0; i < FXP_NTXCB; i++) { 1518 if (txp[i].mb_head != NULL) { 1519 m_freem(txp[i].mb_head); 1520 txp[i].mb_head = NULL; 1521 } 1522 } 1523 } 1524 sc->tx_queued = 0; 1525 1526 /* 1527 * Free all the receive buffers then reallocate/reinitialize 1528 */ 1529 if (sc->rfa_headm != NULL) 1530 m_freem(sc->rfa_headm); 1531 sc->rfa_headm = NULL; 1532 sc->rfa_tailm = NULL; 1533 for (i = 0; i < FXP_NRFABUFS; i++) { 1534 if (fxp_add_rfabuf(sc, NULL) != 0) { 1535 /* 1536 * This "can't happen" - we're at splimp() 1537 * and we just freed all the buffers we need 1538 * above. 1539 */ 1540 panic("fxp_stop: no buffers!"); 1541 } 1542 } 1543 } 1544 1545 /* 1546 * Watchdog/transmission transmit timeout handler. Called when a 1547 * transmission is started on the interface, but no interrupt is 1548 * received before the timeout. This usually indicates that the 1549 * card has wedged for some reason. 1550 */ 1551 static void 1552 fxp_watchdog(struct ifnet *ifp) 1553 { 1554 struct fxp_softc *sc = ifp->if_softc; 1555 1556 device_printf(sc->dev, "device timeout\n"); 1557 ifp->if_oerrors++; 1558 1559 fxp_init(sc); 1560 } 1561 1562 static void 1563 fxp_init(void *xsc) 1564 { 1565 struct fxp_softc *sc = xsc; 1566 struct ifnet *ifp = &sc->arpcom.ac_if; 1567 struct fxp_cb_config *cbp; 1568 struct fxp_cb_ias *cb_ias; 1569 struct fxp_cb_tx *txp; 1570 struct fxp_cb_mcs *mcsp; 1571 int i, prm, s; 1572 1573 s = splimp(); 1574 /* 1575 * Cancel any pending I/O 1576 */ 1577 fxp_stop(sc); 1578 1579 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1580 1581 /* 1582 * Initialize base of CBL and RFA memory. Loading with zero 1583 * sets it up for regular linear addressing. 1584 */ 1585 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1587 1588 fxp_scb_wait(sc); 1589 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1590 1591 /* 1592 * Initialize base of dump-stats buffer. 1593 */ 1594 fxp_scb_wait(sc); 1595 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1597 1598 /* 1599 * Attempt to load microcode if requested. 1600 */ 1601 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1602 fxp_load_ucode(sc); 1603 1604 /* 1605 * Initialize the multicast address list. 1606 */ 1607 if (fxp_mc_addrs(sc)) { 1608 mcsp = sc->mcsp; 1609 mcsp->cb_status = 0; 1610 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1611 mcsp->link_addr = -1; 1612 /* 1613 * Start the multicast setup command. 1614 */ 1615 fxp_scb_wait(sc); 1616 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1617 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1618 /* ...and wait for it to complete. */ 1619 fxp_dma_wait(&mcsp->cb_status, sc); 1620 } 1621 1622 /* 1623 * We temporarily use memory that contains the TxCB list to 1624 * construct the config CB. The TxCB list memory is rebuilt 1625 * later. 1626 */ 1627 cbp = (struct fxp_cb_config *) sc->cbl_base; 1628 1629 /* 1630 * This bcopy is kind of disgusting, but there are a bunch of must be 1631 * zero and must be one bits in this structure and this is the easiest 1632 * way to initialize them all to proper values. 1633 */ 1634 bcopy(fxp_cb_config_template, 1635 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1636 sizeof(fxp_cb_config_template)); 1637 1638 cbp->cb_status = 0; 1639 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1640 cbp->link_addr = -1; /* (no) next command */ 1641 cbp->byte_count = 22; /* (22) bytes to config */ 1642 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1643 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1644 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1645 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1646 cbp->type_enable = 0; /* actually reserved */ 1647 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1648 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1649 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1650 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1651 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1652 cbp->late_scb = 0; /* (don't) defer SCB update */ 1653 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1654 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1655 cbp->ci_int = 1; /* interrupt on CU idle */ 1656 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1657 cbp->ext_stats_dis = 1; /* disable extended counters */ 1658 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1659 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1660 cbp->disc_short_rx = !prm; /* discard short packets */ 1661 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1662 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1663 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1664 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1665 cbp->csma_dis = 0; /* (don't) disable link */ 1666 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1667 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1668 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1669 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1670 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1671 cbp->nsai = 1; /* (don't) disable source addr insert */ 1672 cbp->preamble_length = 2; /* (7 byte) preamble */ 1673 cbp->loopback = 0; /* (don't) loopback */ 1674 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1675 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1676 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1677 cbp->promiscuous = prm; /* promiscuous mode */ 1678 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1679 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1680 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1681 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1682 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1683 1684 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1685 cbp->padding = 1; /* (do) pad short tx packets */ 1686 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1687 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1688 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1689 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1690 /* must set wake_en in PMCSR also */ 1691 cbp->force_fdx = 0; /* (don't) force full duplex */ 1692 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1693 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1694 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1695 1696 if (sc->revision == FXP_REV_82557) { 1697 /* 1698 * The 82557 has no hardware flow control, the values 1699 * below are the defaults for the chip. 1700 */ 1701 cbp->fc_delay_lsb = 0; 1702 cbp->fc_delay_msb = 0x40; 1703 cbp->pri_fc_thresh = 3; 1704 cbp->tx_fc_dis = 0; 1705 cbp->rx_fc_restop = 0; 1706 cbp->rx_fc_restart = 0; 1707 cbp->fc_filter = 0; 1708 cbp->pri_fc_loc = 1; 1709 } else { 1710 cbp->fc_delay_lsb = 0x1f; 1711 cbp->fc_delay_msb = 0x01; 1712 cbp->pri_fc_thresh = 3; 1713 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1714 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1715 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1716 cbp->fc_filter = !prm; /* drop FC frames to host */ 1717 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1718 } 1719 1720 /* 1721 * Start the config command/DMA. 1722 */ 1723 fxp_scb_wait(sc); 1724 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1726 /* ...and wait for it to complete. */ 1727 fxp_dma_wait(&cbp->cb_status, sc); 1728 1729 /* 1730 * Now initialize the station address. Temporarily use the TxCB 1731 * memory area like we did above for the config CB. 1732 */ 1733 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1734 cb_ias->cb_status = 0; 1735 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1736 cb_ias->link_addr = -1; 1737 bcopy(sc->arpcom.ac_enaddr, 1738 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1739 sizeof(sc->arpcom.ac_enaddr)); 1740 1741 /* 1742 * Start the IAS (Individual Address Setup) command/DMA. 1743 */ 1744 fxp_scb_wait(sc); 1745 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1746 /* ...and wait for it to complete. */ 1747 fxp_dma_wait(&cb_ias->cb_status, sc); 1748 1749 /* 1750 * Initialize transmit control block (TxCB) list. 1751 */ 1752 1753 txp = sc->cbl_base; 1754 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1755 for (i = 0; i < FXP_NTXCB; i++) { 1756 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1757 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1758 txp[i].link_addr = 1759 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1760 if (sc->flags & FXP_FLAG_EXT_TXCB) 1761 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1762 else 1763 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1764 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1765 } 1766 /* 1767 * Set the suspend flag on the first TxCB and start the control 1768 * unit. It will execute the NOP and then suspend. 1769 */ 1770 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1771 sc->cbl_first = sc->cbl_last = txp; 1772 sc->tx_queued = 1; 1773 1774 fxp_scb_wait(sc); 1775 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1776 1777 /* 1778 * Initialize receiver buffer area - RFA. 1779 */ 1780 fxp_scb_wait(sc); 1781 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1782 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1783 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1784 1785 /* 1786 * Set current media. 1787 */ 1788 if (sc->miibus != NULL) 1789 mii_mediachg(device_get_softc(sc->miibus)); 1790 1791 ifp->if_flags |= IFF_RUNNING; 1792 ifp->if_flags &= ~IFF_OACTIVE; 1793 1794 /* 1795 * Enable interrupts. 1796 */ 1797 #ifdef DEVICE_POLLING 1798 /* 1799 * ... but only do that if we are not polling. And because (presumably) 1800 * the default is interrupts on, we need to disable them explicitly! 1801 */ 1802 if ( ifp->if_flags & IFF_POLLING ) 1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1804 else 1805 #endif /* DEVICE_POLLING */ 1806 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1807 splx(s); 1808 1809 /* 1810 * Start stats updater. 1811 */ 1812 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1813 } 1814 1815 static int 1816 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1817 { 1818 1819 return (0); 1820 } 1821 1822 static void 1823 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1824 { 1825 1826 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1827 } 1828 1829 /* 1830 * Change media according to request. 1831 */ 1832 static int 1833 fxp_ifmedia_upd(struct ifnet *ifp) 1834 { 1835 struct fxp_softc *sc = ifp->if_softc; 1836 struct mii_data *mii; 1837 1838 mii = device_get_softc(sc->miibus); 1839 mii_mediachg(mii); 1840 return (0); 1841 } 1842 1843 /* 1844 * Notify the world which media we're using. 1845 */ 1846 static void 1847 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1848 { 1849 struct fxp_softc *sc = ifp->if_softc; 1850 struct mii_data *mii; 1851 1852 mii = device_get_softc(sc->miibus); 1853 mii_pollstat(mii); 1854 ifmr->ifm_active = mii->mii_media_active; 1855 ifmr->ifm_status = mii->mii_media_status; 1856 1857 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1858 sc->cu_resume_bug = 1; 1859 else 1860 sc->cu_resume_bug = 0; 1861 } 1862 1863 /* 1864 * Add a buffer to the end of the RFA buffer list. 1865 * Return 0 if successful, 1 for failure. A failure results in 1866 * adding the 'oldm' (if non-NULL) on to the end of the list - 1867 * tossing out its old contents and recycling it. 1868 * The RFA struct is stuck at the beginning of mbuf cluster and the 1869 * data pointer is fixed up to point just past it. 1870 */ 1871 static int 1872 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1873 { 1874 u_int32_t v; 1875 struct mbuf *m; 1876 struct fxp_rfa *rfa, *p_rfa; 1877 1878 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1879 if (m == NULL) { /* try to recycle the old mbuf instead */ 1880 if (oldm == NULL) 1881 return 1; 1882 m = oldm; 1883 m->m_data = m->m_ext.ext_buf; 1884 } 1885 1886 /* 1887 * Move the data pointer up so that the incoming data packet 1888 * will be 32-bit aligned. 1889 */ 1890 m->m_data += RFA_ALIGNMENT_FUDGE; 1891 1892 /* 1893 * Get a pointer to the base of the mbuf cluster and move 1894 * data start past it. 1895 */ 1896 rfa = mtod(m, struct fxp_rfa *); 1897 m->m_data += sizeof(struct fxp_rfa); 1898 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1899 1900 /* 1901 * Initialize the rest of the RFA. Note that since the RFA 1902 * is misaligned, we cannot store values directly. Instead, 1903 * we use an optimized, inline copy. 1904 */ 1905 1906 rfa->rfa_status = 0; 1907 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1908 rfa->actual_size = 0; 1909 1910 v = -1; 1911 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1912 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1913 1914 /* 1915 * If there are other buffers already on the list, attach this 1916 * one to the end by fixing up the tail to point to this one. 1917 */ 1918 if (sc->rfa_headm != NULL) { 1919 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1920 RFA_ALIGNMENT_FUDGE); 1921 sc->rfa_tailm->m_next = m; 1922 v = vtophys(rfa); 1923 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1924 p_rfa->rfa_control = 0; 1925 } else { 1926 sc->rfa_headm = m; 1927 } 1928 sc->rfa_tailm = m; 1929 1930 return (m == oldm); 1931 } 1932 1933 static volatile int 1934 fxp_miibus_readreg(device_t dev, int phy, int reg) 1935 { 1936 struct fxp_softc *sc = device_get_softc(dev); 1937 int count = 10000; 1938 int value; 1939 1940 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1941 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1942 1943 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1944 && count--) 1945 DELAY(10); 1946 1947 if (count <= 0) 1948 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1949 1950 return (value & 0xffff); 1951 } 1952 1953 static void 1954 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1955 { 1956 struct fxp_softc *sc = device_get_softc(dev); 1957 int count = 10000; 1958 1959 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1960 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1961 (value & 0xffff)); 1962 1963 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1964 count--) 1965 DELAY(10); 1966 1967 if (count <= 0) 1968 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1969 } 1970 1971 static int 1972 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1973 { 1974 struct fxp_softc *sc = ifp->if_softc; 1975 struct ifreq *ifr = (struct ifreq *)data; 1976 struct mii_data *mii; 1977 int s, error = 0; 1978 1979 s = splimp(); 1980 1981 switch (command) { 1982 1983 case SIOCSIFFLAGS: 1984 if (ifp->if_flags & IFF_ALLMULTI) 1985 sc->flags |= FXP_FLAG_ALL_MCAST; 1986 else 1987 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1988 1989 /* 1990 * If interface is marked up and not running, then start it. 1991 * If it is marked down and running, stop it. 1992 * XXX If it's up then re-initialize it. This is so flags 1993 * such as IFF_PROMISC are handled. 1994 */ 1995 if (ifp->if_flags & IFF_UP) { 1996 fxp_init(sc); 1997 } else { 1998 if (ifp->if_flags & IFF_RUNNING) 1999 fxp_stop(sc); 2000 } 2001 break; 2002 2003 case SIOCADDMULTI: 2004 case SIOCDELMULTI: 2005 if (ifp->if_flags & IFF_ALLMULTI) 2006 sc->flags |= FXP_FLAG_ALL_MCAST; 2007 else 2008 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2009 /* 2010 * Multicast list has changed; set the hardware filter 2011 * accordingly. 2012 */ 2013 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2014 fxp_mc_setup(sc); 2015 /* 2016 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2017 * again rather than else {}. 2018 */ 2019 if (sc->flags & FXP_FLAG_ALL_MCAST) 2020 fxp_init(sc); 2021 error = 0; 2022 break; 2023 2024 case SIOCSIFMEDIA: 2025 case SIOCGIFMEDIA: 2026 if (sc->miibus != NULL) { 2027 mii = device_get_softc(sc->miibus); 2028 error = ifmedia_ioctl(ifp, ifr, 2029 &mii->mii_media, command); 2030 } else { 2031 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2032 } 2033 break; 2034 2035 default: 2036 error = ether_ioctl(ifp, command, data); 2037 break; 2038 } 2039 splx(s); 2040 return (error); 2041 } 2042 2043 /* 2044 * Fill in the multicast address list and return number of entries. 2045 */ 2046 static int 2047 fxp_mc_addrs(struct fxp_softc *sc) 2048 { 2049 struct fxp_cb_mcs *mcsp = sc->mcsp; 2050 struct ifnet *ifp = &sc->arpcom.ac_if; 2051 struct ifmultiaddr *ifma; 2052 int nmcasts; 2053 2054 nmcasts = 0; 2055 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2056 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2057 if (ifma->ifma_addr->sa_family != AF_LINK) 2058 continue; 2059 if (nmcasts >= MAXMCADDR) { 2060 sc->flags |= FXP_FLAG_ALL_MCAST; 2061 nmcasts = 0; 2062 break; 2063 } 2064 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2065 (void *)(uintptr_t)(volatile void *) 2066 &sc->mcsp->mc_addr[nmcasts][0], 6); 2067 nmcasts++; 2068 } 2069 } 2070 mcsp->mc_cnt = nmcasts * 6; 2071 return (nmcasts); 2072 } 2073 2074 /* 2075 * Program the multicast filter. 2076 * 2077 * We have an artificial restriction that the multicast setup command 2078 * must be the first command in the chain, so we take steps to ensure 2079 * this. By requiring this, it allows us to keep up the performance of 2080 * the pre-initialized command ring (esp. link pointers) by not actually 2081 * inserting the mcsetup command in the ring - i.e. its link pointer 2082 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2083 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2084 * lead into the regular TxCB ring when it completes. 2085 * 2086 * This function must be called at splimp. 2087 */ 2088 static void 2089 fxp_mc_setup(struct fxp_softc *sc) 2090 { 2091 struct fxp_cb_mcs *mcsp = sc->mcsp; 2092 struct ifnet *ifp = &sc->arpcom.ac_if; 2093 int count; 2094 2095 /* 2096 * If there are queued commands, we must wait until they are all 2097 * completed. If we are already waiting, then add a NOP command 2098 * with interrupt option so that we're notified when all commands 2099 * have been completed - fxp_start() ensures that no additional 2100 * TX commands will be added when need_mcsetup is true. 2101 */ 2102 if (sc->tx_queued) { 2103 struct fxp_cb_tx *txp; 2104 2105 /* 2106 * need_mcsetup will be true if we are already waiting for the 2107 * NOP command to be completed (see below). In this case, bail. 2108 */ 2109 if (sc->need_mcsetup) 2110 return; 2111 sc->need_mcsetup = 1; 2112 2113 /* 2114 * Add a NOP command with interrupt so that we are notified 2115 * when all TX commands have been processed. 2116 */ 2117 txp = sc->cbl_last->next; 2118 txp->mb_head = NULL; 2119 txp->cb_status = 0; 2120 txp->cb_command = FXP_CB_COMMAND_NOP | 2121 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2122 /* 2123 * Advance the end of list forward. 2124 */ 2125 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2126 sc->cbl_last = txp; 2127 sc->tx_queued++; 2128 /* 2129 * Issue a resume in case the CU has just suspended. 2130 */ 2131 fxp_scb_wait(sc); 2132 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2133 /* 2134 * Set a 5 second timer just in case we don't hear from the 2135 * card again. 2136 */ 2137 ifp->if_timer = 5; 2138 2139 return; 2140 } 2141 sc->need_mcsetup = 0; 2142 2143 /* 2144 * Initialize multicast setup descriptor. 2145 */ 2146 mcsp->next = sc->cbl_base; 2147 mcsp->mb_head = NULL; 2148 mcsp->cb_status = 0; 2149 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2150 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2151 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2152 (void) fxp_mc_addrs(sc); 2153 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2154 sc->tx_queued = 1; 2155 2156 /* 2157 * Wait until command unit is not active. This should never 2158 * be the case when nothing is queued, but make sure anyway. 2159 */ 2160 count = 100; 2161 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2162 FXP_SCB_CUS_ACTIVE && --count) 2163 DELAY(10); 2164 if (count == 0) { 2165 device_printf(sc->dev, "command queue timeout\n"); 2166 return; 2167 } 2168 2169 /* 2170 * Start the multicast setup command. 2171 */ 2172 fxp_scb_wait(sc); 2173 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2174 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2175 2176 ifp->if_timer = 2; 2177 return; 2178 } 2179 2180 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2181 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2182 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2183 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2184 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2185 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2186 2187 #define UCODE(x) x, sizeof(x) 2188 2189 struct ucode { 2190 u_int32_t revision; 2191 u_int32_t *ucode; 2192 int length; 2193 u_short int_delay_offset; 2194 u_short bundle_max_offset; 2195 } ucode_table[] = { 2196 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2197 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2198 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2199 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2201 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2202 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2203 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2204 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2205 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2206 { 0, NULL, 0, 0, 0 } 2207 }; 2208 2209 static void 2210 fxp_load_ucode(struct fxp_softc *sc) 2211 { 2212 struct ucode *uc; 2213 struct fxp_cb_ucode *cbp; 2214 2215 for (uc = ucode_table; uc->ucode != NULL; uc++) 2216 if (sc->revision == uc->revision) 2217 break; 2218 if (uc->ucode == NULL) 2219 return; 2220 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2221 cbp->cb_status = 0; 2222 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2223 cbp->link_addr = -1; /* (no) next command */ 2224 memcpy(cbp->ucode, uc->ucode, uc->length); 2225 if (uc->int_delay_offset) 2226 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2227 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2228 if (uc->bundle_max_offset) 2229 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2230 sc->tunable_bundle_max; 2231 /* 2232 * Download the ucode to the chip. 2233 */ 2234 fxp_scb_wait(sc); 2235 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2236 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2237 /* ...and wait for it to complete. */ 2238 fxp_dma_wait(&cbp->cb_status, sc); 2239 device_printf(sc->dev, 2240 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2241 sc->tunable_int_delay, 2242 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2243 sc->flags |= FXP_FLAG_UCODE; 2244 } 2245 2246 static int 2247 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2248 { 2249 int error, value; 2250 2251 value = *(int *)arg1; 2252 error = sysctl_handle_int(oidp, &value, 0, req); 2253 if (error || !req->newptr) 2254 return (error); 2255 if (value < low || value > high) 2256 return (EINVAL); 2257 *(int *)arg1 = value; 2258 return (0); 2259 } 2260 2261 /* 2262 * Interrupt delay is expressed in microseconds, a multiplier is used 2263 * to convert this to the appropriate clock ticks before using. 2264 */ 2265 static int 2266 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2267 { 2268 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2269 } 2270 2271 static int 2272 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2273 { 2274 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2275 } 2276