1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.20 2005/01/31 15:39:12 joerg Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 170 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 171 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 174 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 176 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 179 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 180 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 183 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 185 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 186 { 0, -1, NULL }, 187 }; 188 189 static int fxp_probe(device_t dev); 190 static int fxp_attach(device_t dev); 191 static int fxp_detach(device_t dev); 192 static int fxp_shutdown(device_t dev); 193 static int fxp_suspend(device_t dev); 194 static int fxp_resume(device_t dev); 195 196 static void fxp_intr(void *xsc); 197 static void fxp_intr_body(struct fxp_softc *sc, 198 u_int8_t statack, int count); 199 200 static void fxp_init(void *xsc); 201 static void fxp_tick(void *xsc); 202 static void fxp_powerstate_d0(device_t dev); 203 static void fxp_start(struct ifnet *ifp); 204 static void fxp_stop(struct fxp_softc *sc); 205 static void fxp_release(struct fxp_softc *sc); 206 static int fxp_ioctl(struct ifnet *ifp, u_long command, 207 caddr_t data, struct ucred *); 208 static void fxp_watchdog(struct ifnet *ifp); 209 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 210 static int fxp_mc_addrs(struct fxp_softc *sc); 211 static void fxp_mc_setup(struct fxp_softc *sc); 212 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 213 int autosize); 214 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 215 u_int16_t data); 216 static void fxp_autosize_eeprom(struct fxp_softc *sc); 217 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 218 int offset, int words); 219 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 220 int offset, int words); 221 static int fxp_ifmedia_upd(struct ifnet *ifp); 222 static void fxp_ifmedia_sts(struct ifnet *ifp, 223 struct ifmediareq *ifmr); 224 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 225 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 226 struct ifmediareq *ifmr); 227 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 228 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 229 int value); 230 static void fxp_load_ucode(struct fxp_softc *sc); 231 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 232 int low, int high); 233 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 234 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 235 static __inline void fxp_lwcopy(volatile u_int32_t *src, 236 volatile u_int32_t *dst); 237 static __inline void fxp_scb_wait(struct fxp_softc *sc); 238 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 239 static __inline void fxp_dma_wait(volatile u_int16_t *status, 240 struct fxp_softc *sc); 241 242 static device_method_t fxp_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, fxp_probe), 245 DEVMETHOD(device_attach, fxp_attach), 246 DEVMETHOD(device_detach, fxp_detach), 247 DEVMETHOD(device_shutdown, fxp_shutdown), 248 DEVMETHOD(device_suspend, fxp_suspend), 249 DEVMETHOD(device_resume, fxp_resume), 250 251 /* MII interface */ 252 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 253 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 254 255 { 0, 0 } 256 }; 257 258 static driver_t fxp_driver = { 259 "fxp", 260 fxp_methods, 261 sizeof(struct fxp_softc), 262 }; 263 264 static devclass_t fxp_devclass; 265 266 DECLARE_DUMMY_MODULE(if_fxp); 267 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 268 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 269 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 270 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 271 272 static int fxp_rnr; 273 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 274 275 /* 276 * Inline function to copy a 16-bit aligned 32-bit quantity. 277 */ 278 static __inline void 279 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 280 { 281 #ifdef __i386__ 282 *dst = *src; 283 #else 284 volatile u_int16_t *a = (volatile u_int16_t *)src; 285 volatile u_int16_t *b = (volatile u_int16_t *)dst; 286 287 b[0] = a[0]; 288 b[1] = a[1]; 289 #endif 290 } 291 292 /* 293 * Wait for the previous command to be accepted (but not necessarily 294 * completed). 295 */ 296 static __inline void 297 fxp_scb_wait(struct fxp_softc *sc) 298 { 299 int i = 10000; 300 301 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 302 DELAY(2); 303 if (i == 0) 304 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 305 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 306 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 307 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 308 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 309 } 310 311 static __inline void 312 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 313 { 314 315 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 317 fxp_scb_wait(sc); 318 } 319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 320 } 321 322 static __inline void 323 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 324 { 325 int i = 10000; 326 327 while (!(*status & FXP_CB_STATUS_C) && --i) 328 DELAY(2); 329 if (i == 0) 330 device_printf(sc->dev, "DMA timeout\n"); 331 } 332 333 /* 334 * Return identification string if this is device is ours. 335 */ 336 static int 337 fxp_probe(device_t dev) 338 { 339 u_int16_t devid; 340 u_int8_t revid; 341 struct fxp_ident *ident; 342 343 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 344 devid = pci_get_device(dev); 345 revid = pci_get_revid(dev); 346 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 347 if (ident->devid == devid && 348 (ident->revid == revid || ident->revid == -1)) { 349 device_set_desc(dev, ident->name); 350 return (0); 351 } 352 } 353 } 354 return (ENXIO); 355 } 356 357 static void 358 fxp_powerstate_d0(device_t dev) 359 { 360 u_int32_t iobase, membase, irq; 361 362 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 363 /* Save important PCI config data. */ 364 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 365 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 366 irq = pci_read_config(dev, PCIR_INTLINE, 4); 367 368 /* Reset the power state. */ 369 device_printf(dev, "chip is in D%d power mode " 370 "-- setting to D0\n", pci_get_powerstate(dev)); 371 372 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 373 374 /* Restore PCI config data. */ 375 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 376 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 377 pci_write_config(dev, PCIR_INTLINE, irq, 4); 378 } 379 } 380 381 static int 382 fxp_attach(device_t dev) 383 { 384 int error = 0; 385 struct fxp_softc *sc = device_get_softc(dev); 386 struct ifnet *ifp; 387 u_int32_t val; 388 u_int16_t data; 389 int i, rid, m1, m2, prefer_iomap; 390 int s; 391 392 bzero(sc, sizeof(*sc)); 393 sc->dev = dev; 394 callout_init(&sc->fxp_stat_timer); 395 sysctl_ctx_init(&sc->sysctl_ctx); 396 397 s = splimp(); 398 399 /* 400 * Enable bus mastering. Enable memory space too, in case 401 * BIOS/Prom forgot about it. 402 */ 403 val = pci_read_config(dev, PCIR_COMMAND, 2); 404 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 405 pci_write_config(dev, PCIR_COMMAND, val, 2); 406 val = pci_read_config(dev, PCIR_COMMAND, 2); 407 408 fxp_powerstate_d0(dev); 409 410 /* 411 * Figure out which we should try first - memory mapping or i/o mapping? 412 * We default to memory mapping. Then we accept an override from the 413 * command line. Then we check to see which one is enabled. 414 */ 415 m1 = PCIM_CMD_MEMEN; 416 m2 = PCIM_CMD_PORTEN; 417 prefer_iomap = 0; 418 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 419 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 420 m1 = PCIM_CMD_PORTEN; 421 m2 = PCIM_CMD_MEMEN; 422 } 423 424 if (val & m1) { 425 sc->rtp = 426 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 427 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 428 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 429 0, ~0, 1, RF_ACTIVE); 430 } 431 if (sc->mem == NULL && (val & m2)) { 432 sc->rtp = 433 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 434 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 435 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 436 0, ~0, 1, RF_ACTIVE); 437 } 438 439 if (!sc->mem) { 440 device_printf(dev, "could not map device registers\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 if (bootverbose) { 445 device_printf(dev, "using %s space register mapping\n", 446 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 447 } 448 449 sc->sc_st = rman_get_bustag(sc->mem); 450 sc->sc_sh = rman_get_bushandle(sc->mem); 451 452 /* 453 * Allocate our interrupt. 454 */ 455 rid = 0; 456 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 457 RF_SHAREABLE | RF_ACTIVE); 458 if (sc->irq == NULL) { 459 device_printf(dev, "could not map interrupt\n"); 460 error = ENXIO; 461 goto fail; 462 } 463 464 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 465 fxp_intr, sc, &sc->ih); 466 if (error) { 467 device_printf(dev, "could not setup irq\n"); 468 goto fail; 469 } 470 471 /* 472 * Reset to a stable state. 473 */ 474 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 475 DELAY(10); 476 477 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 478 M_DEVBUF, M_WAITOK | M_ZERO); 479 480 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 481 M_WAITOK | M_ZERO); 482 483 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 484 485 /* 486 * Pre-allocate our receive buffers. 487 */ 488 for (i = 0; i < FXP_NRFABUFS; i++) { 489 if (fxp_add_rfabuf(sc, NULL) != 0) { 490 goto failmem; 491 } 492 } 493 494 /* 495 * Find out how large of an SEEPROM we have. 496 */ 497 fxp_autosize_eeprom(sc); 498 499 /* 500 * Determine whether we must use the 503 serial interface. 501 */ 502 fxp_read_eeprom(sc, &data, 6, 1); 503 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 504 (data & FXP_PHY_SERIAL_ONLY)) 505 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 506 507 /* 508 * Create the sysctl tree 509 */ 510 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 511 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 512 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 513 if (sc->sysctl_tree == NULL) 514 goto fail; 515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 516 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 517 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 518 "FXP driver receive interrupt microcode bundling delay"); 519 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 520 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 521 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 522 "FXP driver receive interrupt microcode bundle size limit"); 523 524 /* 525 * Pull in device tunables. 526 */ 527 sc->tunable_int_delay = TUNABLE_INT_DELAY; 528 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "int_delay", &sc->tunable_int_delay); 531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "bundle_max", &sc->tunable_bundle_max); 533 534 /* 535 * Find out the chip revision; lump all 82557 revs together. 536 */ 537 fxp_read_eeprom(sc, &data, 5, 1); 538 if ((data >> 8) == 1) 539 sc->revision = FXP_REV_82557; 540 else 541 sc->revision = pci_get_revid(dev); 542 543 /* 544 * Enable workarounds for certain chip revision deficiencies. 545 * 546 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 547 * some systems based a normal 82559 design, have a defect where 548 * the chip can cause a PCI protocol violation if it receives 549 * a CU_RESUME command when it is entering the IDLE state. The 550 * workaround is to disable Dynamic Standby Mode, so the chip never 551 * deasserts CLKRUN#, and always remains in an active state. 552 * 553 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 554 */ 555 i = pci_get_device(dev); 556 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 557 sc->revision >= FXP_REV_82559_A0) { 558 fxp_read_eeprom(sc, &data, 10, 1); 559 if (data & 0x02) { /* STB enable */ 560 u_int16_t cksum; 561 int i; 562 563 device_printf(dev, 564 "Disabling dynamic standby mode in EEPROM\n"); 565 data &= ~0x02; 566 fxp_write_eeprom(sc, &data, 10, 1); 567 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 568 cksum = 0; 569 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 570 fxp_read_eeprom(sc, &data, i, 1); 571 cksum += data; 572 } 573 i = (1 << sc->eeprom_size) - 1; 574 cksum = 0xBABA - cksum; 575 fxp_read_eeprom(sc, &data, i, 1); 576 fxp_write_eeprom(sc, &cksum, i, 1); 577 device_printf(dev, 578 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 579 i, data, cksum); 580 #if 1 581 /* 582 * If the user elects to continue, try the software 583 * workaround, as it is better than nothing. 584 */ 585 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 586 #endif 587 } 588 } 589 590 /* 591 * If we are not a 82557 chip, we can enable extended features. 592 */ 593 if (sc->revision != FXP_REV_82557) { 594 /* 595 * If MWI is enabled in the PCI configuration, and there 596 * is a valid cacheline size (8 or 16 dwords), then tell 597 * the board to turn on MWI. 598 */ 599 if (val & PCIM_CMD_MWRICEN && 600 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 601 sc->flags |= FXP_FLAG_MWI_ENABLE; 602 603 /* turn on the extended TxCB feature */ 604 sc->flags |= FXP_FLAG_EXT_TXCB; 605 606 /* enable reception of long frames for VLAN */ 607 sc->flags |= FXP_FLAG_LONG_PKT_EN; 608 } 609 610 /* 611 * Read MAC address. 612 */ 613 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 614 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 615 device_printf(dev, "10Mbps"); 616 if (bootverbose) { 617 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 618 pci_get_vendor(dev), pci_get_device(dev), 619 pci_get_subvendor(dev), pci_get_subdevice(dev), 620 pci_get_revid(dev)); 621 fxp_read_eeprom(sc, &data, 10, 1); 622 device_printf(dev, "Dynamic Standby mode is %s\n", 623 data & 0x02 ? "enabled" : "disabled"); 624 } 625 626 /* 627 * If this is only a 10Mbps device, then there is no MII, and 628 * the PHY will use a serial interface instead. 629 * 630 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 631 * doesn't have a programming interface of any sort. The 632 * media is sensed automatically based on how the link partner 633 * is configured. This is, in essence, manual configuration. 634 */ 635 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 636 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 637 fxp_serial_ifmedia_sts); 638 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 639 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 640 } else { 641 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 642 fxp_ifmedia_sts)) { 643 device_printf(dev, "MII without any PHY!\n"); 644 error = ENXIO; 645 goto fail; 646 } 647 } 648 649 ifp = &sc->arpcom.ac_if; 650 if_initname(ifp, "fxp", device_get_unit(dev)); 651 ifp->if_baudrate = 100000000; 652 ifp->if_init = fxp_init; 653 ifp->if_softc = sc; 654 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 655 ifp->if_ioctl = fxp_ioctl; 656 ifp->if_start = fxp_start; 657 ifp->if_watchdog = fxp_watchdog; 658 659 /* 660 * Attach the interface. 661 */ 662 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 663 664 /* 665 * Tell the upper layer(s) we support long frames. 666 */ 667 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 668 669 /* 670 * Let the system queue as many packets as we have available 671 * TX descriptors. 672 */ 673 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 674 675 splx(s); 676 return (0); 677 678 failmem: 679 device_printf(dev, "Failed to malloc memory\n"); 680 error = ENOMEM; 681 fail: 682 splx(s); 683 fxp_release(sc); 684 return (error); 685 } 686 687 /* 688 * release all resources 689 */ 690 static void 691 fxp_release(struct fxp_softc *sc) 692 { 693 694 bus_generic_detach(sc->dev); 695 if (sc->miibus) 696 device_delete_child(sc->dev, sc->miibus); 697 698 if (sc->cbl_base) 699 free(sc->cbl_base, M_DEVBUF); 700 if (sc->fxp_stats) 701 free(sc->fxp_stats, M_DEVBUF); 702 if (sc->mcsp) 703 free(sc->mcsp, M_DEVBUF); 704 if (sc->rfa_headm) 705 m_freem(sc->rfa_headm); 706 707 if (sc->ih) 708 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 709 if (sc->irq) 710 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 711 if (sc->mem) 712 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 713 714 sysctl_ctx_free(&sc->sysctl_ctx); 715 } 716 717 /* 718 * Detach interface. 719 */ 720 static int 721 fxp_detach(device_t dev) 722 { 723 struct fxp_softc *sc = device_get_softc(dev); 724 int s; 725 726 /* disable interrupts */ 727 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 728 729 s = splimp(); 730 731 /* 732 * Stop DMA and drop transmit queue. 733 */ 734 fxp_stop(sc); 735 736 /* 737 * Close down routes etc. 738 */ 739 ether_ifdetach(&sc->arpcom.ac_if); 740 741 /* 742 * Free all media structures. 743 */ 744 ifmedia_removeall(&sc->sc_media); 745 746 splx(s); 747 748 /* Release our allocated resources. */ 749 fxp_release(sc); 750 751 return (0); 752 } 753 754 /* 755 * Device shutdown routine. Called at system shutdown after sync. The 756 * main purpose of this routine is to shut off receiver DMA so that 757 * kernel memory doesn't get clobbered during warmboot. 758 */ 759 static int 760 fxp_shutdown(device_t dev) 761 { 762 /* 763 * Make sure that DMA is disabled prior to reboot. Not doing 764 * do could allow DMA to corrupt kernel memory during the 765 * reboot before the driver initializes. 766 */ 767 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 768 return (0); 769 } 770 771 /* 772 * Device suspend routine. Stop the interface and save some PCI 773 * settings in case the BIOS doesn't restore them properly on 774 * resume. 775 */ 776 static int 777 fxp_suspend(device_t dev) 778 { 779 struct fxp_softc *sc = device_get_softc(dev); 780 int i, s; 781 782 s = splimp(); 783 784 fxp_stop(sc); 785 786 for (i = 0; i < 5; i++) 787 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 788 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 789 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 790 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 791 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 792 793 sc->suspended = 1; 794 795 splx(s); 796 return (0); 797 } 798 799 /* 800 * Device resume routine. Restore some PCI settings in case the BIOS 801 * doesn't, re-enable busmastering, and restart the interface if 802 * appropriate. 803 */ 804 static int 805 fxp_resume(device_t dev) 806 { 807 struct fxp_softc *sc = device_get_softc(dev); 808 struct ifnet *ifp = &sc->arpcom.ac_if; 809 u_int16_t pci_command; 810 int i, s; 811 812 s = splimp(); 813 814 fxp_powerstate_d0(dev); 815 816 /* better way to do this? */ 817 for (i = 0; i < 5; i++) 818 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 819 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 820 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 821 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 822 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 823 824 /* reenable busmastering */ 825 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 826 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 827 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 828 829 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 830 DELAY(10); 831 832 /* reinitialize interface if necessary */ 833 if (ifp->if_flags & IFF_UP) 834 fxp_init(sc); 835 836 sc->suspended = 0; 837 838 splx(s); 839 return (0); 840 } 841 842 static void 843 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 844 { 845 u_int16_t reg; 846 int x; 847 848 /* 849 * Shift in data. 850 */ 851 for (x = 1 << (length - 1); x; x >>= 1) { 852 if (data & x) 853 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 854 else 855 reg = FXP_EEPROM_EECS; 856 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 857 DELAY(1); 858 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 859 DELAY(1); 860 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 861 DELAY(1); 862 } 863 } 864 865 /* 866 * Read from the serial EEPROM. Basically, you manually shift in 867 * the read opcode (one bit at a time) and then shift in the address, 868 * and then you shift out the data (all of this one bit at a time). 869 * The word size is 16 bits, so you have to provide the address for 870 * every 16 bits of data. 871 */ 872 static u_int16_t 873 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 874 { 875 u_int16_t reg, data; 876 int x; 877 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 879 /* 880 * Shift in read opcode. 881 */ 882 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 883 /* 884 * Shift in address. 885 */ 886 data = 0; 887 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 888 if (offset & x) 889 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 890 else 891 reg = FXP_EEPROM_EECS; 892 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 893 DELAY(1); 894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 895 DELAY(1); 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 897 DELAY(1); 898 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 899 data++; 900 if (autosize && reg == 0) { 901 sc->eeprom_size = data; 902 break; 903 } 904 } 905 /* 906 * Shift out data. 907 */ 908 data = 0; 909 reg = FXP_EEPROM_EECS; 910 for (x = 1 << 15; x; x >>= 1) { 911 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 912 DELAY(1); 913 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 914 data |= x; 915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 916 DELAY(1); 917 } 918 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 919 DELAY(1); 920 921 return (data); 922 } 923 924 static void 925 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 926 { 927 int i; 928 929 /* 930 * Erase/write enable. 931 */ 932 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 933 fxp_eeprom_shiftin(sc, 0x4, 3); 934 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 936 DELAY(1); 937 /* 938 * Shift in write opcode, address, data. 939 */ 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 941 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 942 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 943 fxp_eeprom_shiftin(sc, data, 16); 944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 945 DELAY(1); 946 /* 947 * Wait for EEPROM to finish up. 948 */ 949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 950 DELAY(1); 951 for (i = 0; i < 1000; i++) { 952 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 953 break; 954 DELAY(50); 955 } 956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 957 DELAY(1); 958 /* 959 * Erase/write disable. 960 */ 961 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 962 fxp_eeprom_shiftin(sc, 0x4, 3); 963 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 965 DELAY(1); 966 } 967 968 /* 969 * From NetBSD: 970 * 971 * Figure out EEPROM size. 972 * 973 * 559's can have either 64-word or 256-word EEPROMs, the 558 974 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 975 * talks about the existance of 16 to 256 word EEPROMs. 976 * 977 * The only known sizes are 64 and 256, where the 256 version is used 978 * by CardBus cards to store CIS information. 979 * 980 * The address is shifted in msb-to-lsb, and after the last 981 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 982 * after which follows the actual data. We try to detect this zero, by 983 * probing the data-out bit in the EEPROM control register just after 984 * having shifted in a bit. If the bit is zero, we assume we've 985 * shifted enough address bits. The data-out should be tri-state, 986 * before this, which should translate to a logical one. 987 */ 988 static void 989 fxp_autosize_eeprom(struct fxp_softc *sc) 990 { 991 992 /* guess maximum size of 256 words */ 993 sc->eeprom_size = 8; 994 995 /* autosize */ 996 (void) fxp_eeprom_getword(sc, 0, 1); 997 } 998 999 static void 1000 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1001 { 1002 int i; 1003 1004 for (i = 0; i < words; i++) 1005 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1006 } 1007 1008 static void 1009 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1010 { 1011 int i; 1012 1013 for (i = 0; i < words; i++) 1014 fxp_eeprom_putword(sc, offset + i, data[i]); 1015 } 1016 1017 /* 1018 * Start packet transmission on the interface. 1019 */ 1020 static void 1021 fxp_start(struct ifnet *ifp) 1022 { 1023 struct fxp_softc *sc = ifp->if_softc; 1024 struct fxp_cb_tx *txp; 1025 1026 /* 1027 * See if we need to suspend xmit until the multicast filter 1028 * has been reprogrammed (which can only be done at the head 1029 * of the command chain). 1030 */ 1031 if (sc->need_mcsetup) { 1032 return; 1033 } 1034 1035 txp = NULL; 1036 1037 /* 1038 * We're finished if there is nothing more to add to the list or if 1039 * we're all filled up with buffers to transmit. 1040 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1041 * a NOP command when needed. 1042 */ 1043 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1044 struct mbuf *m, *mb_head; 1045 int segment; 1046 1047 /* 1048 * Grab a packet to transmit. 1049 */ 1050 IF_DEQUEUE(&ifp->if_snd, mb_head); 1051 1052 /* 1053 * Get pointer to next available tx desc. 1054 */ 1055 txp = sc->cbl_last->next; 1056 1057 /* 1058 * Go through each of the mbufs in the chain and initialize 1059 * the transmit buffer descriptors with the physical address 1060 * and size of the mbuf. 1061 */ 1062 tbdinit: 1063 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1064 if (m->m_len != 0) { 1065 if (segment == FXP_NTXSEG) 1066 break; 1067 txp->tbd[segment].tb_addr = 1068 vtophys(mtod(m, vm_offset_t)); 1069 txp->tbd[segment].tb_size = m->m_len; 1070 segment++; 1071 } 1072 } 1073 if (m != NULL) { 1074 struct mbuf *mn; 1075 1076 /* 1077 * We ran out of segments. We have to recopy this 1078 * mbuf chain first. Bail out if we can't get the 1079 * new buffers. 1080 */ 1081 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1082 if (mn == NULL) { 1083 m_freem(mb_head); 1084 break; 1085 } 1086 if (mb_head->m_pkthdr.len > MHLEN) { 1087 MCLGET(mn, MB_DONTWAIT); 1088 if ((mn->m_flags & M_EXT) == 0) { 1089 m_freem(mn); 1090 m_freem(mb_head); 1091 break; 1092 } 1093 } 1094 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1095 mtod(mn, caddr_t)); 1096 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1097 m_freem(mb_head); 1098 mb_head = mn; 1099 goto tbdinit; 1100 } 1101 1102 txp->tbd_number = segment; 1103 txp->mb_head = mb_head; 1104 txp->cb_status = 0; 1105 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1106 txp->cb_command = 1107 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1108 FXP_CB_COMMAND_S; 1109 } else { 1110 txp->cb_command = 1111 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1112 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1113 /* 1114 * Set a 5 second timer just in case we don't hear 1115 * from the card again. 1116 */ 1117 ifp->if_timer = 5; 1118 } 1119 txp->tx_threshold = tx_threshold; 1120 1121 /* 1122 * Advance the end of list forward. 1123 */ 1124 1125 #ifdef __alpha__ 1126 /* 1127 * On platforms which can't access memory in 16-bit 1128 * granularities, we must prevent the card from DMA'ing 1129 * up the status while we update the command field. 1130 * This could cause us to overwrite the completion status. 1131 */ 1132 atomic_clear_short(&sc->cbl_last->cb_command, 1133 FXP_CB_COMMAND_S); 1134 #else 1135 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1136 #endif /*__alpha__*/ 1137 sc->cbl_last = txp; 1138 1139 /* 1140 * Advance the beginning of the list forward if there are 1141 * no other packets queued (when nothing is queued, cbl_first 1142 * sits on the last TxCB that was sent out). 1143 */ 1144 if (sc->tx_queued == 0) 1145 sc->cbl_first = txp; 1146 1147 sc->tx_queued++; 1148 1149 BPF_MTAP(ifp, mb_head); 1150 } 1151 1152 /* 1153 * We're finished. If we added to the list, issue a RESUME to get DMA 1154 * going again if suspended. 1155 */ 1156 if (txp != NULL) { 1157 fxp_scb_wait(sc); 1158 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1159 } 1160 } 1161 1162 #ifdef DEVICE_POLLING 1163 static poll_handler_t fxp_poll; 1164 1165 static void 1166 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1167 { 1168 struct fxp_softc *sc = ifp->if_softc; 1169 u_int8_t statack; 1170 1171 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1172 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1173 return; 1174 } 1175 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1176 FXP_SCB_STATACK_FR; 1177 if (cmd == POLL_AND_CHECK_STATUS) { 1178 u_int8_t tmp; 1179 1180 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1181 if (tmp == 0xff || tmp == 0) 1182 return; /* nothing to do */ 1183 tmp &= ~statack; 1184 /* ack what we can */ 1185 if (tmp != 0) 1186 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1187 statack |= tmp; 1188 } 1189 fxp_intr_body(sc, statack, count); 1190 } 1191 #endif /* DEVICE_POLLING */ 1192 1193 /* 1194 * Process interface interrupts. 1195 */ 1196 static void 1197 fxp_intr(void *xsc) 1198 { 1199 struct fxp_softc *sc = xsc; 1200 u_int8_t statack; 1201 1202 #ifdef DEVICE_POLLING 1203 struct ifnet *ifp = &sc->arpcom.ac_if; 1204 1205 if (ifp->if_flags & IFF_POLLING) 1206 return; 1207 if (ether_poll_register(fxp_poll, ifp)) { 1208 /* disable interrupts */ 1209 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1210 fxp_poll(ifp, 0, 1); 1211 return; 1212 } 1213 #endif 1214 1215 if (sc->suspended) { 1216 return; 1217 } 1218 1219 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1220 /* 1221 * It should not be possible to have all bits set; the 1222 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1223 * all bits are set, this may indicate that the card has 1224 * been physically ejected, so ignore it. 1225 */ 1226 if (statack == 0xff) 1227 return; 1228 1229 /* 1230 * First ACK all the interrupts in this pass. 1231 */ 1232 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1233 fxp_intr_body(sc, statack, -1); 1234 } 1235 } 1236 1237 static void 1238 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1239 { 1240 struct ifnet *ifp = &sc->arpcom.ac_if; 1241 struct mbuf *m; 1242 struct fxp_rfa *rfa; 1243 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1244 1245 if (rnr) 1246 fxp_rnr++; 1247 #ifdef DEVICE_POLLING 1248 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1249 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1250 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1251 rnr = 1; 1252 } 1253 #endif 1254 1255 /* 1256 * Free any finished transmit mbuf chains. 1257 * 1258 * Handle the CNA event likt a CXTNO event. It used to 1259 * be that this event (control unit not ready) was not 1260 * encountered, but it is now with the SMPng modifications. 1261 * The exact sequence of events that occur when the interface 1262 * is brought up are different now, and if this event 1263 * goes unhandled, the configuration/rxfilter setup sequence 1264 * can stall for several seconds. The result is that no 1265 * packets go out onto the wire for about 5 to 10 seconds 1266 * after the interface is ifconfig'ed for the first time. 1267 */ 1268 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1269 struct fxp_cb_tx *txp; 1270 1271 for (txp = sc->cbl_first; sc->tx_queued && 1272 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1273 txp = txp->next) { 1274 if ((m = txp->mb_head) != NULL) { 1275 txp->mb_head = NULL; 1276 sc->tx_queued--; 1277 m_freem(m); 1278 } else { 1279 sc->tx_queued--; 1280 } 1281 } 1282 sc->cbl_first = txp; 1283 ifp->if_timer = 0; 1284 if (sc->tx_queued == 0) { 1285 if (sc->need_mcsetup) 1286 fxp_mc_setup(sc); 1287 } 1288 /* 1289 * Try to start more packets transmitting. 1290 */ 1291 if (ifp->if_snd.ifq_head != NULL) 1292 fxp_start(ifp); 1293 } 1294 1295 /* 1296 * Just return if nothing happened on the receive side. 1297 */ 1298 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1299 return; 1300 1301 /* 1302 * Process receiver interrupts. If a no-resource (RNR) 1303 * condition exists, get whatever packets we can and 1304 * re-start the receiver. 1305 * 1306 * When using polling, we do not process the list to completion, 1307 * so when we get an RNR interrupt we must defer the restart 1308 * until we hit the last buffer with the C bit set. 1309 * If we run out of cycles and rfa_headm has the C bit set, 1310 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1311 * that the info will be used in the subsequent polling cycle. 1312 */ 1313 for (;;) { 1314 m = sc->rfa_headm; 1315 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1316 RFA_ALIGNMENT_FUDGE); 1317 1318 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1319 if (count >= 0 && count-- == 0) { 1320 if (rnr) { 1321 /* Defer RNR processing until the next time. */ 1322 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1323 rnr = 0; 1324 } 1325 break; 1326 } 1327 #endif /* DEVICE_POLLING */ 1328 1329 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1330 break; 1331 1332 /* 1333 * Remove first packet from the chain. 1334 */ 1335 sc->rfa_headm = m->m_next; 1336 m->m_next = NULL; 1337 1338 /* 1339 * Add a new buffer to the receive chain. 1340 * If this fails, the old buffer is recycled 1341 * instead. 1342 */ 1343 if (fxp_add_rfabuf(sc, m) == 0) { 1344 int total_len; 1345 1346 /* 1347 * Fetch packet length (the top 2 bits of 1348 * actual_size are flags set by the controller 1349 * upon completion), and drop the packet in case 1350 * of bogus length or CRC errors. 1351 */ 1352 total_len = rfa->actual_size & 0x3fff; 1353 if (total_len < sizeof(struct ether_header) || 1354 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1355 sizeof(struct fxp_rfa) || 1356 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1357 m_freem(m); 1358 continue; 1359 } 1360 m->m_pkthdr.len = m->m_len = total_len; 1361 (*ifp->if_input)(ifp, m); 1362 } 1363 } 1364 if (rnr) { 1365 fxp_scb_wait(sc); 1366 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1367 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1368 RFA_ALIGNMENT_FUDGE); 1369 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1370 } 1371 } 1372 1373 /* 1374 * Update packet in/out/collision statistics. The i82557 doesn't 1375 * allow you to access these counters without doing a fairly 1376 * expensive DMA to get _all_ of the statistics it maintains, so 1377 * we do this operation here only once per second. The statistics 1378 * counters in the kernel are updated from the previous dump-stats 1379 * DMA and then a new dump-stats DMA is started. The on-chip 1380 * counters are zeroed when the DMA completes. If we can't start 1381 * the DMA immediately, we don't wait - we just prepare to read 1382 * them again next time. 1383 */ 1384 static void 1385 fxp_tick(void *xsc) 1386 { 1387 struct fxp_softc *sc = xsc; 1388 struct ifnet *ifp = &sc->arpcom.ac_if; 1389 struct fxp_stats *sp = sc->fxp_stats; 1390 struct fxp_cb_tx *txp; 1391 struct mbuf *m; 1392 int s; 1393 1394 ifp->if_opackets += sp->tx_good; 1395 ifp->if_collisions += sp->tx_total_collisions; 1396 if (sp->rx_good) { 1397 ifp->if_ipackets += sp->rx_good; 1398 sc->rx_idle_secs = 0; 1399 } else { 1400 /* 1401 * Receiver's been idle for another second. 1402 */ 1403 sc->rx_idle_secs++; 1404 } 1405 ifp->if_ierrors += 1406 sp->rx_crc_errors + 1407 sp->rx_alignment_errors + 1408 sp->rx_rnr_errors + 1409 sp->rx_overrun_errors; 1410 /* 1411 * If any transmit underruns occured, bump up the transmit 1412 * threshold by another 512 bytes (64 * 8). 1413 */ 1414 if (sp->tx_underruns) { 1415 ifp->if_oerrors += sp->tx_underruns; 1416 if (tx_threshold < 192) 1417 tx_threshold += 64; 1418 } 1419 s = splimp(); 1420 /* 1421 * Release any xmit buffers that have completed DMA. This isn't 1422 * strictly necessary to do here, but it's advantagous for mbufs 1423 * with external storage to be released in a timely manner rather 1424 * than being defered for a potentially long time. This limits 1425 * the delay to a maximum of one second. 1426 */ 1427 for (txp = sc->cbl_first; sc->tx_queued && 1428 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1429 txp = txp->next) { 1430 if ((m = txp->mb_head) != NULL) { 1431 txp->mb_head = NULL; 1432 sc->tx_queued--; 1433 m_freem(m); 1434 } else { 1435 sc->tx_queued--; 1436 } 1437 } 1438 sc->cbl_first = txp; 1439 /* 1440 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1441 * then assume the receiver has locked up and attempt to clear 1442 * the condition by reprogramming the multicast filter. This is 1443 * a work-around for a bug in the 82557 where the receiver locks 1444 * up if it gets certain types of garbage in the syncronization 1445 * bits prior to the packet header. This bug is supposed to only 1446 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1447 * mode as well (perhaps due to a 10/100 speed transition). 1448 */ 1449 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1450 sc->rx_idle_secs = 0; 1451 fxp_mc_setup(sc); 1452 } 1453 /* 1454 * If there is no pending command, start another stats 1455 * dump. Otherwise punt for now. 1456 */ 1457 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1458 /* 1459 * Start another stats dump. 1460 */ 1461 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1462 } else { 1463 /* 1464 * A previous command is still waiting to be accepted. 1465 * Just zero our copy of the stats and wait for the 1466 * next timer event to update them. 1467 */ 1468 sp->tx_good = 0; 1469 sp->tx_underruns = 0; 1470 sp->tx_total_collisions = 0; 1471 1472 sp->rx_good = 0; 1473 sp->rx_crc_errors = 0; 1474 sp->rx_alignment_errors = 0; 1475 sp->rx_rnr_errors = 0; 1476 sp->rx_overrun_errors = 0; 1477 } 1478 if (sc->miibus != NULL) 1479 mii_tick(device_get_softc(sc->miibus)); 1480 splx(s); 1481 /* 1482 * Schedule another timeout one second from now. 1483 */ 1484 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1485 } 1486 1487 /* 1488 * Stop the interface. Cancels the statistics updater and resets 1489 * the interface. 1490 */ 1491 static void 1492 fxp_stop(struct fxp_softc *sc) 1493 { 1494 struct ifnet *ifp = &sc->arpcom.ac_if; 1495 struct fxp_cb_tx *txp; 1496 int i; 1497 1498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1499 ifp->if_timer = 0; 1500 1501 #ifdef DEVICE_POLLING 1502 ether_poll_deregister(ifp); 1503 #endif 1504 /* 1505 * Cancel stats updater. 1506 */ 1507 callout_stop(&sc->fxp_stat_timer); 1508 1509 /* 1510 * Issue software reset, which also unloads the microcode. 1511 */ 1512 sc->flags &= ~FXP_FLAG_UCODE; 1513 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1514 DELAY(50); 1515 1516 /* 1517 * Release any xmit buffers. 1518 */ 1519 txp = sc->cbl_base; 1520 if (txp != NULL) { 1521 for (i = 0; i < FXP_NTXCB; i++) { 1522 if (txp[i].mb_head != NULL) { 1523 m_freem(txp[i].mb_head); 1524 txp[i].mb_head = NULL; 1525 } 1526 } 1527 } 1528 sc->tx_queued = 0; 1529 1530 /* 1531 * Free all the receive buffers then reallocate/reinitialize 1532 */ 1533 if (sc->rfa_headm != NULL) 1534 m_freem(sc->rfa_headm); 1535 sc->rfa_headm = NULL; 1536 sc->rfa_tailm = NULL; 1537 for (i = 0; i < FXP_NRFABUFS; i++) { 1538 if (fxp_add_rfabuf(sc, NULL) != 0) { 1539 /* 1540 * This "can't happen" - we're at splimp() 1541 * and we just freed all the buffers we need 1542 * above. 1543 */ 1544 panic("fxp_stop: no buffers!"); 1545 } 1546 } 1547 } 1548 1549 /* 1550 * Watchdog/transmission transmit timeout handler. Called when a 1551 * transmission is started on the interface, but no interrupt is 1552 * received before the timeout. This usually indicates that the 1553 * card has wedged for some reason. 1554 */ 1555 static void 1556 fxp_watchdog(struct ifnet *ifp) 1557 { 1558 struct fxp_softc *sc = ifp->if_softc; 1559 1560 device_printf(sc->dev, "device timeout\n"); 1561 ifp->if_oerrors++; 1562 1563 fxp_init(sc); 1564 } 1565 1566 static void 1567 fxp_init(void *xsc) 1568 { 1569 struct fxp_softc *sc = xsc; 1570 struct ifnet *ifp = &sc->arpcom.ac_if; 1571 struct fxp_cb_config *cbp; 1572 struct fxp_cb_ias *cb_ias; 1573 struct fxp_cb_tx *txp; 1574 struct fxp_cb_mcs *mcsp; 1575 int i, prm, s; 1576 1577 s = splimp(); 1578 /* 1579 * Cancel any pending I/O 1580 */ 1581 fxp_stop(sc); 1582 1583 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1584 1585 /* 1586 * Initialize base of CBL and RFA memory. Loading with zero 1587 * sets it up for regular linear addressing. 1588 */ 1589 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1590 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1591 1592 fxp_scb_wait(sc); 1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1594 1595 /* 1596 * Initialize base of dump-stats buffer. 1597 */ 1598 fxp_scb_wait(sc); 1599 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1600 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1601 1602 /* 1603 * Attempt to load microcode if requested. 1604 */ 1605 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1606 fxp_load_ucode(sc); 1607 1608 /* 1609 * Initialize the multicast address list. 1610 */ 1611 if (fxp_mc_addrs(sc)) { 1612 mcsp = sc->mcsp; 1613 mcsp->cb_status = 0; 1614 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1615 mcsp->link_addr = -1; 1616 /* 1617 * Start the multicast setup command. 1618 */ 1619 fxp_scb_wait(sc); 1620 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1621 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1622 /* ...and wait for it to complete. */ 1623 fxp_dma_wait(&mcsp->cb_status, sc); 1624 } 1625 1626 /* 1627 * We temporarily use memory that contains the TxCB list to 1628 * construct the config CB. The TxCB list memory is rebuilt 1629 * later. 1630 */ 1631 cbp = (struct fxp_cb_config *) sc->cbl_base; 1632 1633 /* 1634 * This bcopy is kind of disgusting, but there are a bunch of must be 1635 * zero and must be one bits in this structure and this is the easiest 1636 * way to initialize them all to proper values. 1637 */ 1638 bcopy(fxp_cb_config_template, 1639 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1640 sizeof(fxp_cb_config_template)); 1641 1642 cbp->cb_status = 0; 1643 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1644 cbp->link_addr = -1; /* (no) next command */ 1645 cbp->byte_count = 22; /* (22) bytes to config */ 1646 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1647 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1648 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1649 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1650 cbp->type_enable = 0; /* actually reserved */ 1651 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1652 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1653 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1654 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1655 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1656 cbp->late_scb = 0; /* (don't) defer SCB update */ 1657 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1658 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1659 cbp->ci_int = 1; /* interrupt on CU idle */ 1660 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1661 cbp->ext_stats_dis = 1; /* disable extended counters */ 1662 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1663 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1664 cbp->disc_short_rx = !prm; /* discard short packets */ 1665 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1666 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1667 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1668 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1669 cbp->csma_dis = 0; /* (don't) disable link */ 1670 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1671 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1672 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1673 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1674 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1675 cbp->nsai = 1; /* (don't) disable source addr insert */ 1676 cbp->preamble_length = 2; /* (7 byte) preamble */ 1677 cbp->loopback = 0; /* (don't) loopback */ 1678 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1679 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1680 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1681 cbp->promiscuous = prm; /* promiscuous mode */ 1682 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1683 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1684 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1685 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1686 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1687 1688 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1689 cbp->padding = 1; /* (do) pad short tx packets */ 1690 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1691 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1692 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1693 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1694 /* must set wake_en in PMCSR also */ 1695 cbp->force_fdx = 0; /* (don't) force full duplex */ 1696 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1697 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1698 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1699 1700 if (sc->revision == FXP_REV_82557) { 1701 /* 1702 * The 82557 has no hardware flow control, the values 1703 * below are the defaults for the chip. 1704 */ 1705 cbp->fc_delay_lsb = 0; 1706 cbp->fc_delay_msb = 0x40; 1707 cbp->pri_fc_thresh = 3; 1708 cbp->tx_fc_dis = 0; 1709 cbp->rx_fc_restop = 0; 1710 cbp->rx_fc_restart = 0; 1711 cbp->fc_filter = 0; 1712 cbp->pri_fc_loc = 1; 1713 } else { 1714 cbp->fc_delay_lsb = 0x1f; 1715 cbp->fc_delay_msb = 0x01; 1716 cbp->pri_fc_thresh = 3; 1717 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1718 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1719 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1720 cbp->fc_filter = !prm; /* drop FC frames to host */ 1721 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1722 } 1723 1724 /* 1725 * Start the config command/DMA. 1726 */ 1727 fxp_scb_wait(sc); 1728 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1729 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1730 /* ...and wait for it to complete. */ 1731 fxp_dma_wait(&cbp->cb_status, sc); 1732 1733 /* 1734 * Now initialize the station address. Temporarily use the TxCB 1735 * memory area like we did above for the config CB. 1736 */ 1737 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1738 cb_ias->cb_status = 0; 1739 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1740 cb_ias->link_addr = -1; 1741 bcopy(sc->arpcom.ac_enaddr, 1742 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1743 sizeof(sc->arpcom.ac_enaddr)); 1744 1745 /* 1746 * Start the IAS (Individual Address Setup) command/DMA. 1747 */ 1748 fxp_scb_wait(sc); 1749 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1750 /* ...and wait for it to complete. */ 1751 fxp_dma_wait(&cb_ias->cb_status, sc); 1752 1753 /* 1754 * Initialize transmit control block (TxCB) list. 1755 */ 1756 1757 txp = sc->cbl_base; 1758 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1759 for (i = 0; i < FXP_NTXCB; i++) { 1760 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1761 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1762 txp[i].link_addr = 1763 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1764 if (sc->flags & FXP_FLAG_EXT_TXCB) 1765 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1766 else 1767 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1768 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1769 } 1770 /* 1771 * Set the suspend flag on the first TxCB and start the control 1772 * unit. It will execute the NOP and then suspend. 1773 */ 1774 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1775 sc->cbl_first = sc->cbl_last = txp; 1776 sc->tx_queued = 1; 1777 1778 fxp_scb_wait(sc); 1779 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1780 1781 /* 1782 * Initialize receiver buffer area - RFA. 1783 */ 1784 fxp_scb_wait(sc); 1785 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1786 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1787 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1788 1789 /* 1790 * Set current media. 1791 */ 1792 if (sc->miibus != NULL) 1793 mii_mediachg(device_get_softc(sc->miibus)); 1794 1795 ifp->if_flags |= IFF_RUNNING; 1796 ifp->if_flags &= ~IFF_OACTIVE; 1797 1798 /* 1799 * Enable interrupts. 1800 */ 1801 #ifdef DEVICE_POLLING 1802 /* 1803 * ... but only do that if we are not polling. And because (presumably) 1804 * the default is interrupts on, we need to disable them explicitly! 1805 */ 1806 if ( ifp->if_flags & IFF_POLLING ) 1807 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1808 else 1809 #endif /* DEVICE_POLLING */ 1810 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1811 splx(s); 1812 1813 /* 1814 * Start stats updater. 1815 */ 1816 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1817 } 1818 1819 static int 1820 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1821 { 1822 1823 return (0); 1824 } 1825 1826 static void 1827 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1828 { 1829 1830 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1831 } 1832 1833 /* 1834 * Change media according to request. 1835 */ 1836 static int 1837 fxp_ifmedia_upd(struct ifnet *ifp) 1838 { 1839 struct fxp_softc *sc = ifp->if_softc; 1840 struct mii_data *mii; 1841 1842 mii = device_get_softc(sc->miibus); 1843 mii_mediachg(mii); 1844 return (0); 1845 } 1846 1847 /* 1848 * Notify the world which media we're using. 1849 */ 1850 static void 1851 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1852 { 1853 struct fxp_softc *sc = ifp->if_softc; 1854 struct mii_data *mii; 1855 1856 mii = device_get_softc(sc->miibus); 1857 mii_pollstat(mii); 1858 ifmr->ifm_active = mii->mii_media_active; 1859 ifmr->ifm_status = mii->mii_media_status; 1860 1861 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1862 sc->cu_resume_bug = 1; 1863 else 1864 sc->cu_resume_bug = 0; 1865 } 1866 1867 /* 1868 * Add a buffer to the end of the RFA buffer list. 1869 * Return 0 if successful, 1 for failure. A failure results in 1870 * adding the 'oldm' (if non-NULL) on to the end of the list - 1871 * tossing out its old contents and recycling it. 1872 * The RFA struct is stuck at the beginning of mbuf cluster and the 1873 * data pointer is fixed up to point just past it. 1874 */ 1875 static int 1876 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1877 { 1878 u_int32_t v; 1879 struct mbuf *m; 1880 struct fxp_rfa *rfa, *p_rfa; 1881 1882 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1883 if (m == NULL) { /* try to recycle the old mbuf instead */ 1884 if (oldm == NULL) 1885 return 1; 1886 m = oldm; 1887 m->m_data = m->m_ext.ext_buf; 1888 } 1889 1890 /* 1891 * Move the data pointer up so that the incoming data packet 1892 * will be 32-bit aligned. 1893 */ 1894 m->m_data += RFA_ALIGNMENT_FUDGE; 1895 1896 /* 1897 * Get a pointer to the base of the mbuf cluster and move 1898 * data start past it. 1899 */ 1900 rfa = mtod(m, struct fxp_rfa *); 1901 m->m_data += sizeof(struct fxp_rfa); 1902 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1903 1904 /* 1905 * Initialize the rest of the RFA. Note that since the RFA 1906 * is misaligned, we cannot store values directly. Instead, 1907 * we use an optimized, inline copy. 1908 */ 1909 1910 rfa->rfa_status = 0; 1911 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1912 rfa->actual_size = 0; 1913 1914 v = -1; 1915 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1916 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1917 1918 /* 1919 * If there are other buffers already on the list, attach this 1920 * one to the end by fixing up the tail to point to this one. 1921 */ 1922 if (sc->rfa_headm != NULL) { 1923 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1924 RFA_ALIGNMENT_FUDGE); 1925 sc->rfa_tailm->m_next = m; 1926 v = vtophys(rfa); 1927 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1928 p_rfa->rfa_control = 0; 1929 } else { 1930 sc->rfa_headm = m; 1931 } 1932 sc->rfa_tailm = m; 1933 1934 return (m == oldm); 1935 } 1936 1937 static volatile int 1938 fxp_miibus_readreg(device_t dev, int phy, int reg) 1939 { 1940 struct fxp_softc *sc = device_get_softc(dev); 1941 int count = 10000; 1942 int value; 1943 1944 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1945 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1946 1947 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1948 && count--) 1949 DELAY(10); 1950 1951 if (count <= 0) 1952 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1953 1954 return (value & 0xffff); 1955 } 1956 1957 static void 1958 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1959 { 1960 struct fxp_softc *sc = device_get_softc(dev); 1961 int count = 10000; 1962 1963 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1964 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1965 (value & 0xffff)); 1966 1967 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1968 count--) 1969 DELAY(10); 1970 1971 if (count <= 0) 1972 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1973 } 1974 1975 static int 1976 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1977 { 1978 struct fxp_softc *sc = ifp->if_softc; 1979 struct ifreq *ifr = (struct ifreq *)data; 1980 struct mii_data *mii; 1981 int s, error = 0; 1982 1983 s = splimp(); 1984 1985 switch (command) { 1986 case SIOCSIFADDR: 1987 case SIOCGIFADDR: 1988 case SIOCSIFMTU: 1989 error = ether_ioctl(ifp, command, data); 1990 break; 1991 1992 case SIOCSIFFLAGS: 1993 if (ifp->if_flags & IFF_ALLMULTI) 1994 sc->flags |= FXP_FLAG_ALL_MCAST; 1995 else 1996 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1997 1998 /* 1999 * If interface is marked up and not running, then start it. 2000 * If it is marked down and running, stop it. 2001 * XXX If it's up then re-initialize it. This is so flags 2002 * such as IFF_PROMISC are handled. 2003 */ 2004 if (ifp->if_flags & IFF_UP) { 2005 fxp_init(sc); 2006 } else { 2007 if (ifp->if_flags & IFF_RUNNING) 2008 fxp_stop(sc); 2009 } 2010 break; 2011 2012 case SIOCADDMULTI: 2013 case SIOCDELMULTI: 2014 if (ifp->if_flags & IFF_ALLMULTI) 2015 sc->flags |= FXP_FLAG_ALL_MCAST; 2016 else 2017 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2018 /* 2019 * Multicast list has changed; set the hardware filter 2020 * accordingly. 2021 */ 2022 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2023 fxp_mc_setup(sc); 2024 /* 2025 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2026 * again rather than else {}. 2027 */ 2028 if (sc->flags & FXP_FLAG_ALL_MCAST) 2029 fxp_init(sc); 2030 error = 0; 2031 break; 2032 2033 case SIOCSIFMEDIA: 2034 case SIOCGIFMEDIA: 2035 if (sc->miibus != NULL) { 2036 mii = device_get_softc(sc->miibus); 2037 error = ifmedia_ioctl(ifp, ifr, 2038 &mii->mii_media, command); 2039 } else { 2040 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2041 } 2042 break; 2043 2044 default: 2045 error = EINVAL; 2046 } 2047 splx(s); 2048 return (error); 2049 } 2050 2051 /* 2052 * Fill in the multicast address list and return number of entries. 2053 */ 2054 static int 2055 fxp_mc_addrs(struct fxp_softc *sc) 2056 { 2057 struct fxp_cb_mcs *mcsp = sc->mcsp; 2058 struct ifnet *ifp = &sc->arpcom.ac_if; 2059 struct ifmultiaddr *ifma; 2060 int nmcasts; 2061 2062 nmcasts = 0; 2063 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2064 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2065 if (ifma->ifma_addr->sa_family != AF_LINK) 2066 continue; 2067 if (nmcasts >= MAXMCADDR) { 2068 sc->flags |= FXP_FLAG_ALL_MCAST; 2069 nmcasts = 0; 2070 break; 2071 } 2072 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2073 (void *)(uintptr_t)(volatile void *) 2074 &sc->mcsp->mc_addr[nmcasts][0], 6); 2075 nmcasts++; 2076 } 2077 } 2078 mcsp->mc_cnt = nmcasts * 6; 2079 return (nmcasts); 2080 } 2081 2082 /* 2083 * Program the multicast filter. 2084 * 2085 * We have an artificial restriction that the multicast setup command 2086 * must be the first command in the chain, so we take steps to ensure 2087 * this. By requiring this, it allows us to keep up the performance of 2088 * the pre-initialized command ring (esp. link pointers) by not actually 2089 * inserting the mcsetup command in the ring - i.e. its link pointer 2090 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2091 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2092 * lead into the regular TxCB ring when it completes. 2093 * 2094 * This function must be called at splimp. 2095 */ 2096 static void 2097 fxp_mc_setup(struct fxp_softc *sc) 2098 { 2099 struct fxp_cb_mcs *mcsp = sc->mcsp; 2100 struct ifnet *ifp = &sc->arpcom.ac_if; 2101 int count; 2102 2103 /* 2104 * If there are queued commands, we must wait until they are all 2105 * completed. If we are already waiting, then add a NOP command 2106 * with interrupt option so that we're notified when all commands 2107 * have been completed - fxp_start() ensures that no additional 2108 * TX commands will be added when need_mcsetup is true. 2109 */ 2110 if (sc->tx_queued) { 2111 struct fxp_cb_tx *txp; 2112 2113 /* 2114 * need_mcsetup will be true if we are already waiting for the 2115 * NOP command to be completed (see below). In this case, bail. 2116 */ 2117 if (sc->need_mcsetup) 2118 return; 2119 sc->need_mcsetup = 1; 2120 2121 /* 2122 * Add a NOP command with interrupt so that we are notified 2123 * when all TX commands have been processed. 2124 */ 2125 txp = sc->cbl_last->next; 2126 txp->mb_head = NULL; 2127 txp->cb_status = 0; 2128 txp->cb_command = FXP_CB_COMMAND_NOP | 2129 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2130 /* 2131 * Advance the end of list forward. 2132 */ 2133 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2134 sc->cbl_last = txp; 2135 sc->tx_queued++; 2136 /* 2137 * Issue a resume in case the CU has just suspended. 2138 */ 2139 fxp_scb_wait(sc); 2140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2141 /* 2142 * Set a 5 second timer just in case we don't hear from the 2143 * card again. 2144 */ 2145 ifp->if_timer = 5; 2146 2147 return; 2148 } 2149 sc->need_mcsetup = 0; 2150 2151 /* 2152 * Initialize multicast setup descriptor. 2153 */ 2154 mcsp->next = sc->cbl_base; 2155 mcsp->mb_head = NULL; 2156 mcsp->cb_status = 0; 2157 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2158 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2159 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2160 (void) fxp_mc_addrs(sc); 2161 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2162 sc->tx_queued = 1; 2163 2164 /* 2165 * Wait until command unit is not active. This should never 2166 * be the case when nothing is queued, but make sure anyway. 2167 */ 2168 count = 100; 2169 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2170 FXP_SCB_CUS_ACTIVE && --count) 2171 DELAY(10); 2172 if (count == 0) { 2173 device_printf(sc->dev, "command queue timeout\n"); 2174 return; 2175 } 2176 2177 /* 2178 * Start the multicast setup command. 2179 */ 2180 fxp_scb_wait(sc); 2181 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2182 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2183 2184 ifp->if_timer = 2; 2185 return; 2186 } 2187 2188 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2189 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2190 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2191 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2192 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2193 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2194 2195 #define UCODE(x) x, sizeof(x) 2196 2197 struct ucode { 2198 u_int32_t revision; 2199 u_int32_t *ucode; 2200 int length; 2201 u_short int_delay_offset; 2202 u_short bundle_max_offset; 2203 } ucode_table[] = { 2204 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2205 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2206 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2207 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2208 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2209 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2210 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2211 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2212 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2213 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2214 { 0, NULL, 0, 0, 0 } 2215 }; 2216 2217 static void 2218 fxp_load_ucode(struct fxp_softc *sc) 2219 { 2220 struct ucode *uc; 2221 struct fxp_cb_ucode *cbp; 2222 2223 for (uc = ucode_table; uc->ucode != NULL; uc++) 2224 if (sc->revision == uc->revision) 2225 break; 2226 if (uc->ucode == NULL) 2227 return; 2228 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2229 cbp->cb_status = 0; 2230 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2231 cbp->link_addr = -1; /* (no) next command */ 2232 memcpy(cbp->ucode, uc->ucode, uc->length); 2233 if (uc->int_delay_offset) 2234 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2235 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2236 if (uc->bundle_max_offset) 2237 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2238 sc->tunable_bundle_max; 2239 /* 2240 * Download the ucode to the chip. 2241 */ 2242 fxp_scb_wait(sc); 2243 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2244 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2245 /* ...and wait for it to complete. */ 2246 fxp_dma_wait(&cbp->cb_status, sc); 2247 device_printf(sc->dev, 2248 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2249 sc->tunable_int_delay, 2250 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2251 sc->flags |= FXP_FLAG_UCODE; 2252 } 2253 2254 static int 2255 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2256 { 2257 int error, value; 2258 2259 value = *(int *)arg1; 2260 error = sysctl_handle_int(oidp, &value, 0, req); 2261 if (error || !req->newptr) 2262 return (error); 2263 if (value < low || value > high) 2264 return (EINVAL); 2265 *(int *)arg1 = value; 2266 return (0); 2267 } 2268 2269 /* 2270 * Interrupt delay is expressed in microseconds, a multiplier is used 2271 * to convert this to the appropriate clock ticks before using. 2272 */ 2273 static int 2274 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2275 { 2276 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2277 } 2278 2279 static int 2280 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2281 { 2282 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2283 } 2284