1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/bitops.h> 37 #include <sys/endian.h> 38 #include <sys/kernel.h> 39 #include <sys/bus.h> 40 #include <sys/interrupt.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/serialize.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/bpf.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/ifq_var.h> 56 #include <net/vlan/if_vlan_var.h> 57 58 #include <dev/netif/mii_layer/miivar.h> 59 60 #include <bus/pci/pcireg.h> 61 #include <bus/pci/pcivar.h> 62 #include <bus/pci/pcidevs.h> 63 64 #include <dev/netif/et/if_etreg.h> 65 #include <dev/netif/et/if_etvar.h> 66 67 #include "miibus_if.h" 68 69 static int et_probe(device_t); 70 static int et_attach(device_t); 71 static int et_detach(device_t); 72 static int et_shutdown(device_t); 73 74 static int et_miibus_readreg(device_t, int, int); 75 static int et_miibus_writereg(device_t, int, int, int); 76 static void et_miibus_statchg(device_t); 77 78 static void et_init(void *); 79 static int et_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 80 static void et_start(struct ifnet *, struct ifaltq_subque *); 81 static void et_watchdog(struct ifnet *); 82 static int et_ifmedia_upd(struct ifnet *); 83 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 84 85 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 86 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 87 88 static void et_intr(void *); 89 static void et_enable_intrs(struct et_softc *, uint32_t); 90 static void et_disable_intrs(struct et_softc *); 91 static void et_rxeof(struct et_softc *); 92 static void et_txeof(struct et_softc *, int); 93 94 static int et_dma_alloc(device_t); 95 static void et_dma_free(device_t); 96 static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 97 static int et_dma_mbuf_create(device_t); 98 static void et_dma_mbuf_destroy(device_t, int, const int[]); 99 static int et_jumbo_mem_alloc(device_t); 100 static void et_jumbo_mem_free(device_t); 101 static int et_init_tx_ring(struct et_softc *); 102 static int et_init_rx_ring(struct et_softc *); 103 static void et_free_tx_ring(struct et_softc *); 104 static void et_free_rx_ring(struct et_softc *); 105 static int et_encap(struct et_softc *, struct mbuf **); 106 static struct et_jslot * 107 et_jalloc(struct et_jumbo_data *); 108 static void et_jfree(void *); 109 static void et_jref(void *); 110 static int et_newbuf(struct et_rxbuf_data *, int, int, int); 111 static int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 112 static int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 113 static int et_newbuf_jumbo(struct et_rxbuf_data *, int, int); 114 115 static void et_stop(struct et_softc *); 116 static int et_chip_init(struct et_softc *); 117 static void et_chip_attach(struct et_softc *); 118 static void et_init_mac(struct et_softc *); 119 static void et_init_rxmac(struct et_softc *); 120 static void et_init_txmac(struct et_softc *); 121 static int et_init_rxdma(struct et_softc *); 122 static int et_init_txdma(struct et_softc *); 123 static int et_start_rxdma(struct et_softc *); 124 static int et_start_txdma(struct et_softc *); 125 static int et_stop_rxdma(struct et_softc *); 126 static int et_stop_txdma(struct et_softc *); 127 static int et_enable_txrx(struct et_softc *, int); 128 static void et_reset(struct et_softc *); 129 static int et_bus_config(device_t); 130 static void et_get_eaddr(device_t, uint8_t[]); 131 static void et_setmulti(struct et_softc *); 132 static void et_tick(void *); 133 static void et_setmedia(struct et_softc *); 134 static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t); 135 136 static const struct et_dev { 137 uint16_t vid; 138 uint16_t did; 139 const char *desc; 140 } et_devices[] = { 141 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 142 "Agere ET1310 Gigabit Ethernet" }, 143 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 144 "Agere ET1310 Fast Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static device_method_t et_methods[] = { 149 DEVMETHOD(device_probe, et_probe), 150 DEVMETHOD(device_attach, et_attach), 151 DEVMETHOD(device_detach, et_detach), 152 DEVMETHOD(device_shutdown, et_shutdown), 153 #if 0 154 DEVMETHOD(device_suspend, et_suspend), 155 DEVMETHOD(device_resume, et_resume), 156 #endif 157 158 DEVMETHOD(bus_print_child, bus_generic_print_child), 159 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 160 161 DEVMETHOD(miibus_readreg, et_miibus_readreg), 162 DEVMETHOD(miibus_writereg, et_miibus_writereg), 163 DEVMETHOD(miibus_statchg, et_miibus_statchg), 164 165 DEVMETHOD_END 166 }; 167 168 static driver_t et_driver = { 169 "et", 170 et_methods, 171 sizeof(struct et_softc) 172 }; 173 174 static devclass_t et_devclass; 175 176 DECLARE_DUMMY_MODULE(if_et); 177 MODULE_DEPEND(if_et, miibus, 1, 1, 1); 178 DRIVER_MODULE(if_et, pci, et_driver, et_devclass, NULL, NULL); 179 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, NULL, NULL); 180 181 static int et_rx_intr_npkts = 129; 182 static int et_rx_intr_delay = 25; /* x4 usec */ 183 static int et_tx_intr_nsegs = 256; 184 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 185 186 TUNABLE_INT("hw.et.timer", &et_timer); 187 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 188 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 189 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 190 191 struct et_bsize { 192 int bufsize; 193 int jumbo; 194 et_newbuf_t newbuf; 195 }; 196 197 static const struct et_bsize et_bufsize_std[ET_RX_NRING] = { 198 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0, 199 .newbuf = et_newbuf_hdr }, 200 { .bufsize = ET_RXDMA_CTRL_RING1_2048, .jumbo = 0, 201 .newbuf = et_newbuf_cluster }, 202 }; 203 204 static const struct et_bsize et_bufsize_jumbo[ET_RX_NRING] = { 205 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0, 206 .newbuf = et_newbuf_hdr }, 207 { .bufsize = ET_RXDMA_CTRL_RING1_16384, .jumbo = 1, 208 .newbuf = et_newbuf_jumbo }, 209 }; 210 211 static int 212 et_probe(device_t dev) 213 { 214 const struct et_dev *d; 215 uint16_t did, vid; 216 217 vid = pci_get_vendor(dev); 218 did = pci_get_device(dev); 219 220 for (d = et_devices; d->desc != NULL; ++d) { 221 if (vid == d->vid && did == d->did) { 222 device_set_desc(dev, d->desc); 223 return 0; 224 } 225 } 226 return ENXIO; 227 } 228 229 static int 230 et_attach(device_t dev) 231 { 232 struct et_softc *sc = device_get_softc(dev); 233 struct ifnet *ifp = &sc->arpcom.ac_if; 234 uint8_t eaddr[ETHER_ADDR_LEN]; 235 int error; 236 237 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 238 callout_init(&sc->sc_tick); 239 240 /* 241 * Initialize tunables 242 */ 243 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 244 sc->sc_rx_intr_delay = et_rx_intr_delay; 245 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 246 sc->sc_timer = et_timer; 247 248 #ifndef BURN_BRIDGES 249 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 250 uint32_t irq, mem; 251 252 irq = pci_read_config(dev, PCIR_INTLINE, 4); 253 mem = pci_read_config(dev, ET_PCIR_BAR, 4); 254 255 device_printf(dev, "chip is in D%d power mode " 256 "-- setting to D0\n", pci_get_powerstate(dev)); 257 258 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 259 260 pci_write_config(dev, PCIR_INTLINE, irq, 4); 261 pci_write_config(dev, ET_PCIR_BAR, mem, 4); 262 } 263 #endif /* !BURN_BRIDGE */ 264 265 /* Enable bus mastering */ 266 pci_enable_busmaster(dev); 267 268 /* 269 * Allocate IO memory 270 */ 271 sc->sc_mem_rid = ET_PCIR_BAR; 272 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 273 &sc->sc_mem_rid, RF_ACTIVE); 274 if (sc->sc_mem_res == NULL) { 275 device_printf(dev, "can't allocate IO memory\n"); 276 return ENXIO; 277 } 278 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res); 279 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res); 280 281 /* 282 * Allocate IRQ 283 */ 284 sc->sc_irq_rid = 0; 285 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 286 &sc->sc_irq_rid, 287 RF_SHAREABLE | RF_ACTIVE); 288 if (sc->sc_irq_res == NULL) { 289 device_printf(dev, "can't allocate irq\n"); 290 error = ENXIO; 291 goto fail; 292 } 293 294 /* 295 * Create sysctl tree 296 */ 297 sysctl_ctx_init(&sc->sc_sysctl_ctx); 298 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 299 SYSCTL_STATIC_CHILDREN(_hw), 300 OID_AUTO, 301 device_get_nameunit(dev), 302 CTLFLAG_RD, 0, ""); 303 if (sc->sc_sysctl_tree == NULL) { 304 device_printf(dev, "can't add sysctl node\n"); 305 error = ENXIO; 306 goto fail; 307 } 308 309 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx, 310 SYSCTL_CHILDREN(sc->sc_sysctl_tree), 311 OID_AUTO, "rx_intr_npkts", CTLTYPE_INT | CTLFLAG_RW, 312 sc, 0, et_sysctl_rx_intr_npkts, "I", 313 "RX IM, # packets per RX interrupt"); 314 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx, 315 SYSCTL_CHILDREN(sc->sc_sysctl_tree), 316 OID_AUTO, "rx_intr_delay", CTLTYPE_INT | CTLFLAG_RW, 317 sc, 0, et_sysctl_rx_intr_delay, "I", 318 "RX IM, RX interrupt delay (x10 usec)"); 319 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx, 320 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO, 321 "tx_intr_nsegs", CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 322 "TX IM, # segments per TX interrupt"); 323 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx, 324 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO, 325 "timer", CTLFLAG_RW, &sc->sc_timer, 0, 326 "TX timer"); 327 328 error = et_bus_config(dev); 329 if (error) 330 goto fail; 331 332 et_get_eaddr(dev, eaddr); 333 334 CSR_WRITE_4(sc, ET_PM, 335 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 336 337 et_reset(sc); 338 339 et_disable_intrs(sc); 340 341 error = et_dma_alloc(dev); 342 if (error) 343 goto fail; 344 345 ifp->if_softc = sc; 346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 347 ifp->if_init = et_init; 348 ifp->if_ioctl = et_ioctl; 349 ifp->if_start = et_start; 350 ifp->if_watchdog = et_watchdog; 351 ifp->if_mtu = ETHERMTU; 352 ifp->if_capabilities = IFCAP_VLAN_MTU; 353 ifp->if_capenable = ifp->if_capabilities; 354 ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC); 355 ifq_set_ready(&ifp->if_snd); 356 357 et_chip_attach(sc); 358 359 error = mii_phy_probe(dev, &sc->sc_miibus, 360 et_ifmedia_upd, et_ifmedia_sts); 361 if (error) { 362 device_printf(dev, "can't probe any PHY\n"); 363 goto fail; 364 } 365 366 ether_ifattach(ifp, eaddr, NULL); 367 368 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, et_intr, sc, 369 &sc->sc_irq_handle, ifp->if_serializer); 370 if (error) { 371 ether_ifdetach(ifp); 372 device_printf(dev, "can't setup intr\n"); 373 goto fail; 374 } 375 376 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res)); 377 378 return 0; 379 fail: 380 et_detach(dev); 381 return error; 382 } 383 384 static int 385 et_detach(device_t dev) 386 { 387 struct et_softc *sc = device_get_softc(dev); 388 389 if (device_is_attached(dev)) { 390 struct ifnet *ifp = &sc->arpcom.ac_if; 391 392 lwkt_serialize_enter(ifp->if_serializer); 393 et_stop(sc); 394 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 395 lwkt_serialize_exit(ifp->if_serializer); 396 397 ether_ifdetach(ifp); 398 } 399 400 if (sc->sc_sysctl_tree != NULL) 401 sysctl_ctx_free(&sc->sc_sysctl_ctx); 402 403 if (sc->sc_miibus != NULL) 404 device_delete_child(dev, sc->sc_miibus); 405 bus_generic_detach(dev); 406 407 if (sc->sc_irq_res != NULL) { 408 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 409 sc->sc_irq_res); 410 } 411 412 if (sc->sc_mem_res != NULL) { 413 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 414 sc->sc_mem_res); 415 } 416 417 et_dma_free(dev); 418 419 return 0; 420 } 421 422 static int 423 et_shutdown(device_t dev) 424 { 425 struct et_softc *sc = device_get_softc(dev); 426 struct ifnet *ifp = &sc->arpcom.ac_if; 427 428 lwkt_serialize_enter(ifp->if_serializer); 429 et_stop(sc); 430 lwkt_serialize_exit(ifp->if_serializer); 431 return 0; 432 } 433 434 static int 435 et_miibus_readreg(device_t dev, int phy, int reg) 436 { 437 struct et_softc *sc = device_get_softc(dev); 438 uint32_t val; 439 int i, ret; 440 441 /* Stop any pending operations */ 442 CSR_WRITE_4(sc, ET_MII_CMD, 0); 443 444 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 445 __SHIFTIN(reg, ET_MII_ADDR_REG); 446 CSR_WRITE_4(sc, ET_MII_ADDR, val); 447 448 /* Start reading */ 449 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 450 451 #define NRETRY 50 452 453 for (i = 0; i < NRETRY; ++i) { 454 val = CSR_READ_4(sc, ET_MII_IND); 455 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 456 break; 457 DELAY(50); 458 } 459 if (i == NRETRY) { 460 if_printf(&sc->arpcom.ac_if, 461 "read phy %d, reg %d timed out\n", phy, reg); 462 ret = 0; 463 goto back; 464 } 465 466 #undef NRETRY 467 468 val = CSR_READ_4(sc, ET_MII_STAT); 469 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 470 471 back: 472 /* Make sure that the current operation is stopped */ 473 CSR_WRITE_4(sc, ET_MII_CMD, 0); 474 return ret; 475 } 476 477 static int 478 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 479 { 480 struct et_softc *sc = device_get_softc(dev); 481 uint32_t val; 482 int i; 483 484 /* Stop any pending operations */ 485 CSR_WRITE_4(sc, ET_MII_CMD, 0); 486 487 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 488 __SHIFTIN(reg, ET_MII_ADDR_REG); 489 CSR_WRITE_4(sc, ET_MII_ADDR, val); 490 491 /* Start writing */ 492 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 493 494 #define NRETRY 100 495 496 for (i = 0; i < NRETRY; ++i) { 497 val = CSR_READ_4(sc, ET_MII_IND); 498 if ((val & ET_MII_IND_BUSY) == 0) 499 break; 500 DELAY(50); 501 } 502 if (i == NRETRY) { 503 if_printf(&sc->arpcom.ac_if, 504 "write phy %d, reg %d timed out\n", phy, reg); 505 et_miibus_readreg(dev, phy, reg); 506 } 507 508 #undef NRETRY 509 510 /* Make sure that the current operation is stopped */ 511 CSR_WRITE_4(sc, ET_MII_CMD, 0); 512 return 0; 513 } 514 515 static void 516 et_miibus_statchg(device_t dev) 517 { 518 et_setmedia(device_get_softc(dev)); 519 } 520 521 static int 522 et_ifmedia_upd(struct ifnet *ifp) 523 { 524 struct et_softc *sc = ifp->if_softc; 525 struct mii_data *mii = device_get_softc(sc->sc_miibus); 526 527 if (mii->mii_instance != 0) { 528 struct mii_softc *miisc; 529 530 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 531 mii_phy_reset(miisc); 532 } 533 mii_mediachg(mii); 534 535 return 0; 536 } 537 538 static void 539 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 540 { 541 struct et_softc *sc = ifp->if_softc; 542 struct mii_data *mii = device_get_softc(sc->sc_miibus); 543 544 mii_pollstat(mii); 545 ifmr->ifm_active = mii->mii_media_active; 546 ifmr->ifm_status = mii->mii_media_status; 547 } 548 549 static void 550 et_stop(struct et_softc *sc) 551 { 552 struct ifnet *ifp = &sc->arpcom.ac_if; 553 554 ASSERT_SERIALIZED(ifp->if_serializer); 555 556 callout_stop(&sc->sc_tick); 557 558 et_stop_rxdma(sc); 559 et_stop_txdma(sc); 560 561 et_disable_intrs(sc); 562 563 et_free_tx_ring(sc); 564 et_free_rx_ring(sc); 565 566 et_reset(sc); 567 568 sc->sc_tx = 0; 569 sc->sc_tx_intr = 0; 570 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 571 572 ifp->if_timer = 0; 573 ifp->if_flags &= ~IFF_RUNNING; 574 ifq_clr_oactive(&ifp->if_snd); 575 } 576 577 static int 578 et_bus_config(device_t dev) 579 { 580 uint32_t val, max_plsz; 581 uint16_t ack_latency, replay_timer; 582 583 /* 584 * Test whether EEPROM is valid 585 * NOTE: Read twice to get the correct value 586 */ 587 pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1); 588 val = pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1); 589 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 590 device_printf(dev, "EEPROM status error 0x%02x\n", val); 591 return ENXIO; 592 } 593 594 /* TODO: LED */ 595 596 /* 597 * Configure ACK latency and replay timer according to 598 * max playload size 599 */ 600 val = pci_read_config(dev, ET_PCIR_DEVICE_CAPS, 4); 601 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 602 603 switch (max_plsz) { 604 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 605 ack_latency = ET_PCIV_ACK_LATENCY_128; 606 replay_timer = ET_PCIV_REPLAY_TIMER_128; 607 break; 608 609 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 610 ack_latency = ET_PCIV_ACK_LATENCY_256; 611 replay_timer = ET_PCIV_REPLAY_TIMER_256; 612 break; 613 614 default: 615 ack_latency = pci_read_config(dev, ET_PCIR_ACK_LATENCY, 2); 616 replay_timer = pci_read_config(dev, ET_PCIR_REPLAY_TIMER, 2); 617 device_printf(dev, "ack latency %u, replay timer %u\n", 618 ack_latency, replay_timer); 619 break; 620 } 621 if (ack_latency != 0) { 622 pci_write_config(dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 623 pci_write_config(dev, ET_PCIR_REPLAY_TIMER, replay_timer, 2); 624 } 625 626 /* 627 * Set L0s and L1 latency timer to 2us 628 */ 629 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 630 pci_write_config(dev, ET_PCIR_L0S_L1_LATENCY, val, 1); 631 632 /* 633 * Set max read request size to 2048 bytes 634 */ 635 val = pci_read_config(dev, ET_PCIR_DEVICE_CTRL, 2); 636 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 637 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 638 pci_write_config(dev, ET_PCIR_DEVICE_CTRL, val, 2); 639 640 return 0; 641 } 642 643 static void 644 et_get_eaddr(device_t dev, uint8_t eaddr[]) 645 { 646 uint32_t val; 647 int i; 648 649 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 650 for (i = 0; i < 4; ++i) 651 eaddr[i] = (val >> (8 * i)) & 0xff; 652 653 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 654 for (; i < ETHER_ADDR_LEN; ++i) 655 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 656 } 657 658 static void 659 et_reset(struct et_softc *sc) 660 { 661 CSR_WRITE_4(sc, ET_MAC_CFG1, 662 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 663 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 664 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 665 666 CSR_WRITE_4(sc, ET_SWRST, 667 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 668 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 669 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 670 671 CSR_WRITE_4(sc, ET_MAC_CFG1, 672 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 673 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 674 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 675 } 676 677 static void 678 et_disable_intrs(struct et_softc *sc) 679 { 680 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 681 } 682 683 static void 684 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 685 { 686 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 687 } 688 689 static int 690 et_dma_alloc(device_t dev) 691 { 692 struct et_softc *sc = device_get_softc(dev); 693 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 694 struct et_txstatus_data *txsd = &sc->sc_tx_status; 695 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 696 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 697 int i, error; 698 699 /* 700 * Create top level DMA tag 701 */ 702 error = bus_dma_tag_create(NULL, 1, 0, 703 BUS_SPACE_MAXADDR, 704 BUS_SPACE_MAXADDR, 705 NULL, NULL, 706 BUS_SPACE_MAXSIZE_32BIT, 707 0, 708 BUS_SPACE_MAXSIZE_32BIT, 709 0, &sc->sc_dtag); 710 if (error) { 711 device_printf(dev, "can't create DMA tag\n"); 712 return error; 713 } 714 715 /* 716 * Create TX ring DMA stuffs 717 */ 718 tx_ring->tr_desc = bus_dmamem_coherent_any(sc->sc_dtag, 719 ET_ALIGN, ET_TX_RING_SIZE, 720 BUS_DMA_WAITOK | BUS_DMA_ZERO, 721 &tx_ring->tr_dtag, &tx_ring->tr_dmap, 722 &tx_ring->tr_paddr); 723 if (tx_ring->tr_desc == NULL) { 724 device_printf(dev, "can't create TX ring DMA stuffs\n"); 725 return ENOMEM; 726 } 727 728 /* 729 * Create TX status DMA stuffs 730 */ 731 txsd->txsd_status = bus_dmamem_coherent_any(sc->sc_dtag, 732 ET_ALIGN, sizeof(uint32_t), 733 BUS_DMA_WAITOK | BUS_DMA_ZERO, 734 &txsd->txsd_dtag, &txsd->txsd_dmap, 735 &txsd->txsd_paddr); 736 if (txsd->txsd_status == NULL) { 737 device_printf(dev, "can't create TX status DMA stuffs\n"); 738 return ENOMEM; 739 } 740 741 /* 742 * Create DMA stuffs for RX rings 743 */ 744 for (i = 0; i < ET_RX_NRING; ++i) { 745 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 746 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 747 748 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 749 750 rx_ring->rr_desc = bus_dmamem_coherent_any(sc->sc_dtag, 751 ET_ALIGN, ET_RX_RING_SIZE, 752 BUS_DMA_WAITOK | BUS_DMA_ZERO, 753 &rx_ring->rr_dtag, &rx_ring->rr_dmap, 754 &rx_ring->rr_paddr); 755 if (rx_ring->rr_desc == NULL) { 756 device_printf(dev, "can't create DMA stuffs for " 757 "the %d RX ring\n", i); 758 return ENOMEM; 759 } 760 rx_ring->rr_posreg = rx_ring_posreg[i]; 761 } 762 763 /* 764 * Create RX stat ring DMA stuffs 765 */ 766 rxst_ring->rsr_stat = bus_dmamem_coherent_any(sc->sc_dtag, 767 ET_ALIGN, ET_RXSTAT_RING_SIZE, 768 BUS_DMA_WAITOK | BUS_DMA_ZERO, 769 &rxst_ring->rsr_dtag, &rxst_ring->rsr_dmap, 770 &rxst_ring->rsr_paddr); 771 if (rxst_ring->rsr_stat == NULL) { 772 device_printf(dev, "can't create RX stat ring DMA stuffs\n"); 773 return ENOMEM; 774 } 775 776 /* 777 * Create RX status DMA stuffs 778 */ 779 rxsd->rxsd_status = bus_dmamem_coherent_any(sc->sc_dtag, 780 ET_ALIGN, sizeof(struct et_rxstatus), 781 BUS_DMA_WAITOK | BUS_DMA_ZERO, 782 &rxsd->rxsd_dtag, &rxsd->rxsd_dmap, 783 &rxsd->rxsd_paddr); 784 if (rxsd->rxsd_status == NULL) { 785 device_printf(dev, "can't create RX status DMA stuffs\n"); 786 return ENOMEM; 787 } 788 789 /* 790 * Create mbuf DMA stuffs 791 */ 792 error = et_dma_mbuf_create(dev); 793 if (error) 794 return error; 795 796 /* 797 * Create jumbo buffer DMA stuffs 798 * NOTE: Allow it to fail 799 */ 800 if (et_jumbo_mem_alloc(dev) == 0) 801 sc->sc_flags |= ET_FLAG_JUMBO; 802 803 return 0; 804 } 805 806 static void 807 et_dma_free(device_t dev) 808 { 809 struct et_softc *sc = device_get_softc(dev); 810 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 811 struct et_txstatus_data *txsd = &sc->sc_tx_status; 812 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 813 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 814 int i, rx_done[ET_RX_NRING]; 815 816 /* 817 * Destroy TX ring DMA stuffs 818 */ 819 et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc, 820 tx_ring->tr_dmap); 821 822 /* 823 * Destroy TX status DMA stuffs 824 */ 825 et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status, 826 txsd->txsd_dmap); 827 828 /* 829 * Destroy DMA stuffs for RX rings 830 */ 831 for (i = 0; i < ET_RX_NRING; ++i) { 832 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 833 834 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc, 835 rx_ring->rr_dmap); 836 } 837 838 /* 839 * Destroy RX stat ring DMA stuffs 840 */ 841 et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat, 842 rxst_ring->rsr_dmap); 843 844 /* 845 * Destroy RX status DMA stuffs 846 */ 847 et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status, 848 rxsd->rxsd_dmap); 849 850 /* 851 * Destroy mbuf DMA stuffs 852 */ 853 for (i = 0; i < ET_RX_NRING; ++i) 854 rx_done[i] = ET_RX_NDESC; 855 et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done); 856 857 /* 858 * Destroy jumbo buffer DMA stuffs 859 */ 860 if (sc->sc_flags & ET_FLAG_JUMBO) 861 et_jumbo_mem_free(dev); 862 863 /* 864 * Destroy top level DMA tag 865 */ 866 if (sc->sc_dtag != NULL) 867 bus_dma_tag_destroy(sc->sc_dtag); 868 } 869 870 static int 871 et_dma_mbuf_create(device_t dev) 872 { 873 struct et_softc *sc = device_get_softc(dev); 874 struct et_txbuf_data *tbd = &sc->sc_tx_data; 875 int i, error, rx_done[ET_RX_NRING]; 876 877 /* 878 * Create RX mbuf DMA tag 879 */ 880 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 881 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 882 NULL, NULL, 883 MCLBYTES, 1, MCLBYTES, 884 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 885 &sc->sc_rxbuf_dtag); 886 if (error) { 887 device_printf(dev, "can't create RX mbuf DMA tag\n"); 888 return error; 889 } 890 891 /* 892 * Create spare DMA map for RX mbufs 893 */ 894 error = bus_dmamap_create(sc->sc_rxbuf_dtag, BUS_DMA_WAITOK, 895 &sc->sc_rxbuf_tmp_dmap); 896 if (error) { 897 device_printf(dev, "can't create spare mbuf DMA map\n"); 898 bus_dma_tag_destroy(sc->sc_rxbuf_dtag); 899 sc->sc_rxbuf_dtag = NULL; 900 return error; 901 } 902 903 /* 904 * Create DMA maps for RX mbufs 905 */ 906 bzero(rx_done, sizeof(rx_done)); 907 for (i = 0; i < ET_RX_NRING; ++i) { 908 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 909 int j; 910 911 for (j = 0; j < ET_RX_NDESC; ++j) { 912 error = bus_dmamap_create(sc->sc_rxbuf_dtag, 913 BUS_DMA_WAITOK, 914 &rbd->rbd_buf[j].rb_dmap); 915 if (error) { 916 device_printf(dev, "can't create %d RX mbuf " 917 "for %d RX ring\n", j, i); 918 rx_done[i] = j; 919 et_dma_mbuf_destroy(dev, 0, rx_done); 920 return error; 921 } 922 } 923 rx_done[i] = ET_RX_NDESC; 924 925 rbd->rbd_softc = sc; 926 rbd->rbd_ring = &sc->sc_rx_ring[i]; 927 } 928 929 /* 930 * Create TX mbuf DMA tag 931 */ 932 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 933 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 934 NULL, NULL, 935 ET_JUMBO_FRAMELEN, ET_NSEG_MAX, MCLBYTES, 936 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 937 BUS_DMA_ONEBPAGE, 938 &sc->sc_txbuf_dtag); 939 if (error) { 940 device_printf(dev, "can't create TX mbuf DMA tag\n"); 941 return error; 942 } 943 944 /* 945 * Create DMA maps for TX mbufs 946 */ 947 for (i = 0; i < ET_TX_NDESC; ++i) { 948 error = bus_dmamap_create(sc->sc_txbuf_dtag, 949 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 950 &tbd->tbd_buf[i].tb_dmap); 951 if (error) { 952 device_printf(dev, "can't create %d TX mbuf " 953 "DMA map\n", i); 954 et_dma_mbuf_destroy(dev, i, rx_done); 955 return error; 956 } 957 } 958 959 return 0; 960 } 961 962 static void 963 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[]) 964 { 965 struct et_softc *sc = device_get_softc(dev); 966 struct et_txbuf_data *tbd = &sc->sc_tx_data; 967 int i; 968 969 /* 970 * Destroy DMA tag and maps for RX mbufs 971 */ 972 if (sc->sc_rxbuf_dtag) { 973 for (i = 0; i < ET_RX_NRING; ++i) { 974 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 975 int j; 976 977 for (j = 0; j < rx_done[i]; ++j) { 978 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 979 980 KASSERT(rb->rb_mbuf == NULL, 981 ("RX mbuf in %d RX ring is " 982 "not freed yet", i)); 983 bus_dmamap_destroy(sc->sc_rxbuf_dtag, 984 rb->rb_dmap); 985 } 986 } 987 bus_dmamap_destroy(sc->sc_rxbuf_dtag, sc->sc_rxbuf_tmp_dmap); 988 bus_dma_tag_destroy(sc->sc_rxbuf_dtag); 989 sc->sc_rxbuf_dtag = NULL; 990 } 991 992 /* 993 * Destroy DMA tag and maps for TX mbufs 994 */ 995 if (sc->sc_txbuf_dtag) { 996 for (i = 0; i < tx_done; ++i) { 997 struct et_txbuf *tb = &tbd->tbd_buf[i]; 998 999 KASSERT(tb->tb_mbuf == NULL, 1000 ("TX mbuf is not freed yet")); 1001 bus_dmamap_destroy(sc->sc_txbuf_dtag, tb->tb_dmap); 1002 } 1003 bus_dma_tag_destroy(sc->sc_txbuf_dtag); 1004 sc->sc_txbuf_dtag = NULL; 1005 } 1006 } 1007 1008 static void 1009 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 1010 { 1011 if (dtag != NULL) { 1012 bus_dmamap_unload(dtag, dmap); 1013 bus_dmamem_free(dtag, addr, dmap); 1014 bus_dma_tag_destroy(dtag); 1015 } 1016 } 1017 1018 static void 1019 et_chip_attach(struct et_softc *sc) 1020 { 1021 uint32_t val; 1022 1023 /* 1024 * Perform minimal initialization 1025 */ 1026 1027 /* Disable loopback */ 1028 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1029 1030 /* Reset MAC */ 1031 CSR_WRITE_4(sc, ET_MAC_CFG1, 1032 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1033 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1034 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1035 1036 /* 1037 * Setup half duplex mode 1038 */ 1039 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1040 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1041 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1042 ET_MAC_HDX_EXC_DEFER; 1043 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1044 1045 /* Clear MAC control */ 1046 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1047 1048 /* Reset MII */ 1049 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1050 1051 /* Bring MAC out of reset state */ 1052 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1053 1054 /* Enable memory controllers */ 1055 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1056 } 1057 1058 static void 1059 et_intr(void *xsc) 1060 { 1061 struct et_softc *sc = xsc; 1062 struct ifnet *ifp = &sc->arpcom.ac_if; 1063 uint32_t intrs; 1064 1065 ASSERT_SERIALIZED(ifp->if_serializer); 1066 1067 if ((ifp->if_flags & IFF_RUNNING) == 0) 1068 return; 1069 1070 et_disable_intrs(sc); 1071 1072 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 1073 intrs &= ET_INTRS; 1074 if (intrs == 0) /* Not interested */ 1075 goto back; 1076 1077 if (intrs & ET_INTR_RXEOF) 1078 et_rxeof(sc); 1079 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 1080 et_txeof(sc, 1); 1081 if (intrs & ET_INTR_TIMER) 1082 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1083 back: 1084 et_enable_intrs(sc, ET_INTRS); 1085 } 1086 1087 static void 1088 et_init(void *xsc) 1089 { 1090 struct et_softc *sc = xsc; 1091 struct ifnet *ifp = &sc->arpcom.ac_if; 1092 const struct et_bsize *arr; 1093 int error, i; 1094 1095 ASSERT_SERIALIZED(ifp->if_serializer); 1096 1097 et_stop(sc); 1098 1099 arr = ET_FRAMELEN(ifp->if_mtu) < MCLBYTES ? 1100 et_bufsize_std : et_bufsize_jumbo; 1101 for (i = 0; i < ET_RX_NRING; ++i) { 1102 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize; 1103 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf; 1104 sc->sc_rx_data[i].rbd_jumbo = arr[i].jumbo; 1105 } 1106 1107 error = et_init_tx_ring(sc); 1108 if (error) 1109 goto back; 1110 1111 error = et_init_rx_ring(sc); 1112 if (error) 1113 goto back; 1114 1115 error = et_chip_init(sc); 1116 if (error) 1117 goto back; 1118 1119 error = et_enable_txrx(sc, 1); 1120 if (error) 1121 goto back; 1122 1123 et_enable_intrs(sc, ET_INTRS); 1124 1125 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1126 1127 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1128 1129 ifp->if_flags |= IFF_RUNNING; 1130 ifq_clr_oactive(&ifp->if_snd); 1131 back: 1132 if (error) 1133 et_stop(sc); 1134 } 1135 1136 static int 1137 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1138 { 1139 struct et_softc *sc = ifp->if_softc; 1140 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1141 struct ifreq *ifr = (struct ifreq *)data; 1142 int error = 0, max_framelen; 1143 1144 ASSERT_SERIALIZED(ifp->if_serializer); 1145 1146 switch (cmd) { 1147 case SIOCSIFFLAGS: 1148 if (ifp->if_flags & IFF_UP) { 1149 if (ifp->if_flags & IFF_RUNNING) { 1150 if ((ifp->if_flags ^ sc->sc_if_flags) & 1151 (IFF_ALLMULTI | IFF_PROMISC)) 1152 et_setmulti(sc); 1153 } else { 1154 et_init(sc); 1155 } 1156 } else { 1157 if (ifp->if_flags & IFF_RUNNING) 1158 et_stop(sc); 1159 } 1160 sc->sc_if_flags = ifp->if_flags; 1161 break; 1162 1163 case SIOCSIFMEDIA: 1164 case SIOCGIFMEDIA: 1165 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1166 break; 1167 1168 case SIOCADDMULTI: 1169 case SIOCDELMULTI: 1170 if (ifp->if_flags & IFF_RUNNING) 1171 et_setmulti(sc); 1172 break; 1173 1174 case SIOCSIFMTU: 1175 if (sc->sc_flags & ET_FLAG_JUMBO) 1176 max_framelen = ET_JUMBO_FRAMELEN; 1177 else 1178 max_framelen = MCLBYTES - 1; 1179 1180 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1181 error = EOPNOTSUPP; 1182 break; 1183 } 1184 1185 ifp->if_mtu = ifr->ifr_mtu; 1186 if (ifp->if_flags & IFF_RUNNING) 1187 et_init(sc); 1188 break; 1189 1190 default: 1191 error = ether_ioctl(ifp, cmd, data); 1192 break; 1193 } 1194 return error; 1195 } 1196 1197 static void 1198 et_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1199 { 1200 struct et_softc *sc = ifp->if_softc; 1201 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1202 int trans, oactive; 1203 1204 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1205 ASSERT_SERIALIZED(ifp->if_serializer); 1206 1207 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) { 1208 ifq_purge(&ifp->if_snd); 1209 return; 1210 } 1211 1212 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1213 return; 1214 1215 oactive = 0; 1216 trans = 0; 1217 for (;;) { 1218 struct mbuf *m; 1219 int error; 1220 1221 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1222 if (oactive) { 1223 ifq_set_oactive(&ifp->if_snd); 1224 break; 1225 } 1226 1227 et_txeof(sc, 0); 1228 oactive = 1; 1229 continue; 1230 } 1231 1232 m = ifq_dequeue(&ifp->if_snd, NULL); 1233 if (m == NULL) 1234 break; 1235 1236 error = et_encap(sc, &m); 1237 if (error) { 1238 IFNET_STAT_INC(ifp, oerrors, 1); 1239 KKASSERT(m == NULL); 1240 1241 if (error == EFBIG) { 1242 /* 1243 * Excessive fragmented packets 1244 */ 1245 if (oactive) { 1246 ifq_set_oactive(&ifp->if_snd); 1247 break; 1248 } 1249 et_txeof(sc, 0); 1250 oactive = 1; 1251 } 1252 continue; 1253 } else { 1254 oactive = 0; 1255 } 1256 trans = 1; 1257 1258 BPF_MTAP(ifp, m); 1259 } 1260 1261 if (trans) 1262 ifp->if_timer = 5; 1263 } 1264 1265 static void 1266 et_watchdog(struct ifnet *ifp) 1267 { 1268 ASSERT_SERIALIZED(ifp->if_serializer); 1269 1270 if_printf(ifp, "watchdog timed out\n"); 1271 1272 ifp->if_init(ifp->if_softc); 1273 if_devstart(ifp); 1274 } 1275 1276 static int 1277 et_stop_rxdma(struct et_softc *sc) 1278 { 1279 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1280 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1281 1282 DELAY(5); 1283 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1284 if_printf(&sc->arpcom.ac_if, "can't stop RX DMA engine\n"); 1285 return ETIMEDOUT; 1286 } 1287 return 0; 1288 } 1289 1290 static int 1291 et_stop_txdma(struct et_softc *sc) 1292 { 1293 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1294 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1295 return 0; 1296 } 1297 1298 static void 1299 et_free_tx_ring(struct et_softc *sc) 1300 { 1301 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1302 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1303 int i; 1304 1305 for (i = 0; i < ET_TX_NDESC; ++i) { 1306 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1307 1308 if (tb->tb_mbuf != NULL) { 1309 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap); 1310 m_freem(tb->tb_mbuf); 1311 tb->tb_mbuf = NULL; 1312 } 1313 } 1314 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1315 } 1316 1317 static void 1318 et_free_rx_ring(struct et_softc *sc) 1319 { 1320 int n; 1321 1322 for (n = 0; n < ET_RX_NRING; ++n) { 1323 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1324 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1325 int i; 1326 1327 for (i = 0; i < ET_RX_NDESC; ++i) { 1328 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1329 1330 if (rb->rb_mbuf != NULL) { 1331 if (!rbd->rbd_jumbo) { 1332 bus_dmamap_unload(sc->sc_rxbuf_dtag, 1333 rb->rb_dmap); 1334 } 1335 m_freem(rb->rb_mbuf); 1336 rb->rb_mbuf = NULL; 1337 } 1338 } 1339 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1340 } 1341 } 1342 1343 static void 1344 et_setmulti(struct et_softc *sc) 1345 { 1346 struct ifnet *ifp = &sc->arpcom.ac_if; 1347 uint32_t hash[4] = { 0, 0, 0, 0 }; 1348 uint32_t rxmac_ctrl, pktfilt; 1349 struct ifmultiaddr *ifma; 1350 int i, count; 1351 1352 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1353 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1354 1355 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1356 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1357 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1358 goto back; 1359 } 1360 1361 count = 0; 1362 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1363 uint32_t *hp, h; 1364 1365 if (ifma->ifma_addr->sa_family != AF_LINK) 1366 continue; 1367 1368 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1369 ifma->ifma_addr), ETHER_ADDR_LEN); 1370 h = (h & 0x3f800000) >> 23; 1371 1372 hp = &hash[0]; 1373 if (h >= 32 && h < 64) { 1374 h -= 32; 1375 hp = &hash[1]; 1376 } else if (h >= 64 && h < 96) { 1377 h -= 64; 1378 hp = &hash[2]; 1379 } else if (h >= 96) { 1380 h -= 96; 1381 hp = &hash[3]; 1382 } 1383 *hp |= (1 << h); 1384 1385 ++count; 1386 } 1387 1388 for (i = 0; i < 4; ++i) 1389 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1390 1391 if (count > 0) 1392 pktfilt |= ET_PKTFILT_MCAST; 1393 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1394 back: 1395 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1396 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1397 } 1398 1399 static int 1400 et_chip_init(struct et_softc *sc) 1401 { 1402 struct ifnet *ifp = &sc->arpcom.ac_if; 1403 uint32_t rxq_end; 1404 int error, frame_len, rxmem_size; 1405 1406 /* 1407 * Split 16Kbytes internal memory between TX and RX 1408 * according to frame length. 1409 */ 1410 frame_len = ET_FRAMELEN(ifp->if_mtu); 1411 if (frame_len < 2048) { 1412 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1413 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1414 rxmem_size = ET_MEM_SIZE / 2; 1415 } else { 1416 rxmem_size = ET_MEM_SIZE - 1417 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1418 } 1419 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1420 1421 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1422 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1423 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1424 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1425 1426 /* No loopback */ 1427 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1428 1429 /* Clear MSI configure */ 1430 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1431 1432 /* Disable timer */ 1433 CSR_WRITE_4(sc, ET_TIMER, 0); 1434 1435 /* Initialize MAC */ 1436 et_init_mac(sc); 1437 1438 /* Enable memory controllers */ 1439 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1440 1441 /* Initialize RX MAC */ 1442 et_init_rxmac(sc); 1443 1444 /* Initialize TX MAC */ 1445 et_init_txmac(sc); 1446 1447 /* Initialize RX DMA engine */ 1448 error = et_init_rxdma(sc); 1449 if (error) 1450 return error; 1451 1452 /* Initialize TX DMA engine */ 1453 error = et_init_txdma(sc); 1454 if (error) 1455 return error; 1456 1457 return 0; 1458 } 1459 1460 static int 1461 et_init_tx_ring(struct et_softc *sc) 1462 { 1463 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1464 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1465 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1466 1467 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1468 1469 tbd->tbd_start_index = 0; 1470 tbd->tbd_start_wrap = 0; 1471 tbd->tbd_used = 0; 1472 1473 bzero(txsd->txsd_status, sizeof(uint32_t)); 1474 1475 return 0; 1476 } 1477 1478 static int 1479 et_init_rx_ring(struct et_softc *sc) 1480 { 1481 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1482 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1483 int n; 1484 1485 for (n = 0; n < ET_RX_NRING; ++n) { 1486 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1487 int i, error; 1488 1489 for (i = 0; i < ET_RX_NDESC; ++i) { 1490 error = rbd->rbd_newbuf(rbd, i, 1); 1491 if (error) { 1492 if_printf(&sc->arpcom.ac_if, "%d ring %d buf, " 1493 "newbuf failed: %d\n", n, i, error); 1494 return error; 1495 } 1496 } 1497 } 1498 1499 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1500 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1501 1502 return 0; 1503 } 1504 1505 static int 1506 et_init_rxdma(struct et_softc *sc) 1507 { 1508 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1509 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1510 struct et_rxdesc_ring *rx_ring; 1511 int error; 1512 1513 error = et_stop_rxdma(sc); 1514 if (error) { 1515 if_printf(&sc->arpcom.ac_if, "can't init RX DMA engine\n"); 1516 return error; 1517 } 1518 1519 /* 1520 * Install RX status 1521 */ 1522 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1523 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1524 1525 /* 1526 * Install RX stat ring 1527 */ 1528 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1529 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1530 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1531 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1532 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1533 1534 /* Match ET_RXSTAT_POS */ 1535 rxst_ring->rsr_index = 0; 1536 rxst_ring->rsr_wrap = 0; 1537 1538 /* 1539 * Install the 2nd RX descriptor ring 1540 */ 1541 rx_ring = &sc->sc_rx_ring[1]; 1542 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1543 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1544 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1545 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1546 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1547 1548 /* Match ET_RX_RING1_POS */ 1549 rx_ring->rr_index = 0; 1550 rx_ring->rr_wrap = 1; 1551 1552 /* 1553 * Install the 1st RX descriptor ring 1554 */ 1555 rx_ring = &sc->sc_rx_ring[0]; 1556 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1557 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1558 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1559 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1560 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1561 1562 /* Match ET_RX_RING0_POS */ 1563 rx_ring->rr_index = 0; 1564 rx_ring->rr_wrap = 1; 1565 1566 /* 1567 * RX intr moderation 1568 */ 1569 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1570 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1571 1572 return 0; 1573 } 1574 1575 static int 1576 et_init_txdma(struct et_softc *sc) 1577 { 1578 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1579 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1580 int error; 1581 1582 error = et_stop_txdma(sc); 1583 if (error) { 1584 if_printf(&sc->arpcom.ac_if, "can't init TX DMA engine\n"); 1585 return error; 1586 } 1587 1588 /* 1589 * Install TX descriptor ring 1590 */ 1591 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1592 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1593 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1594 1595 /* 1596 * Install TX status 1597 */ 1598 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1599 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1600 1601 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1602 1603 /* Match ET_TX_READY_POS */ 1604 tx_ring->tr_ready_index = 0; 1605 tx_ring->tr_ready_wrap = 0; 1606 1607 return 0; 1608 } 1609 1610 static void 1611 et_init_mac(struct et_softc *sc) 1612 { 1613 struct ifnet *ifp = &sc->arpcom.ac_if; 1614 const uint8_t *eaddr = IF_LLADDR(ifp); 1615 uint32_t val; 1616 1617 /* Reset MAC */ 1618 CSR_WRITE_4(sc, ET_MAC_CFG1, 1619 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1620 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1621 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1622 1623 /* 1624 * Setup inter packet gap 1625 */ 1626 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1627 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1628 __SHIFTIN(80, ET_IPG_MINIFG) | 1629 __SHIFTIN(96, ET_IPG_B2B); 1630 CSR_WRITE_4(sc, ET_IPG, val); 1631 1632 /* 1633 * Setup half duplex mode 1634 */ 1635 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1636 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1637 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1638 ET_MAC_HDX_EXC_DEFER; 1639 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1640 1641 /* Clear MAC control */ 1642 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1643 1644 /* Reset MII */ 1645 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1646 1647 /* 1648 * Set MAC address 1649 */ 1650 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1651 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1652 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1653 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1654 1655 /* Set max frame length */ 1656 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1657 1658 /* Bring MAC out of reset state */ 1659 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1660 } 1661 1662 static void 1663 et_init_rxmac(struct et_softc *sc) 1664 { 1665 struct ifnet *ifp = &sc->arpcom.ac_if; 1666 const uint8_t *eaddr = IF_LLADDR(ifp); 1667 uint32_t val; 1668 int i; 1669 1670 /* Disable RX MAC and WOL */ 1671 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1672 1673 /* 1674 * Clear all WOL related registers 1675 */ 1676 for (i = 0; i < 3; ++i) 1677 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1678 for (i = 0; i < 20; ++i) 1679 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1680 1681 /* 1682 * Set WOL source address. XXX is this necessary? 1683 */ 1684 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1685 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1686 val = (eaddr[0] << 8) | eaddr[1]; 1687 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1688 1689 /* Clear packet filters */ 1690 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1691 1692 /* No ucast filtering */ 1693 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1694 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1695 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1696 1697 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1698 /* 1699 * In order to transmit jumbo packets greater than 1700 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1701 * RX MAC and RX DMA needs to be reduced in size to 1702 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1703 * order to implement this, we must use "cut through" 1704 * mode in the RX MAC, which chops packets down into 1705 * segments. In this case we selected 256 bytes, 1706 * since this is the size of the PCI-Express TLP's 1707 * that the ET1310 uses. 1708 */ 1709 val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) | 1710 ET_RXMAC_MC_SEGSZ_ENABLE; 1711 } else { 1712 val = 0; 1713 } 1714 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1715 1716 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1717 1718 /* Initialize RX MAC management register */ 1719 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1720 1721 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1722 1723 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1724 ET_RXMAC_MGT_PASS_ECRC | 1725 ET_RXMAC_MGT_PASS_ELEN | 1726 ET_RXMAC_MGT_PASS_ETRUNC | 1727 ET_RXMAC_MGT_CHECK_PKT); 1728 1729 /* 1730 * Configure runt filtering (may not work on certain chip generation) 1731 */ 1732 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1733 CSR_WRITE_4(sc, ET_PKTFILT, val); 1734 1735 /* Enable RX MAC but leave WOL disabled */ 1736 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1737 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1738 1739 /* 1740 * Setup multicast hash and allmulti/promisc mode 1741 */ 1742 et_setmulti(sc); 1743 } 1744 1745 static void 1746 et_init_txmac(struct et_softc *sc) 1747 { 1748 /* Disable TX MAC and FC(?) */ 1749 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1750 1751 /* No flow control yet */ 1752 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1753 1754 /* Enable TX MAC but leave FC(?) diabled */ 1755 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1756 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1757 } 1758 1759 static int 1760 et_start_rxdma(struct et_softc *sc) 1761 { 1762 uint32_t val = 0; 1763 1764 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1765 ET_RXDMA_CTRL_RING0_SIZE) | 1766 ET_RXDMA_CTRL_RING0_ENABLE; 1767 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1768 ET_RXDMA_CTRL_RING1_SIZE) | 1769 ET_RXDMA_CTRL_RING1_ENABLE; 1770 1771 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1772 1773 DELAY(5); 1774 1775 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1776 if_printf(&sc->arpcom.ac_if, "can't start RX DMA engine\n"); 1777 return ETIMEDOUT; 1778 } 1779 return 0; 1780 } 1781 1782 static int 1783 et_start_txdma(struct et_softc *sc) 1784 { 1785 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1786 return 0; 1787 } 1788 1789 static int 1790 et_enable_txrx(struct et_softc *sc, int media_upd) 1791 { 1792 struct ifnet *ifp = &sc->arpcom.ac_if; 1793 uint32_t val; 1794 int i, error; 1795 1796 val = CSR_READ_4(sc, ET_MAC_CFG1); 1797 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1798 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1799 ET_MAC_CFG1_LOOPBACK); 1800 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1801 1802 if (media_upd) 1803 et_ifmedia_upd(ifp); 1804 else 1805 et_setmedia(sc); 1806 1807 #define NRETRY 100 1808 1809 for (i = 0; i < NRETRY; ++i) { 1810 val = CSR_READ_4(sc, ET_MAC_CFG1); 1811 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1812 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1813 break; 1814 1815 DELAY(10); 1816 } 1817 if (i == NRETRY) { 1818 if_printf(ifp, "can't enable RX/TX\n"); 1819 return 0; 1820 } 1821 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 1822 1823 #undef NRETRY 1824 1825 /* 1826 * Start TX/RX DMA engine 1827 */ 1828 error = et_start_rxdma(sc); 1829 if (error) 1830 return error; 1831 1832 error = et_start_txdma(sc); 1833 if (error) 1834 return error; 1835 1836 return 0; 1837 } 1838 1839 static void 1840 et_rxeof(struct et_softc *sc) 1841 { 1842 struct ifnet *ifp = &sc->arpcom.ac_if; 1843 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1844 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1845 uint32_t rxs_stat_ring; 1846 int rxst_wrap, rxst_index; 1847 1848 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1849 return; 1850 1851 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1852 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1853 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1854 1855 while (rxst_index != rxst_ring->rsr_index || 1856 rxst_wrap != rxst_ring->rsr_wrap) { 1857 struct et_rxbuf_data *rbd; 1858 struct et_rxdesc_ring *rx_ring; 1859 struct et_rxstat *st; 1860 struct mbuf *m; 1861 int buflen, buf_idx, ring_idx; 1862 uint32_t rxstat_pos, rxring_pos; 1863 1864 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1865 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1866 1867 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1868 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1869 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1870 1871 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1872 rxst_ring->rsr_index = 0; 1873 rxst_ring->rsr_wrap ^= 1; 1874 } 1875 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1876 ET_RXSTAT_POS_INDEX); 1877 if (rxst_ring->rsr_wrap) 1878 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1879 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1880 1881 if (ring_idx >= ET_RX_NRING) { 1882 IFNET_STAT_INC(ifp, ierrors, 1); 1883 if_printf(ifp, "invalid ring index %d\n", ring_idx); 1884 continue; 1885 } 1886 if (buf_idx >= ET_RX_NDESC) { 1887 IFNET_STAT_INC(ifp, ierrors, 1); 1888 if_printf(ifp, "invalid buf index %d\n", buf_idx); 1889 continue; 1890 } 1891 1892 rbd = &sc->sc_rx_data[ring_idx]; 1893 m = rbd->rbd_buf[buf_idx].rb_mbuf; 1894 1895 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1896 if (buflen < ETHER_CRC_LEN) { 1897 m_freem(m); 1898 IFNET_STAT_INC(ifp, ierrors, 1); 1899 } else { 1900 m->m_pkthdr.len = m->m_len = buflen; 1901 m->m_pkthdr.rcvif = ifp; 1902 1903 m_adj(m, -ETHER_CRC_LEN); 1904 1905 IFNET_STAT_INC(ifp, ipackets, 1); 1906 ifp->if_input(ifp, m); 1907 } 1908 } else { 1909 IFNET_STAT_INC(ifp, ierrors, 1); 1910 } 1911 m = NULL; /* Catch invalid reference */ 1912 1913 rx_ring = &sc->sc_rx_ring[ring_idx]; 1914 1915 if (buf_idx != rx_ring->rr_index) { 1916 if_printf(ifp, "WARNING!! ring %d, " 1917 "buf_idx %d, rr_idx %d\n", 1918 ring_idx, buf_idx, rx_ring->rr_index); 1919 } 1920 1921 KKASSERT(rx_ring->rr_index < ET_RX_NDESC); 1922 if (++rx_ring->rr_index == ET_RX_NDESC) { 1923 rx_ring->rr_index = 0; 1924 rx_ring->rr_wrap ^= 1; 1925 } 1926 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1927 if (rx_ring->rr_wrap) 1928 rxring_pos |= ET_RX_RING_POS_WRAP; 1929 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1930 } 1931 } 1932 1933 static int 1934 et_encap(struct et_softc *sc, struct mbuf **m0) 1935 { 1936 bus_dma_segment_t segs[ET_NSEG_MAX]; 1937 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1938 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1939 struct et_txdesc *td; 1940 bus_dmamap_t map; 1941 int error, maxsegs, nsegs, first_idx, last_idx, i; 1942 uint32_t tx_ready_pos, last_td_ctrl2; 1943 1944 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1945 if (maxsegs > ET_NSEG_MAX) 1946 maxsegs = ET_NSEG_MAX; 1947 KASSERT(maxsegs >= ET_NSEG_SPARE, 1948 ("not enough spare TX desc (%d)", maxsegs)); 1949 1950 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1951 first_idx = tx_ring->tr_ready_index; 1952 map = tbd->tbd_buf[first_idx].tb_dmap; 1953 1954 error = bus_dmamap_load_mbuf_defrag(sc->sc_txbuf_dtag, map, m0, 1955 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1956 if (error) 1957 goto back; 1958 bus_dmamap_sync(sc->sc_txbuf_dtag, map, BUS_DMASYNC_PREWRITE); 1959 1960 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1961 sc->sc_tx += nsegs; 1962 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1963 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1964 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1965 } 1966 1967 last_idx = -1; 1968 for (i = 0; i < nsegs; ++i) { 1969 int idx; 1970 1971 idx = (first_idx + i) % ET_TX_NDESC; 1972 td = &tx_ring->tr_desc[idx]; 1973 td->td_addr_hi = ET_ADDR_HI(segs[i].ds_addr); 1974 td->td_addr_lo = ET_ADDR_LO(segs[i].ds_addr); 1975 td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN); 1976 1977 if (i == nsegs - 1) { /* Last frag */ 1978 td->td_ctrl2 = last_td_ctrl2; 1979 last_idx = idx; 1980 } 1981 1982 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1983 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1984 tx_ring->tr_ready_index = 0; 1985 tx_ring->tr_ready_wrap ^= 1; 1986 } 1987 } 1988 td = &tx_ring->tr_desc[first_idx]; 1989 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1990 1991 KKASSERT(last_idx >= 0); 1992 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1993 tbd->tbd_buf[last_idx].tb_dmap = map; 1994 tbd->tbd_buf[last_idx].tb_mbuf = *m0; 1995 1996 tbd->tbd_used += nsegs; 1997 KKASSERT(tbd->tbd_used <= ET_TX_NDESC); 1998 1999 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 2000 ET_TX_READY_POS_INDEX); 2001 if (tx_ring->tr_ready_wrap) 2002 tx_ready_pos |= ET_TX_READY_POS_WRAP; 2003 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 2004 2005 error = 0; 2006 back: 2007 if (error) { 2008 m_freem(*m0); 2009 *m0 = NULL; 2010 } 2011 return error; 2012 } 2013 2014 static void 2015 et_txeof(struct et_softc *sc, int start) 2016 { 2017 struct ifnet *ifp = &sc->arpcom.ac_if; 2018 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 2019 struct et_txbuf_data *tbd = &sc->sc_tx_data; 2020 uint32_t tx_done; 2021 int end, wrap; 2022 2023 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2024 return; 2025 2026 if (tbd->tbd_used == 0) 2027 return; 2028 2029 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2030 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 2031 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2032 2033 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2034 struct et_txbuf *tb; 2035 2036 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC); 2037 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2038 2039 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 2040 sizeof(struct et_txdesc)); 2041 2042 if (tb->tb_mbuf != NULL) { 2043 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap); 2044 m_freem(tb->tb_mbuf); 2045 tb->tb_mbuf = NULL; 2046 IFNET_STAT_INC(ifp, opackets, 1); 2047 } 2048 2049 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2050 tbd->tbd_start_index = 0; 2051 tbd->tbd_start_wrap ^= 1; 2052 } 2053 2054 KKASSERT(tbd->tbd_used > 0); 2055 tbd->tbd_used--; 2056 } 2057 2058 if (tbd->tbd_used == 0) 2059 ifp->if_timer = 0; 2060 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 2061 ifq_clr_oactive(&ifp->if_snd); 2062 2063 if (start) 2064 if_devstart(ifp); 2065 } 2066 2067 static void 2068 et_tick(void *xsc) 2069 { 2070 struct et_softc *sc = xsc; 2071 struct ifnet *ifp = &sc->arpcom.ac_if; 2072 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2073 2074 lwkt_serialize_enter(ifp->if_serializer); 2075 2076 mii_tick(mii); 2077 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 2078 (mii->mii_media_status & IFM_ACTIVE) && 2079 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2080 if_printf(ifp, "Link up, enable TX/RX\n"); 2081 if (et_enable_txrx(sc, 0) == 0) 2082 if_devstart(ifp); 2083 } 2084 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2085 2086 lwkt_serialize_exit(ifp->if_serializer); 2087 } 2088 2089 static int 2090 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2091 { 2092 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 2093 } 2094 2095 static int 2096 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2097 { 2098 return et_newbuf(rbd, buf_idx, init, MHLEN); 2099 } 2100 2101 static int 2102 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2103 { 2104 struct et_softc *sc = rbd->rbd_softc; 2105 struct et_rxbuf *rb; 2106 struct mbuf *m; 2107 bus_dma_segment_t seg; 2108 bus_dmamap_t dmap; 2109 int error, len, nseg; 2110 2111 KASSERT(!rbd->rbd_jumbo, ("calling %s with jumbo ring", __func__)); 2112 2113 KKASSERT(buf_idx < ET_RX_NDESC); 2114 rb = &rbd->rbd_buf[buf_idx]; 2115 2116 m = m_getl(len0, init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR, &len); 2117 if (m == NULL) { 2118 error = ENOBUFS; 2119 2120 if (init) { 2121 if_printf(&sc->arpcom.ac_if, 2122 "m_getl failed, size %d\n", len0); 2123 return error; 2124 } else { 2125 goto back; 2126 } 2127 } 2128 m->m_len = m->m_pkthdr.len = len; 2129 2130 /* 2131 * Try load RX mbuf into temporary DMA tag 2132 */ 2133 error = bus_dmamap_load_mbuf_segment(sc->sc_rxbuf_dtag, 2134 sc->sc_rxbuf_tmp_dmap, m, &seg, 1, &nseg, 2135 BUS_DMA_NOWAIT); 2136 if (error) { 2137 m_freem(m); 2138 if (init) { 2139 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 2140 return error; 2141 } else { 2142 goto back; 2143 } 2144 } 2145 2146 if (!init) { 2147 bus_dmamap_sync(sc->sc_rxbuf_dtag, rb->rb_dmap, 2148 BUS_DMASYNC_POSTREAD); 2149 bus_dmamap_unload(sc->sc_rxbuf_dtag, rb->rb_dmap); 2150 } 2151 rb->rb_mbuf = m; 2152 rb->rb_paddr = seg.ds_addr; 2153 2154 /* 2155 * Swap RX buf's DMA map with the loaded temporary one 2156 */ 2157 dmap = rb->rb_dmap; 2158 rb->rb_dmap = sc->sc_rxbuf_tmp_dmap; 2159 sc->sc_rxbuf_tmp_dmap = dmap; 2160 2161 error = 0; 2162 back: 2163 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2164 return error; 2165 } 2166 2167 static int 2168 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2169 { 2170 struct et_softc *sc = arg1; 2171 struct ifnet *ifp = &sc->arpcom.ac_if; 2172 int error = 0, v; 2173 2174 lwkt_serialize_enter(ifp->if_serializer); 2175 2176 v = sc->sc_rx_intr_npkts; 2177 error = sysctl_handle_int(oidp, &v, 0, req); 2178 if (error || req->newptr == NULL) 2179 goto back; 2180 if (v <= 0) { 2181 error = EINVAL; 2182 goto back; 2183 } 2184 2185 if (sc->sc_rx_intr_npkts != v) { 2186 if (ifp->if_flags & IFF_RUNNING) 2187 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2188 sc->sc_rx_intr_npkts = v; 2189 } 2190 back: 2191 lwkt_serialize_exit(ifp->if_serializer); 2192 return error; 2193 } 2194 2195 static int 2196 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2197 { 2198 struct et_softc *sc = arg1; 2199 struct ifnet *ifp = &sc->arpcom.ac_if; 2200 int error = 0, v; 2201 2202 lwkt_serialize_enter(ifp->if_serializer); 2203 2204 v = sc->sc_rx_intr_delay; 2205 error = sysctl_handle_int(oidp, &v, 0, req); 2206 if (error || req->newptr == NULL) 2207 goto back; 2208 if (v <= 0) { 2209 error = EINVAL; 2210 goto back; 2211 } 2212 2213 if (sc->sc_rx_intr_delay != v) { 2214 if (ifp->if_flags & IFF_RUNNING) 2215 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2216 sc->sc_rx_intr_delay = v; 2217 } 2218 back: 2219 lwkt_serialize_exit(ifp->if_serializer); 2220 return error; 2221 } 2222 2223 static void 2224 et_setmedia(struct et_softc *sc) 2225 { 2226 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2227 uint32_t cfg2, ctrl; 2228 2229 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 2230 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 2231 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 2232 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 2233 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 2234 2235 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 2236 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 2237 2238 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 2239 cfg2 |= ET_MAC_CFG2_MODE_GMII; 2240 } else { 2241 cfg2 |= ET_MAC_CFG2_MODE_MII; 2242 ctrl |= ET_MAC_CTRL_MODE_MII; 2243 } 2244 2245 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 2246 cfg2 |= ET_MAC_CFG2_FDX; 2247 else 2248 ctrl |= ET_MAC_CTRL_GHDX; 2249 2250 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 2251 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 2252 } 2253 2254 static int 2255 et_jumbo_mem_alloc(device_t dev) 2256 { 2257 struct et_softc *sc = device_get_softc(dev); 2258 struct et_jumbo_data *jd = &sc->sc_jumbo_data; 2259 bus_addr_t paddr; 2260 uint8_t *buf; 2261 int i; 2262 2263 jd->jd_buf = bus_dmamem_coherent_any(sc->sc_dtag, 2264 ET_JUMBO_ALIGN, ET_JUMBO_MEM_SIZE, BUS_DMA_WAITOK, 2265 &jd->jd_dtag, &jd->jd_dmap, &paddr); 2266 if (jd->jd_buf == NULL) { 2267 device_printf(dev, "can't create jumbo DMA stuffs\n"); 2268 return ENOMEM; 2269 } 2270 2271 jd->jd_slots = kmalloc(sizeof(*jd->jd_slots) * ET_JSLOTS, M_DEVBUF, 2272 M_WAITOK | M_ZERO); 2273 lwkt_serialize_init(&jd->jd_serializer); 2274 SLIST_INIT(&jd->jd_free_slots); 2275 2276 buf = jd->jd_buf; 2277 for (i = 0; i < ET_JSLOTS; ++i) { 2278 struct et_jslot *jslot = &jd->jd_slots[i]; 2279 2280 jslot->jslot_data = jd; 2281 jslot->jslot_buf = buf; 2282 jslot->jslot_paddr = paddr; 2283 jslot->jslot_inuse = 0; 2284 jslot->jslot_index = i; 2285 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, jslot_link); 2286 2287 buf += ET_JLEN; 2288 paddr += ET_JLEN; 2289 } 2290 return 0; 2291 } 2292 2293 static void 2294 et_jumbo_mem_free(device_t dev) 2295 { 2296 struct et_softc *sc = device_get_softc(dev); 2297 struct et_jumbo_data *jd = &sc->sc_jumbo_data; 2298 2299 KKASSERT(sc->sc_flags & ET_FLAG_JUMBO); 2300 2301 kfree(jd->jd_slots, M_DEVBUF); 2302 et_dma_mem_destroy(jd->jd_dtag, jd->jd_buf, jd->jd_dmap); 2303 } 2304 2305 static struct et_jslot * 2306 et_jalloc(struct et_jumbo_data *jd) 2307 { 2308 struct et_jslot *jslot; 2309 2310 lwkt_serialize_enter(&jd->jd_serializer); 2311 2312 jslot = SLIST_FIRST(&jd->jd_free_slots); 2313 if (jslot) { 2314 SLIST_REMOVE_HEAD(&jd->jd_free_slots, jslot_link); 2315 jslot->jslot_inuse = 1; 2316 } 2317 2318 lwkt_serialize_exit(&jd->jd_serializer); 2319 return jslot; 2320 } 2321 2322 static void 2323 et_jfree(void *xjslot) 2324 { 2325 struct et_jslot *jslot = xjslot; 2326 struct et_jumbo_data *jd = jslot->jslot_data; 2327 2328 if (&jd->jd_slots[jslot->jslot_index] != jslot) { 2329 panic("%s wrong jslot!?", __func__); 2330 } else if (jslot->jslot_inuse == 0) { 2331 panic("%s jslot already freed", __func__); 2332 } else { 2333 lwkt_serialize_enter(&jd->jd_serializer); 2334 2335 atomic_subtract_int(&jslot->jslot_inuse, 1); 2336 if (jslot->jslot_inuse == 0) { 2337 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, 2338 jslot_link); 2339 } 2340 2341 lwkt_serialize_exit(&jd->jd_serializer); 2342 } 2343 } 2344 2345 static void 2346 et_jref(void *xjslot) 2347 { 2348 struct et_jslot *jslot = xjslot; 2349 struct et_jumbo_data *jd = jslot->jslot_data; 2350 2351 if (&jd->jd_slots[jslot->jslot_index] != jslot) 2352 panic("%s wrong jslot!?", __func__); 2353 else if (jslot->jslot_inuse == 0) 2354 panic("%s jslot already freed", __func__); 2355 else 2356 atomic_add_int(&jslot->jslot_inuse, 1); 2357 } 2358 2359 static int 2360 et_newbuf_jumbo(struct et_rxbuf_data *rbd, int buf_idx, int init) 2361 { 2362 struct et_softc *sc = rbd->rbd_softc; 2363 struct et_rxbuf *rb; 2364 struct mbuf *m; 2365 struct et_jslot *jslot; 2366 int error; 2367 2368 KASSERT(rbd->rbd_jumbo, ("calling %s with non-jumbo ring", __func__)); 2369 2370 KKASSERT(buf_idx < ET_RX_NDESC); 2371 rb = &rbd->rbd_buf[buf_idx]; 2372 2373 error = ENOBUFS; 2374 2375 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 2376 if (m == NULL) { 2377 if (init) { 2378 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 2379 return error; 2380 } else { 2381 goto back; 2382 } 2383 } 2384 2385 jslot = et_jalloc(&sc->sc_jumbo_data); 2386 if (jslot == NULL) { 2387 m_freem(m); 2388 2389 if (init) { 2390 if_printf(&sc->arpcom.ac_if, 2391 "jslot allocation failed\n"); 2392 return error; 2393 } else { 2394 goto back; 2395 } 2396 } 2397 2398 m->m_ext.ext_arg = jslot; 2399 m->m_ext.ext_buf = jslot->jslot_buf; 2400 m->m_ext.ext_free = et_jfree; 2401 m->m_ext.ext_ref = et_jref; 2402 m->m_ext.ext_size = ET_JUMBO_FRAMELEN; 2403 m->m_flags |= M_EXT; 2404 m->m_data = m->m_ext.ext_buf; 2405 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2406 2407 rb->rb_mbuf = m; 2408 rb->rb_paddr = jslot->jslot_paddr; 2409 2410 error = 0; 2411 back: 2412 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2413 return error; 2414 } 2415 2416 static void 2417 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr) 2418 { 2419 struct et_rxdesc_ring *rx_ring = rbd->rbd_ring; 2420 struct et_rxdesc *desc; 2421 2422 KKASSERT(buf_idx < ET_RX_NDESC); 2423 desc = &rx_ring->rr_desc[buf_idx]; 2424 2425 desc->rd_addr_hi = ET_ADDR_HI(paddr); 2426 desc->rd_addr_lo = ET_ADDR_LO(paddr); 2427 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2428 } 2429