1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_emx.h" 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/endian.h> 73 #include <sys/interrupt.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/malloc.h> 77 #include <sys/mbuf.h> 78 #include <sys/proc.h> 79 #include <sys/rman.h> 80 #include <sys/serialize.h> 81 #include <sys/serialize2.h> 82 #include <sys/socket.h> 83 #include <sys/sockio.h> 84 #include <sys/sysctl.h> 85 #include <sys/systm.h> 86 87 #include <net/bpf.h> 88 #include <net/ethernet.h> 89 #include <net/if.h> 90 #include <net/if_arp.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/ifq_var.h> 94 #include <net/toeplitz.h> 95 #include <net/toeplitz2.h> 96 #include <net/vlan/if_vlan_var.h> 97 #include <net/vlan/if_vlan_ether.h> 98 #include <net/if_poll.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 #include <netinet/udp.h> 105 106 #include <bus/pci/pcivar.h> 107 #include <bus/pci/pcireg.h> 108 109 #include <dev/netif/ig_hal/e1000_api.h> 110 #include <dev/netif/ig_hal/e1000_82571.h> 111 #include <dev/netif/emx/if_emx.h> 112 113 #ifdef EMX_RSS_DEBUG 114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 115 do { \ 116 if (sc->rss_debug >= lvl) \ 117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 118 } while (0) 119 #else /* !EMX_RSS_DEBUG */ 120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 121 #endif /* EMX_RSS_DEBUG */ 122 123 #define EMX_TX_SERIALIZE 1 124 #define EMX_RX_SERIALIZE 2 125 126 #define EMX_NAME "Intel(R) PRO/1000 " 127 128 #define EMX_DEVICE(id) \ 129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 130 #define EMX_DEVICE_NULL { 0, 0, NULL } 131 132 static const struct emx_device { 133 uint16_t vid; 134 uint16_t did; 135 const char *desc; 136 } emx_devices[] = { 137 EMX_DEVICE(82571EB_COPPER), 138 EMX_DEVICE(82571EB_FIBER), 139 EMX_DEVICE(82571EB_SERDES), 140 EMX_DEVICE(82571EB_SERDES_DUAL), 141 EMX_DEVICE(82571EB_SERDES_QUAD), 142 EMX_DEVICE(82571EB_QUAD_COPPER), 143 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 144 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 145 EMX_DEVICE(82571EB_QUAD_FIBER), 146 EMX_DEVICE(82571PT_QUAD_COPPER), 147 148 EMX_DEVICE(82572EI_COPPER), 149 EMX_DEVICE(82572EI_FIBER), 150 EMX_DEVICE(82572EI_SERDES), 151 EMX_DEVICE(82572EI), 152 153 EMX_DEVICE(82573E), 154 EMX_DEVICE(82573E_IAMT), 155 EMX_DEVICE(82573L), 156 157 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 158 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 159 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 160 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 161 162 EMX_DEVICE(82574L), 163 EMX_DEVICE(82574LA), 164 165 /* required last entry */ 166 EMX_DEVICE_NULL 167 }; 168 169 static int emx_probe(device_t); 170 static int emx_attach(device_t); 171 static int emx_detach(device_t); 172 static int emx_shutdown(device_t); 173 static int emx_suspend(device_t); 174 static int emx_resume(device_t); 175 176 static void emx_init(void *); 177 static void emx_stop(struct emx_softc *); 178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 179 static void emx_start(struct ifnet *); 180 #ifdef IFPOLL_ENABLE 181 static void emx_qpoll(struct ifnet *, struct ifpoll_info *); 182 #endif 183 static void emx_watchdog(struct ifnet *); 184 static void emx_media_status(struct ifnet *, struct ifmediareq *); 185 static int emx_media_change(struct ifnet *); 186 static void emx_timer(void *); 187 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 188 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 189 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 190 #ifdef INVARIANTS 191 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 192 boolean_t); 193 #endif 194 195 static void emx_intr(void *); 196 static void emx_intr_mask(void *); 197 static void emx_intr_body(struct emx_softc *, boolean_t); 198 static void emx_rxeof(struct emx_softc *, int, int); 199 static void emx_txeof(struct emx_softc *); 200 static void emx_tx_collect(struct emx_softc *); 201 static void emx_tx_purge(struct emx_softc *); 202 static void emx_enable_intr(struct emx_softc *); 203 static void emx_disable_intr(struct emx_softc *); 204 205 static int emx_dma_alloc(struct emx_softc *); 206 static void emx_dma_free(struct emx_softc *); 207 static void emx_init_tx_ring(struct emx_softc *); 208 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *); 209 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *); 210 static int emx_create_tx_ring(struct emx_softc *); 211 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *); 212 static void emx_destroy_tx_ring(struct emx_softc *, int); 213 static void emx_destroy_rx_ring(struct emx_softc *, 214 struct emx_rxdata *, int); 215 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int); 216 static int emx_encap(struct emx_softc *, struct mbuf **); 217 static int emx_txcsum(struct emx_softc *, struct mbuf *, 218 uint32_t *, uint32_t *); 219 static int emx_tso_pullup(struct emx_softc *, struct mbuf **); 220 static int emx_tso_setup(struct emx_softc *, struct mbuf *, 221 uint32_t *, uint32_t *); 222 223 static int emx_is_valid_eaddr(const uint8_t *); 224 static int emx_reset(struct emx_softc *); 225 static void emx_setup_ifp(struct emx_softc *); 226 static void emx_init_tx_unit(struct emx_softc *); 227 static void emx_init_rx_unit(struct emx_softc *); 228 static void emx_update_stats(struct emx_softc *); 229 static void emx_set_promisc(struct emx_softc *); 230 static void emx_disable_promisc(struct emx_softc *); 231 static void emx_set_multi(struct emx_softc *); 232 static void emx_update_link_status(struct emx_softc *); 233 static void emx_smartspeed(struct emx_softc *); 234 static void emx_set_itr(struct emx_softc *, uint32_t); 235 static void emx_disable_aspm(struct emx_softc *); 236 237 static void emx_print_debug_info(struct emx_softc *); 238 static void emx_print_nvm_info(struct emx_softc *); 239 static void emx_print_hw_stats(struct emx_softc *); 240 241 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 242 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 243 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 244 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 245 static void emx_add_sysctl(struct emx_softc *); 246 247 static void emx_serialize_skipmain(struct emx_softc *); 248 static void emx_deserialize_skipmain(struct emx_softc *); 249 250 /* Management and WOL Support */ 251 static void emx_get_mgmt(struct emx_softc *); 252 static void emx_rel_mgmt(struct emx_softc *); 253 static void emx_get_hw_control(struct emx_softc *); 254 static void emx_rel_hw_control(struct emx_softc *); 255 static void emx_enable_wol(device_t); 256 257 static device_method_t emx_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, emx_probe), 260 DEVMETHOD(device_attach, emx_attach), 261 DEVMETHOD(device_detach, emx_detach), 262 DEVMETHOD(device_shutdown, emx_shutdown), 263 DEVMETHOD(device_suspend, emx_suspend), 264 DEVMETHOD(device_resume, emx_resume), 265 { 0, 0 } 266 }; 267 268 static driver_t emx_driver = { 269 "emx", 270 emx_methods, 271 sizeof(struct emx_softc), 272 }; 273 274 static devclass_t emx_devclass; 275 276 DECLARE_DUMMY_MODULE(if_emx); 277 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 278 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 279 280 /* 281 * Tunables 282 */ 283 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 284 static int emx_rxd = EMX_DEFAULT_RXD; 285 static int emx_txd = EMX_DEFAULT_TXD; 286 static int emx_smart_pwr_down = 0; 287 static int emx_rxr = 0; 288 289 /* Controls whether promiscuous also shows bad packets */ 290 static int emx_debug_sbp = 0; 291 292 static int emx_82573_workaround = 1; 293 static int emx_msi_enable = 1; 294 295 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 296 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 297 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 298 TUNABLE_INT("hw.emx.txd", &emx_txd); 299 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 300 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 301 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 302 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 303 304 /* Global used in WOL setup with multiport cards */ 305 static int emx_global_quad_port_a = 0; 306 307 /* Set this to one to display debug statistics */ 308 static int emx_display_debug_stats = 0; 309 310 #if !defined(KTR_IF_EMX) 311 #define KTR_IF_EMX KTR_ALL 312 #endif 313 KTR_INFO_MASTER(if_emx); 314 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 315 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 316 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 317 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 318 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 319 #define logif(name) KTR_LOG(if_emx_ ## name) 320 321 static __inline void 322 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 323 { 324 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 325 /* DD bit must be cleared */ 326 rxd->rxd_staterr = 0; 327 } 328 329 static __inline void 330 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 331 { 332 /* Ignore Checksum bit is set */ 333 if (staterr & E1000_RXD_STAT_IXSM) 334 return; 335 336 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 337 E1000_RXD_STAT_IPCS) 338 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 339 340 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 341 E1000_RXD_STAT_TCPCS) { 342 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 343 CSUM_PSEUDO_HDR | 344 CSUM_FRAG_NOT_CHECKED; 345 mp->m_pkthdr.csum_data = htons(0xffff); 346 } 347 } 348 349 static __inline struct pktinfo * 350 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 351 uint32_t mrq, uint32_t hash, uint32_t staterr) 352 { 353 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 354 case EMX_RXDMRQ_IPV4_TCP: 355 pi->pi_netisr = NETISR_IP; 356 pi->pi_flags = 0; 357 pi->pi_l3proto = IPPROTO_TCP; 358 break; 359 360 case EMX_RXDMRQ_IPV6_TCP: 361 pi->pi_netisr = NETISR_IPV6; 362 pi->pi_flags = 0; 363 pi->pi_l3proto = IPPROTO_TCP; 364 break; 365 366 case EMX_RXDMRQ_IPV4: 367 if (staterr & E1000_RXD_STAT_IXSM) 368 return NULL; 369 370 if ((staterr & 371 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 372 E1000_RXD_STAT_TCPCS) { 373 pi->pi_netisr = NETISR_IP; 374 pi->pi_flags = 0; 375 pi->pi_l3proto = IPPROTO_UDP; 376 break; 377 } 378 /* FALL THROUGH */ 379 default: 380 return NULL; 381 } 382 383 m->m_flags |= M_HASH; 384 m->m_pkthdr.hash = toeplitz_hash(hash); 385 return pi; 386 } 387 388 static int 389 emx_probe(device_t dev) 390 { 391 const struct emx_device *d; 392 uint16_t vid, did; 393 394 vid = pci_get_vendor(dev); 395 did = pci_get_device(dev); 396 397 for (d = emx_devices; d->desc != NULL; ++d) { 398 if (vid == d->vid && did == d->did) { 399 device_set_desc(dev, d->desc); 400 device_set_async_attach(dev, TRUE); 401 return 0; 402 } 403 } 404 return ENXIO; 405 } 406 407 static int 408 emx_attach(device_t dev) 409 { 410 struct emx_softc *sc = device_get_softc(dev); 411 struct ifnet *ifp = &sc->arpcom.ac_if; 412 int error = 0, i, throttle, msi_enable; 413 u_int intr_flags; 414 uint16_t eeprom_data, device_id, apme_mask; 415 driver_intr_t *intr_func; 416 417 lwkt_serialize_init(&sc->main_serialize); 418 lwkt_serialize_init(&sc->tx_serialize); 419 for (i = 0; i < EMX_NRX_RING; ++i) 420 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 421 422 i = 0; 423 sc->serializes[i++] = &sc->main_serialize; 424 sc->serializes[i++] = &sc->tx_serialize; 425 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 426 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 427 KKASSERT(i == EMX_NSERIALIZE); 428 429 callout_init_mp(&sc->timer); 430 431 sc->dev = sc->osdep.dev = dev; 432 433 /* 434 * Determine hardware and mac type 435 */ 436 sc->hw.vendor_id = pci_get_vendor(dev); 437 sc->hw.device_id = pci_get_device(dev); 438 sc->hw.revision_id = pci_get_revid(dev); 439 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 440 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 441 442 if (e1000_set_mac_type(&sc->hw)) 443 return ENXIO; 444 445 /* 446 * Pullup extra 4bytes into the first data segment, see: 447 * 82571/82572 specification update errata #7 448 * 449 * NOTE: 450 * 4bytes instead of 2bytes, which are mentioned in the errata, 451 * are pulled; mainly to keep rest of the data properly aligned. 452 */ 453 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572) 454 sc->flags |= EMX_FLAG_TSO_PULLEX; 455 456 /* Enable bus mastering */ 457 pci_enable_busmaster(dev); 458 459 /* 460 * Allocate IO memory 461 */ 462 sc->memory_rid = EMX_BAR_MEM; 463 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 464 &sc->memory_rid, RF_ACTIVE); 465 if (sc->memory == NULL) { 466 device_printf(dev, "Unable to allocate bus resource: memory\n"); 467 error = ENXIO; 468 goto fail; 469 } 470 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 471 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 472 473 /* XXX This is quite goofy, it is not actually used */ 474 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 475 476 /* 477 * Don't enable MSI-X on 82574, see: 478 * 82574 specification update errata #15 479 * 480 * Don't enable MSI on 82571/82572, see: 481 * 82571/82572 specification update errata #63 482 */ 483 msi_enable = emx_msi_enable; 484 if (msi_enable && 485 (sc->hw.mac.type == e1000_82571 || 486 sc->hw.mac.type == e1000_82572)) 487 msi_enable = 0; 488 489 /* 490 * Allocate interrupt 491 */ 492 sc->intr_type = pci_alloc_1intr(dev, msi_enable, 493 &sc->intr_rid, &intr_flags); 494 495 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) { 496 int unshared; 497 498 unshared = device_getenv_int(dev, "irq.unshared", 0); 499 if (!unshared) { 500 sc->flags |= EMX_FLAG_SHARED_INTR; 501 if (bootverbose) 502 device_printf(dev, "IRQ shared\n"); 503 } else { 504 intr_flags &= ~RF_SHAREABLE; 505 if (bootverbose) 506 device_printf(dev, "IRQ unshared\n"); 507 } 508 } 509 510 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 511 intr_flags); 512 if (sc->intr_res == NULL) { 513 device_printf(dev, "Unable to allocate bus resource: " 514 "interrupt\n"); 515 error = ENXIO; 516 goto fail; 517 } 518 519 /* Save PCI command register for Shared Code */ 520 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 521 sc->hw.back = &sc->osdep; 522 523 /* Do Shared Code initialization */ 524 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 525 device_printf(dev, "Setup of Shared code failed\n"); 526 error = ENXIO; 527 goto fail; 528 } 529 e1000_get_bus_info(&sc->hw); 530 531 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 532 sc->hw.phy.autoneg_wait_to_complete = FALSE; 533 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 534 535 /* 536 * Interrupt throttle rate 537 */ 538 throttle = device_getenv_int(dev, "int_throttle_ceil", 539 emx_int_throttle_ceil); 540 if (throttle == 0) { 541 sc->int_throttle_ceil = 0; 542 } else { 543 if (throttle < 0) 544 throttle = EMX_DEFAULT_ITR; 545 546 /* Recalculate the tunable value to get the exact frequency. */ 547 throttle = 1000000000 / 256 / throttle; 548 549 /* Upper 16bits of ITR is reserved and should be zero */ 550 if (throttle & 0xffff0000) 551 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 552 553 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 554 } 555 556 e1000_init_script_state_82541(&sc->hw, TRUE); 557 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 558 559 /* Copper options */ 560 if (sc->hw.phy.media_type == e1000_media_type_copper) { 561 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 562 sc->hw.phy.disable_polarity_correction = FALSE; 563 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 564 } 565 566 /* Set the frame limits assuming standard ethernet sized frames. */ 567 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 568 sc->min_frame_size = ETHER_MIN_LEN; 569 570 /* This controls when hardware reports transmit completion status. */ 571 sc->hw.mac.report_tx_early = 1; 572 573 /* Calculate # of RX rings */ 574 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 575 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING); 576 577 /* Allocate RX/TX rings' busdma(9) stuffs */ 578 error = emx_dma_alloc(sc); 579 if (error) 580 goto fail; 581 582 /* Allocate multicast array memory. */ 583 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 584 M_DEVBUF, M_WAITOK); 585 586 /* Indicate SOL/IDER usage */ 587 if (e1000_check_reset_block(&sc->hw)) { 588 device_printf(dev, 589 "PHY reset is blocked due to SOL/IDER session.\n"); 590 } 591 592 /* 593 * Start from a known state, this is important in reading the 594 * nvm and mac from that. 595 */ 596 e1000_reset_hw(&sc->hw); 597 598 /* Make sure we have a good EEPROM before we read from it */ 599 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 600 /* 601 * Some PCI-E parts fail the first check due to 602 * the link being in sleep state, call it again, 603 * if it fails a second time its a real issue. 604 */ 605 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 606 device_printf(dev, 607 "The EEPROM Checksum Is Not Valid\n"); 608 error = EIO; 609 goto fail; 610 } 611 } 612 613 /* Copy the permanent MAC address out of the EEPROM */ 614 if (e1000_read_mac_addr(&sc->hw) < 0) { 615 device_printf(dev, "EEPROM read error while reading MAC" 616 " address\n"); 617 error = EIO; 618 goto fail; 619 } 620 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 621 device_printf(dev, "Invalid MAC address\n"); 622 error = EIO; 623 goto fail; 624 } 625 626 /* Determine if we have to control management hardware */ 627 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 628 629 /* 630 * Setup Wake-on-Lan 631 */ 632 apme_mask = EMX_EEPROM_APME; 633 eeprom_data = 0; 634 switch (sc->hw.mac.type) { 635 case e1000_82573: 636 sc->has_amt = 1; 637 /* FALL THROUGH */ 638 639 case e1000_82571: 640 case e1000_82572: 641 case e1000_80003es2lan: 642 if (sc->hw.bus.func == 1) { 643 e1000_read_nvm(&sc->hw, 644 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 645 } else { 646 e1000_read_nvm(&sc->hw, 647 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 648 } 649 break; 650 651 default: 652 e1000_read_nvm(&sc->hw, 653 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 654 break; 655 } 656 if (eeprom_data & apme_mask) 657 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 658 659 /* 660 * We have the eeprom settings, now apply the special cases 661 * where the eeprom may be wrong or the board won't support 662 * wake on lan on a particular port 663 */ 664 device_id = pci_get_device(dev); 665 switch (device_id) { 666 case E1000_DEV_ID_82571EB_FIBER: 667 /* 668 * Wake events only supported on port A for dual fiber 669 * regardless of eeprom setting 670 */ 671 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 672 E1000_STATUS_FUNC_1) 673 sc->wol = 0; 674 break; 675 676 case E1000_DEV_ID_82571EB_QUAD_COPPER: 677 case E1000_DEV_ID_82571EB_QUAD_FIBER: 678 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 679 /* if quad port sc, disable WoL on all but port A */ 680 if (emx_global_quad_port_a != 0) 681 sc->wol = 0; 682 /* Reset for multiple quad port adapters */ 683 if (++emx_global_quad_port_a == 4) 684 emx_global_quad_port_a = 0; 685 break; 686 } 687 688 /* XXX disable wol */ 689 sc->wol = 0; 690 691 /* Setup OS specific network interface */ 692 emx_setup_ifp(sc); 693 694 /* Add sysctl tree, must after em_setup_ifp() */ 695 emx_add_sysctl(sc); 696 697 /* Reset the hardware */ 698 error = emx_reset(sc); 699 if (error) { 700 device_printf(dev, "Unable to reset the hardware\n"); 701 goto fail; 702 } 703 704 /* Initialize statistics */ 705 emx_update_stats(sc); 706 707 sc->hw.mac.get_link_status = 1; 708 emx_update_link_status(sc); 709 710 sc->spare_tx_desc = EMX_TX_SPARE; 711 712 /* 713 * Keep following relationship between spare_tx_desc, oact_tx_desc 714 * and tx_int_nsegs: 715 * (spare_tx_desc + EMX_TX_RESERVED) <= 716 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 717 */ 718 sc->oact_tx_desc = sc->num_tx_desc / 8; 719 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX) 720 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX; 721 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED) 722 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED; 723 724 sc->tx_int_nsegs = sc->num_tx_desc / 16; 725 if (sc->tx_int_nsegs < sc->oact_tx_desc) 726 sc->tx_int_nsegs = sc->oact_tx_desc; 727 728 /* Non-AMT based hardware can now take control from firmware */ 729 if (sc->has_manage && !sc->has_amt) 730 emx_get_hw_control(sc); 731 732 /* 733 * Missing Interrupt Following ICR read: 734 * 735 * 82571/82572 specification update errata #76 736 * 82573 specification update errata #31 737 * 82574 specification update errata #12 738 */ 739 intr_func = emx_intr; 740 if ((sc->flags & EMX_FLAG_SHARED_INTR) && 741 (sc->hw.mac.type == e1000_82571 || 742 sc->hw.mac.type == e1000_82572 || 743 sc->hw.mac.type == e1000_82573 || 744 sc->hw.mac.type == e1000_82574)) 745 intr_func = emx_intr_mask; 746 747 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc, 748 &sc->intr_tag, &sc->main_serialize); 749 if (error) { 750 device_printf(dev, "Failed to register interrupt handler"); 751 ether_ifdetach(&sc->arpcom.ac_if); 752 goto fail; 753 } 754 755 ifp->if_cpuid = rman_get_cpuid(sc->intr_res); 756 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 757 return (0); 758 fail: 759 emx_detach(dev); 760 return (error); 761 } 762 763 static int 764 emx_detach(device_t dev) 765 { 766 struct emx_softc *sc = device_get_softc(dev); 767 768 if (device_is_attached(dev)) { 769 struct ifnet *ifp = &sc->arpcom.ac_if; 770 771 ifnet_serialize_all(ifp); 772 773 emx_stop(sc); 774 775 e1000_phy_hw_reset(&sc->hw); 776 777 emx_rel_mgmt(sc); 778 emx_rel_hw_control(sc); 779 780 if (sc->wol) { 781 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 782 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 783 emx_enable_wol(dev); 784 } 785 786 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 787 788 ifnet_deserialize_all(ifp); 789 790 ether_ifdetach(ifp); 791 } else if (sc->memory != NULL) { 792 emx_rel_hw_control(sc); 793 } 794 bus_generic_detach(dev); 795 796 if (sc->intr_res != NULL) { 797 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 798 sc->intr_res); 799 } 800 801 if (sc->intr_type == PCI_INTR_TYPE_MSI) 802 pci_release_msi(dev); 803 804 if (sc->memory != NULL) { 805 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 806 sc->memory); 807 } 808 809 emx_dma_free(sc); 810 811 /* Free sysctl tree */ 812 if (sc->sysctl_tree != NULL) 813 sysctl_ctx_free(&sc->sysctl_ctx); 814 815 if (sc->mta != NULL) 816 kfree(sc->mta, M_DEVBUF); 817 818 return (0); 819 } 820 821 static int 822 emx_shutdown(device_t dev) 823 { 824 return emx_suspend(dev); 825 } 826 827 static int 828 emx_suspend(device_t dev) 829 { 830 struct emx_softc *sc = device_get_softc(dev); 831 struct ifnet *ifp = &sc->arpcom.ac_if; 832 833 ifnet_serialize_all(ifp); 834 835 emx_stop(sc); 836 837 emx_rel_mgmt(sc); 838 emx_rel_hw_control(sc); 839 840 if (sc->wol) { 841 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 842 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 843 emx_enable_wol(dev); 844 } 845 846 ifnet_deserialize_all(ifp); 847 848 return bus_generic_suspend(dev); 849 } 850 851 static int 852 emx_resume(device_t dev) 853 { 854 struct emx_softc *sc = device_get_softc(dev); 855 struct ifnet *ifp = &sc->arpcom.ac_if; 856 857 ifnet_serialize_all(ifp); 858 859 emx_init(sc); 860 emx_get_mgmt(sc); 861 if_devstart(ifp); 862 863 ifnet_deserialize_all(ifp); 864 865 return bus_generic_resume(dev); 866 } 867 868 static void 869 emx_start(struct ifnet *ifp) 870 { 871 struct emx_softc *sc = ifp->if_softc; 872 struct mbuf *m_head; 873 874 ASSERT_SERIALIZED(&sc->tx_serialize); 875 876 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 877 return; 878 879 if (!sc->link_active) { 880 ifq_purge(&ifp->if_snd); 881 return; 882 } 883 884 while (!ifq_is_empty(&ifp->if_snd)) { 885 /* Now do we at least have a minimal? */ 886 if (EMX_IS_OACTIVE(sc)) { 887 emx_tx_collect(sc); 888 if (EMX_IS_OACTIVE(sc)) { 889 ifp->if_flags |= IFF_OACTIVE; 890 sc->no_tx_desc_avail1++; 891 break; 892 } 893 } 894 895 logif(pkt_txqueue); 896 m_head = ifq_dequeue(&ifp->if_snd, NULL); 897 if (m_head == NULL) 898 break; 899 900 if (emx_encap(sc, &m_head)) { 901 ifp->if_oerrors++; 902 emx_tx_collect(sc); 903 continue; 904 } 905 906 /* Send a copy of the frame to the BPF listener */ 907 ETHER_BPF_MTAP(ifp, m_head); 908 909 /* Set timeout in case hardware has problems transmitting. */ 910 ifp->if_timer = EMX_TX_TIMEOUT; 911 } 912 } 913 914 static int 915 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 916 { 917 struct emx_softc *sc = ifp->if_softc; 918 struct ifreq *ifr = (struct ifreq *)data; 919 uint16_t eeprom_data = 0; 920 int max_frame_size, mask, reinit; 921 int error = 0; 922 923 ASSERT_IFNET_SERIALIZED_ALL(ifp); 924 925 switch (command) { 926 case SIOCSIFMTU: 927 switch (sc->hw.mac.type) { 928 case e1000_82573: 929 /* 930 * 82573 only supports jumbo frames 931 * if ASPM is disabled. 932 */ 933 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 934 &eeprom_data); 935 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 936 max_frame_size = ETHER_MAX_LEN; 937 break; 938 } 939 /* FALL THROUGH */ 940 941 /* Limit Jumbo Frame size */ 942 case e1000_82571: 943 case e1000_82572: 944 case e1000_82574: 945 case e1000_80003es2lan: 946 max_frame_size = 9234; 947 break; 948 949 default: 950 max_frame_size = MAX_JUMBO_FRAME_SIZE; 951 break; 952 } 953 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 954 ETHER_CRC_LEN) { 955 error = EINVAL; 956 break; 957 } 958 959 ifp->if_mtu = ifr->ifr_mtu; 960 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 961 ETHER_CRC_LEN; 962 963 if (ifp->if_flags & IFF_RUNNING) 964 emx_init(sc); 965 break; 966 967 case SIOCSIFFLAGS: 968 if (ifp->if_flags & IFF_UP) { 969 if ((ifp->if_flags & IFF_RUNNING)) { 970 if ((ifp->if_flags ^ sc->if_flags) & 971 (IFF_PROMISC | IFF_ALLMULTI)) { 972 emx_disable_promisc(sc); 973 emx_set_promisc(sc); 974 } 975 } else { 976 emx_init(sc); 977 } 978 } else if (ifp->if_flags & IFF_RUNNING) { 979 emx_stop(sc); 980 } 981 sc->if_flags = ifp->if_flags; 982 break; 983 984 case SIOCADDMULTI: 985 case SIOCDELMULTI: 986 if (ifp->if_flags & IFF_RUNNING) { 987 emx_disable_intr(sc); 988 emx_set_multi(sc); 989 #ifdef IFPOLL_ENABLE 990 if (!(ifp->if_flags & IFF_NPOLLING)) 991 #endif 992 emx_enable_intr(sc); 993 } 994 break; 995 996 case SIOCSIFMEDIA: 997 /* Check SOL/IDER usage */ 998 if (e1000_check_reset_block(&sc->hw)) { 999 device_printf(sc->dev, "Media change is" 1000 " blocked due to SOL/IDER session.\n"); 1001 break; 1002 } 1003 /* FALL THROUGH */ 1004 1005 case SIOCGIFMEDIA: 1006 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 1007 break; 1008 1009 case SIOCSIFCAP: 1010 reinit = 0; 1011 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1012 if (mask & IFCAP_RXCSUM) { 1013 ifp->if_capenable ^= IFCAP_RXCSUM; 1014 reinit = 1; 1015 } 1016 if (mask & IFCAP_VLAN_HWTAGGING) { 1017 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1018 reinit = 1; 1019 } 1020 if (mask & IFCAP_TXCSUM) { 1021 ifp->if_capenable ^= IFCAP_TXCSUM; 1022 if (ifp->if_capenable & IFCAP_TXCSUM) 1023 ifp->if_hwassist |= EMX_CSUM_FEATURES; 1024 else 1025 ifp->if_hwassist &= ~EMX_CSUM_FEATURES; 1026 } 1027 if (mask & IFCAP_TSO) { 1028 ifp->if_capenable ^= IFCAP_TSO; 1029 if (ifp->if_capenable & IFCAP_TSO) 1030 ifp->if_hwassist |= CSUM_TSO; 1031 else 1032 ifp->if_hwassist &= ~CSUM_TSO; 1033 } 1034 if (mask & IFCAP_RSS) 1035 ifp->if_capenable ^= IFCAP_RSS; 1036 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1037 emx_init(sc); 1038 break; 1039 1040 default: 1041 error = ether_ioctl(ifp, command, data); 1042 break; 1043 } 1044 return (error); 1045 } 1046 1047 static void 1048 emx_watchdog(struct ifnet *ifp) 1049 { 1050 struct emx_softc *sc = ifp->if_softc; 1051 1052 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1053 1054 /* 1055 * The timer is set to 5 every time start queues a packet. 1056 * Then txeof keeps resetting it as long as it cleans at 1057 * least one descriptor. 1058 * Finally, anytime all descriptors are clean the timer is 1059 * set to 0. 1060 */ 1061 1062 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 1063 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 1064 /* 1065 * If we reach here, all TX jobs are completed and 1066 * the TX engine should have been idled for some time. 1067 * We don't need to call if_devstart() here. 1068 */ 1069 ifp->if_flags &= ~IFF_OACTIVE; 1070 ifp->if_timer = 0; 1071 return; 1072 } 1073 1074 /* 1075 * If we are in this routine because of pause frames, then 1076 * don't reset the hardware. 1077 */ 1078 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1079 ifp->if_timer = EMX_TX_TIMEOUT; 1080 return; 1081 } 1082 1083 if (e1000_check_for_link(&sc->hw) == 0) 1084 if_printf(ifp, "watchdog timeout -- resetting\n"); 1085 1086 ifp->if_oerrors++; 1087 sc->watchdog_events++; 1088 1089 emx_init(sc); 1090 1091 if (!ifq_is_empty(&ifp->if_snd)) 1092 if_devstart(ifp); 1093 } 1094 1095 static void 1096 emx_init(void *xsc) 1097 { 1098 struct emx_softc *sc = xsc; 1099 struct ifnet *ifp = &sc->arpcom.ac_if; 1100 device_t dev = sc->dev; 1101 uint32_t pba; 1102 int i; 1103 1104 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1105 1106 emx_stop(sc); 1107 1108 /* 1109 * Packet Buffer Allocation (PBA) 1110 * Writing PBA sets the receive portion of the buffer 1111 * the remainder is used for the transmit buffer. 1112 */ 1113 switch (sc->hw.mac.type) { 1114 /* Total Packet Buffer on these is 48K */ 1115 case e1000_82571: 1116 case e1000_82572: 1117 case e1000_80003es2lan: 1118 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1119 break; 1120 1121 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1122 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1123 break; 1124 1125 case e1000_82574: 1126 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1127 break; 1128 1129 default: 1130 /* Devices before 82547 had a Packet Buffer of 64K. */ 1131 if (sc->max_frame_size > 8192) 1132 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1133 else 1134 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1135 } 1136 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1137 1138 /* Get the latest mac address, User can use a LAA */ 1139 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1140 1141 /* Put the address into the Receive Address Array */ 1142 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1143 1144 /* 1145 * With the 82571 sc, RAR[0] may be overwritten 1146 * when the other port is reset, we make a duplicate 1147 * in RAR[14] for that eventuality, this assures 1148 * the interface continues to function. 1149 */ 1150 if (sc->hw.mac.type == e1000_82571) { 1151 e1000_set_laa_state_82571(&sc->hw, TRUE); 1152 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1153 E1000_RAR_ENTRIES - 1); 1154 } 1155 1156 /* Initialize the hardware */ 1157 if (emx_reset(sc)) { 1158 device_printf(dev, "Unable to reset the hardware\n"); 1159 /* XXX emx_stop()? */ 1160 return; 1161 } 1162 emx_update_link_status(sc); 1163 1164 /* Setup VLAN support, basic and offload if available */ 1165 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1166 1167 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1168 uint32_t ctrl; 1169 1170 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1171 ctrl |= E1000_CTRL_VME; 1172 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1173 } 1174 1175 /* Configure for OS presence */ 1176 emx_get_mgmt(sc); 1177 1178 /* Prepare transmit descriptors and buffers */ 1179 emx_init_tx_ring(sc); 1180 emx_init_tx_unit(sc); 1181 1182 /* Setup Multicast table */ 1183 emx_set_multi(sc); 1184 1185 /* Prepare receive descriptors and buffers */ 1186 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1187 if (emx_init_rx_ring(sc, &sc->rx_data[i])) { 1188 device_printf(dev, 1189 "Could not setup receive structures\n"); 1190 emx_stop(sc); 1191 return; 1192 } 1193 } 1194 emx_init_rx_unit(sc); 1195 1196 /* Don't lose promiscuous settings */ 1197 emx_set_promisc(sc); 1198 1199 ifp->if_flags |= IFF_RUNNING; 1200 ifp->if_flags &= ~IFF_OACTIVE; 1201 1202 callout_reset(&sc->timer, hz, emx_timer, sc); 1203 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1204 1205 /* MSI/X configuration for 82574 */ 1206 if (sc->hw.mac.type == e1000_82574) { 1207 int tmp; 1208 1209 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1210 tmp |= E1000_CTRL_EXT_PBA_CLR; 1211 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1212 /* 1213 * XXX MSIX 1214 * Set the IVAR - interrupt vector routing. 1215 * Each nibble represents a vector, high bit 1216 * is enable, other 3 bits are the MSIX table 1217 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1218 * Link (other) to 2, hence the magic number. 1219 */ 1220 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1221 } 1222 1223 #ifdef IFPOLL_ENABLE 1224 /* 1225 * Only enable interrupts if we are not polling, make sure 1226 * they are off otherwise. 1227 */ 1228 if (ifp->if_flags & IFF_NPOLLING) 1229 emx_disable_intr(sc); 1230 else 1231 #endif /* IFPOLL_ENABLE */ 1232 emx_enable_intr(sc); 1233 1234 /* AMT based hardware can now take control from firmware */ 1235 if (sc->has_manage && sc->has_amt) 1236 emx_get_hw_control(sc); 1237 1238 /* Don't reset the phy next time init gets called */ 1239 sc->hw.phy.reset_disable = TRUE; 1240 } 1241 1242 static void 1243 emx_intr(void *xsc) 1244 { 1245 emx_intr_body(xsc, TRUE); 1246 } 1247 1248 static void 1249 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted) 1250 { 1251 struct ifnet *ifp = &sc->arpcom.ac_if; 1252 uint32_t reg_icr; 1253 1254 logif(intr_beg); 1255 ASSERT_SERIALIZED(&sc->main_serialize); 1256 1257 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1258 1259 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1260 logif(intr_end); 1261 return; 1262 } 1263 1264 /* 1265 * XXX: some laptops trigger several spurious interrupts 1266 * on emx(4) when in the resume cycle. The ICR register 1267 * reports all-ones value in this case. Processing such 1268 * interrupts would lead to a freeze. I don't know why. 1269 */ 1270 if (reg_icr == 0xffffffff) { 1271 logif(intr_end); 1272 return; 1273 } 1274 1275 if (ifp->if_flags & IFF_RUNNING) { 1276 if (reg_icr & 1277 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1278 int i; 1279 1280 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1281 lwkt_serialize_enter( 1282 &sc->rx_data[i].rx_serialize); 1283 emx_rxeof(sc, i, -1); 1284 lwkt_serialize_exit( 1285 &sc->rx_data[i].rx_serialize); 1286 } 1287 } 1288 if (reg_icr & E1000_ICR_TXDW) { 1289 lwkt_serialize_enter(&sc->tx_serialize); 1290 emx_txeof(sc); 1291 if (!ifq_is_empty(&ifp->if_snd)) 1292 if_devstart(ifp); 1293 lwkt_serialize_exit(&sc->tx_serialize); 1294 } 1295 } 1296 1297 /* Link status change */ 1298 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1299 emx_serialize_skipmain(sc); 1300 1301 callout_stop(&sc->timer); 1302 sc->hw.mac.get_link_status = 1; 1303 emx_update_link_status(sc); 1304 1305 /* Deal with TX cruft when link lost */ 1306 emx_tx_purge(sc); 1307 1308 callout_reset(&sc->timer, hz, emx_timer, sc); 1309 1310 emx_deserialize_skipmain(sc); 1311 } 1312 1313 if (reg_icr & E1000_ICR_RXO) 1314 sc->rx_overruns++; 1315 1316 logif(intr_end); 1317 } 1318 1319 static void 1320 emx_intr_mask(void *xsc) 1321 { 1322 struct emx_softc *sc = xsc; 1323 1324 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 1325 /* 1326 * NOTE: 1327 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1328 * so don't check it. 1329 */ 1330 emx_intr_body(sc, FALSE); 1331 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 1332 } 1333 1334 static void 1335 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1336 { 1337 struct emx_softc *sc = ifp->if_softc; 1338 1339 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1340 1341 emx_update_link_status(sc); 1342 1343 ifmr->ifm_status = IFM_AVALID; 1344 ifmr->ifm_active = IFM_ETHER; 1345 1346 if (!sc->link_active) 1347 return; 1348 1349 ifmr->ifm_status |= IFM_ACTIVE; 1350 1351 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1352 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1353 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1354 } else { 1355 switch (sc->link_speed) { 1356 case 10: 1357 ifmr->ifm_active |= IFM_10_T; 1358 break; 1359 case 100: 1360 ifmr->ifm_active |= IFM_100_TX; 1361 break; 1362 1363 case 1000: 1364 ifmr->ifm_active |= IFM_1000_T; 1365 break; 1366 } 1367 if (sc->link_duplex == FULL_DUPLEX) 1368 ifmr->ifm_active |= IFM_FDX; 1369 else 1370 ifmr->ifm_active |= IFM_HDX; 1371 } 1372 } 1373 1374 static int 1375 emx_media_change(struct ifnet *ifp) 1376 { 1377 struct emx_softc *sc = ifp->if_softc; 1378 struct ifmedia *ifm = &sc->media; 1379 1380 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1381 1382 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1383 return (EINVAL); 1384 1385 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1386 case IFM_AUTO: 1387 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1388 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1389 break; 1390 1391 case IFM_1000_LX: 1392 case IFM_1000_SX: 1393 case IFM_1000_T: 1394 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1395 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1396 break; 1397 1398 case IFM_100_TX: 1399 sc->hw.mac.autoneg = FALSE; 1400 sc->hw.phy.autoneg_advertised = 0; 1401 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1402 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1403 else 1404 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1405 break; 1406 1407 case IFM_10_T: 1408 sc->hw.mac.autoneg = FALSE; 1409 sc->hw.phy.autoneg_advertised = 0; 1410 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1411 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1412 else 1413 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1414 break; 1415 1416 default: 1417 if_printf(ifp, "Unsupported media type\n"); 1418 break; 1419 } 1420 1421 /* 1422 * As the speed/duplex settings my have changed we need to 1423 * reset the PHY. 1424 */ 1425 sc->hw.phy.reset_disable = FALSE; 1426 1427 emx_init(sc); 1428 1429 return (0); 1430 } 1431 1432 static int 1433 emx_encap(struct emx_softc *sc, struct mbuf **m_headp) 1434 { 1435 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1436 bus_dmamap_t map; 1437 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1438 struct e1000_tx_desc *ctxd = NULL; 1439 struct mbuf *m_head = *m_headp; 1440 uint32_t txd_upper, txd_lower, cmd = 0; 1441 int maxsegs, nsegs, i, j, first, last = 0, error; 1442 1443 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1444 error = emx_tso_pullup(sc, m_headp); 1445 if (error) 1446 return error; 1447 m_head = *m_headp; 1448 } 1449 1450 txd_upper = txd_lower = 0; 1451 1452 /* 1453 * Capture the first descriptor index, this descriptor 1454 * will have the index of the EOP which is the only one 1455 * that now gets a DONE bit writeback. 1456 */ 1457 first = sc->next_avail_tx_desc; 1458 tx_buffer = &sc->tx_buf[first]; 1459 tx_buffer_mapped = tx_buffer; 1460 map = tx_buffer->map; 1461 1462 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED; 1463 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc")); 1464 if (maxsegs > EMX_MAX_SCATTER) 1465 maxsegs = EMX_MAX_SCATTER; 1466 1467 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp, 1468 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1469 if (error) { 1470 if (error == ENOBUFS) 1471 sc->mbuf_alloc_failed++; 1472 else 1473 sc->no_tx_dma_setup++; 1474 1475 m_freem(*m_headp); 1476 *m_headp = NULL; 1477 return error; 1478 } 1479 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1480 1481 m_head = *m_headp; 1482 sc->tx_nsegs += nsegs; 1483 1484 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1485 /* TSO will consume one TX desc */ 1486 sc->tx_nsegs += emx_tso_setup(sc, m_head, 1487 &txd_upper, &txd_lower); 1488 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1489 /* TX csum offloading will consume one TX desc */ 1490 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower); 1491 } 1492 i = sc->next_avail_tx_desc; 1493 1494 /* Set up our transmit descriptors */ 1495 for (j = 0; j < nsegs; j++) { 1496 tx_buffer = &sc->tx_buf[i]; 1497 ctxd = &sc->tx_desc_base[i]; 1498 1499 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1500 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1501 txd_lower | segs[j].ds_len); 1502 ctxd->upper.data = htole32(txd_upper); 1503 1504 last = i; 1505 if (++i == sc->num_tx_desc) 1506 i = 0; 1507 } 1508 1509 sc->next_avail_tx_desc = i; 1510 1511 KKASSERT(sc->num_tx_desc_avail > nsegs); 1512 sc->num_tx_desc_avail -= nsegs; 1513 1514 /* Handle VLAN tag */ 1515 if (m_head->m_flags & M_VLANTAG) { 1516 /* Set the vlan id. */ 1517 ctxd->upper.fields.special = 1518 htole16(m_head->m_pkthdr.ether_vlantag); 1519 1520 /* Tell hardware to add tag */ 1521 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1522 } 1523 1524 tx_buffer->m_head = m_head; 1525 tx_buffer_mapped->map = tx_buffer->map; 1526 tx_buffer->map = map; 1527 1528 if (sc->tx_nsegs >= sc->tx_int_nsegs) { 1529 sc->tx_nsegs = 0; 1530 1531 /* 1532 * Report Status (RS) is turned on 1533 * every tx_int_nsegs descriptors. 1534 */ 1535 cmd = E1000_TXD_CMD_RS; 1536 1537 /* 1538 * Keep track of the descriptor, which will 1539 * be written back by hardware. 1540 */ 1541 sc->tx_dd[sc->tx_dd_tail] = last; 1542 EMX_INC_TXDD_IDX(sc->tx_dd_tail); 1543 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head); 1544 } 1545 1546 /* 1547 * Last Descriptor of Packet needs End Of Packet (EOP) 1548 */ 1549 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1550 1551 /* 1552 * Advance the Transmit Descriptor Tail (TDT), this tells 1553 * the E1000 that this frame is available to transmit. 1554 */ 1555 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i); 1556 1557 return (0); 1558 } 1559 1560 static void 1561 emx_set_promisc(struct emx_softc *sc) 1562 { 1563 struct ifnet *ifp = &sc->arpcom.ac_if; 1564 uint32_t reg_rctl; 1565 1566 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1567 1568 if (ifp->if_flags & IFF_PROMISC) { 1569 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1570 /* Turn this on if you want to see bad packets */ 1571 if (emx_debug_sbp) 1572 reg_rctl |= E1000_RCTL_SBP; 1573 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1574 } else if (ifp->if_flags & IFF_ALLMULTI) { 1575 reg_rctl |= E1000_RCTL_MPE; 1576 reg_rctl &= ~E1000_RCTL_UPE; 1577 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1578 } 1579 } 1580 1581 static void 1582 emx_disable_promisc(struct emx_softc *sc) 1583 { 1584 uint32_t reg_rctl; 1585 1586 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1587 1588 reg_rctl &= ~E1000_RCTL_UPE; 1589 reg_rctl &= ~E1000_RCTL_MPE; 1590 reg_rctl &= ~E1000_RCTL_SBP; 1591 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1592 } 1593 1594 static void 1595 emx_set_multi(struct emx_softc *sc) 1596 { 1597 struct ifnet *ifp = &sc->arpcom.ac_if; 1598 struct ifmultiaddr *ifma; 1599 uint32_t reg_rctl = 0; 1600 uint8_t *mta; 1601 int mcnt = 0; 1602 1603 mta = sc->mta; 1604 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1605 1606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1607 if (ifma->ifma_addr->sa_family != AF_LINK) 1608 continue; 1609 1610 if (mcnt == EMX_MCAST_ADDR_MAX) 1611 break; 1612 1613 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1614 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1615 mcnt++; 1616 } 1617 1618 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1619 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1620 reg_rctl |= E1000_RCTL_MPE; 1621 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1622 } else { 1623 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1624 } 1625 } 1626 1627 /* 1628 * This routine checks for link status and updates statistics. 1629 */ 1630 static void 1631 emx_timer(void *xsc) 1632 { 1633 struct emx_softc *sc = xsc; 1634 struct ifnet *ifp = &sc->arpcom.ac_if; 1635 1636 lwkt_serialize_enter(&sc->main_serialize); 1637 1638 emx_update_link_status(sc); 1639 emx_update_stats(sc); 1640 1641 /* Reset LAA into RAR[0] on 82571 */ 1642 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1643 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1644 1645 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1646 emx_print_hw_stats(sc); 1647 1648 emx_smartspeed(sc); 1649 1650 callout_reset(&sc->timer, hz, emx_timer, sc); 1651 1652 lwkt_serialize_exit(&sc->main_serialize); 1653 } 1654 1655 static void 1656 emx_update_link_status(struct emx_softc *sc) 1657 { 1658 struct e1000_hw *hw = &sc->hw; 1659 struct ifnet *ifp = &sc->arpcom.ac_if; 1660 device_t dev = sc->dev; 1661 uint32_t link_check = 0; 1662 1663 /* Get the cached link value or read phy for real */ 1664 switch (hw->phy.media_type) { 1665 case e1000_media_type_copper: 1666 if (hw->mac.get_link_status) { 1667 /* Do the work to read phy */ 1668 e1000_check_for_link(hw); 1669 link_check = !hw->mac.get_link_status; 1670 if (link_check) /* ESB2 fix */ 1671 e1000_cfg_on_link_up(hw); 1672 } else { 1673 link_check = TRUE; 1674 } 1675 break; 1676 1677 case e1000_media_type_fiber: 1678 e1000_check_for_link(hw); 1679 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1680 break; 1681 1682 case e1000_media_type_internal_serdes: 1683 e1000_check_for_link(hw); 1684 link_check = sc->hw.mac.serdes_has_link; 1685 break; 1686 1687 case e1000_media_type_unknown: 1688 default: 1689 break; 1690 } 1691 1692 /* Now check for a transition */ 1693 if (link_check && sc->link_active == 0) { 1694 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1695 &sc->link_duplex); 1696 1697 /* 1698 * Check if we should enable/disable SPEED_MODE bit on 1699 * 82571EB/82572EI 1700 */ 1701 if (sc->link_speed != SPEED_1000 && 1702 (hw->mac.type == e1000_82571 || 1703 hw->mac.type == e1000_82572)) { 1704 int tarc0; 1705 1706 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1707 tarc0 &= ~EMX_TARC_SPEED_MODE; 1708 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1709 } 1710 if (bootverbose) { 1711 device_printf(dev, "Link is up %d Mbps %s\n", 1712 sc->link_speed, 1713 ((sc->link_duplex == FULL_DUPLEX) ? 1714 "Full Duplex" : "Half Duplex")); 1715 } 1716 sc->link_active = 1; 1717 sc->smartspeed = 0; 1718 ifp->if_baudrate = sc->link_speed * 1000000; 1719 ifp->if_link_state = LINK_STATE_UP; 1720 if_link_state_change(ifp); 1721 } else if (!link_check && sc->link_active == 1) { 1722 ifp->if_baudrate = sc->link_speed = 0; 1723 sc->link_duplex = 0; 1724 if (bootverbose) 1725 device_printf(dev, "Link is Down\n"); 1726 sc->link_active = 0; 1727 #if 0 1728 /* Link down, disable watchdog */ 1729 if->if_timer = 0; 1730 #endif 1731 ifp->if_link_state = LINK_STATE_DOWN; 1732 if_link_state_change(ifp); 1733 } 1734 } 1735 1736 static void 1737 emx_stop(struct emx_softc *sc) 1738 { 1739 struct ifnet *ifp = &sc->arpcom.ac_if; 1740 int i; 1741 1742 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1743 1744 emx_disable_intr(sc); 1745 1746 callout_stop(&sc->timer); 1747 1748 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1749 ifp->if_timer = 0; 1750 1751 /* 1752 * Disable multiple receive queues. 1753 * 1754 * NOTE: 1755 * We should disable multiple receive queues before 1756 * resetting the hardware. 1757 */ 1758 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1759 1760 e1000_reset_hw(&sc->hw); 1761 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1762 1763 for (i = 0; i < sc->num_tx_desc; i++) { 1764 struct emx_txbuf *tx_buffer = &sc->tx_buf[i]; 1765 1766 if (tx_buffer->m_head != NULL) { 1767 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1768 m_freem(tx_buffer->m_head); 1769 tx_buffer->m_head = NULL; 1770 } 1771 } 1772 1773 for (i = 0; i < sc->rx_ring_cnt; ++i) 1774 emx_free_rx_ring(sc, &sc->rx_data[i]); 1775 1776 sc->csum_flags = 0; 1777 sc->csum_lhlen = 0; 1778 sc->csum_iphlen = 0; 1779 sc->csum_thlen = 0; 1780 sc->csum_mss = 0; 1781 sc->csum_pktlen = 0; 1782 1783 sc->tx_dd_head = 0; 1784 sc->tx_dd_tail = 0; 1785 sc->tx_nsegs = 0; 1786 } 1787 1788 static int 1789 emx_reset(struct emx_softc *sc) 1790 { 1791 device_t dev = sc->dev; 1792 uint16_t rx_buffer_size; 1793 1794 /* Set up smart power down as default off on newer adapters. */ 1795 if (!emx_smart_pwr_down && 1796 (sc->hw.mac.type == e1000_82571 || 1797 sc->hw.mac.type == e1000_82572)) { 1798 uint16_t phy_tmp = 0; 1799 1800 /* Speed up time to link by disabling smart power down. */ 1801 e1000_read_phy_reg(&sc->hw, 1802 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1803 phy_tmp &= ~IGP02E1000_PM_SPD; 1804 e1000_write_phy_reg(&sc->hw, 1805 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1806 } 1807 1808 /* 1809 * These parameters control the automatic generation (Tx) and 1810 * response (Rx) to Ethernet PAUSE frames. 1811 * - High water mark should allow for at least two frames to be 1812 * received after sending an XOFF. 1813 * - Low water mark works best when it is very near the high water mark. 1814 * This allows the receiver to restart by sending XON when it has 1815 * drained a bit. Here we use an arbitary value of 1500 which will 1816 * restart after one full frame is pulled from the buffer. There 1817 * could be several smaller frames in the buffer and if so they will 1818 * not trigger the XON until their total number reduces the buffer 1819 * by 1500. 1820 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1821 */ 1822 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1823 1824 sc->hw.fc.high_water = rx_buffer_size - 1825 roundup2(sc->max_frame_size, 1024); 1826 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1827 1828 if (sc->hw.mac.type == e1000_80003es2lan) 1829 sc->hw.fc.pause_time = 0xFFFF; 1830 else 1831 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1832 sc->hw.fc.send_xon = TRUE; 1833 sc->hw.fc.requested_mode = e1000_fc_full; 1834 1835 /* Issue a global reset */ 1836 e1000_reset_hw(&sc->hw); 1837 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1838 emx_disable_aspm(sc); 1839 1840 if (e1000_init_hw(&sc->hw) < 0) { 1841 device_printf(dev, "Hardware Initialization Failed\n"); 1842 return (EIO); 1843 } 1844 1845 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1846 e1000_get_phy_info(&sc->hw); 1847 e1000_check_for_link(&sc->hw); 1848 1849 return (0); 1850 } 1851 1852 static void 1853 emx_setup_ifp(struct emx_softc *sc) 1854 { 1855 struct ifnet *ifp = &sc->arpcom.ac_if; 1856 1857 if_initname(ifp, device_get_name(sc->dev), 1858 device_get_unit(sc->dev)); 1859 ifp->if_softc = sc; 1860 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1861 ifp->if_init = emx_init; 1862 ifp->if_ioctl = emx_ioctl; 1863 ifp->if_start = emx_start; 1864 #ifdef IFPOLL_ENABLE 1865 ifp->if_qpoll = emx_qpoll; 1866 #endif 1867 ifp->if_watchdog = emx_watchdog; 1868 ifp->if_serialize = emx_serialize; 1869 ifp->if_deserialize = emx_deserialize; 1870 ifp->if_tryserialize = emx_tryserialize; 1871 #ifdef INVARIANTS 1872 ifp->if_serialize_assert = emx_serialize_assert; 1873 #endif 1874 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 1875 ifq_set_ready(&ifp->if_snd); 1876 1877 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1878 1879 ifp->if_capabilities = IFCAP_HWCSUM | 1880 IFCAP_VLAN_HWTAGGING | 1881 IFCAP_VLAN_MTU | 1882 IFCAP_TSO; 1883 if (sc->rx_ring_cnt > 1) 1884 ifp->if_capabilities |= IFCAP_RSS; 1885 ifp->if_capenable = ifp->if_capabilities; 1886 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO; 1887 1888 /* 1889 * Tell the upper layer(s) we support long frames. 1890 */ 1891 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1892 1893 /* 1894 * Specify the media types supported by this sc and register 1895 * callbacks to update media and link information 1896 */ 1897 ifmedia_init(&sc->media, IFM_IMASK, 1898 emx_media_change, emx_media_status); 1899 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1900 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1901 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1902 0, NULL); 1903 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1904 } else { 1905 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1906 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1907 0, NULL); 1908 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1909 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1910 0, NULL); 1911 if (sc->hw.phy.type != e1000_phy_ife) { 1912 ifmedia_add(&sc->media, 1913 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1914 ifmedia_add(&sc->media, 1915 IFM_ETHER | IFM_1000_T, 0, NULL); 1916 } 1917 } 1918 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1919 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1920 } 1921 1922 /* 1923 * Workaround for SmartSpeed on 82541 and 82547 controllers 1924 */ 1925 static void 1926 emx_smartspeed(struct emx_softc *sc) 1927 { 1928 uint16_t phy_tmp; 1929 1930 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1931 sc->hw.mac.autoneg == 0 || 1932 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1933 return; 1934 1935 if (sc->smartspeed == 0) { 1936 /* 1937 * If Master/Slave config fault is asserted twice, 1938 * we assume back-to-back 1939 */ 1940 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1941 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1942 return; 1943 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1944 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1945 e1000_read_phy_reg(&sc->hw, 1946 PHY_1000T_CTRL, &phy_tmp); 1947 if (phy_tmp & CR_1000T_MS_ENABLE) { 1948 phy_tmp &= ~CR_1000T_MS_ENABLE; 1949 e1000_write_phy_reg(&sc->hw, 1950 PHY_1000T_CTRL, phy_tmp); 1951 sc->smartspeed++; 1952 if (sc->hw.mac.autoneg && 1953 !e1000_phy_setup_autoneg(&sc->hw) && 1954 !e1000_read_phy_reg(&sc->hw, 1955 PHY_CONTROL, &phy_tmp)) { 1956 phy_tmp |= MII_CR_AUTO_NEG_EN | 1957 MII_CR_RESTART_AUTO_NEG; 1958 e1000_write_phy_reg(&sc->hw, 1959 PHY_CONTROL, phy_tmp); 1960 } 1961 } 1962 } 1963 return; 1964 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 1965 /* If still no link, perhaps using 2/3 pair cable */ 1966 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1967 phy_tmp |= CR_1000T_MS_ENABLE; 1968 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1969 if (sc->hw.mac.autoneg && 1970 !e1000_phy_setup_autoneg(&sc->hw) && 1971 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 1972 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 1973 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 1974 } 1975 } 1976 1977 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 1978 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 1979 sc->smartspeed = 0; 1980 } 1981 1982 static int 1983 emx_create_tx_ring(struct emx_softc *sc) 1984 { 1985 device_t dev = sc->dev; 1986 struct emx_txbuf *tx_buffer; 1987 int error, i, tsize, ntxd; 1988 1989 /* 1990 * Validate number of transmit descriptors. It must not exceed 1991 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 1992 */ 1993 ntxd = device_getenv_int(dev, "txd", emx_txd); 1994 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 1995 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 1996 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 1997 EMX_DEFAULT_TXD, ntxd); 1998 sc->num_tx_desc = EMX_DEFAULT_TXD; 1999 } else { 2000 sc->num_tx_desc = ntxd; 2001 } 2002 2003 /* 2004 * Allocate Transmit Descriptor ring 2005 */ 2006 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc), 2007 EMX_DBA_ALIGN); 2008 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag, 2009 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 2010 &sc->tx_desc_dtag, &sc->tx_desc_dmap, 2011 &sc->tx_desc_paddr); 2012 if (sc->tx_desc_base == NULL) { 2013 device_printf(dev, "Unable to allocate tx_desc memory\n"); 2014 return ENOMEM; 2015 } 2016 2017 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc, 2018 M_DEVBUF, M_WAITOK | M_ZERO); 2019 2020 /* 2021 * Create DMA tags for tx buffers 2022 */ 2023 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2024 1, 0, /* alignment, bounds */ 2025 BUS_SPACE_MAXADDR, /* lowaddr */ 2026 BUS_SPACE_MAXADDR, /* highaddr */ 2027 NULL, NULL, /* filter, filterarg */ 2028 EMX_TSO_SIZE, /* maxsize */ 2029 EMX_MAX_SCATTER, /* nsegments */ 2030 EMX_MAX_SEGSIZE, /* maxsegsize */ 2031 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2032 BUS_DMA_ONEBPAGE, /* flags */ 2033 &sc->txtag); 2034 if (error) { 2035 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2036 kfree(sc->tx_buf, M_DEVBUF); 2037 sc->tx_buf = NULL; 2038 return error; 2039 } 2040 2041 /* 2042 * Create DMA maps for tx buffers 2043 */ 2044 for (i = 0; i < sc->num_tx_desc; i++) { 2045 tx_buffer = &sc->tx_buf[i]; 2046 2047 error = bus_dmamap_create(sc->txtag, 2048 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2049 &tx_buffer->map); 2050 if (error) { 2051 device_printf(dev, "Unable to create TX DMA map\n"); 2052 emx_destroy_tx_ring(sc, i); 2053 return error; 2054 } 2055 } 2056 return (0); 2057 } 2058 2059 static void 2060 emx_init_tx_ring(struct emx_softc *sc) 2061 { 2062 /* Clear the old ring contents */ 2063 bzero(sc->tx_desc_base, 2064 sizeof(struct e1000_tx_desc) * sc->num_tx_desc); 2065 2066 /* Reset state */ 2067 sc->next_avail_tx_desc = 0; 2068 sc->next_tx_to_clean = 0; 2069 sc->num_tx_desc_avail = sc->num_tx_desc; 2070 } 2071 2072 static void 2073 emx_init_tx_unit(struct emx_softc *sc) 2074 { 2075 uint32_t tctl, tarc, tipg = 0; 2076 uint64_t bus_addr; 2077 2078 /* Setup the Base and Length of the Tx Descriptor Ring */ 2079 bus_addr = sc->tx_desc_paddr; 2080 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 2081 sc->num_tx_desc * sizeof(struct e1000_tx_desc)); 2082 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 2083 (uint32_t)(bus_addr >> 32)); 2084 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 2085 (uint32_t)bus_addr); 2086 /* Setup the HW Tx Head and Tail descriptor pointers */ 2087 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 2088 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 2089 2090 /* Set the default values for the Tx Inter Packet Gap timer */ 2091 switch (sc->hw.mac.type) { 2092 case e1000_80003es2lan: 2093 tipg = DEFAULT_82543_TIPG_IPGR1; 2094 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2095 E1000_TIPG_IPGR2_SHIFT; 2096 break; 2097 2098 default: 2099 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2100 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2101 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2102 else 2103 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2104 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2105 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2106 break; 2107 } 2108 2109 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2110 2111 /* NOTE: 0 is not allowed for TIDV */ 2112 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2113 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2114 2115 if (sc->hw.mac.type == e1000_82571 || 2116 sc->hw.mac.type == e1000_82572) { 2117 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2118 tarc |= EMX_TARC_SPEED_MODE; 2119 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2120 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2121 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2122 tarc |= 1; 2123 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2124 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2125 tarc |= 1; 2126 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2127 } 2128 2129 /* Program the Transmit Control Register */ 2130 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2131 tctl &= ~E1000_TCTL_CT; 2132 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2133 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2134 tctl |= E1000_TCTL_MULR; 2135 2136 /* This write will effectively turn on the transmit unit. */ 2137 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2138 } 2139 2140 static void 2141 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc) 2142 { 2143 struct emx_txbuf *tx_buffer; 2144 int i; 2145 2146 /* Free Transmit Descriptor ring */ 2147 if (sc->tx_desc_base) { 2148 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap); 2149 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base, 2150 sc->tx_desc_dmap); 2151 bus_dma_tag_destroy(sc->tx_desc_dtag); 2152 2153 sc->tx_desc_base = NULL; 2154 } 2155 2156 if (sc->tx_buf == NULL) 2157 return; 2158 2159 for (i = 0; i < ndesc; i++) { 2160 tx_buffer = &sc->tx_buf[i]; 2161 2162 KKASSERT(tx_buffer->m_head == NULL); 2163 bus_dmamap_destroy(sc->txtag, tx_buffer->map); 2164 } 2165 bus_dma_tag_destroy(sc->txtag); 2166 2167 kfree(sc->tx_buf, M_DEVBUF); 2168 sc->tx_buf = NULL; 2169 } 2170 2171 /* 2172 * The offload context needs to be set when we transfer the first 2173 * packet of a particular protocol (TCP/UDP). This routine has been 2174 * enhanced to deal with inserted VLAN headers. 2175 * 2176 * If the new packet's ether header length, ip header length and 2177 * csum offloading type are same as the previous packet, we should 2178 * avoid allocating a new csum context descriptor; mainly to take 2179 * advantage of the pipeline effect of the TX data read request. 2180 * 2181 * This function returns number of TX descrptors allocated for 2182 * csum context. 2183 */ 2184 static int 2185 emx_txcsum(struct emx_softc *sc, struct mbuf *mp, 2186 uint32_t *txd_upper, uint32_t *txd_lower) 2187 { 2188 struct e1000_context_desc *TXD; 2189 int curr_txd, ehdrlen, csum_flags; 2190 uint32_t cmd, hdr_len, ip_hlen; 2191 2192 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2193 ip_hlen = mp->m_pkthdr.csum_iphlen; 2194 ehdrlen = mp->m_pkthdr.csum_lhlen; 2195 2196 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen && 2197 sc->csum_flags == csum_flags) { 2198 /* 2199 * Same csum offload context as the previous packets; 2200 * just return. 2201 */ 2202 *txd_upper = sc->csum_txd_upper; 2203 *txd_lower = sc->csum_txd_lower; 2204 return 0; 2205 } 2206 2207 /* 2208 * Setup a new csum offload context. 2209 */ 2210 2211 curr_txd = sc->next_avail_tx_desc; 2212 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 2213 2214 cmd = 0; 2215 2216 /* Setup of IP header checksum. */ 2217 if (csum_flags & CSUM_IP) { 2218 /* 2219 * Start offset for header checksum calculation. 2220 * End offset for header checksum calculation. 2221 * Offset of place to put the checksum. 2222 */ 2223 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2224 TXD->lower_setup.ip_fields.ipcse = 2225 htole16(ehdrlen + ip_hlen - 1); 2226 TXD->lower_setup.ip_fields.ipcso = 2227 ehdrlen + offsetof(struct ip, ip_sum); 2228 cmd |= E1000_TXD_CMD_IP; 2229 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2230 } 2231 hdr_len = ehdrlen + ip_hlen; 2232 2233 if (csum_flags & CSUM_TCP) { 2234 /* 2235 * Start offset for payload checksum calculation. 2236 * End offset for payload checksum calculation. 2237 * Offset of place to put the checksum. 2238 */ 2239 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2240 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2241 TXD->upper_setup.tcp_fields.tucso = 2242 hdr_len + offsetof(struct tcphdr, th_sum); 2243 cmd |= E1000_TXD_CMD_TCP; 2244 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2245 } else if (csum_flags & CSUM_UDP) { 2246 /* 2247 * Start offset for header checksum calculation. 2248 * End offset for header checksum calculation. 2249 * Offset of place to put the checksum. 2250 */ 2251 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2252 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2253 TXD->upper_setup.tcp_fields.tucso = 2254 hdr_len + offsetof(struct udphdr, uh_sum); 2255 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2256 } 2257 2258 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2259 E1000_TXD_DTYP_D; /* Data descr */ 2260 2261 /* Save the information for this csum offloading context */ 2262 sc->csum_lhlen = ehdrlen; 2263 sc->csum_iphlen = ip_hlen; 2264 sc->csum_flags = csum_flags; 2265 sc->csum_txd_upper = *txd_upper; 2266 sc->csum_txd_lower = *txd_lower; 2267 2268 TXD->tcp_seg_setup.data = htole32(0); 2269 TXD->cmd_and_length = 2270 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2271 2272 if (++curr_txd == sc->num_tx_desc) 2273 curr_txd = 0; 2274 2275 KKASSERT(sc->num_tx_desc_avail > 0); 2276 sc->num_tx_desc_avail--; 2277 2278 sc->next_avail_tx_desc = curr_txd; 2279 return 1; 2280 } 2281 2282 static void 2283 emx_txeof(struct emx_softc *sc) 2284 { 2285 struct ifnet *ifp = &sc->arpcom.ac_if; 2286 struct emx_txbuf *tx_buffer; 2287 int first, num_avail; 2288 2289 if (sc->tx_dd_head == sc->tx_dd_tail) 2290 return; 2291 2292 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2293 return; 2294 2295 num_avail = sc->num_tx_desc_avail; 2296 first = sc->next_tx_to_clean; 2297 2298 while (sc->tx_dd_head != sc->tx_dd_tail) { 2299 int dd_idx = sc->tx_dd[sc->tx_dd_head]; 2300 struct e1000_tx_desc *tx_desc; 2301 2302 tx_desc = &sc->tx_desc_base[dd_idx]; 2303 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2304 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2305 2306 if (++dd_idx == sc->num_tx_desc) 2307 dd_idx = 0; 2308 2309 while (first != dd_idx) { 2310 logif(pkt_txclean); 2311 2312 num_avail++; 2313 2314 tx_buffer = &sc->tx_buf[first]; 2315 if (tx_buffer->m_head) { 2316 ifp->if_opackets++; 2317 bus_dmamap_unload(sc->txtag, 2318 tx_buffer->map); 2319 m_freem(tx_buffer->m_head); 2320 tx_buffer->m_head = NULL; 2321 } 2322 2323 if (++first == sc->num_tx_desc) 2324 first = 0; 2325 } 2326 } else { 2327 break; 2328 } 2329 } 2330 sc->next_tx_to_clean = first; 2331 sc->num_tx_desc_avail = num_avail; 2332 2333 if (sc->tx_dd_head == sc->tx_dd_tail) { 2334 sc->tx_dd_head = 0; 2335 sc->tx_dd_tail = 0; 2336 } 2337 2338 if (!EMX_IS_OACTIVE(sc)) { 2339 ifp->if_flags &= ~IFF_OACTIVE; 2340 2341 /* All clean, turn off the timer */ 2342 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2343 ifp->if_timer = 0; 2344 } 2345 } 2346 2347 static void 2348 emx_tx_collect(struct emx_softc *sc) 2349 { 2350 struct ifnet *ifp = &sc->arpcom.ac_if; 2351 struct emx_txbuf *tx_buffer; 2352 int tdh, first, num_avail, dd_idx = -1; 2353 2354 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2355 return; 2356 2357 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0)); 2358 if (tdh == sc->next_tx_to_clean) 2359 return; 2360 2361 if (sc->tx_dd_head != sc->tx_dd_tail) 2362 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2363 2364 num_avail = sc->num_tx_desc_avail; 2365 first = sc->next_tx_to_clean; 2366 2367 while (first != tdh) { 2368 logif(pkt_txclean); 2369 2370 num_avail++; 2371 2372 tx_buffer = &sc->tx_buf[first]; 2373 if (tx_buffer->m_head) { 2374 ifp->if_opackets++; 2375 bus_dmamap_unload(sc->txtag, 2376 tx_buffer->map); 2377 m_freem(tx_buffer->m_head); 2378 tx_buffer->m_head = NULL; 2379 } 2380 2381 if (first == dd_idx) { 2382 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2383 if (sc->tx_dd_head == sc->tx_dd_tail) { 2384 sc->tx_dd_head = 0; 2385 sc->tx_dd_tail = 0; 2386 dd_idx = -1; 2387 } else { 2388 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2389 } 2390 } 2391 2392 if (++first == sc->num_tx_desc) 2393 first = 0; 2394 } 2395 sc->next_tx_to_clean = first; 2396 sc->num_tx_desc_avail = num_avail; 2397 2398 if (!EMX_IS_OACTIVE(sc)) { 2399 ifp->if_flags &= ~IFF_OACTIVE; 2400 2401 /* All clean, turn off the timer */ 2402 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2403 ifp->if_timer = 0; 2404 } 2405 } 2406 2407 /* 2408 * When Link is lost sometimes there is work still in the TX ring 2409 * which will result in a watchdog, rather than allow that do an 2410 * attempted cleanup and then reinit here. Note that this has been 2411 * seens mostly with fiber adapters. 2412 */ 2413 static void 2414 emx_tx_purge(struct emx_softc *sc) 2415 { 2416 struct ifnet *ifp = &sc->arpcom.ac_if; 2417 2418 if (!sc->link_active && ifp->if_timer) { 2419 emx_tx_collect(sc); 2420 if (ifp->if_timer) { 2421 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2422 ifp->if_timer = 0; 2423 emx_init(sc); 2424 } 2425 } 2426 } 2427 2428 static int 2429 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init) 2430 { 2431 struct mbuf *m; 2432 bus_dma_segment_t seg; 2433 bus_dmamap_t map; 2434 struct emx_rxbuf *rx_buffer; 2435 int error, nseg; 2436 2437 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2438 if (m == NULL) { 2439 rdata->mbuf_cluster_failed++; 2440 if (init) { 2441 if_printf(&sc->arpcom.ac_if, 2442 "Unable to allocate RX mbuf\n"); 2443 } 2444 return (ENOBUFS); 2445 } 2446 m->m_len = m->m_pkthdr.len = MCLBYTES; 2447 2448 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2449 m_adj(m, ETHER_ALIGN); 2450 2451 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2452 rdata->rx_sparemap, m, 2453 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2454 if (error) { 2455 m_freem(m); 2456 if (init) { 2457 if_printf(&sc->arpcom.ac_if, 2458 "Unable to load RX mbuf\n"); 2459 } 2460 return (error); 2461 } 2462 2463 rx_buffer = &rdata->rx_buf[i]; 2464 if (rx_buffer->m_head != NULL) 2465 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2466 2467 map = rx_buffer->map; 2468 rx_buffer->map = rdata->rx_sparemap; 2469 rdata->rx_sparemap = map; 2470 2471 rx_buffer->m_head = m; 2472 rx_buffer->paddr = seg.ds_addr; 2473 2474 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2475 return (0); 2476 } 2477 2478 static int 2479 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2480 { 2481 device_t dev = sc->dev; 2482 struct emx_rxbuf *rx_buffer; 2483 int i, error, rsize, nrxd; 2484 2485 /* 2486 * Validate number of receive descriptors. It must not exceed 2487 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2488 */ 2489 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2490 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2491 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2492 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2493 EMX_DEFAULT_RXD, nrxd); 2494 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2495 } else { 2496 rdata->num_rx_desc = nrxd; 2497 } 2498 2499 /* 2500 * Allocate Receive Descriptor ring 2501 */ 2502 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2503 EMX_DBA_ALIGN); 2504 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag, 2505 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2506 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2507 &rdata->rx_desc_paddr); 2508 if (rdata->rx_desc == NULL) { 2509 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2510 return ENOMEM; 2511 } 2512 2513 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc, 2514 M_DEVBUF, M_WAITOK | M_ZERO); 2515 2516 /* 2517 * Create DMA tag for rx buffers 2518 */ 2519 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2520 1, 0, /* alignment, bounds */ 2521 BUS_SPACE_MAXADDR, /* lowaddr */ 2522 BUS_SPACE_MAXADDR, /* highaddr */ 2523 NULL, NULL, /* filter, filterarg */ 2524 MCLBYTES, /* maxsize */ 2525 1, /* nsegments */ 2526 MCLBYTES, /* maxsegsize */ 2527 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2528 &rdata->rxtag); 2529 if (error) { 2530 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2531 kfree(rdata->rx_buf, M_DEVBUF); 2532 rdata->rx_buf = NULL; 2533 return error; 2534 } 2535 2536 /* 2537 * Create spare DMA map for rx buffers 2538 */ 2539 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2540 &rdata->rx_sparemap); 2541 if (error) { 2542 device_printf(dev, "Unable to create spare RX DMA map\n"); 2543 bus_dma_tag_destroy(rdata->rxtag); 2544 kfree(rdata->rx_buf, M_DEVBUF); 2545 rdata->rx_buf = NULL; 2546 return error; 2547 } 2548 2549 /* 2550 * Create DMA maps for rx buffers 2551 */ 2552 for (i = 0; i < rdata->num_rx_desc; i++) { 2553 rx_buffer = &rdata->rx_buf[i]; 2554 2555 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2556 &rx_buffer->map); 2557 if (error) { 2558 device_printf(dev, "Unable to create RX DMA map\n"); 2559 emx_destroy_rx_ring(sc, rdata, i); 2560 return error; 2561 } 2562 } 2563 return (0); 2564 } 2565 2566 static void 2567 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2568 { 2569 int i; 2570 2571 for (i = 0; i < rdata->num_rx_desc; i++) { 2572 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2573 2574 if (rx_buffer->m_head != NULL) { 2575 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2576 m_freem(rx_buffer->m_head); 2577 rx_buffer->m_head = NULL; 2578 } 2579 } 2580 2581 if (rdata->fmp != NULL) 2582 m_freem(rdata->fmp); 2583 rdata->fmp = NULL; 2584 rdata->lmp = NULL; 2585 } 2586 2587 static int 2588 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2589 { 2590 int i, error; 2591 2592 /* Reset descriptor ring */ 2593 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2594 2595 /* Allocate new ones. */ 2596 for (i = 0; i < rdata->num_rx_desc; i++) { 2597 error = emx_newbuf(sc, rdata, i, 1); 2598 if (error) 2599 return (error); 2600 } 2601 2602 /* Setup our descriptor pointers */ 2603 rdata->next_rx_desc_to_check = 0; 2604 2605 return (0); 2606 } 2607 2608 static void 2609 emx_init_rx_unit(struct emx_softc *sc) 2610 { 2611 struct ifnet *ifp = &sc->arpcom.ac_if; 2612 uint64_t bus_addr; 2613 uint32_t rctl, itr, rfctl; 2614 int i; 2615 2616 /* 2617 * Make sure receives are disabled while setting 2618 * up the descriptor ring 2619 */ 2620 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2621 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2622 2623 /* 2624 * Set the interrupt throttling rate. Value is calculated 2625 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2626 */ 2627 if (sc->int_throttle_ceil) 2628 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2629 else 2630 itr = 0; 2631 emx_set_itr(sc, itr); 2632 2633 /* Use extended RX descriptor */ 2634 rfctl = E1000_RFCTL_EXTEN; 2635 2636 /* Disable accelerated ackknowledge */ 2637 if (sc->hw.mac.type == e1000_82574) 2638 rfctl |= E1000_RFCTL_ACK_DIS; 2639 2640 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2641 2642 /* 2643 * Receive Checksum Offload for TCP and UDP 2644 * 2645 * Checksum offloading is also enabled if multiple receive 2646 * queue is to be supported, since we need it to figure out 2647 * packet type. 2648 */ 2649 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2650 sc->rx_ring_cnt > 1) { 2651 uint32_t rxcsum; 2652 2653 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2654 2655 /* 2656 * NOTE: 2657 * PCSD must be enabled to enable multiple 2658 * receive queues. 2659 */ 2660 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2661 E1000_RXCSUM_PCSD; 2662 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2663 } 2664 2665 /* 2666 * Configure multiple receive queue (RSS) 2667 */ 2668 if (sc->rx_ring_cnt > 1) { 2669 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2670 uint32_t reta; 2671 2672 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2673 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2674 2675 /* 2676 * NOTE: 2677 * When we reach here, RSS has already been disabled 2678 * in emx_stop(), so we could safely configure RSS key 2679 * and redirect table. 2680 */ 2681 2682 /* 2683 * Configure RSS key 2684 */ 2685 toeplitz_get_key(key, sizeof(key)); 2686 for (i = 0; i < EMX_NRSSRK; ++i) { 2687 uint32_t rssrk; 2688 2689 rssrk = EMX_RSSRK_VAL(key, i); 2690 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2691 2692 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2693 } 2694 2695 /* 2696 * Configure RSS redirect table in following fashion: 2697 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2698 */ 2699 reta = 0; 2700 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2701 uint32_t q; 2702 2703 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT; 2704 reta |= q << (8 * i); 2705 } 2706 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2707 2708 for (i = 0; i < EMX_NRETA; ++i) 2709 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2710 2711 /* 2712 * Enable multiple receive queues. 2713 * Enable IPv4 RSS standard hash functions. 2714 * Disable RSS interrupt. 2715 */ 2716 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2717 E1000_MRQC_ENABLE_RSS_2Q | 2718 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2719 E1000_MRQC_RSS_FIELD_IPV4); 2720 } 2721 2722 /* 2723 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2724 * long latencies are observed, like Lenovo X60. This 2725 * change eliminates the problem, but since having positive 2726 * values in RDTR is a known source of problems on other 2727 * platforms another solution is being sought. 2728 */ 2729 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2730 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2731 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2732 } 2733 2734 for (i = 0; i < sc->rx_ring_cnt; ++i) { 2735 struct emx_rxdata *rdata = &sc->rx_data[i]; 2736 2737 /* 2738 * Setup the Base and Length of the Rx Descriptor Ring 2739 */ 2740 bus_addr = rdata->rx_desc_paddr; 2741 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2742 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2743 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2744 (uint32_t)(bus_addr >> 32)); 2745 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2746 (uint32_t)bus_addr); 2747 2748 /* 2749 * Setup the HW Rx Head and Tail Descriptor Pointers 2750 */ 2751 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2752 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2753 sc->rx_data[i].num_rx_desc - 1); 2754 } 2755 2756 /* Setup the Receive Control Register */ 2757 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2758 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2759 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2760 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2761 2762 /* Make sure VLAN Filters are off */ 2763 rctl &= ~E1000_RCTL_VFE; 2764 2765 /* Don't store bad paket */ 2766 rctl &= ~E1000_RCTL_SBP; 2767 2768 /* MCLBYTES */ 2769 rctl |= E1000_RCTL_SZ_2048; 2770 2771 if (ifp->if_mtu > ETHERMTU) 2772 rctl |= E1000_RCTL_LPE; 2773 else 2774 rctl &= ~E1000_RCTL_LPE; 2775 2776 /* Enable Receives */ 2777 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2778 } 2779 2780 static void 2781 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc) 2782 { 2783 struct emx_rxbuf *rx_buffer; 2784 int i; 2785 2786 /* Free Receive Descriptor ring */ 2787 if (rdata->rx_desc) { 2788 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2789 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2790 rdata->rx_desc_dmap); 2791 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2792 2793 rdata->rx_desc = NULL; 2794 } 2795 2796 if (rdata->rx_buf == NULL) 2797 return; 2798 2799 for (i = 0; i < ndesc; i++) { 2800 rx_buffer = &rdata->rx_buf[i]; 2801 2802 KKASSERT(rx_buffer->m_head == NULL); 2803 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2804 } 2805 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2806 bus_dma_tag_destroy(rdata->rxtag); 2807 2808 kfree(rdata->rx_buf, M_DEVBUF); 2809 rdata->rx_buf = NULL; 2810 } 2811 2812 static void 2813 emx_rxeof(struct emx_softc *sc, int ring_idx, int count) 2814 { 2815 struct emx_rxdata *rdata = &sc->rx_data[ring_idx]; 2816 struct ifnet *ifp = &sc->arpcom.ac_if; 2817 uint32_t staterr; 2818 emx_rxdesc_t *current_desc; 2819 struct mbuf *mp; 2820 int i; 2821 2822 i = rdata->next_rx_desc_to_check; 2823 current_desc = &rdata->rx_desc[i]; 2824 staterr = le32toh(current_desc->rxd_staterr); 2825 2826 if (!(staterr & E1000_RXD_STAT_DD)) 2827 return; 2828 2829 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2830 struct pktinfo *pi = NULL, pi0; 2831 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2832 struct mbuf *m = NULL; 2833 int eop, len; 2834 2835 logif(pkt_receive); 2836 2837 mp = rx_buf->m_head; 2838 2839 /* 2840 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2841 * needs to access the last received byte in the mbuf. 2842 */ 2843 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2844 BUS_DMASYNC_POSTREAD); 2845 2846 len = le16toh(current_desc->rxd_length); 2847 if (staterr & E1000_RXD_STAT_EOP) { 2848 count--; 2849 eop = 1; 2850 } else { 2851 eop = 0; 2852 } 2853 2854 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2855 uint16_t vlan = 0; 2856 uint32_t mrq, rss_hash; 2857 2858 /* 2859 * Save several necessary information, 2860 * before emx_newbuf() destroy it. 2861 */ 2862 if ((staterr & E1000_RXD_STAT_VP) && eop) 2863 vlan = le16toh(current_desc->rxd_vlan); 2864 2865 mrq = le32toh(current_desc->rxd_mrq); 2866 rss_hash = le32toh(current_desc->rxd_rss); 2867 2868 EMX_RSS_DPRINTF(sc, 10, 2869 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2870 ring_idx, mrq, rss_hash); 2871 2872 if (emx_newbuf(sc, rdata, i, 0) != 0) { 2873 ifp->if_iqdrops++; 2874 goto discard; 2875 } 2876 2877 /* Assign correct length to the current fragment */ 2878 mp->m_len = len; 2879 2880 if (rdata->fmp == NULL) { 2881 mp->m_pkthdr.len = len; 2882 rdata->fmp = mp; /* Store the first mbuf */ 2883 rdata->lmp = mp; 2884 } else { 2885 /* 2886 * Chain mbuf's together 2887 */ 2888 rdata->lmp->m_next = mp; 2889 rdata->lmp = rdata->lmp->m_next; 2890 rdata->fmp->m_pkthdr.len += len; 2891 } 2892 2893 if (eop) { 2894 rdata->fmp->m_pkthdr.rcvif = ifp; 2895 ifp->if_ipackets++; 2896 2897 if (ifp->if_capenable & IFCAP_RXCSUM) 2898 emx_rxcsum(staterr, rdata->fmp); 2899 2900 if (staterr & E1000_RXD_STAT_VP) { 2901 rdata->fmp->m_pkthdr.ether_vlantag = 2902 vlan; 2903 rdata->fmp->m_flags |= M_VLANTAG; 2904 } 2905 m = rdata->fmp; 2906 rdata->fmp = NULL; 2907 rdata->lmp = NULL; 2908 2909 if (ifp->if_capenable & IFCAP_RSS) { 2910 pi = emx_rssinfo(m, &pi0, mrq, 2911 rss_hash, staterr); 2912 } 2913 #ifdef EMX_RSS_DEBUG 2914 rdata->rx_pkts++; 2915 #endif 2916 } 2917 } else { 2918 ifp->if_ierrors++; 2919 discard: 2920 emx_setup_rxdesc(current_desc, rx_buf); 2921 if (rdata->fmp != NULL) { 2922 m_freem(rdata->fmp); 2923 rdata->fmp = NULL; 2924 rdata->lmp = NULL; 2925 } 2926 m = NULL; 2927 } 2928 2929 if (m != NULL) 2930 ether_input_pkt(ifp, m, pi); 2931 2932 /* Advance our pointers to the next descriptor. */ 2933 if (++i == rdata->num_rx_desc) 2934 i = 0; 2935 2936 current_desc = &rdata->rx_desc[i]; 2937 staterr = le32toh(current_desc->rxd_staterr); 2938 } 2939 rdata->next_rx_desc_to_check = i; 2940 2941 /* Advance the E1000's Receive Queue "Tail Pointer". */ 2942 if (--i < 0) 2943 i = rdata->num_rx_desc - 1; 2944 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i); 2945 } 2946 2947 static void 2948 emx_enable_intr(struct emx_softc *sc) 2949 { 2950 uint32_t ims_mask = IMS_ENABLE_MASK; 2951 2952 lwkt_serialize_handler_enable(&sc->main_serialize); 2953 2954 #if 0 2955 if (sc->hw.mac.type == e1000_82574) { 2956 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 2957 ims_mask |= EM_MSIX_MASK; 2958 } 2959 #endif 2960 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 2961 } 2962 2963 static void 2964 emx_disable_intr(struct emx_softc *sc) 2965 { 2966 if (sc->hw.mac.type == e1000_82574) 2967 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 2968 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 2969 2970 lwkt_serialize_handler_disable(&sc->main_serialize); 2971 } 2972 2973 /* 2974 * Bit of a misnomer, what this really means is 2975 * to enable OS management of the system... aka 2976 * to disable special hardware management features 2977 */ 2978 static void 2979 emx_get_mgmt(struct emx_softc *sc) 2980 { 2981 /* A shared code workaround */ 2982 if (sc->has_manage) { 2983 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 2984 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2985 2986 /* disable hardware interception of ARP */ 2987 manc &= ~(E1000_MANC_ARP_EN); 2988 2989 /* enable receiving management packets to the host */ 2990 manc |= E1000_MANC_EN_MNG2HOST; 2991 #define E1000_MNG2HOST_PORT_623 (1 << 5) 2992 #define E1000_MNG2HOST_PORT_664 (1 << 6) 2993 manc2h |= E1000_MNG2HOST_PORT_623; 2994 manc2h |= E1000_MNG2HOST_PORT_664; 2995 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 2996 2997 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 2998 } 2999 } 3000 3001 /* 3002 * Give control back to hardware management 3003 * controller if there is one. 3004 */ 3005 static void 3006 emx_rel_mgmt(struct emx_softc *sc) 3007 { 3008 if (sc->has_manage) { 3009 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3010 3011 /* re-enable hardware interception of ARP */ 3012 manc |= E1000_MANC_ARP_EN; 3013 manc &= ~E1000_MANC_EN_MNG2HOST; 3014 3015 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3016 } 3017 } 3018 3019 /* 3020 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3021 * For ASF and Pass Through versions of f/w this means that 3022 * the driver is loaded. For AMT version (only with 82573) 3023 * of the f/w this means that the network i/f is open. 3024 */ 3025 static void 3026 emx_get_hw_control(struct emx_softc *sc) 3027 { 3028 /* Let firmware know the driver has taken over */ 3029 if (sc->hw.mac.type == e1000_82573) { 3030 uint32_t swsm; 3031 3032 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3033 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3034 swsm | E1000_SWSM_DRV_LOAD); 3035 } else { 3036 uint32_t ctrl_ext; 3037 3038 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3039 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3040 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3041 } 3042 sc->control_hw = 1; 3043 } 3044 3045 /* 3046 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3047 * For ASF and Pass Through versions of f/w this means that the 3048 * driver is no longer loaded. For AMT version (only with 82573) 3049 * of the f/w this means that the network i/f is closed. 3050 */ 3051 static void 3052 emx_rel_hw_control(struct emx_softc *sc) 3053 { 3054 if (!sc->control_hw) 3055 return; 3056 sc->control_hw = 0; 3057 3058 /* Let firmware taken over control of h/w */ 3059 if (sc->hw.mac.type == e1000_82573) { 3060 uint32_t swsm; 3061 3062 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3063 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3064 swsm & ~E1000_SWSM_DRV_LOAD); 3065 } else { 3066 uint32_t ctrl_ext; 3067 3068 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3069 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3070 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3071 } 3072 } 3073 3074 static int 3075 emx_is_valid_eaddr(const uint8_t *addr) 3076 { 3077 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3078 3079 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3080 return (FALSE); 3081 3082 return (TRUE); 3083 } 3084 3085 /* 3086 * Enable PCI Wake On Lan capability 3087 */ 3088 void 3089 emx_enable_wol(device_t dev) 3090 { 3091 uint16_t cap, status; 3092 uint8_t id; 3093 3094 /* First find the capabilities pointer*/ 3095 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3096 3097 /* Read the PM Capabilities */ 3098 id = pci_read_config(dev, cap, 1); 3099 if (id != PCIY_PMG) /* Something wrong */ 3100 return; 3101 3102 /* 3103 * OK, we have the power capabilities, 3104 * so now get the status register 3105 */ 3106 cap += PCIR_POWER_STATUS; 3107 status = pci_read_config(dev, cap, 2); 3108 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3109 pci_write_config(dev, cap, status, 2); 3110 } 3111 3112 static void 3113 emx_update_stats(struct emx_softc *sc) 3114 { 3115 struct ifnet *ifp = &sc->arpcom.ac_if; 3116 3117 if (sc->hw.phy.media_type == e1000_media_type_copper || 3118 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3119 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3120 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3121 } 3122 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3123 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3124 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3125 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3126 3127 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3128 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3129 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3130 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3131 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3132 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3133 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3134 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3135 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3136 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3137 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3138 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3139 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3140 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3141 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3142 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3143 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3144 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3145 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3146 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3147 3148 /* For the 64-bit byte counters the low dword must be read first. */ 3149 /* Both registers clear on the read of the high dword */ 3150 3151 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3152 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3153 3154 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3155 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3156 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3157 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3158 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3159 3160 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3161 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3162 3163 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3164 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3165 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3166 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3167 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3168 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3169 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3170 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3171 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3172 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3173 3174 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3175 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3176 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3177 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3178 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3179 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3180 3181 ifp->if_collisions = sc->stats.colc; 3182 3183 /* Rx Errors */ 3184 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3185 sc->stats.crcerrs + sc->stats.algnerrc + 3186 sc->stats.ruc + sc->stats.roc + 3187 sc->stats.mpc + sc->stats.cexterr; 3188 3189 /* Tx Errors */ 3190 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3191 sc->watchdog_events; 3192 } 3193 3194 static void 3195 emx_print_debug_info(struct emx_softc *sc) 3196 { 3197 device_t dev = sc->dev; 3198 uint8_t *hw_addr = sc->hw.hw_addr; 3199 3200 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3201 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3202 E1000_READ_REG(&sc->hw, E1000_CTRL), 3203 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3204 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3205 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3206 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3207 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3208 sc->hw.fc.high_water, sc->hw.fc.low_water); 3209 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3210 E1000_READ_REG(&sc->hw, E1000_TIDV), 3211 E1000_READ_REG(&sc->hw, E1000_TADV)); 3212 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3213 E1000_READ_REG(&sc->hw, E1000_RDTR), 3214 E1000_READ_REG(&sc->hw, E1000_RADV)); 3215 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3216 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3217 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3218 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3219 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3220 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3221 device_printf(dev, "Num Tx descriptors avail = %d\n", 3222 sc->num_tx_desc_avail); 3223 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3224 sc->no_tx_desc_avail1); 3225 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3226 sc->no_tx_desc_avail2); 3227 device_printf(dev, "Std mbuf failed = %ld\n", 3228 sc->mbuf_alloc_failed); 3229 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3230 sc->rx_data[0].mbuf_cluster_failed); 3231 device_printf(dev, "Driver dropped packets = %ld\n", 3232 sc->dropped_pkts); 3233 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3234 sc->no_tx_dma_setup); 3235 3236 device_printf(dev, "TSO segments %lu\n", sc->tso_segments); 3237 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused); 3238 } 3239 3240 static void 3241 emx_print_hw_stats(struct emx_softc *sc) 3242 { 3243 device_t dev = sc->dev; 3244 3245 device_printf(dev, "Excessive collisions = %lld\n", 3246 (long long)sc->stats.ecol); 3247 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3248 device_printf(dev, "Symbol errors = %lld\n", 3249 (long long)sc->stats.symerrs); 3250 #endif 3251 device_printf(dev, "Sequence errors = %lld\n", 3252 (long long)sc->stats.sec); 3253 device_printf(dev, "Defer count = %lld\n", 3254 (long long)sc->stats.dc); 3255 device_printf(dev, "Missed Packets = %lld\n", 3256 (long long)sc->stats.mpc); 3257 device_printf(dev, "Receive No Buffers = %lld\n", 3258 (long long)sc->stats.rnbc); 3259 /* RLEC is inaccurate on some hardware, calculate our own. */ 3260 device_printf(dev, "Receive Length Errors = %lld\n", 3261 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3262 device_printf(dev, "Receive errors = %lld\n", 3263 (long long)sc->stats.rxerrc); 3264 device_printf(dev, "Crc errors = %lld\n", 3265 (long long)sc->stats.crcerrs); 3266 device_printf(dev, "Alignment errors = %lld\n", 3267 (long long)sc->stats.algnerrc); 3268 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3269 (long long)sc->stats.cexterr); 3270 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3271 device_printf(dev, "watchdog timeouts = %ld\n", 3272 sc->watchdog_events); 3273 device_printf(dev, "XON Rcvd = %lld\n", 3274 (long long)sc->stats.xonrxc); 3275 device_printf(dev, "XON Xmtd = %lld\n", 3276 (long long)sc->stats.xontxc); 3277 device_printf(dev, "XOFF Rcvd = %lld\n", 3278 (long long)sc->stats.xoffrxc); 3279 device_printf(dev, "XOFF Xmtd = %lld\n", 3280 (long long)sc->stats.xofftxc); 3281 device_printf(dev, "Good Packets Rcvd = %lld\n", 3282 (long long)sc->stats.gprc); 3283 device_printf(dev, "Good Packets Xmtd = %lld\n", 3284 (long long)sc->stats.gptc); 3285 } 3286 3287 static void 3288 emx_print_nvm_info(struct emx_softc *sc) 3289 { 3290 uint16_t eeprom_data; 3291 int i, j, row = 0; 3292 3293 /* Its a bit crude, but it gets the job done */ 3294 kprintf("\nInterface EEPROM Dump:\n"); 3295 kprintf("Offset\n0x0000 "); 3296 for (i = 0, j = 0; i < 32; i++, j++) { 3297 if (j == 8) { /* Make the offset block */ 3298 j = 0; ++row; 3299 kprintf("\n0x00%x0 ",row); 3300 } 3301 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3302 kprintf("%04x ", eeprom_data); 3303 } 3304 kprintf("\n"); 3305 } 3306 3307 static int 3308 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3309 { 3310 struct emx_softc *sc; 3311 struct ifnet *ifp; 3312 int error, result; 3313 3314 result = -1; 3315 error = sysctl_handle_int(oidp, &result, 0, req); 3316 if (error || !req->newptr) 3317 return (error); 3318 3319 sc = (struct emx_softc *)arg1; 3320 ifp = &sc->arpcom.ac_if; 3321 3322 ifnet_serialize_all(ifp); 3323 3324 if (result == 1) 3325 emx_print_debug_info(sc); 3326 3327 /* 3328 * This value will cause a hex dump of the 3329 * first 32 16-bit words of the EEPROM to 3330 * the screen. 3331 */ 3332 if (result == 2) 3333 emx_print_nvm_info(sc); 3334 3335 ifnet_deserialize_all(ifp); 3336 3337 return (error); 3338 } 3339 3340 static int 3341 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3342 { 3343 int error, result; 3344 3345 result = -1; 3346 error = sysctl_handle_int(oidp, &result, 0, req); 3347 if (error || !req->newptr) 3348 return (error); 3349 3350 if (result == 1) { 3351 struct emx_softc *sc = (struct emx_softc *)arg1; 3352 struct ifnet *ifp = &sc->arpcom.ac_if; 3353 3354 ifnet_serialize_all(ifp); 3355 emx_print_hw_stats(sc); 3356 ifnet_deserialize_all(ifp); 3357 } 3358 return (error); 3359 } 3360 3361 static void 3362 emx_add_sysctl(struct emx_softc *sc) 3363 { 3364 #ifdef EMX_RSS_DEBUG 3365 char rx_pkt[32]; 3366 int i; 3367 #endif 3368 3369 sysctl_ctx_init(&sc->sysctl_ctx); 3370 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3371 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3372 device_get_nameunit(sc->dev), 3373 CTLFLAG_RD, 0, ""); 3374 if (sc->sysctl_tree == NULL) { 3375 device_printf(sc->dev, "can't add sysctl node\n"); 3376 return; 3377 } 3378 3379 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3380 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3381 emx_sysctl_debug_info, "I", "Debug Information"); 3382 3383 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3384 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3385 emx_sysctl_stats, "I", "Statistics"); 3386 3387 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3388 OID_AUTO, "rxd", CTLFLAG_RD, 3389 &sc->rx_data[0].num_rx_desc, 0, NULL); 3390 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3391 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL); 3392 3393 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3394 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3395 sc, 0, emx_sysctl_int_throttle, "I", 3396 "interrupt throttling rate"); 3397 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3398 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3399 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3400 "# segments per TX interrupt"); 3401 3402 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3403 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, 3404 &sc->rx_ring_cnt, 0, "RX ring count"); 3405 3406 #ifdef EMX_RSS_DEBUG 3407 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3408 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3409 0, "RSS debug level"); 3410 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3411 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3412 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3413 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3414 rx_pkt, CTLFLAG_RW, 3415 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3416 } 3417 #endif 3418 } 3419 3420 static int 3421 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3422 { 3423 struct emx_softc *sc = (void *)arg1; 3424 struct ifnet *ifp = &sc->arpcom.ac_if; 3425 int error, throttle; 3426 3427 throttle = sc->int_throttle_ceil; 3428 error = sysctl_handle_int(oidp, &throttle, 0, req); 3429 if (error || req->newptr == NULL) 3430 return error; 3431 if (throttle < 0 || throttle > 1000000000 / 256) 3432 return EINVAL; 3433 3434 if (throttle) { 3435 /* 3436 * Set the interrupt throttling rate in 256ns increments, 3437 * recalculate sysctl value assignment to get exact frequency. 3438 */ 3439 throttle = 1000000000 / 256 / throttle; 3440 3441 /* Upper 16bits of ITR is reserved and should be zero */ 3442 if (throttle & 0xffff0000) 3443 return EINVAL; 3444 } 3445 3446 ifnet_serialize_all(ifp); 3447 3448 if (throttle) 3449 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3450 else 3451 sc->int_throttle_ceil = 0; 3452 3453 if (ifp->if_flags & IFF_RUNNING) 3454 emx_set_itr(sc, throttle); 3455 3456 ifnet_deserialize_all(ifp); 3457 3458 if (bootverbose) { 3459 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3460 sc->int_throttle_ceil); 3461 } 3462 return 0; 3463 } 3464 3465 static int 3466 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3467 { 3468 struct emx_softc *sc = (void *)arg1; 3469 struct ifnet *ifp = &sc->arpcom.ac_if; 3470 int error, segs; 3471 3472 segs = sc->tx_int_nsegs; 3473 error = sysctl_handle_int(oidp, &segs, 0, req); 3474 if (error || req->newptr == NULL) 3475 return error; 3476 if (segs <= 0) 3477 return EINVAL; 3478 3479 ifnet_serialize_all(ifp); 3480 3481 /* 3482 * Don't allow int_tx_nsegs to become: 3483 * o Less the oact_tx_desc 3484 * o Too large that no TX desc will cause TX interrupt to 3485 * be generated (OACTIVE will never recover) 3486 * o Too small that will cause tx_dd[] overflow 3487 */ 3488 if (segs < sc->oact_tx_desc || 3489 segs >= sc->num_tx_desc - sc->oact_tx_desc || 3490 segs < sc->num_tx_desc / EMX_TXDD_SAFE) { 3491 error = EINVAL; 3492 } else { 3493 error = 0; 3494 sc->tx_int_nsegs = segs; 3495 } 3496 3497 ifnet_deserialize_all(ifp); 3498 3499 return error; 3500 } 3501 3502 static int 3503 emx_dma_alloc(struct emx_softc *sc) 3504 { 3505 int error, i; 3506 3507 /* 3508 * Create top level busdma tag 3509 */ 3510 error = bus_dma_tag_create(NULL, 1, 0, 3511 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3512 NULL, NULL, 3513 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3514 0, &sc->parent_dtag); 3515 if (error) { 3516 device_printf(sc->dev, "could not create top level DMA tag\n"); 3517 return error; 3518 } 3519 3520 /* 3521 * Allocate transmit descriptors ring and buffers 3522 */ 3523 error = emx_create_tx_ring(sc); 3524 if (error) { 3525 device_printf(sc->dev, "Could not setup transmit structures\n"); 3526 return error; 3527 } 3528 3529 /* 3530 * Allocate receive descriptors ring and buffers 3531 */ 3532 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3533 error = emx_create_rx_ring(sc, &sc->rx_data[i]); 3534 if (error) { 3535 device_printf(sc->dev, 3536 "Could not setup receive structures\n"); 3537 return error; 3538 } 3539 } 3540 return 0; 3541 } 3542 3543 static void 3544 emx_dma_free(struct emx_softc *sc) 3545 { 3546 int i; 3547 3548 emx_destroy_tx_ring(sc, sc->num_tx_desc); 3549 3550 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3551 emx_destroy_rx_ring(sc, &sc->rx_data[i], 3552 sc->rx_data[i].num_rx_desc); 3553 } 3554 3555 /* Free top level busdma tag */ 3556 if (sc->parent_dtag != NULL) 3557 bus_dma_tag_destroy(sc->parent_dtag); 3558 } 3559 3560 static void 3561 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3562 { 3563 struct emx_softc *sc = ifp->if_softc; 3564 3565 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 3566 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3567 } 3568 3569 static void 3570 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3571 { 3572 struct emx_softc *sc = ifp->if_softc; 3573 3574 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 3575 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3576 } 3577 3578 static int 3579 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3580 { 3581 struct emx_softc *sc = ifp->if_softc; 3582 3583 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 3584 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3585 } 3586 3587 static void 3588 emx_serialize_skipmain(struct emx_softc *sc) 3589 { 3590 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3591 } 3592 3593 static void 3594 emx_deserialize_skipmain(struct emx_softc *sc) 3595 { 3596 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3597 } 3598 3599 #ifdef INVARIANTS 3600 3601 static void 3602 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3603 boolean_t serialized) 3604 { 3605 struct emx_softc *sc = ifp->if_softc; 3606 3607 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3608 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized); 3609 } 3610 3611 #endif /* INVARIANTS */ 3612 3613 #ifdef IFPOLL_ENABLE 3614 3615 static void 3616 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused) 3617 { 3618 struct emx_softc *sc = ifp->if_softc; 3619 uint32_t reg_icr; 3620 3621 ASSERT_SERIALIZED(&sc->main_serialize); 3622 3623 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3624 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3625 callout_stop(&sc->timer); 3626 sc->hw.mac.get_link_status = 1; 3627 emx_update_link_status(sc); 3628 callout_reset(&sc->timer, hz, emx_timer, sc); 3629 } 3630 } 3631 3632 static void 3633 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused) 3634 { 3635 struct emx_softc *sc = ifp->if_softc; 3636 3637 ASSERT_SERIALIZED(&sc->tx_serialize); 3638 3639 emx_txeof(sc); 3640 if (!ifq_is_empty(&ifp->if_snd)) 3641 if_devstart(ifp); 3642 } 3643 3644 static void 3645 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle) 3646 { 3647 struct emx_softc *sc = ifp->if_softc; 3648 struct emx_rxdata *rdata = arg; 3649 3650 ASSERT_SERIALIZED(&rdata->rx_serialize); 3651 3652 emx_rxeof(sc, rdata - sc->rx_data, cycle); 3653 } 3654 3655 static void 3656 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info) 3657 { 3658 struct emx_softc *sc = ifp->if_softc; 3659 3660 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3661 3662 if (info) { 3663 int i; 3664 3665 info->ifpi_status.status_func = emx_qpoll_status; 3666 info->ifpi_status.serializer = &sc->main_serialize; 3667 3668 info->ifpi_tx[0].poll_func = emx_qpoll_tx; 3669 info->ifpi_tx[0].arg = NULL; 3670 info->ifpi_tx[0].serializer = &sc->tx_serialize; 3671 3672 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3673 info->ifpi_rx[i].poll_func = emx_qpoll_rx; 3674 info->ifpi_rx[i].arg = &sc->rx_data[i]; 3675 info->ifpi_rx[i].serializer = 3676 &sc->rx_data[i].rx_serialize; 3677 } 3678 3679 if (ifp->if_flags & IFF_RUNNING) 3680 emx_disable_intr(sc); 3681 } else if (ifp->if_flags & IFF_RUNNING) { 3682 emx_enable_intr(sc); 3683 } 3684 } 3685 3686 #endif /* IFPOLL_ENABLE */ 3687 3688 static void 3689 emx_set_itr(struct emx_softc *sc, uint32_t itr) 3690 { 3691 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 3692 if (sc->hw.mac.type == e1000_82574) { 3693 int i; 3694 3695 /* 3696 * When using MSIX interrupts we need to 3697 * throttle using the EITR register 3698 */ 3699 for (i = 0; i < 4; ++i) 3700 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 3701 } 3702 } 3703 3704 /* 3705 * Disable the L0s, 82574L Errata #20 3706 */ 3707 static void 3708 emx_disable_aspm(struct emx_softc *sc) 3709 { 3710 uint16_t link_cap, link_ctrl, disable; 3711 uint8_t pcie_ptr, reg; 3712 device_t dev = sc->dev; 3713 3714 switch (sc->hw.mac.type) { 3715 case e1000_82571: 3716 case e1000_82572: 3717 case e1000_82573: 3718 /* 3719 * 82573 specification update 3720 * errata #8 disable L0s 3721 * errata #41 disable L1 3722 * 3723 * 82571/82572 specification update 3724 # errata #13 disable L1 3725 * errata #68 disable L0s 3726 */ 3727 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 3728 break; 3729 3730 case e1000_82574: 3731 /* 3732 * 82574 specification update errata #20 3733 * 3734 * There is no need to disable L1 3735 */ 3736 disable = PCIEM_LNKCTL_ASPM_L0S; 3737 break; 3738 3739 default: 3740 return; 3741 } 3742 3743 pcie_ptr = pci_get_pciecap_ptr(dev); 3744 if (pcie_ptr == 0) 3745 return; 3746 3747 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 3748 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 3749 return; 3750 3751 if (bootverbose) 3752 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable); 3753 3754 reg = pcie_ptr + PCIER_LINKCTRL; 3755 link_ctrl = pci_read_config(dev, reg, 2); 3756 link_ctrl &= ~disable; 3757 pci_write_config(dev, reg, link_ctrl, 2); 3758 } 3759 3760 static int 3761 emx_tso_pullup(struct emx_softc *sc, struct mbuf **mp) 3762 { 3763 int iphlen, hoff, thoff, ex = 0; 3764 struct mbuf *m; 3765 struct ip *ip; 3766 3767 m = *mp; 3768 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 3769 3770 iphlen = m->m_pkthdr.csum_iphlen; 3771 thoff = m->m_pkthdr.csum_thlen; 3772 hoff = m->m_pkthdr.csum_lhlen; 3773 3774 KASSERT(iphlen > 0, ("invalid ip hlen")); 3775 KASSERT(thoff > 0, ("invalid tcp hlen")); 3776 KASSERT(hoff > 0, ("invalid ether hlen")); 3777 3778 if (sc->flags & EMX_FLAG_TSO_PULLEX) 3779 ex = 4; 3780 3781 if (m->m_len < hoff + iphlen + thoff + ex) { 3782 m = m_pullup(m, hoff + iphlen + thoff + ex); 3783 if (m == NULL) { 3784 *mp = NULL; 3785 return ENOBUFS; 3786 } 3787 *mp = m; 3788 } 3789 ip = mtodoff(m, struct ip *, hoff); 3790 ip->ip_len = 0; 3791 3792 return 0; 3793 } 3794 3795 static int 3796 emx_tso_setup(struct emx_softc *sc, struct mbuf *mp, 3797 uint32_t *txd_upper, uint32_t *txd_lower) 3798 { 3799 struct e1000_context_desc *TXD; 3800 int hoff, iphlen, thoff, hlen; 3801 int mss, pktlen, curr_txd; 3802 3803 #ifdef EMX_TSO_DEBUG 3804 sc->tso_segments++; 3805 #endif 3806 3807 iphlen = mp->m_pkthdr.csum_iphlen; 3808 thoff = mp->m_pkthdr.csum_thlen; 3809 hoff = mp->m_pkthdr.csum_lhlen; 3810 mss = mp->m_pkthdr.tso_segsz; 3811 pktlen = mp->m_pkthdr.len; 3812 3813 if (sc->csum_flags == CSUM_TSO && 3814 sc->csum_iphlen == iphlen && 3815 sc->csum_lhlen == hoff && 3816 sc->csum_thlen == thoff && 3817 sc->csum_mss == mss && 3818 sc->csum_pktlen == pktlen) { 3819 *txd_upper = sc->csum_txd_upper; 3820 *txd_lower = sc->csum_txd_lower; 3821 #ifdef EMX_TSO_DEBUG 3822 sc->tso_ctx_reused++; 3823 #endif 3824 return 0; 3825 } 3826 hlen = hoff + iphlen + thoff; 3827 3828 /* 3829 * Setup a new TSO context. 3830 */ 3831 3832 curr_txd = sc->next_avail_tx_desc; 3833 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 3834 3835 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3836 E1000_TXD_DTYP_D | /* Data descr type */ 3837 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 3838 3839 /* IP and/or TCP header checksum calculation and insertion. */ 3840 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 3841 3842 /* 3843 * Start offset for header checksum calculation. 3844 * End offset for header checksum calculation. 3845 * Offset of place put the checksum. 3846 */ 3847 TXD->lower_setup.ip_fields.ipcss = hoff; 3848 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 3849 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 3850 3851 /* 3852 * Start offset for payload checksum calculation. 3853 * End offset for payload checksum calculation. 3854 * Offset of place to put the checksum. 3855 */ 3856 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 3857 TXD->upper_setup.tcp_fields.tucse = 0; 3858 TXD->upper_setup.tcp_fields.tucso = 3859 hoff + iphlen + offsetof(struct tcphdr, th_sum); 3860 3861 /* 3862 * Payload size per packet w/o any headers. 3863 * Length of all headers up to payload. 3864 */ 3865 TXD->tcp_seg_setup.fields.mss = htole16(mss); 3866 TXD->tcp_seg_setup.fields.hdr_len = hlen; 3867 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 3868 E1000_TXD_CMD_DEXT | /* Extended descr */ 3869 E1000_TXD_CMD_TSE | /* TSE context */ 3870 E1000_TXD_CMD_IP | /* Do IP csum */ 3871 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3872 (pktlen - hlen)); /* Total len */ 3873 3874 /* Save the information for this TSO context */ 3875 sc->csum_flags = CSUM_TSO; 3876 sc->csum_lhlen = hoff; 3877 sc->csum_iphlen = iphlen; 3878 sc->csum_thlen = thoff; 3879 sc->csum_mss = mss; 3880 sc->csum_pktlen = pktlen; 3881 sc->csum_txd_upper = *txd_upper; 3882 sc->csum_txd_lower = *txd_lower; 3883 3884 if (++curr_txd == sc->num_tx_desc) 3885 curr_txd = 0; 3886 3887 KKASSERT(sc->num_tx_desc_avail > 0); 3888 sc->num_tx_desc_avail--; 3889 3890 sc->next_avail_tx_desc = curr_txd; 3891 return 1; 3892 } 3893