1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_emx.h" 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/endian.h> 73 #include <sys/interrupt.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/malloc.h> 77 #include <sys/mbuf.h> 78 #include <sys/proc.h> 79 #include <sys/rman.h> 80 #include <sys/serialize.h> 81 #include <sys/serialize2.h> 82 #include <sys/socket.h> 83 #include <sys/sockio.h> 84 #include <sys/sysctl.h> 85 #include <sys/systm.h> 86 87 #include <net/bpf.h> 88 #include <net/ethernet.h> 89 #include <net/if.h> 90 #include <net/if_arp.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/ifq_var.h> 94 #include <net/toeplitz.h> 95 #include <net/toeplitz2.h> 96 #include <net/vlan/if_vlan_var.h> 97 #include <net/vlan/if_vlan_ether.h> 98 #include <net/if_poll.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 #include <netinet/udp.h> 105 106 #include <bus/pci/pcivar.h> 107 #include <bus/pci/pcireg.h> 108 109 #include <dev/netif/ig_hal/e1000_api.h> 110 #include <dev/netif/ig_hal/e1000_82571.h> 111 #include <dev/netif/emx/if_emx.h> 112 113 #ifdef EMX_RSS_DEBUG 114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 115 do { \ 116 if (sc->rss_debug >= lvl) \ 117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 118 } while (0) 119 #else /* !EMX_RSS_DEBUG */ 120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 121 #endif /* EMX_RSS_DEBUG */ 122 123 #define EMX_NAME "Intel(R) PRO/1000 " 124 125 #define EMX_DEVICE(id) \ 126 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 127 #define EMX_DEVICE_NULL { 0, 0, NULL } 128 129 static const struct emx_device { 130 uint16_t vid; 131 uint16_t did; 132 const char *desc; 133 } emx_devices[] = { 134 EMX_DEVICE(82571EB_COPPER), 135 EMX_DEVICE(82571EB_FIBER), 136 EMX_DEVICE(82571EB_SERDES), 137 EMX_DEVICE(82571EB_SERDES_DUAL), 138 EMX_DEVICE(82571EB_SERDES_QUAD), 139 EMX_DEVICE(82571EB_QUAD_COPPER), 140 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 141 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 142 EMX_DEVICE(82571EB_QUAD_FIBER), 143 EMX_DEVICE(82571PT_QUAD_COPPER), 144 145 EMX_DEVICE(82572EI_COPPER), 146 EMX_DEVICE(82572EI_FIBER), 147 EMX_DEVICE(82572EI_SERDES), 148 EMX_DEVICE(82572EI), 149 150 EMX_DEVICE(82573E), 151 EMX_DEVICE(82573E_IAMT), 152 EMX_DEVICE(82573L), 153 154 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 155 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 156 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 157 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 158 159 EMX_DEVICE(82574L), 160 EMX_DEVICE(82574LA), 161 162 /* required last entry */ 163 EMX_DEVICE_NULL 164 }; 165 166 static int emx_probe(device_t); 167 static int emx_attach(device_t); 168 static int emx_detach(device_t); 169 static int emx_shutdown(device_t); 170 static int emx_suspend(device_t); 171 static int emx_resume(device_t); 172 173 static void emx_init(void *); 174 static void emx_stop(struct emx_softc *); 175 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 176 static void emx_start(struct ifnet *, struct ifaltq_subque *); 177 #ifdef IFPOLL_ENABLE 178 static void emx_npoll(struct ifnet *, struct ifpoll_info *); 179 static void emx_npoll_status(struct ifnet *); 180 static void emx_npoll_tx(struct ifnet *, void *, int); 181 static void emx_npoll_rx(struct ifnet *, void *, int); 182 #endif 183 static void emx_watchdog(struct ifaltq_subque *); 184 static void emx_media_status(struct ifnet *, struct ifmediareq *); 185 static int emx_media_change(struct ifnet *); 186 static void emx_timer(void *); 187 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 188 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 189 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 190 #ifdef INVARIANTS 191 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 192 boolean_t); 193 #endif 194 195 static void emx_intr(void *); 196 static void emx_intr_mask(void *); 197 static void emx_intr_body(struct emx_softc *, boolean_t); 198 static void emx_rxeof(struct emx_rxdata *, int); 199 static void emx_txeof(struct emx_txdata *); 200 static void emx_tx_collect(struct emx_txdata *); 201 static void emx_tx_purge(struct emx_softc *); 202 static void emx_enable_intr(struct emx_softc *); 203 static void emx_disable_intr(struct emx_softc *); 204 205 static int emx_dma_alloc(struct emx_softc *); 206 static void emx_dma_free(struct emx_softc *); 207 static void emx_init_tx_ring(struct emx_txdata *); 208 static int emx_init_rx_ring(struct emx_rxdata *); 209 static void emx_free_tx_ring(struct emx_txdata *); 210 static void emx_free_rx_ring(struct emx_rxdata *); 211 static int emx_create_tx_ring(struct emx_txdata *); 212 static int emx_create_rx_ring(struct emx_rxdata *); 213 static void emx_destroy_tx_ring(struct emx_txdata *, int); 214 static void emx_destroy_rx_ring(struct emx_rxdata *, int); 215 static int emx_newbuf(struct emx_rxdata *, int, int); 216 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *); 217 static int emx_txcsum(struct emx_txdata *, struct mbuf *, 218 uint32_t *, uint32_t *); 219 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **); 220 static int emx_tso_setup(struct emx_txdata *, struct mbuf *, 221 uint32_t *, uint32_t *); 222 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t); 223 224 static int emx_is_valid_eaddr(const uint8_t *); 225 static int emx_reset(struct emx_softc *); 226 static void emx_setup_ifp(struct emx_softc *); 227 static void emx_init_tx_unit(struct emx_softc *); 228 static void emx_init_rx_unit(struct emx_softc *); 229 static void emx_update_stats(struct emx_softc *); 230 static void emx_set_promisc(struct emx_softc *); 231 static void emx_disable_promisc(struct emx_softc *); 232 static void emx_set_multi(struct emx_softc *); 233 static void emx_update_link_status(struct emx_softc *); 234 static void emx_smartspeed(struct emx_softc *); 235 static void emx_set_itr(struct emx_softc *, uint32_t); 236 static void emx_disable_aspm(struct emx_softc *); 237 238 static void emx_print_debug_info(struct emx_softc *); 239 static void emx_print_nvm_info(struct emx_softc *); 240 static void emx_print_hw_stats(struct emx_softc *); 241 242 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 243 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 244 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 245 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS); 246 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS); 247 #ifdef IFPOLL_ENABLE 248 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 249 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 250 #endif 251 static void emx_add_sysctl(struct emx_softc *); 252 253 static void emx_serialize_skipmain(struct emx_softc *); 254 static void emx_deserialize_skipmain(struct emx_softc *); 255 256 /* Management and WOL Support */ 257 static void emx_get_mgmt(struct emx_softc *); 258 static void emx_rel_mgmt(struct emx_softc *); 259 static void emx_get_hw_control(struct emx_softc *); 260 static void emx_rel_hw_control(struct emx_softc *); 261 static void emx_enable_wol(device_t); 262 263 static device_method_t emx_methods[] = { 264 /* Device interface */ 265 DEVMETHOD(device_probe, emx_probe), 266 DEVMETHOD(device_attach, emx_attach), 267 DEVMETHOD(device_detach, emx_detach), 268 DEVMETHOD(device_shutdown, emx_shutdown), 269 DEVMETHOD(device_suspend, emx_suspend), 270 DEVMETHOD(device_resume, emx_resume), 271 DEVMETHOD_END 272 }; 273 274 static driver_t emx_driver = { 275 "emx", 276 emx_methods, 277 sizeof(struct emx_softc), 278 }; 279 280 static devclass_t emx_devclass; 281 282 DECLARE_DUMMY_MODULE(if_emx); 283 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 284 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 285 286 /* 287 * Tunables 288 */ 289 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 290 static int emx_rxd = EMX_DEFAULT_RXD; 291 static int emx_txd = EMX_DEFAULT_TXD; 292 static int emx_smart_pwr_down = 0; 293 static int emx_rxr = 0; 294 static int emx_txr = 1; 295 296 /* Controls whether promiscuous also shows bad packets */ 297 static int emx_debug_sbp = 0; 298 299 static int emx_82573_workaround = 1; 300 static int emx_msi_enable = 1; 301 302 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 303 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 304 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 305 TUNABLE_INT("hw.emx.txd", &emx_txd); 306 TUNABLE_INT("hw.emx.txr", &emx_txr); 307 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 308 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 309 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 310 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 311 312 /* Global used in WOL setup with multiport cards */ 313 static int emx_global_quad_port_a = 0; 314 315 /* Set this to one to display debug statistics */ 316 static int emx_display_debug_stats = 0; 317 318 #if !defined(KTR_IF_EMX) 319 #define KTR_IF_EMX KTR_ALL 320 #endif 321 KTR_INFO_MASTER(if_emx); 322 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 323 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 324 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 325 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 326 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 327 #define logif(name) KTR_LOG(if_emx_ ## name) 328 329 static __inline void 330 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 331 { 332 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 333 /* DD bit must be cleared */ 334 rxd->rxd_staterr = 0; 335 } 336 337 static __inline void 338 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 339 { 340 /* Ignore Checksum bit is set */ 341 if (staterr & E1000_RXD_STAT_IXSM) 342 return; 343 344 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 345 E1000_RXD_STAT_IPCS) 346 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 347 348 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 349 E1000_RXD_STAT_TCPCS) { 350 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 351 CSUM_PSEUDO_HDR | 352 CSUM_FRAG_NOT_CHECKED; 353 mp->m_pkthdr.csum_data = htons(0xffff); 354 } 355 } 356 357 static __inline struct pktinfo * 358 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 359 uint32_t mrq, uint32_t hash, uint32_t staterr) 360 { 361 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 362 case EMX_RXDMRQ_IPV4_TCP: 363 pi->pi_netisr = NETISR_IP; 364 pi->pi_flags = 0; 365 pi->pi_l3proto = IPPROTO_TCP; 366 break; 367 368 case EMX_RXDMRQ_IPV6_TCP: 369 pi->pi_netisr = NETISR_IPV6; 370 pi->pi_flags = 0; 371 pi->pi_l3proto = IPPROTO_TCP; 372 break; 373 374 case EMX_RXDMRQ_IPV4: 375 if (staterr & E1000_RXD_STAT_IXSM) 376 return NULL; 377 378 if ((staterr & 379 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 380 E1000_RXD_STAT_TCPCS) { 381 pi->pi_netisr = NETISR_IP; 382 pi->pi_flags = 0; 383 pi->pi_l3proto = IPPROTO_UDP; 384 break; 385 } 386 /* FALL THROUGH */ 387 default: 388 return NULL; 389 } 390 391 m->m_flags |= M_HASH; 392 m->m_pkthdr.hash = toeplitz_hash(hash); 393 return pi; 394 } 395 396 static int 397 emx_probe(device_t dev) 398 { 399 const struct emx_device *d; 400 uint16_t vid, did; 401 402 vid = pci_get_vendor(dev); 403 did = pci_get_device(dev); 404 405 for (d = emx_devices; d->desc != NULL; ++d) { 406 if (vid == d->vid && did == d->did) { 407 device_set_desc(dev, d->desc); 408 device_set_async_attach(dev, TRUE); 409 return 0; 410 } 411 } 412 return ENXIO; 413 } 414 415 static int 416 emx_attach(device_t dev) 417 { 418 struct emx_softc *sc = device_get_softc(dev); 419 int error = 0, i, throttle, msi_enable, tx_ring_max; 420 u_int intr_flags; 421 uint16_t eeprom_data, device_id, apme_mask; 422 driver_intr_t *intr_func; 423 #ifdef IFPOLL_ENABLE 424 int offset, offset_def; 425 #endif 426 427 /* 428 * Setup RX rings 429 */ 430 for (i = 0; i < EMX_NRX_RING; ++i) { 431 sc->rx_data[i].sc = sc; 432 sc->rx_data[i].idx = i; 433 } 434 435 /* 436 * Setup TX ring 437 */ 438 for (i = 0; i < EMX_NTX_RING; ++i) { 439 sc->tx_data[i].sc = sc; 440 sc->tx_data[i].idx = i; 441 } 442 443 /* 444 * Initialize serializers 445 */ 446 lwkt_serialize_init(&sc->main_serialize); 447 for (i = 0; i < EMX_NTX_RING; ++i) 448 lwkt_serialize_init(&sc->tx_data[i].tx_serialize); 449 for (i = 0; i < EMX_NRX_RING; ++i) 450 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 451 452 /* 453 * Initialize serializer array 454 */ 455 i = 0; 456 457 KKASSERT(i < EMX_NSERIALIZE); 458 sc->serializes[i++] = &sc->main_serialize; 459 460 KKASSERT(i < EMX_NSERIALIZE); 461 sc->serializes[i++] = &sc->tx_data[0].tx_serialize; 462 KKASSERT(i < EMX_NSERIALIZE); 463 sc->serializes[i++] = &sc->tx_data[1].tx_serialize; 464 465 KKASSERT(i < EMX_NSERIALIZE); 466 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 467 KKASSERT(i < EMX_NSERIALIZE); 468 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 469 470 KKASSERT(i == EMX_NSERIALIZE); 471 472 callout_init_mp(&sc->timer); 473 474 sc->dev = sc->osdep.dev = dev; 475 476 /* 477 * Determine hardware and mac type 478 */ 479 sc->hw.vendor_id = pci_get_vendor(dev); 480 sc->hw.device_id = pci_get_device(dev); 481 sc->hw.revision_id = pci_get_revid(dev); 482 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 483 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 484 485 if (e1000_set_mac_type(&sc->hw)) 486 return ENXIO; 487 488 /* Enable bus mastering */ 489 pci_enable_busmaster(dev); 490 491 /* 492 * Allocate IO memory 493 */ 494 sc->memory_rid = EMX_BAR_MEM; 495 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 496 &sc->memory_rid, RF_ACTIVE); 497 if (sc->memory == NULL) { 498 device_printf(dev, "Unable to allocate bus resource: memory\n"); 499 error = ENXIO; 500 goto fail; 501 } 502 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 503 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 504 505 /* XXX This is quite goofy, it is not actually used */ 506 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 507 508 /* 509 * Don't enable MSI-X on 82574, see: 510 * 82574 specification update errata #15 511 * 512 * Don't enable MSI on 82571/82572, see: 513 * 82571/82572 specification update errata #63 514 */ 515 msi_enable = emx_msi_enable; 516 if (msi_enable && 517 (sc->hw.mac.type == e1000_82571 || 518 sc->hw.mac.type == e1000_82572)) 519 msi_enable = 0; 520 521 /* 522 * Allocate interrupt 523 */ 524 sc->intr_type = pci_alloc_1intr(dev, msi_enable, 525 &sc->intr_rid, &intr_flags); 526 527 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) { 528 int unshared; 529 530 unshared = device_getenv_int(dev, "irq.unshared", 0); 531 if (!unshared) { 532 sc->flags |= EMX_FLAG_SHARED_INTR; 533 if (bootverbose) 534 device_printf(dev, "IRQ shared\n"); 535 } else { 536 intr_flags &= ~RF_SHAREABLE; 537 if (bootverbose) 538 device_printf(dev, "IRQ unshared\n"); 539 } 540 } 541 542 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 543 intr_flags); 544 if (sc->intr_res == NULL) { 545 device_printf(dev, "Unable to allocate bus resource: " 546 "interrupt\n"); 547 error = ENXIO; 548 goto fail; 549 } 550 551 /* Save PCI command register for Shared Code */ 552 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 553 sc->hw.back = &sc->osdep; 554 555 /* Do Shared Code initialization */ 556 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 557 device_printf(dev, "Setup of Shared code failed\n"); 558 error = ENXIO; 559 goto fail; 560 } 561 e1000_get_bus_info(&sc->hw); 562 563 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 564 sc->hw.phy.autoneg_wait_to_complete = FALSE; 565 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 566 567 /* 568 * Interrupt throttle rate 569 */ 570 throttle = device_getenv_int(dev, "int_throttle_ceil", 571 emx_int_throttle_ceil); 572 if (throttle == 0) { 573 sc->int_throttle_ceil = 0; 574 } else { 575 if (throttle < 0) 576 throttle = EMX_DEFAULT_ITR; 577 578 /* Recalculate the tunable value to get the exact frequency. */ 579 throttle = 1000000000 / 256 / throttle; 580 581 /* Upper 16bits of ITR is reserved and should be zero */ 582 if (throttle & 0xffff0000) 583 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 584 585 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 586 } 587 588 e1000_init_script_state_82541(&sc->hw, TRUE); 589 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 590 591 /* Copper options */ 592 if (sc->hw.phy.media_type == e1000_media_type_copper) { 593 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 594 sc->hw.phy.disable_polarity_correction = FALSE; 595 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 596 } 597 598 /* Set the frame limits assuming standard ethernet sized frames. */ 599 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 600 sc->min_frame_size = ETHER_MIN_LEN; 601 602 /* This controls when hardware reports transmit completion status. */ 603 sc->hw.mac.report_tx_early = 1; 604 605 /* Calculate # of RX rings */ 606 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 607 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING); 608 609 /* 610 * Calculate # of TX rings 611 * 612 * NOTE: 613 * Don't enable multiple TX queues on 82574; it always gives 614 * watchdog timeout on TX queue0, when multiple TCP streams are 615 * received. It was originally suspected that the hardware TX 616 * checksum offloading caused this watchdog timeout, since only 617 * TCP ACKs are sent during TCP receiving tests. However, even 618 * if the hardware TX checksum offloading is disable, TX queue0 619 * still will give watchdog. 620 */ 621 tx_ring_max = 1; 622 if (sc->hw.mac.type == e1000_82571 || 623 sc->hw.mac.type == e1000_82572 || 624 sc->hw.mac.type == e1000_80003es2lan) 625 tx_ring_max = EMX_NTX_RING; 626 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr); 627 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max); 628 629 /* Allocate RX/TX rings' busdma(9) stuffs */ 630 error = emx_dma_alloc(sc); 631 if (error) 632 goto fail; 633 634 /* Allocate multicast array memory. */ 635 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 636 M_DEVBUF, M_WAITOK); 637 638 /* Indicate SOL/IDER usage */ 639 if (e1000_check_reset_block(&sc->hw)) { 640 device_printf(dev, 641 "PHY reset is blocked due to SOL/IDER session.\n"); 642 } 643 644 /* 645 * Start from a known state, this is important in reading the 646 * nvm and mac from that. 647 */ 648 e1000_reset_hw(&sc->hw); 649 650 /* Make sure we have a good EEPROM before we read from it */ 651 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 652 /* 653 * Some PCI-E parts fail the first check due to 654 * the link being in sleep state, call it again, 655 * if it fails a second time its a real issue. 656 */ 657 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 658 device_printf(dev, 659 "The EEPROM Checksum Is Not Valid\n"); 660 error = EIO; 661 goto fail; 662 } 663 } 664 665 /* Copy the permanent MAC address out of the EEPROM */ 666 if (e1000_read_mac_addr(&sc->hw) < 0) { 667 device_printf(dev, "EEPROM read error while reading MAC" 668 " address\n"); 669 error = EIO; 670 goto fail; 671 } 672 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 673 device_printf(dev, "Invalid MAC address\n"); 674 error = EIO; 675 goto fail; 676 } 677 678 /* Determine if we have to control management hardware */ 679 if (e1000_enable_mng_pass_thru(&sc->hw)) 680 sc->flags |= EMX_FLAG_HAS_MGMT; 681 682 /* 683 * Setup Wake-on-Lan 684 */ 685 apme_mask = EMX_EEPROM_APME; 686 eeprom_data = 0; 687 switch (sc->hw.mac.type) { 688 case e1000_82573: 689 sc->flags |= EMX_FLAG_HAS_AMT; 690 /* FALL THROUGH */ 691 692 case e1000_82571: 693 case e1000_82572: 694 case e1000_80003es2lan: 695 if (sc->hw.bus.func == 1) { 696 e1000_read_nvm(&sc->hw, 697 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 698 } else { 699 e1000_read_nvm(&sc->hw, 700 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 701 } 702 break; 703 704 default: 705 e1000_read_nvm(&sc->hw, 706 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 707 break; 708 } 709 if (eeprom_data & apme_mask) 710 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 711 712 /* 713 * We have the eeprom settings, now apply the special cases 714 * where the eeprom may be wrong or the board won't support 715 * wake on lan on a particular port 716 */ 717 device_id = pci_get_device(dev); 718 switch (device_id) { 719 case E1000_DEV_ID_82571EB_FIBER: 720 /* 721 * Wake events only supported on port A for dual fiber 722 * regardless of eeprom setting 723 */ 724 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 725 E1000_STATUS_FUNC_1) 726 sc->wol = 0; 727 break; 728 729 case E1000_DEV_ID_82571EB_QUAD_COPPER: 730 case E1000_DEV_ID_82571EB_QUAD_FIBER: 731 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 732 /* if quad port sc, disable WoL on all but port A */ 733 if (emx_global_quad_port_a != 0) 734 sc->wol = 0; 735 /* Reset for multiple quad port adapters */ 736 if (++emx_global_quad_port_a == 4) 737 emx_global_quad_port_a = 0; 738 break; 739 } 740 741 /* XXX disable wol */ 742 sc->wol = 0; 743 744 #ifdef IFPOLL_ENABLE 745 /* 746 * NPOLLING RX CPU offset 747 */ 748 if (sc->rx_ring_cnt == ncpus2) { 749 offset = 0; 750 } else { 751 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2; 752 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 753 if (offset >= ncpus2 || 754 offset % sc->rx_ring_cnt != 0) { 755 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 756 offset, offset_def); 757 offset = offset_def; 758 } 759 } 760 sc->rx_npoll_off = offset; 761 762 /* 763 * NPOLLING TX CPU offset 764 */ 765 if (sc->tx_ring_cnt == ncpus2) { 766 offset = 0; 767 } else { 768 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2; 769 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 770 if (offset >= ncpus2 || 771 offset % sc->tx_ring_cnt != 0) { 772 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 773 offset, offset_def); 774 offset = offset_def; 775 } 776 } 777 sc->tx_npoll_off = offset; 778 #endif 779 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE); 780 781 /* Setup OS specific network interface */ 782 emx_setup_ifp(sc); 783 784 /* Add sysctl tree, must after em_setup_ifp() */ 785 emx_add_sysctl(sc); 786 787 /* Reset the hardware */ 788 error = emx_reset(sc); 789 if (error) { 790 device_printf(dev, "Unable to reset the hardware\n"); 791 goto fail; 792 } 793 794 /* Initialize statistics */ 795 emx_update_stats(sc); 796 797 sc->hw.mac.get_link_status = 1; 798 emx_update_link_status(sc); 799 800 /* Non-AMT based hardware can now take control from firmware */ 801 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 802 EMX_FLAG_HAS_MGMT) 803 emx_get_hw_control(sc); 804 805 /* 806 * Missing Interrupt Following ICR read: 807 * 808 * 82571/82572 specification update errata #76 809 * 82573 specification update errata #31 810 * 82574 specification update errata #12 811 */ 812 intr_func = emx_intr; 813 if ((sc->flags & EMX_FLAG_SHARED_INTR) && 814 (sc->hw.mac.type == e1000_82571 || 815 sc->hw.mac.type == e1000_82572 || 816 sc->hw.mac.type == e1000_82573 || 817 sc->hw.mac.type == e1000_82574)) 818 intr_func = emx_intr_mask; 819 820 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc, 821 &sc->intr_tag, &sc->main_serialize); 822 if (error) { 823 device_printf(dev, "Failed to register interrupt handler"); 824 ether_ifdetach(&sc->arpcom.ac_if); 825 goto fail; 826 } 827 return (0); 828 fail: 829 emx_detach(dev); 830 return (error); 831 } 832 833 static int 834 emx_detach(device_t dev) 835 { 836 struct emx_softc *sc = device_get_softc(dev); 837 838 if (device_is_attached(dev)) { 839 struct ifnet *ifp = &sc->arpcom.ac_if; 840 841 ifnet_serialize_all(ifp); 842 843 emx_stop(sc); 844 845 e1000_phy_hw_reset(&sc->hw); 846 847 emx_rel_mgmt(sc); 848 emx_rel_hw_control(sc); 849 850 if (sc->wol) { 851 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 852 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 853 emx_enable_wol(dev); 854 } 855 856 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 857 858 ifnet_deserialize_all(ifp); 859 860 ether_ifdetach(ifp); 861 } else if (sc->memory != NULL) { 862 emx_rel_hw_control(sc); 863 } 864 bus_generic_detach(dev); 865 866 if (sc->intr_res != NULL) { 867 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 868 sc->intr_res); 869 } 870 871 if (sc->intr_type == PCI_INTR_TYPE_MSI) 872 pci_release_msi(dev); 873 874 if (sc->memory != NULL) { 875 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 876 sc->memory); 877 } 878 879 emx_dma_free(sc); 880 881 /* Free sysctl tree */ 882 if (sc->sysctl_tree != NULL) 883 sysctl_ctx_free(&sc->sysctl_ctx); 884 885 if (sc->mta != NULL) 886 kfree(sc->mta, M_DEVBUF); 887 888 return (0); 889 } 890 891 static int 892 emx_shutdown(device_t dev) 893 { 894 return emx_suspend(dev); 895 } 896 897 static int 898 emx_suspend(device_t dev) 899 { 900 struct emx_softc *sc = device_get_softc(dev); 901 struct ifnet *ifp = &sc->arpcom.ac_if; 902 903 ifnet_serialize_all(ifp); 904 905 emx_stop(sc); 906 907 emx_rel_mgmt(sc); 908 emx_rel_hw_control(sc); 909 910 if (sc->wol) { 911 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 912 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 913 emx_enable_wol(dev); 914 } 915 916 ifnet_deserialize_all(ifp); 917 918 return bus_generic_suspend(dev); 919 } 920 921 static int 922 emx_resume(device_t dev) 923 { 924 struct emx_softc *sc = device_get_softc(dev); 925 struct ifnet *ifp = &sc->arpcom.ac_if; 926 int i; 927 928 ifnet_serialize_all(ifp); 929 930 emx_init(sc); 931 emx_get_mgmt(sc); 932 for (i = 0; i < sc->tx_ring_inuse; ++i) 933 ifsq_devstart_sched(sc->tx_data[i].ifsq); 934 935 ifnet_deserialize_all(ifp); 936 937 return bus_generic_resume(dev); 938 } 939 940 static void 941 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 942 { 943 struct emx_softc *sc = ifp->if_softc; 944 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 945 struct mbuf *m_head; 946 int idx = -1, nsegs = 0; 947 948 KKASSERT(tdata->ifsq == ifsq); 949 ASSERT_SERIALIZED(&tdata->tx_serialize); 950 951 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq)) 952 return; 953 954 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) { 955 ifsq_purge(ifsq); 956 return; 957 } 958 959 while (!ifsq_is_empty(ifsq)) { 960 /* Now do we at least have a minimal? */ 961 if (EMX_IS_OACTIVE(tdata)) { 962 emx_tx_collect(tdata); 963 if (EMX_IS_OACTIVE(tdata)) { 964 ifsq_set_oactive(ifsq); 965 break; 966 } 967 } 968 969 logif(pkt_txqueue); 970 m_head = ifsq_dequeue(ifsq, NULL); 971 if (m_head == NULL) 972 break; 973 974 if (emx_encap(tdata, &m_head, &nsegs, &idx)) { 975 IFNET_STAT_INC(ifp, oerrors, 1); 976 emx_tx_collect(tdata); 977 continue; 978 } 979 980 if (nsegs >= tdata->tx_wreg_nsegs) { 981 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 982 nsegs = 0; 983 idx = -1; 984 } 985 986 /* Send a copy of the frame to the BPF listener */ 987 ETHER_BPF_MTAP(ifp, m_head); 988 989 /* Set timeout in case hardware has problems transmitting. */ 990 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 991 } 992 if (idx >= 0) 993 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 994 } 995 996 static int 997 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 998 { 999 struct emx_softc *sc = ifp->if_softc; 1000 struct ifreq *ifr = (struct ifreq *)data; 1001 uint16_t eeprom_data = 0; 1002 int max_frame_size, mask, reinit; 1003 int error = 0; 1004 1005 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1006 1007 switch (command) { 1008 case SIOCSIFMTU: 1009 switch (sc->hw.mac.type) { 1010 case e1000_82573: 1011 /* 1012 * 82573 only supports jumbo frames 1013 * if ASPM is disabled. 1014 */ 1015 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 1016 &eeprom_data); 1017 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1018 max_frame_size = ETHER_MAX_LEN; 1019 break; 1020 } 1021 /* FALL THROUGH */ 1022 1023 /* Limit Jumbo Frame size */ 1024 case e1000_82571: 1025 case e1000_82572: 1026 case e1000_82574: 1027 case e1000_80003es2lan: 1028 max_frame_size = 9234; 1029 break; 1030 1031 default: 1032 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1033 break; 1034 } 1035 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1036 ETHER_CRC_LEN) { 1037 error = EINVAL; 1038 break; 1039 } 1040 1041 ifp->if_mtu = ifr->ifr_mtu; 1042 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 1043 ETHER_CRC_LEN; 1044 1045 if (ifp->if_flags & IFF_RUNNING) 1046 emx_init(sc); 1047 break; 1048 1049 case SIOCSIFFLAGS: 1050 if (ifp->if_flags & IFF_UP) { 1051 if ((ifp->if_flags & IFF_RUNNING)) { 1052 if ((ifp->if_flags ^ sc->if_flags) & 1053 (IFF_PROMISC | IFF_ALLMULTI)) { 1054 emx_disable_promisc(sc); 1055 emx_set_promisc(sc); 1056 } 1057 } else { 1058 emx_init(sc); 1059 } 1060 } else if (ifp->if_flags & IFF_RUNNING) { 1061 emx_stop(sc); 1062 } 1063 sc->if_flags = ifp->if_flags; 1064 break; 1065 1066 case SIOCADDMULTI: 1067 case SIOCDELMULTI: 1068 if (ifp->if_flags & IFF_RUNNING) { 1069 emx_disable_intr(sc); 1070 emx_set_multi(sc); 1071 #ifdef IFPOLL_ENABLE 1072 if (!(ifp->if_flags & IFF_NPOLLING)) 1073 #endif 1074 emx_enable_intr(sc); 1075 } 1076 break; 1077 1078 case SIOCSIFMEDIA: 1079 /* Check SOL/IDER usage */ 1080 if (e1000_check_reset_block(&sc->hw)) { 1081 device_printf(sc->dev, "Media change is" 1082 " blocked due to SOL/IDER session.\n"); 1083 break; 1084 } 1085 /* FALL THROUGH */ 1086 1087 case SIOCGIFMEDIA: 1088 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 1089 break; 1090 1091 case SIOCSIFCAP: 1092 reinit = 0; 1093 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1094 if (mask & IFCAP_RXCSUM) { 1095 ifp->if_capenable ^= IFCAP_RXCSUM; 1096 reinit = 1; 1097 } 1098 if (mask & IFCAP_VLAN_HWTAGGING) { 1099 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1100 reinit = 1; 1101 } 1102 if (mask & IFCAP_TXCSUM) { 1103 ifp->if_capenable ^= IFCAP_TXCSUM; 1104 if (ifp->if_capenable & IFCAP_TXCSUM) 1105 ifp->if_hwassist |= EMX_CSUM_FEATURES; 1106 else 1107 ifp->if_hwassist &= ~EMX_CSUM_FEATURES; 1108 } 1109 if (mask & IFCAP_TSO) { 1110 ifp->if_capenable ^= IFCAP_TSO; 1111 if (ifp->if_capenable & IFCAP_TSO) 1112 ifp->if_hwassist |= CSUM_TSO; 1113 else 1114 ifp->if_hwassist &= ~CSUM_TSO; 1115 } 1116 if (mask & IFCAP_RSS) 1117 ifp->if_capenable ^= IFCAP_RSS; 1118 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1119 emx_init(sc); 1120 break; 1121 1122 default: 1123 error = ether_ioctl(ifp, command, data); 1124 break; 1125 } 1126 return (error); 1127 } 1128 1129 static void 1130 emx_watchdog(struct ifaltq_subque *ifsq) 1131 { 1132 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 1133 struct ifnet *ifp = ifsq_get_ifp(ifsq); 1134 struct emx_softc *sc = ifp->if_softc; 1135 int i; 1136 1137 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1138 1139 /* 1140 * The timer is set to 5 every time start queues a packet. 1141 * Then txeof keeps resetting it as long as it cleans at 1142 * least one descriptor. 1143 * Finally, anytime all descriptors are clean the timer is 1144 * set to 0. 1145 */ 1146 1147 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) == 1148 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) { 1149 /* 1150 * If we reach here, all TX jobs are completed and 1151 * the TX engine should have been idled for some time. 1152 * We don't need to call ifsq_devstart_sched() here. 1153 */ 1154 ifsq_clr_oactive(ifsq); 1155 tdata->tx_watchdog.wd_timer = 0; 1156 return; 1157 } 1158 1159 /* 1160 * If we are in this routine because of pause frames, then 1161 * don't reset the hardware. 1162 */ 1163 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1164 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 1165 return; 1166 } 1167 1168 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx); 1169 1170 IFNET_STAT_INC(ifp, oerrors, 1); 1171 1172 emx_init(sc); 1173 for (i = 0; i < sc->tx_ring_inuse; ++i) 1174 ifsq_devstart_sched(sc->tx_data[i].ifsq); 1175 } 1176 1177 static void 1178 emx_init(void *xsc) 1179 { 1180 struct emx_softc *sc = xsc; 1181 struct ifnet *ifp = &sc->arpcom.ac_if; 1182 device_t dev = sc->dev; 1183 boolean_t polling; 1184 int i; 1185 1186 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1187 1188 emx_stop(sc); 1189 1190 /* Get the latest mac address, User can use a LAA */ 1191 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1192 1193 /* Put the address into the Receive Address Array */ 1194 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1195 1196 /* 1197 * With the 82571 sc, RAR[0] may be overwritten 1198 * when the other port is reset, we make a duplicate 1199 * in RAR[14] for that eventuality, this assures 1200 * the interface continues to function. 1201 */ 1202 if (sc->hw.mac.type == e1000_82571) { 1203 e1000_set_laa_state_82571(&sc->hw, TRUE); 1204 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1205 E1000_RAR_ENTRIES - 1); 1206 } 1207 1208 /* Initialize the hardware */ 1209 if (emx_reset(sc)) { 1210 device_printf(dev, "Unable to reset the hardware\n"); 1211 /* XXX emx_stop()? */ 1212 return; 1213 } 1214 emx_update_link_status(sc); 1215 1216 /* Setup VLAN support, basic and offload if available */ 1217 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1218 1219 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1220 uint32_t ctrl; 1221 1222 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1223 ctrl |= E1000_CTRL_VME; 1224 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1225 } 1226 1227 /* Configure for OS presence */ 1228 emx_get_mgmt(sc); 1229 1230 polling = FALSE; 1231 #ifdef IFPOLL_ENABLE 1232 if (ifp->if_flags & IFF_NPOLLING) 1233 polling = TRUE; 1234 #endif 1235 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling); 1236 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1); 1237 1238 /* Prepare transmit descriptors and buffers */ 1239 for (i = 0; i < sc->tx_ring_inuse; ++i) 1240 emx_init_tx_ring(&sc->tx_data[i]); 1241 emx_init_tx_unit(sc); 1242 1243 /* Setup Multicast table */ 1244 emx_set_multi(sc); 1245 1246 /* Prepare receive descriptors and buffers */ 1247 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1248 if (emx_init_rx_ring(&sc->rx_data[i])) { 1249 device_printf(dev, 1250 "Could not setup receive structures\n"); 1251 emx_stop(sc); 1252 return; 1253 } 1254 } 1255 emx_init_rx_unit(sc); 1256 1257 /* Don't lose promiscuous settings */ 1258 emx_set_promisc(sc); 1259 1260 ifp->if_flags |= IFF_RUNNING; 1261 for (i = 0; i < sc->tx_ring_inuse; ++i) { 1262 ifsq_clr_oactive(sc->tx_data[i].ifsq); 1263 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog); 1264 } 1265 1266 callout_reset(&sc->timer, hz, emx_timer, sc); 1267 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1268 1269 /* MSI/X configuration for 82574 */ 1270 if (sc->hw.mac.type == e1000_82574) { 1271 int tmp; 1272 1273 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1274 tmp |= E1000_CTRL_EXT_PBA_CLR; 1275 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1276 /* 1277 * XXX MSIX 1278 * Set the IVAR - interrupt vector routing. 1279 * Each nibble represents a vector, high bit 1280 * is enable, other 3 bits are the MSIX table 1281 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1282 * Link (other) to 2, hence the magic number. 1283 */ 1284 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1285 } 1286 1287 /* 1288 * Only enable interrupts if we are not polling, make sure 1289 * they are off otherwise. 1290 */ 1291 if (polling) 1292 emx_disable_intr(sc); 1293 else 1294 emx_enable_intr(sc); 1295 1296 /* AMT based hardware can now take control from firmware */ 1297 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 1298 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) 1299 emx_get_hw_control(sc); 1300 } 1301 1302 static void 1303 emx_intr(void *xsc) 1304 { 1305 emx_intr_body(xsc, TRUE); 1306 } 1307 1308 static void 1309 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted) 1310 { 1311 struct ifnet *ifp = &sc->arpcom.ac_if; 1312 uint32_t reg_icr; 1313 1314 logif(intr_beg); 1315 ASSERT_SERIALIZED(&sc->main_serialize); 1316 1317 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1318 1319 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1320 logif(intr_end); 1321 return; 1322 } 1323 1324 /* 1325 * XXX: some laptops trigger several spurious interrupts 1326 * on emx(4) when in the resume cycle. The ICR register 1327 * reports all-ones value in this case. Processing such 1328 * interrupts would lead to a freeze. I don't know why. 1329 */ 1330 if (reg_icr == 0xffffffff) { 1331 logif(intr_end); 1332 return; 1333 } 1334 1335 if (ifp->if_flags & IFF_RUNNING) { 1336 if (reg_icr & 1337 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1338 int i; 1339 1340 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1341 lwkt_serialize_enter( 1342 &sc->rx_data[i].rx_serialize); 1343 emx_rxeof(&sc->rx_data[i], -1); 1344 lwkt_serialize_exit( 1345 &sc->rx_data[i].rx_serialize); 1346 } 1347 } 1348 if (reg_icr & E1000_ICR_TXDW) { 1349 struct emx_txdata *tdata = &sc->tx_data[0]; 1350 1351 lwkt_serialize_enter(&tdata->tx_serialize); 1352 emx_txeof(tdata); 1353 if (!ifsq_is_empty(tdata->ifsq)) 1354 ifsq_devstart(tdata->ifsq); 1355 lwkt_serialize_exit(&tdata->tx_serialize); 1356 } 1357 } 1358 1359 /* Link status change */ 1360 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1361 emx_serialize_skipmain(sc); 1362 1363 callout_stop(&sc->timer); 1364 sc->hw.mac.get_link_status = 1; 1365 emx_update_link_status(sc); 1366 1367 /* Deal with TX cruft when link lost */ 1368 emx_tx_purge(sc); 1369 1370 callout_reset(&sc->timer, hz, emx_timer, sc); 1371 1372 emx_deserialize_skipmain(sc); 1373 } 1374 1375 if (reg_icr & E1000_ICR_RXO) 1376 sc->rx_overruns++; 1377 1378 logif(intr_end); 1379 } 1380 1381 static void 1382 emx_intr_mask(void *xsc) 1383 { 1384 struct emx_softc *sc = xsc; 1385 1386 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 1387 /* 1388 * NOTE: 1389 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1390 * so don't check it. 1391 */ 1392 emx_intr_body(sc, FALSE); 1393 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 1394 } 1395 1396 static void 1397 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1398 { 1399 struct emx_softc *sc = ifp->if_softc; 1400 1401 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1402 1403 emx_update_link_status(sc); 1404 1405 ifmr->ifm_status = IFM_AVALID; 1406 ifmr->ifm_active = IFM_ETHER; 1407 1408 if (!sc->link_active) 1409 return; 1410 1411 ifmr->ifm_status |= IFM_ACTIVE; 1412 1413 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1414 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1415 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1416 } else { 1417 switch (sc->link_speed) { 1418 case 10: 1419 ifmr->ifm_active |= IFM_10_T; 1420 break; 1421 case 100: 1422 ifmr->ifm_active |= IFM_100_TX; 1423 break; 1424 1425 case 1000: 1426 ifmr->ifm_active |= IFM_1000_T; 1427 break; 1428 } 1429 if (sc->link_duplex == FULL_DUPLEX) 1430 ifmr->ifm_active |= IFM_FDX; 1431 else 1432 ifmr->ifm_active |= IFM_HDX; 1433 } 1434 } 1435 1436 static int 1437 emx_media_change(struct ifnet *ifp) 1438 { 1439 struct emx_softc *sc = ifp->if_softc; 1440 struct ifmedia *ifm = &sc->media; 1441 1442 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1443 1444 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1445 return (EINVAL); 1446 1447 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1448 case IFM_AUTO: 1449 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1450 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1451 break; 1452 1453 case IFM_1000_LX: 1454 case IFM_1000_SX: 1455 case IFM_1000_T: 1456 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1457 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1458 break; 1459 1460 case IFM_100_TX: 1461 sc->hw.mac.autoneg = FALSE; 1462 sc->hw.phy.autoneg_advertised = 0; 1463 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1464 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1465 else 1466 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1467 break; 1468 1469 case IFM_10_T: 1470 sc->hw.mac.autoneg = FALSE; 1471 sc->hw.phy.autoneg_advertised = 0; 1472 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1473 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1474 else 1475 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1476 break; 1477 1478 default: 1479 if_printf(ifp, "Unsupported media type\n"); 1480 break; 1481 } 1482 1483 emx_init(sc); 1484 1485 return (0); 1486 } 1487 1488 static int 1489 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp, 1490 int *segs_used, int *idx) 1491 { 1492 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1493 bus_dmamap_t map; 1494 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1495 struct e1000_tx_desc *ctxd = NULL; 1496 struct mbuf *m_head = *m_headp; 1497 uint32_t txd_upper, txd_lower, cmd = 0; 1498 int maxsegs, nsegs, i, j, first, last = 0, error; 1499 1500 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1501 error = emx_tso_pullup(tdata, m_headp); 1502 if (error) 1503 return error; 1504 m_head = *m_headp; 1505 } 1506 1507 txd_upper = txd_lower = 0; 1508 1509 /* 1510 * Capture the first descriptor index, this descriptor 1511 * will have the index of the EOP which is the only one 1512 * that now gets a DONE bit writeback. 1513 */ 1514 first = tdata->next_avail_tx_desc; 1515 tx_buffer = &tdata->tx_buf[first]; 1516 tx_buffer_mapped = tx_buffer; 1517 map = tx_buffer->map; 1518 1519 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED; 1520 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc")); 1521 if (maxsegs > EMX_MAX_SCATTER) 1522 maxsegs = EMX_MAX_SCATTER; 1523 1524 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp, 1525 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1526 if (error) { 1527 m_freem(*m_headp); 1528 *m_headp = NULL; 1529 return error; 1530 } 1531 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE); 1532 1533 m_head = *m_headp; 1534 tdata->tx_nsegs += nsegs; 1535 *segs_used += nsegs; 1536 1537 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1538 /* TSO will consume one TX desc */ 1539 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower); 1540 tdata->tx_nsegs += i; 1541 *segs_used += i; 1542 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1543 /* TX csum offloading will consume one TX desc */ 1544 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower); 1545 tdata->tx_nsegs += i; 1546 *segs_used += i; 1547 } 1548 i = tdata->next_avail_tx_desc; 1549 1550 /* Set up our transmit descriptors */ 1551 for (j = 0; j < nsegs; j++) { 1552 tx_buffer = &tdata->tx_buf[i]; 1553 ctxd = &tdata->tx_desc_base[i]; 1554 1555 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1556 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1557 txd_lower | segs[j].ds_len); 1558 ctxd->upper.data = htole32(txd_upper); 1559 1560 last = i; 1561 if (++i == tdata->num_tx_desc) 1562 i = 0; 1563 } 1564 1565 tdata->next_avail_tx_desc = i; 1566 1567 KKASSERT(tdata->num_tx_desc_avail > nsegs); 1568 tdata->num_tx_desc_avail -= nsegs; 1569 1570 /* Handle VLAN tag */ 1571 if (m_head->m_flags & M_VLANTAG) { 1572 /* Set the vlan id. */ 1573 ctxd->upper.fields.special = 1574 htole16(m_head->m_pkthdr.ether_vlantag); 1575 1576 /* Tell hardware to add tag */ 1577 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1578 } 1579 1580 tx_buffer->m_head = m_head; 1581 tx_buffer_mapped->map = tx_buffer->map; 1582 tx_buffer->map = map; 1583 1584 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) { 1585 tdata->tx_nsegs = 0; 1586 1587 /* 1588 * Report Status (RS) is turned on 1589 * every tx_intr_nsegs descriptors. 1590 */ 1591 cmd = E1000_TXD_CMD_RS; 1592 1593 /* 1594 * Keep track of the descriptor, which will 1595 * be written back by hardware. 1596 */ 1597 tdata->tx_dd[tdata->tx_dd_tail] = last; 1598 EMX_INC_TXDD_IDX(tdata->tx_dd_tail); 1599 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head); 1600 } 1601 1602 /* 1603 * Last Descriptor of Packet needs End Of Packet (EOP) 1604 */ 1605 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1606 1607 /* 1608 * Defer TDT updating, until enough descriptors are setup 1609 */ 1610 *idx = i; 1611 1612 #ifdef EMX_TSS_DEBUG 1613 tdata->tx_pkts++; 1614 #endif 1615 1616 return (0); 1617 } 1618 1619 static void 1620 emx_set_promisc(struct emx_softc *sc) 1621 { 1622 struct ifnet *ifp = &sc->arpcom.ac_if; 1623 uint32_t reg_rctl; 1624 1625 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1626 1627 if (ifp->if_flags & IFF_PROMISC) { 1628 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1629 /* Turn this on if you want to see bad packets */ 1630 if (emx_debug_sbp) 1631 reg_rctl |= E1000_RCTL_SBP; 1632 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1633 } else if (ifp->if_flags & IFF_ALLMULTI) { 1634 reg_rctl |= E1000_RCTL_MPE; 1635 reg_rctl &= ~E1000_RCTL_UPE; 1636 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1637 } 1638 } 1639 1640 static void 1641 emx_disable_promisc(struct emx_softc *sc) 1642 { 1643 uint32_t reg_rctl; 1644 1645 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1646 1647 reg_rctl &= ~E1000_RCTL_UPE; 1648 reg_rctl &= ~E1000_RCTL_MPE; 1649 reg_rctl &= ~E1000_RCTL_SBP; 1650 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1651 } 1652 1653 static void 1654 emx_set_multi(struct emx_softc *sc) 1655 { 1656 struct ifnet *ifp = &sc->arpcom.ac_if; 1657 struct ifmultiaddr *ifma; 1658 uint32_t reg_rctl = 0; 1659 uint8_t *mta; 1660 int mcnt = 0; 1661 1662 mta = sc->mta; 1663 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1664 1665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1666 if (ifma->ifma_addr->sa_family != AF_LINK) 1667 continue; 1668 1669 if (mcnt == EMX_MCAST_ADDR_MAX) 1670 break; 1671 1672 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1673 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1674 mcnt++; 1675 } 1676 1677 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1678 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1679 reg_rctl |= E1000_RCTL_MPE; 1680 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1681 } else { 1682 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1683 } 1684 } 1685 1686 /* 1687 * This routine checks for link status and updates statistics. 1688 */ 1689 static void 1690 emx_timer(void *xsc) 1691 { 1692 struct emx_softc *sc = xsc; 1693 struct ifnet *ifp = &sc->arpcom.ac_if; 1694 1695 lwkt_serialize_enter(&sc->main_serialize); 1696 1697 emx_update_link_status(sc); 1698 emx_update_stats(sc); 1699 1700 /* Reset LAA into RAR[0] on 82571 */ 1701 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1702 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1703 1704 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1705 emx_print_hw_stats(sc); 1706 1707 emx_smartspeed(sc); 1708 1709 callout_reset(&sc->timer, hz, emx_timer, sc); 1710 1711 lwkt_serialize_exit(&sc->main_serialize); 1712 } 1713 1714 static void 1715 emx_update_link_status(struct emx_softc *sc) 1716 { 1717 struct e1000_hw *hw = &sc->hw; 1718 struct ifnet *ifp = &sc->arpcom.ac_if; 1719 device_t dev = sc->dev; 1720 uint32_t link_check = 0; 1721 1722 /* Get the cached link value or read phy for real */ 1723 switch (hw->phy.media_type) { 1724 case e1000_media_type_copper: 1725 if (hw->mac.get_link_status) { 1726 /* Do the work to read phy */ 1727 e1000_check_for_link(hw); 1728 link_check = !hw->mac.get_link_status; 1729 if (link_check) /* ESB2 fix */ 1730 e1000_cfg_on_link_up(hw); 1731 } else { 1732 link_check = TRUE; 1733 } 1734 break; 1735 1736 case e1000_media_type_fiber: 1737 e1000_check_for_link(hw); 1738 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1739 break; 1740 1741 case e1000_media_type_internal_serdes: 1742 e1000_check_for_link(hw); 1743 link_check = sc->hw.mac.serdes_has_link; 1744 break; 1745 1746 case e1000_media_type_unknown: 1747 default: 1748 break; 1749 } 1750 1751 /* Now check for a transition */ 1752 if (link_check && sc->link_active == 0) { 1753 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1754 &sc->link_duplex); 1755 1756 /* 1757 * Check if we should enable/disable SPEED_MODE bit on 1758 * 82571EB/82572EI 1759 */ 1760 if (sc->link_speed != SPEED_1000 && 1761 (hw->mac.type == e1000_82571 || 1762 hw->mac.type == e1000_82572)) { 1763 int tarc0; 1764 1765 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1766 tarc0 &= ~EMX_TARC_SPEED_MODE; 1767 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1768 } 1769 if (bootverbose) { 1770 device_printf(dev, "Link is up %d Mbps %s\n", 1771 sc->link_speed, 1772 ((sc->link_duplex == FULL_DUPLEX) ? 1773 "Full Duplex" : "Half Duplex")); 1774 } 1775 sc->link_active = 1; 1776 sc->smartspeed = 0; 1777 ifp->if_baudrate = sc->link_speed * 1000000; 1778 ifp->if_link_state = LINK_STATE_UP; 1779 if_link_state_change(ifp); 1780 } else if (!link_check && sc->link_active == 1) { 1781 ifp->if_baudrate = sc->link_speed = 0; 1782 sc->link_duplex = 0; 1783 if (bootverbose) 1784 device_printf(dev, "Link is Down\n"); 1785 sc->link_active = 0; 1786 ifp->if_link_state = LINK_STATE_DOWN; 1787 if_link_state_change(ifp); 1788 } 1789 } 1790 1791 static void 1792 emx_stop(struct emx_softc *sc) 1793 { 1794 struct ifnet *ifp = &sc->arpcom.ac_if; 1795 int i; 1796 1797 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1798 1799 emx_disable_intr(sc); 1800 1801 callout_stop(&sc->timer); 1802 1803 ifp->if_flags &= ~IFF_RUNNING; 1804 for (i = 0; i < sc->tx_ring_cnt; ++i) { 1805 struct emx_txdata *tdata = &sc->tx_data[i]; 1806 1807 ifsq_clr_oactive(tdata->ifsq); 1808 ifsq_watchdog_stop(&tdata->tx_watchdog); 1809 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED; 1810 } 1811 1812 /* 1813 * Disable multiple receive queues. 1814 * 1815 * NOTE: 1816 * We should disable multiple receive queues before 1817 * resetting the hardware. 1818 */ 1819 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1820 1821 e1000_reset_hw(&sc->hw); 1822 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1823 1824 for (i = 0; i < sc->tx_ring_cnt; ++i) 1825 emx_free_tx_ring(&sc->tx_data[i]); 1826 for (i = 0; i < sc->rx_ring_cnt; ++i) 1827 emx_free_rx_ring(&sc->rx_data[i]); 1828 } 1829 1830 static int 1831 emx_reset(struct emx_softc *sc) 1832 { 1833 device_t dev = sc->dev; 1834 uint16_t rx_buffer_size; 1835 uint32_t pba; 1836 1837 /* Set up smart power down as default off on newer adapters. */ 1838 if (!emx_smart_pwr_down && 1839 (sc->hw.mac.type == e1000_82571 || 1840 sc->hw.mac.type == e1000_82572)) { 1841 uint16_t phy_tmp = 0; 1842 1843 /* Speed up time to link by disabling smart power down. */ 1844 e1000_read_phy_reg(&sc->hw, 1845 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1846 phy_tmp &= ~IGP02E1000_PM_SPD; 1847 e1000_write_phy_reg(&sc->hw, 1848 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1849 } 1850 1851 /* 1852 * Packet Buffer Allocation (PBA) 1853 * Writing PBA sets the receive portion of the buffer 1854 * the remainder is used for the transmit buffer. 1855 */ 1856 switch (sc->hw.mac.type) { 1857 /* Total Packet Buffer on these is 48K */ 1858 case e1000_82571: 1859 case e1000_82572: 1860 case e1000_80003es2lan: 1861 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1862 break; 1863 1864 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1865 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1866 break; 1867 1868 case e1000_82574: 1869 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1870 break; 1871 1872 default: 1873 /* Devices before 82547 had a Packet Buffer of 64K. */ 1874 if (sc->max_frame_size > 8192) 1875 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1876 else 1877 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1878 } 1879 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1880 1881 /* 1882 * These parameters control the automatic generation (Tx) and 1883 * response (Rx) to Ethernet PAUSE frames. 1884 * - High water mark should allow for at least two frames to be 1885 * received after sending an XOFF. 1886 * - Low water mark works best when it is very near the high water mark. 1887 * This allows the receiver to restart by sending XON when it has 1888 * drained a bit. Here we use an arbitary value of 1500 which will 1889 * restart after one full frame is pulled from the buffer. There 1890 * could be several smaller frames in the buffer and if so they will 1891 * not trigger the XON until their total number reduces the buffer 1892 * by 1500. 1893 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1894 */ 1895 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1896 1897 sc->hw.fc.high_water = rx_buffer_size - 1898 roundup2(sc->max_frame_size, 1024); 1899 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1900 1901 if (sc->hw.mac.type == e1000_80003es2lan) 1902 sc->hw.fc.pause_time = 0xFFFF; 1903 else 1904 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1905 sc->hw.fc.send_xon = TRUE; 1906 sc->hw.fc.requested_mode = e1000_fc_full; 1907 1908 /* Issue a global reset */ 1909 e1000_reset_hw(&sc->hw); 1910 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1911 emx_disable_aspm(sc); 1912 1913 if (e1000_init_hw(&sc->hw) < 0) { 1914 device_printf(dev, "Hardware Initialization Failed\n"); 1915 return (EIO); 1916 } 1917 1918 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1919 e1000_get_phy_info(&sc->hw); 1920 e1000_check_for_link(&sc->hw); 1921 1922 return (0); 1923 } 1924 1925 static void 1926 emx_setup_ifp(struct emx_softc *sc) 1927 { 1928 struct ifnet *ifp = &sc->arpcom.ac_if; 1929 int i; 1930 1931 if_initname(ifp, device_get_name(sc->dev), 1932 device_get_unit(sc->dev)); 1933 ifp->if_softc = sc; 1934 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1935 ifp->if_init = emx_init; 1936 ifp->if_ioctl = emx_ioctl; 1937 ifp->if_start = emx_start; 1938 #ifdef IFPOLL_ENABLE 1939 ifp->if_npoll = emx_npoll; 1940 #endif 1941 ifp->if_serialize = emx_serialize; 1942 ifp->if_deserialize = emx_deserialize; 1943 ifp->if_tryserialize = emx_tryserialize; 1944 #ifdef INVARIANTS 1945 ifp->if_serialize_assert = emx_serialize_assert; 1946 #endif 1947 1948 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1); 1949 ifq_set_ready(&ifp->if_snd); 1950 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt); 1951 1952 ifp->if_mapsubq = ifq_mapsubq_mask; 1953 ifq_set_subq_mask(&ifp->if_snd, 0); 1954 1955 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1956 1957 ifp->if_capabilities = IFCAP_HWCSUM | 1958 IFCAP_VLAN_HWTAGGING | 1959 IFCAP_VLAN_MTU | 1960 IFCAP_TSO; 1961 if (sc->rx_ring_cnt > 1) 1962 ifp->if_capabilities |= IFCAP_RSS; 1963 ifp->if_capenable = ifp->if_capabilities; 1964 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO; 1965 1966 /* 1967 * Tell the upper layer(s) we support long frames. 1968 */ 1969 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1970 1971 for (i = 0; i < sc->tx_ring_cnt; ++i) { 1972 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i); 1973 struct emx_txdata *tdata = &sc->tx_data[i]; 1974 1975 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res)); 1976 ifsq_set_priv(ifsq, tdata); 1977 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize); 1978 tdata->ifsq = ifsq; 1979 1980 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog); 1981 } 1982 1983 /* 1984 * Specify the media types supported by this sc and register 1985 * callbacks to update media and link information 1986 */ 1987 ifmedia_init(&sc->media, IFM_IMASK, 1988 emx_media_change, emx_media_status); 1989 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1990 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1991 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1992 0, NULL); 1993 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1994 } else { 1995 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1996 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1997 0, NULL); 1998 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1999 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2000 0, NULL); 2001 if (sc->hw.phy.type != e1000_phy_ife) { 2002 ifmedia_add(&sc->media, 2003 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2004 ifmedia_add(&sc->media, 2005 IFM_ETHER | IFM_1000_T, 0, NULL); 2006 } 2007 } 2008 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2009 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2010 } 2011 2012 /* 2013 * Workaround for SmartSpeed on 82541 and 82547 controllers 2014 */ 2015 static void 2016 emx_smartspeed(struct emx_softc *sc) 2017 { 2018 uint16_t phy_tmp; 2019 2020 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 2021 sc->hw.mac.autoneg == 0 || 2022 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2023 return; 2024 2025 if (sc->smartspeed == 0) { 2026 /* 2027 * If Master/Slave config fault is asserted twice, 2028 * we assume back-to-back 2029 */ 2030 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2031 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2032 return; 2033 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2034 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2035 e1000_read_phy_reg(&sc->hw, 2036 PHY_1000T_CTRL, &phy_tmp); 2037 if (phy_tmp & CR_1000T_MS_ENABLE) { 2038 phy_tmp &= ~CR_1000T_MS_ENABLE; 2039 e1000_write_phy_reg(&sc->hw, 2040 PHY_1000T_CTRL, phy_tmp); 2041 sc->smartspeed++; 2042 if (sc->hw.mac.autoneg && 2043 !e1000_phy_setup_autoneg(&sc->hw) && 2044 !e1000_read_phy_reg(&sc->hw, 2045 PHY_CONTROL, &phy_tmp)) { 2046 phy_tmp |= MII_CR_AUTO_NEG_EN | 2047 MII_CR_RESTART_AUTO_NEG; 2048 e1000_write_phy_reg(&sc->hw, 2049 PHY_CONTROL, phy_tmp); 2050 } 2051 } 2052 } 2053 return; 2054 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 2055 /* If still no link, perhaps using 2/3 pair cable */ 2056 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2057 phy_tmp |= CR_1000T_MS_ENABLE; 2058 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2059 if (sc->hw.mac.autoneg && 2060 !e1000_phy_setup_autoneg(&sc->hw) && 2061 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2062 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2063 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2064 } 2065 } 2066 2067 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 2068 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 2069 sc->smartspeed = 0; 2070 } 2071 2072 static int 2073 emx_create_tx_ring(struct emx_txdata *tdata) 2074 { 2075 device_t dev = tdata->sc->dev; 2076 struct emx_txbuf *tx_buffer; 2077 int error, i, tsize, ntxd; 2078 2079 /* 2080 * Validate number of transmit descriptors. It must not exceed 2081 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2082 */ 2083 ntxd = device_getenv_int(dev, "txd", emx_txd); 2084 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 2085 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 2086 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 2087 EMX_DEFAULT_TXD, ntxd); 2088 tdata->num_tx_desc = EMX_DEFAULT_TXD; 2089 } else { 2090 tdata->num_tx_desc = ntxd; 2091 } 2092 2093 /* 2094 * Allocate Transmit Descriptor ring 2095 */ 2096 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc), 2097 EMX_DBA_ALIGN); 2098 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag, 2099 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 2100 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap, 2101 &tdata->tx_desc_paddr); 2102 if (tdata->tx_desc_base == NULL) { 2103 device_printf(dev, "Unable to allocate tx_desc memory\n"); 2104 return ENOMEM; 2105 } 2106 2107 tsize = __VM_CACHELINE_ALIGN( 2108 sizeof(struct emx_txbuf) * tdata->num_tx_desc); 2109 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO); 2110 2111 /* 2112 * Create DMA tags for tx buffers 2113 */ 2114 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */ 2115 1, 0, /* alignment, bounds */ 2116 BUS_SPACE_MAXADDR, /* lowaddr */ 2117 BUS_SPACE_MAXADDR, /* highaddr */ 2118 NULL, NULL, /* filter, filterarg */ 2119 EMX_TSO_SIZE, /* maxsize */ 2120 EMX_MAX_SCATTER, /* nsegments */ 2121 EMX_MAX_SEGSIZE, /* maxsegsize */ 2122 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2123 BUS_DMA_ONEBPAGE, /* flags */ 2124 &tdata->txtag); 2125 if (error) { 2126 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2127 kfree(tdata->tx_buf, M_DEVBUF); 2128 tdata->tx_buf = NULL; 2129 return error; 2130 } 2131 2132 /* 2133 * Create DMA maps for tx buffers 2134 */ 2135 for (i = 0; i < tdata->num_tx_desc; i++) { 2136 tx_buffer = &tdata->tx_buf[i]; 2137 2138 error = bus_dmamap_create(tdata->txtag, 2139 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2140 &tx_buffer->map); 2141 if (error) { 2142 device_printf(dev, "Unable to create TX DMA map\n"); 2143 emx_destroy_tx_ring(tdata, i); 2144 return error; 2145 } 2146 } 2147 2148 /* 2149 * Setup TX parameters 2150 */ 2151 tdata->spare_tx_desc = EMX_TX_SPARE; 2152 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG; 2153 2154 /* 2155 * Keep following relationship between spare_tx_desc, oact_tx_desc 2156 * and tx_intr_nsegs: 2157 * (spare_tx_desc + EMX_TX_RESERVED) <= 2158 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs 2159 */ 2160 tdata->oact_tx_desc = tdata->num_tx_desc / 8; 2161 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX) 2162 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX; 2163 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED) 2164 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED; 2165 2166 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16; 2167 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc) 2168 tdata->tx_intr_nsegs = tdata->oact_tx_desc; 2169 2170 /* 2171 * Pullup extra 4bytes into the first data segment, see: 2172 * 82571/82572 specification update errata #7 2173 * 2174 * NOTE: 2175 * 4bytes instead of 2bytes, which are mentioned in the errata, 2176 * are pulled; mainly to keep rest of the data properly aligned. 2177 */ 2178 if (tdata->sc->hw.mac.type == e1000_82571 || 2179 tdata->sc->hw.mac.type == e1000_82572) 2180 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX; 2181 2182 return (0); 2183 } 2184 2185 static void 2186 emx_init_tx_ring(struct emx_txdata *tdata) 2187 { 2188 /* Clear the old ring contents */ 2189 bzero(tdata->tx_desc_base, 2190 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc); 2191 2192 /* Reset state */ 2193 tdata->next_avail_tx_desc = 0; 2194 tdata->next_tx_to_clean = 0; 2195 tdata->num_tx_desc_avail = tdata->num_tx_desc; 2196 2197 tdata->tx_flags |= EMX_TXFLAG_ENABLED; 2198 if (tdata->sc->tx_ring_inuse > 1) { 2199 tdata->tx_flags |= EMX_TXFLAG_FORCECTX; 2200 if (bootverbose) { 2201 if_printf(&tdata->sc->arpcom.ac_if, 2202 "TX %d force ctx setup\n", tdata->idx); 2203 } 2204 } 2205 } 2206 2207 static void 2208 emx_init_tx_unit(struct emx_softc *sc) 2209 { 2210 uint32_t tctl, tarc, tipg = 0; 2211 int i; 2212 2213 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2214 struct emx_txdata *tdata = &sc->tx_data[i]; 2215 uint64_t bus_addr; 2216 2217 /* Setup the Base and Length of the Tx Descriptor Ring */ 2218 bus_addr = tdata->tx_desc_paddr; 2219 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i), 2220 tdata->num_tx_desc * sizeof(struct e1000_tx_desc)); 2221 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i), 2222 (uint32_t)(bus_addr >> 32)); 2223 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i), 2224 (uint32_t)bus_addr); 2225 /* Setup the HW Tx Head and Tail descriptor pointers */ 2226 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0); 2227 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0); 2228 } 2229 2230 /* Set the default values for the Tx Inter Packet Gap timer */ 2231 switch (sc->hw.mac.type) { 2232 case e1000_80003es2lan: 2233 tipg = DEFAULT_82543_TIPG_IPGR1; 2234 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2235 E1000_TIPG_IPGR2_SHIFT; 2236 break; 2237 2238 default: 2239 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2240 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2241 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2242 else 2243 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2244 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2245 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2246 break; 2247 } 2248 2249 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2250 2251 /* NOTE: 0 is not allowed for TIDV */ 2252 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2253 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2254 2255 if (sc->hw.mac.type == e1000_82571 || 2256 sc->hw.mac.type == e1000_82572) { 2257 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2258 tarc |= EMX_TARC_SPEED_MODE; 2259 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2260 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2261 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2262 tarc |= 1; 2263 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2264 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2265 tarc |= 1; 2266 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2267 } 2268 2269 /* Program the Transmit Control Register */ 2270 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2271 tctl &= ~E1000_TCTL_CT; 2272 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2273 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2274 tctl |= E1000_TCTL_MULR; 2275 2276 /* This write will effectively turn on the transmit unit. */ 2277 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2278 2279 if (sc->hw.mac.type == e1000_82571 || 2280 sc->hw.mac.type == e1000_82572 || 2281 sc->hw.mac.type == e1000_80003es2lan) { 2282 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2283 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2284 tarc &= ~(1 << 28); 2285 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2286 } 2287 2288 if (sc->tx_ring_inuse > 1) { 2289 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2290 tarc &= ~EMX_TARC_COUNT_MASK; 2291 tarc |= 1; 2292 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2293 2294 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2295 tarc &= ~EMX_TARC_COUNT_MASK; 2296 tarc |= 1; 2297 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2298 } 2299 } 2300 2301 static void 2302 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc) 2303 { 2304 struct emx_txbuf *tx_buffer; 2305 int i; 2306 2307 /* Free Transmit Descriptor ring */ 2308 if (tdata->tx_desc_base) { 2309 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap); 2310 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base, 2311 tdata->tx_desc_dmap); 2312 bus_dma_tag_destroy(tdata->tx_desc_dtag); 2313 2314 tdata->tx_desc_base = NULL; 2315 } 2316 2317 if (tdata->tx_buf == NULL) 2318 return; 2319 2320 for (i = 0; i < ndesc; i++) { 2321 tx_buffer = &tdata->tx_buf[i]; 2322 2323 KKASSERT(tx_buffer->m_head == NULL); 2324 bus_dmamap_destroy(tdata->txtag, tx_buffer->map); 2325 } 2326 bus_dma_tag_destroy(tdata->txtag); 2327 2328 kfree(tdata->tx_buf, M_DEVBUF); 2329 tdata->tx_buf = NULL; 2330 } 2331 2332 /* 2333 * The offload context needs to be set when we transfer the first 2334 * packet of a particular protocol (TCP/UDP). This routine has been 2335 * enhanced to deal with inserted VLAN headers. 2336 * 2337 * If the new packet's ether header length, ip header length and 2338 * csum offloading type are same as the previous packet, we should 2339 * avoid allocating a new csum context descriptor; mainly to take 2340 * advantage of the pipeline effect of the TX data read request. 2341 * 2342 * This function returns number of TX descrptors allocated for 2343 * csum context. 2344 */ 2345 static int 2346 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp, 2347 uint32_t *txd_upper, uint32_t *txd_lower) 2348 { 2349 struct e1000_context_desc *TXD; 2350 int curr_txd, ehdrlen, csum_flags; 2351 uint32_t cmd, hdr_len, ip_hlen; 2352 2353 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2354 ip_hlen = mp->m_pkthdr.csum_iphlen; 2355 ehdrlen = mp->m_pkthdr.csum_lhlen; 2356 2357 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 2358 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen && 2359 tdata->csum_flags == csum_flags) { 2360 /* 2361 * Same csum offload context as the previous packets; 2362 * just return. 2363 */ 2364 *txd_upper = tdata->csum_txd_upper; 2365 *txd_lower = tdata->csum_txd_lower; 2366 return 0; 2367 } 2368 2369 /* 2370 * Setup a new csum offload context. 2371 */ 2372 2373 curr_txd = tdata->next_avail_tx_desc; 2374 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 2375 2376 cmd = 0; 2377 2378 /* Setup of IP header checksum. */ 2379 if (csum_flags & CSUM_IP) { 2380 /* 2381 * Start offset for header checksum calculation. 2382 * End offset for header checksum calculation. 2383 * Offset of place to put the checksum. 2384 */ 2385 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2386 TXD->lower_setup.ip_fields.ipcse = 2387 htole16(ehdrlen + ip_hlen - 1); 2388 TXD->lower_setup.ip_fields.ipcso = 2389 ehdrlen + offsetof(struct ip, ip_sum); 2390 cmd |= E1000_TXD_CMD_IP; 2391 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2392 } 2393 hdr_len = ehdrlen + ip_hlen; 2394 2395 if (csum_flags & CSUM_TCP) { 2396 /* 2397 * Start offset for payload checksum calculation. 2398 * End offset for payload checksum calculation. 2399 * Offset of place to put the checksum. 2400 */ 2401 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2402 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2403 TXD->upper_setup.tcp_fields.tucso = 2404 hdr_len + offsetof(struct tcphdr, th_sum); 2405 cmd |= E1000_TXD_CMD_TCP; 2406 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2407 } else if (csum_flags & CSUM_UDP) { 2408 /* 2409 * Start offset for header checksum calculation. 2410 * End offset for header checksum calculation. 2411 * Offset of place to put the checksum. 2412 */ 2413 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2414 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2415 TXD->upper_setup.tcp_fields.tucso = 2416 hdr_len + offsetof(struct udphdr, uh_sum); 2417 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2418 } 2419 2420 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2421 E1000_TXD_DTYP_D; /* Data descr */ 2422 2423 /* Save the information for this csum offloading context */ 2424 tdata->csum_lhlen = ehdrlen; 2425 tdata->csum_iphlen = ip_hlen; 2426 tdata->csum_flags = csum_flags; 2427 tdata->csum_txd_upper = *txd_upper; 2428 tdata->csum_txd_lower = *txd_lower; 2429 2430 TXD->tcp_seg_setup.data = htole32(0); 2431 TXD->cmd_and_length = 2432 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2433 2434 if (++curr_txd == tdata->num_tx_desc) 2435 curr_txd = 0; 2436 2437 KKASSERT(tdata->num_tx_desc_avail > 0); 2438 tdata->num_tx_desc_avail--; 2439 2440 tdata->next_avail_tx_desc = curr_txd; 2441 return 1; 2442 } 2443 2444 static void 2445 emx_txeof(struct emx_txdata *tdata) 2446 { 2447 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2448 struct emx_txbuf *tx_buffer; 2449 int first, num_avail; 2450 2451 if (tdata->tx_dd_head == tdata->tx_dd_tail) 2452 return; 2453 2454 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2455 return; 2456 2457 num_avail = tdata->num_tx_desc_avail; 2458 first = tdata->next_tx_to_clean; 2459 2460 while (tdata->tx_dd_head != tdata->tx_dd_tail) { 2461 int dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2462 struct e1000_tx_desc *tx_desc; 2463 2464 tx_desc = &tdata->tx_desc_base[dd_idx]; 2465 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2466 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2467 2468 if (++dd_idx == tdata->num_tx_desc) 2469 dd_idx = 0; 2470 2471 while (first != dd_idx) { 2472 logif(pkt_txclean); 2473 2474 num_avail++; 2475 2476 tx_buffer = &tdata->tx_buf[first]; 2477 if (tx_buffer->m_head) { 2478 IFNET_STAT_INC(ifp, opackets, 1); 2479 bus_dmamap_unload(tdata->txtag, 2480 tx_buffer->map); 2481 m_freem(tx_buffer->m_head); 2482 tx_buffer->m_head = NULL; 2483 } 2484 2485 if (++first == tdata->num_tx_desc) 2486 first = 0; 2487 } 2488 } else { 2489 break; 2490 } 2491 } 2492 tdata->next_tx_to_clean = first; 2493 tdata->num_tx_desc_avail = num_avail; 2494 2495 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2496 tdata->tx_dd_head = 0; 2497 tdata->tx_dd_tail = 0; 2498 } 2499 2500 if (!EMX_IS_OACTIVE(tdata)) { 2501 ifsq_clr_oactive(tdata->ifsq); 2502 2503 /* All clean, turn off the timer */ 2504 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2505 tdata->tx_watchdog.wd_timer = 0; 2506 } 2507 } 2508 2509 static void 2510 emx_tx_collect(struct emx_txdata *tdata) 2511 { 2512 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2513 struct emx_txbuf *tx_buffer; 2514 int tdh, first, num_avail, dd_idx = -1; 2515 2516 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2517 return; 2518 2519 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx)); 2520 if (tdh == tdata->next_tx_to_clean) 2521 return; 2522 2523 if (tdata->tx_dd_head != tdata->tx_dd_tail) 2524 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2525 2526 num_avail = tdata->num_tx_desc_avail; 2527 first = tdata->next_tx_to_clean; 2528 2529 while (first != tdh) { 2530 logif(pkt_txclean); 2531 2532 num_avail++; 2533 2534 tx_buffer = &tdata->tx_buf[first]; 2535 if (tx_buffer->m_head) { 2536 IFNET_STAT_INC(ifp, opackets, 1); 2537 bus_dmamap_unload(tdata->txtag, 2538 tx_buffer->map); 2539 m_freem(tx_buffer->m_head); 2540 tx_buffer->m_head = NULL; 2541 } 2542 2543 if (first == dd_idx) { 2544 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2545 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2546 tdata->tx_dd_head = 0; 2547 tdata->tx_dd_tail = 0; 2548 dd_idx = -1; 2549 } else { 2550 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2551 } 2552 } 2553 2554 if (++first == tdata->num_tx_desc) 2555 first = 0; 2556 } 2557 tdata->next_tx_to_clean = first; 2558 tdata->num_tx_desc_avail = num_avail; 2559 2560 if (!EMX_IS_OACTIVE(tdata)) { 2561 ifsq_clr_oactive(tdata->ifsq); 2562 2563 /* All clean, turn off the timer */ 2564 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2565 tdata->tx_watchdog.wd_timer = 0; 2566 } 2567 } 2568 2569 /* 2570 * When Link is lost sometimes there is work still in the TX ring 2571 * which will result in a watchdog, rather than allow that do an 2572 * attempted cleanup and then reinit here. Note that this has been 2573 * seens mostly with fiber adapters. 2574 */ 2575 static void 2576 emx_tx_purge(struct emx_softc *sc) 2577 { 2578 int i; 2579 2580 if (sc->link_active) 2581 return; 2582 2583 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2584 struct emx_txdata *tdata = &sc->tx_data[i]; 2585 2586 if (tdata->tx_watchdog.wd_timer) { 2587 emx_tx_collect(tdata); 2588 if (tdata->tx_watchdog.wd_timer) { 2589 if_printf(&sc->arpcom.ac_if, 2590 "Link lost, TX pending, reinit\n"); 2591 emx_init(sc); 2592 return; 2593 } 2594 } 2595 } 2596 } 2597 2598 static int 2599 emx_newbuf(struct emx_rxdata *rdata, int i, int init) 2600 { 2601 struct mbuf *m; 2602 bus_dma_segment_t seg; 2603 bus_dmamap_t map; 2604 struct emx_rxbuf *rx_buffer; 2605 int error, nseg; 2606 2607 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2608 if (m == NULL) { 2609 if (init) { 2610 if_printf(&rdata->sc->arpcom.ac_if, 2611 "Unable to allocate RX mbuf\n"); 2612 } 2613 return (ENOBUFS); 2614 } 2615 m->m_len = m->m_pkthdr.len = MCLBYTES; 2616 2617 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2618 m_adj(m, ETHER_ALIGN); 2619 2620 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2621 rdata->rx_sparemap, m, 2622 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2623 if (error) { 2624 m_freem(m); 2625 if (init) { 2626 if_printf(&rdata->sc->arpcom.ac_if, 2627 "Unable to load RX mbuf\n"); 2628 } 2629 return (error); 2630 } 2631 2632 rx_buffer = &rdata->rx_buf[i]; 2633 if (rx_buffer->m_head != NULL) 2634 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2635 2636 map = rx_buffer->map; 2637 rx_buffer->map = rdata->rx_sparemap; 2638 rdata->rx_sparemap = map; 2639 2640 rx_buffer->m_head = m; 2641 rx_buffer->paddr = seg.ds_addr; 2642 2643 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2644 return (0); 2645 } 2646 2647 static int 2648 emx_create_rx_ring(struct emx_rxdata *rdata) 2649 { 2650 device_t dev = rdata->sc->dev; 2651 struct emx_rxbuf *rx_buffer; 2652 int i, error, rsize, nrxd; 2653 2654 /* 2655 * Validate number of receive descriptors. It must not exceed 2656 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2657 */ 2658 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2659 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2660 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2661 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2662 EMX_DEFAULT_RXD, nrxd); 2663 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2664 } else { 2665 rdata->num_rx_desc = nrxd; 2666 } 2667 2668 /* 2669 * Allocate Receive Descriptor ring 2670 */ 2671 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2672 EMX_DBA_ALIGN); 2673 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag, 2674 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2675 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2676 &rdata->rx_desc_paddr); 2677 if (rdata->rx_desc == NULL) { 2678 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2679 return ENOMEM; 2680 } 2681 2682 rsize = __VM_CACHELINE_ALIGN( 2683 sizeof(struct emx_rxbuf) * rdata->num_rx_desc); 2684 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO); 2685 2686 /* 2687 * Create DMA tag for rx buffers 2688 */ 2689 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */ 2690 1, 0, /* alignment, bounds */ 2691 BUS_SPACE_MAXADDR, /* lowaddr */ 2692 BUS_SPACE_MAXADDR, /* highaddr */ 2693 NULL, NULL, /* filter, filterarg */ 2694 MCLBYTES, /* maxsize */ 2695 1, /* nsegments */ 2696 MCLBYTES, /* maxsegsize */ 2697 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2698 &rdata->rxtag); 2699 if (error) { 2700 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2701 kfree(rdata->rx_buf, M_DEVBUF); 2702 rdata->rx_buf = NULL; 2703 return error; 2704 } 2705 2706 /* 2707 * Create spare DMA map for rx buffers 2708 */ 2709 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2710 &rdata->rx_sparemap); 2711 if (error) { 2712 device_printf(dev, "Unable to create spare RX DMA map\n"); 2713 bus_dma_tag_destroy(rdata->rxtag); 2714 kfree(rdata->rx_buf, M_DEVBUF); 2715 rdata->rx_buf = NULL; 2716 return error; 2717 } 2718 2719 /* 2720 * Create DMA maps for rx buffers 2721 */ 2722 for (i = 0; i < rdata->num_rx_desc; i++) { 2723 rx_buffer = &rdata->rx_buf[i]; 2724 2725 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2726 &rx_buffer->map); 2727 if (error) { 2728 device_printf(dev, "Unable to create RX DMA map\n"); 2729 emx_destroy_rx_ring(rdata, i); 2730 return error; 2731 } 2732 } 2733 return (0); 2734 } 2735 2736 static void 2737 emx_free_rx_ring(struct emx_rxdata *rdata) 2738 { 2739 int i; 2740 2741 for (i = 0; i < rdata->num_rx_desc; i++) { 2742 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2743 2744 if (rx_buffer->m_head != NULL) { 2745 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2746 m_freem(rx_buffer->m_head); 2747 rx_buffer->m_head = NULL; 2748 } 2749 } 2750 2751 if (rdata->fmp != NULL) 2752 m_freem(rdata->fmp); 2753 rdata->fmp = NULL; 2754 rdata->lmp = NULL; 2755 } 2756 2757 static void 2758 emx_free_tx_ring(struct emx_txdata *tdata) 2759 { 2760 int i; 2761 2762 for (i = 0; i < tdata->num_tx_desc; i++) { 2763 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i]; 2764 2765 if (tx_buffer->m_head != NULL) { 2766 bus_dmamap_unload(tdata->txtag, tx_buffer->map); 2767 m_freem(tx_buffer->m_head); 2768 tx_buffer->m_head = NULL; 2769 } 2770 } 2771 2772 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX; 2773 2774 tdata->csum_flags = 0; 2775 tdata->csum_lhlen = 0; 2776 tdata->csum_iphlen = 0; 2777 tdata->csum_thlen = 0; 2778 tdata->csum_mss = 0; 2779 tdata->csum_pktlen = 0; 2780 2781 tdata->tx_dd_head = 0; 2782 tdata->tx_dd_tail = 0; 2783 tdata->tx_nsegs = 0; 2784 } 2785 2786 static int 2787 emx_init_rx_ring(struct emx_rxdata *rdata) 2788 { 2789 int i, error; 2790 2791 /* Reset descriptor ring */ 2792 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2793 2794 /* Allocate new ones. */ 2795 for (i = 0; i < rdata->num_rx_desc; i++) { 2796 error = emx_newbuf(rdata, i, 1); 2797 if (error) 2798 return (error); 2799 } 2800 2801 /* Setup our descriptor pointers */ 2802 rdata->next_rx_desc_to_check = 0; 2803 2804 return (0); 2805 } 2806 2807 static void 2808 emx_init_rx_unit(struct emx_softc *sc) 2809 { 2810 struct ifnet *ifp = &sc->arpcom.ac_if; 2811 uint64_t bus_addr; 2812 uint32_t rctl, itr, rfctl; 2813 int i; 2814 2815 /* 2816 * Make sure receives are disabled while setting 2817 * up the descriptor ring 2818 */ 2819 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2820 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2821 2822 /* 2823 * Set the interrupt throttling rate. Value is calculated 2824 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2825 */ 2826 if (sc->int_throttle_ceil) 2827 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2828 else 2829 itr = 0; 2830 emx_set_itr(sc, itr); 2831 2832 /* Use extended RX descriptor */ 2833 rfctl = E1000_RFCTL_EXTEN; 2834 2835 /* Disable accelerated ackknowledge */ 2836 if (sc->hw.mac.type == e1000_82574) 2837 rfctl |= E1000_RFCTL_ACK_DIS; 2838 2839 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2840 2841 /* 2842 * Receive Checksum Offload for TCP and UDP 2843 * 2844 * Checksum offloading is also enabled if multiple receive 2845 * queue is to be supported, since we need it to figure out 2846 * packet type. 2847 */ 2848 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2849 sc->rx_ring_cnt > 1) { 2850 uint32_t rxcsum; 2851 2852 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2853 2854 /* 2855 * NOTE: 2856 * PCSD must be enabled to enable multiple 2857 * receive queues. 2858 */ 2859 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2860 E1000_RXCSUM_PCSD; 2861 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2862 } 2863 2864 /* 2865 * Configure multiple receive queue (RSS) 2866 */ 2867 if (sc->rx_ring_cnt > 1) { 2868 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2869 uint32_t reta; 2870 2871 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2872 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2873 2874 /* 2875 * NOTE: 2876 * When we reach here, RSS has already been disabled 2877 * in emx_stop(), so we could safely configure RSS key 2878 * and redirect table. 2879 */ 2880 2881 /* 2882 * Configure RSS key 2883 */ 2884 toeplitz_get_key(key, sizeof(key)); 2885 for (i = 0; i < EMX_NRSSRK; ++i) { 2886 uint32_t rssrk; 2887 2888 rssrk = EMX_RSSRK_VAL(key, i); 2889 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2890 2891 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2892 } 2893 2894 /* 2895 * Configure RSS redirect table in following fashion: 2896 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2897 */ 2898 reta = 0; 2899 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2900 uint32_t q; 2901 2902 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT; 2903 reta |= q << (8 * i); 2904 } 2905 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2906 2907 for (i = 0; i < EMX_NRETA; ++i) 2908 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2909 2910 /* 2911 * Enable multiple receive queues. 2912 * Enable IPv4 RSS standard hash functions. 2913 * Disable RSS interrupt. 2914 */ 2915 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2916 E1000_MRQC_ENABLE_RSS_2Q | 2917 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2918 E1000_MRQC_RSS_FIELD_IPV4); 2919 } 2920 2921 /* 2922 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2923 * long latencies are observed, like Lenovo X60. This 2924 * change eliminates the problem, but since having positive 2925 * values in RDTR is a known source of problems on other 2926 * platforms another solution is being sought. 2927 */ 2928 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2929 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2930 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2931 } 2932 2933 for (i = 0; i < sc->rx_ring_cnt; ++i) { 2934 struct emx_rxdata *rdata = &sc->rx_data[i]; 2935 2936 /* 2937 * Setup the Base and Length of the Rx Descriptor Ring 2938 */ 2939 bus_addr = rdata->rx_desc_paddr; 2940 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2941 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2942 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2943 (uint32_t)(bus_addr >> 32)); 2944 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2945 (uint32_t)bus_addr); 2946 2947 /* 2948 * Setup the HW Rx Head and Tail Descriptor Pointers 2949 */ 2950 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2951 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2952 sc->rx_data[i].num_rx_desc - 1); 2953 } 2954 2955 /* Setup the Receive Control Register */ 2956 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2957 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2958 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2959 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2960 2961 /* Make sure VLAN Filters are off */ 2962 rctl &= ~E1000_RCTL_VFE; 2963 2964 /* Don't store bad paket */ 2965 rctl &= ~E1000_RCTL_SBP; 2966 2967 /* MCLBYTES */ 2968 rctl |= E1000_RCTL_SZ_2048; 2969 2970 if (ifp->if_mtu > ETHERMTU) 2971 rctl |= E1000_RCTL_LPE; 2972 else 2973 rctl &= ~E1000_RCTL_LPE; 2974 2975 /* Enable Receives */ 2976 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2977 } 2978 2979 static void 2980 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc) 2981 { 2982 struct emx_rxbuf *rx_buffer; 2983 int i; 2984 2985 /* Free Receive Descriptor ring */ 2986 if (rdata->rx_desc) { 2987 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2988 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2989 rdata->rx_desc_dmap); 2990 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2991 2992 rdata->rx_desc = NULL; 2993 } 2994 2995 if (rdata->rx_buf == NULL) 2996 return; 2997 2998 for (i = 0; i < ndesc; i++) { 2999 rx_buffer = &rdata->rx_buf[i]; 3000 3001 KKASSERT(rx_buffer->m_head == NULL); 3002 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 3003 } 3004 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 3005 bus_dma_tag_destroy(rdata->rxtag); 3006 3007 kfree(rdata->rx_buf, M_DEVBUF); 3008 rdata->rx_buf = NULL; 3009 } 3010 3011 static void 3012 emx_rxeof(struct emx_rxdata *rdata, int count) 3013 { 3014 struct ifnet *ifp = &rdata->sc->arpcom.ac_if; 3015 uint32_t staterr; 3016 emx_rxdesc_t *current_desc; 3017 struct mbuf *mp; 3018 int i; 3019 3020 i = rdata->next_rx_desc_to_check; 3021 current_desc = &rdata->rx_desc[i]; 3022 staterr = le32toh(current_desc->rxd_staterr); 3023 3024 if (!(staterr & E1000_RXD_STAT_DD)) 3025 return; 3026 3027 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 3028 struct pktinfo *pi = NULL, pi0; 3029 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 3030 struct mbuf *m = NULL; 3031 int eop, len; 3032 3033 logif(pkt_receive); 3034 3035 mp = rx_buf->m_head; 3036 3037 /* 3038 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3039 * needs to access the last received byte in the mbuf. 3040 */ 3041 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 3042 BUS_DMASYNC_POSTREAD); 3043 3044 len = le16toh(current_desc->rxd_length); 3045 if (staterr & E1000_RXD_STAT_EOP) { 3046 count--; 3047 eop = 1; 3048 } else { 3049 eop = 0; 3050 } 3051 3052 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 3053 uint16_t vlan = 0; 3054 uint32_t mrq, rss_hash; 3055 3056 /* 3057 * Save several necessary information, 3058 * before emx_newbuf() destroy it. 3059 */ 3060 if ((staterr & E1000_RXD_STAT_VP) && eop) 3061 vlan = le16toh(current_desc->rxd_vlan); 3062 3063 mrq = le32toh(current_desc->rxd_mrq); 3064 rss_hash = le32toh(current_desc->rxd_rss); 3065 3066 EMX_RSS_DPRINTF(rdata->sc, 10, 3067 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 3068 rdata->idx, mrq, rss_hash); 3069 3070 if (emx_newbuf(rdata, i, 0) != 0) { 3071 IFNET_STAT_INC(ifp, iqdrops, 1); 3072 goto discard; 3073 } 3074 3075 /* Assign correct length to the current fragment */ 3076 mp->m_len = len; 3077 3078 if (rdata->fmp == NULL) { 3079 mp->m_pkthdr.len = len; 3080 rdata->fmp = mp; /* Store the first mbuf */ 3081 rdata->lmp = mp; 3082 } else { 3083 /* 3084 * Chain mbuf's together 3085 */ 3086 rdata->lmp->m_next = mp; 3087 rdata->lmp = rdata->lmp->m_next; 3088 rdata->fmp->m_pkthdr.len += len; 3089 } 3090 3091 if (eop) { 3092 rdata->fmp->m_pkthdr.rcvif = ifp; 3093 IFNET_STAT_INC(ifp, ipackets, 1); 3094 3095 if (ifp->if_capenable & IFCAP_RXCSUM) 3096 emx_rxcsum(staterr, rdata->fmp); 3097 3098 if (staterr & E1000_RXD_STAT_VP) { 3099 rdata->fmp->m_pkthdr.ether_vlantag = 3100 vlan; 3101 rdata->fmp->m_flags |= M_VLANTAG; 3102 } 3103 m = rdata->fmp; 3104 rdata->fmp = NULL; 3105 rdata->lmp = NULL; 3106 3107 if (ifp->if_capenable & IFCAP_RSS) { 3108 pi = emx_rssinfo(m, &pi0, mrq, 3109 rss_hash, staterr); 3110 } 3111 #ifdef EMX_RSS_DEBUG 3112 rdata->rx_pkts++; 3113 #endif 3114 } 3115 } else { 3116 IFNET_STAT_INC(ifp, ierrors, 1); 3117 discard: 3118 emx_setup_rxdesc(current_desc, rx_buf); 3119 if (rdata->fmp != NULL) { 3120 m_freem(rdata->fmp); 3121 rdata->fmp = NULL; 3122 rdata->lmp = NULL; 3123 } 3124 m = NULL; 3125 } 3126 3127 if (m != NULL) 3128 ether_input_pkt(ifp, m, pi); 3129 3130 /* Advance our pointers to the next descriptor. */ 3131 if (++i == rdata->num_rx_desc) 3132 i = 0; 3133 3134 current_desc = &rdata->rx_desc[i]; 3135 staterr = le32toh(current_desc->rxd_staterr); 3136 } 3137 rdata->next_rx_desc_to_check = i; 3138 3139 /* Advance the E1000's Receive Queue "Tail Pointer". */ 3140 if (--i < 0) 3141 i = rdata->num_rx_desc - 1; 3142 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i); 3143 } 3144 3145 static void 3146 emx_enable_intr(struct emx_softc *sc) 3147 { 3148 uint32_t ims_mask = IMS_ENABLE_MASK; 3149 3150 lwkt_serialize_handler_enable(&sc->main_serialize); 3151 3152 #if 0 3153 if (sc->hw.mac.type == e1000_82574) { 3154 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 3155 ims_mask |= EM_MSIX_MASK; 3156 } 3157 #endif 3158 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 3159 } 3160 3161 static void 3162 emx_disable_intr(struct emx_softc *sc) 3163 { 3164 if (sc->hw.mac.type == e1000_82574) 3165 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 3166 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 3167 3168 lwkt_serialize_handler_disable(&sc->main_serialize); 3169 } 3170 3171 /* 3172 * Bit of a misnomer, what this really means is 3173 * to enable OS management of the system... aka 3174 * to disable special hardware management features 3175 */ 3176 static void 3177 emx_get_mgmt(struct emx_softc *sc) 3178 { 3179 /* A shared code workaround */ 3180 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3181 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3182 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3183 3184 /* disable hardware interception of ARP */ 3185 manc &= ~(E1000_MANC_ARP_EN); 3186 3187 /* enable receiving management packets to the host */ 3188 manc |= E1000_MANC_EN_MNG2HOST; 3189 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3190 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3191 manc2h |= E1000_MNG2HOST_PORT_623; 3192 manc2h |= E1000_MNG2HOST_PORT_664; 3193 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3194 3195 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3196 } 3197 } 3198 3199 /* 3200 * Give control back to hardware management 3201 * controller if there is one. 3202 */ 3203 static void 3204 emx_rel_mgmt(struct emx_softc *sc) 3205 { 3206 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3207 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3208 3209 /* re-enable hardware interception of ARP */ 3210 manc |= E1000_MANC_ARP_EN; 3211 manc &= ~E1000_MANC_EN_MNG2HOST; 3212 3213 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3214 } 3215 } 3216 3217 /* 3218 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3219 * For ASF and Pass Through versions of f/w this means that 3220 * the driver is loaded. For AMT version (only with 82573) 3221 * of the f/w this means that the network i/f is open. 3222 */ 3223 static void 3224 emx_get_hw_control(struct emx_softc *sc) 3225 { 3226 /* Let firmware know the driver has taken over */ 3227 if (sc->hw.mac.type == e1000_82573) { 3228 uint32_t swsm; 3229 3230 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3231 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3232 swsm | E1000_SWSM_DRV_LOAD); 3233 } else { 3234 uint32_t ctrl_ext; 3235 3236 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3237 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3238 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3239 } 3240 sc->flags |= EMX_FLAG_HW_CTRL; 3241 } 3242 3243 /* 3244 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3245 * For ASF and Pass Through versions of f/w this means that the 3246 * driver is no longer loaded. For AMT version (only with 82573) 3247 * of the f/w this means that the network i/f is closed. 3248 */ 3249 static void 3250 emx_rel_hw_control(struct emx_softc *sc) 3251 { 3252 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0) 3253 return; 3254 sc->flags &= ~EMX_FLAG_HW_CTRL; 3255 3256 /* Let firmware taken over control of h/w */ 3257 if (sc->hw.mac.type == e1000_82573) { 3258 uint32_t swsm; 3259 3260 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3261 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3262 swsm & ~E1000_SWSM_DRV_LOAD); 3263 } else { 3264 uint32_t ctrl_ext; 3265 3266 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3267 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3268 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3269 } 3270 } 3271 3272 static int 3273 emx_is_valid_eaddr(const uint8_t *addr) 3274 { 3275 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3276 3277 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3278 return (FALSE); 3279 3280 return (TRUE); 3281 } 3282 3283 /* 3284 * Enable PCI Wake On Lan capability 3285 */ 3286 void 3287 emx_enable_wol(device_t dev) 3288 { 3289 uint16_t cap, status; 3290 uint8_t id; 3291 3292 /* First find the capabilities pointer*/ 3293 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3294 3295 /* Read the PM Capabilities */ 3296 id = pci_read_config(dev, cap, 1); 3297 if (id != PCIY_PMG) /* Something wrong */ 3298 return; 3299 3300 /* 3301 * OK, we have the power capabilities, 3302 * so now get the status register 3303 */ 3304 cap += PCIR_POWER_STATUS; 3305 status = pci_read_config(dev, cap, 2); 3306 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3307 pci_write_config(dev, cap, status, 2); 3308 } 3309 3310 static void 3311 emx_update_stats(struct emx_softc *sc) 3312 { 3313 struct ifnet *ifp = &sc->arpcom.ac_if; 3314 3315 if (sc->hw.phy.media_type == e1000_media_type_copper || 3316 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3317 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3318 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3319 } 3320 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3321 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3322 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3323 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3324 3325 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3326 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3327 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3328 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3329 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3330 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3331 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3332 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3333 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3334 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3335 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3336 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3337 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3338 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3339 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3340 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3341 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3342 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3343 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3344 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3345 3346 /* For the 64-bit byte counters the low dword must be read first. */ 3347 /* Both registers clear on the read of the high dword */ 3348 3349 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3350 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3351 3352 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3353 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3354 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3355 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3356 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3357 3358 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3359 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3360 3361 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3362 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3363 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3364 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3365 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3366 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3367 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3368 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3369 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3370 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3371 3372 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3373 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3374 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3375 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3376 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3377 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3378 3379 IFNET_STAT_SET(ifp, collisions, sc->stats.colc); 3380 3381 /* Rx Errors */ 3382 IFNET_STAT_SET(ifp, ierrors, 3383 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc + 3384 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr); 3385 3386 /* Tx Errors */ 3387 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol); 3388 } 3389 3390 static void 3391 emx_print_debug_info(struct emx_softc *sc) 3392 { 3393 device_t dev = sc->dev; 3394 uint8_t *hw_addr = sc->hw.hw_addr; 3395 int i; 3396 3397 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3398 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3399 E1000_READ_REG(&sc->hw, E1000_CTRL), 3400 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3401 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3402 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3403 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3404 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3405 sc->hw.fc.high_water, sc->hw.fc.low_water); 3406 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3407 E1000_READ_REG(&sc->hw, E1000_TIDV), 3408 E1000_READ_REG(&sc->hw, E1000_TADV)); 3409 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3410 E1000_READ_REG(&sc->hw, E1000_RDTR), 3411 E1000_READ_REG(&sc->hw, E1000_RADV)); 3412 3413 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3414 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i, 3415 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 3416 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 3417 } 3418 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3419 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i, 3420 E1000_READ_REG(&sc->hw, E1000_RDH(i)), 3421 E1000_READ_REG(&sc->hw, E1000_RDT(i))); 3422 } 3423 3424 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3425 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i, 3426 sc->tx_data[i].num_tx_desc_avail); 3427 device_printf(dev, "TX %d TSO segments = %lu\n", i, 3428 sc->tx_data[i].tso_segments); 3429 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i, 3430 sc->tx_data[i].tso_ctx_reused); 3431 } 3432 } 3433 3434 static void 3435 emx_print_hw_stats(struct emx_softc *sc) 3436 { 3437 device_t dev = sc->dev; 3438 3439 device_printf(dev, "Excessive collisions = %lld\n", 3440 (long long)sc->stats.ecol); 3441 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3442 device_printf(dev, "Symbol errors = %lld\n", 3443 (long long)sc->stats.symerrs); 3444 #endif 3445 device_printf(dev, "Sequence errors = %lld\n", 3446 (long long)sc->stats.sec); 3447 device_printf(dev, "Defer count = %lld\n", 3448 (long long)sc->stats.dc); 3449 device_printf(dev, "Missed Packets = %lld\n", 3450 (long long)sc->stats.mpc); 3451 device_printf(dev, "Receive No Buffers = %lld\n", 3452 (long long)sc->stats.rnbc); 3453 /* RLEC is inaccurate on some hardware, calculate our own. */ 3454 device_printf(dev, "Receive Length Errors = %lld\n", 3455 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3456 device_printf(dev, "Receive errors = %lld\n", 3457 (long long)sc->stats.rxerrc); 3458 device_printf(dev, "Crc errors = %lld\n", 3459 (long long)sc->stats.crcerrs); 3460 device_printf(dev, "Alignment errors = %lld\n", 3461 (long long)sc->stats.algnerrc); 3462 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3463 (long long)sc->stats.cexterr); 3464 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3465 device_printf(dev, "XON Rcvd = %lld\n", 3466 (long long)sc->stats.xonrxc); 3467 device_printf(dev, "XON Xmtd = %lld\n", 3468 (long long)sc->stats.xontxc); 3469 device_printf(dev, "XOFF Rcvd = %lld\n", 3470 (long long)sc->stats.xoffrxc); 3471 device_printf(dev, "XOFF Xmtd = %lld\n", 3472 (long long)sc->stats.xofftxc); 3473 device_printf(dev, "Good Packets Rcvd = %lld\n", 3474 (long long)sc->stats.gprc); 3475 device_printf(dev, "Good Packets Xmtd = %lld\n", 3476 (long long)sc->stats.gptc); 3477 } 3478 3479 static void 3480 emx_print_nvm_info(struct emx_softc *sc) 3481 { 3482 uint16_t eeprom_data; 3483 int i, j, row = 0; 3484 3485 /* Its a bit crude, but it gets the job done */ 3486 kprintf("\nInterface EEPROM Dump:\n"); 3487 kprintf("Offset\n0x0000 "); 3488 for (i = 0, j = 0; i < 32; i++, j++) { 3489 if (j == 8) { /* Make the offset block */ 3490 j = 0; ++row; 3491 kprintf("\n0x00%x0 ",row); 3492 } 3493 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3494 kprintf("%04x ", eeprom_data); 3495 } 3496 kprintf("\n"); 3497 } 3498 3499 static int 3500 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3501 { 3502 struct emx_softc *sc; 3503 struct ifnet *ifp; 3504 int error, result; 3505 3506 result = -1; 3507 error = sysctl_handle_int(oidp, &result, 0, req); 3508 if (error || !req->newptr) 3509 return (error); 3510 3511 sc = (struct emx_softc *)arg1; 3512 ifp = &sc->arpcom.ac_if; 3513 3514 ifnet_serialize_all(ifp); 3515 3516 if (result == 1) 3517 emx_print_debug_info(sc); 3518 3519 /* 3520 * This value will cause a hex dump of the 3521 * first 32 16-bit words of the EEPROM to 3522 * the screen. 3523 */ 3524 if (result == 2) 3525 emx_print_nvm_info(sc); 3526 3527 ifnet_deserialize_all(ifp); 3528 3529 return (error); 3530 } 3531 3532 static int 3533 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3534 { 3535 int error, result; 3536 3537 result = -1; 3538 error = sysctl_handle_int(oidp, &result, 0, req); 3539 if (error || !req->newptr) 3540 return (error); 3541 3542 if (result == 1) { 3543 struct emx_softc *sc = (struct emx_softc *)arg1; 3544 struct ifnet *ifp = &sc->arpcom.ac_if; 3545 3546 ifnet_serialize_all(ifp); 3547 emx_print_hw_stats(sc); 3548 ifnet_deserialize_all(ifp); 3549 } 3550 return (error); 3551 } 3552 3553 static void 3554 emx_add_sysctl(struct emx_softc *sc) 3555 { 3556 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG) 3557 char pkt_desc[32]; 3558 int i; 3559 #endif 3560 3561 sysctl_ctx_init(&sc->sysctl_ctx); 3562 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3563 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3564 device_get_nameunit(sc->dev), 3565 CTLFLAG_RD, 0, ""); 3566 if (sc->sysctl_tree == NULL) { 3567 device_printf(sc->dev, "can't add sysctl node\n"); 3568 return; 3569 } 3570 3571 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3572 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3573 emx_sysctl_debug_info, "I", "Debug Information"); 3574 3575 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3576 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3577 emx_sysctl_stats, "I", "Statistics"); 3578 3579 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3580 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0, 3581 "# of RX descs"); 3582 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3583 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0, 3584 "# of TX descs"); 3585 3586 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3587 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3588 emx_sysctl_int_throttle, "I", "interrupt throttling rate"); 3589 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3590 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3591 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt"); 3592 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3593 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3594 emx_sysctl_tx_wreg_nsegs, "I", 3595 "# segments sent before write to hardware register"); 3596 3597 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3598 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0, 3599 "# of RX rings"); 3600 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3601 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0, 3602 "# of TX rings"); 3603 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3604 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0, 3605 "# of TX rings used"); 3606 3607 #ifdef IFPOLL_ENABLE 3608 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3609 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, 3610 sc, 0, emx_sysctl_npoll_rxoff, "I", 3611 "NPOLLING RX cpu offset"); 3612 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3613 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, 3614 sc, 0, emx_sysctl_npoll_txoff, "I", 3615 "NPOLLING TX cpu offset"); 3616 #endif 3617 3618 #ifdef EMX_RSS_DEBUG 3619 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3620 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3621 0, "RSS debug level"); 3622 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3623 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i); 3624 SYSCTL_ADD_ULONG(&sc->sysctl_ctx, 3625 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3626 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts, 3627 "RXed packets"); 3628 } 3629 #endif 3630 #ifdef EMX_TSS_DEBUG 3631 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3632 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i); 3633 SYSCTL_ADD_ULONG(&sc->sysctl_ctx, 3634 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3635 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts, 3636 "TXed packets"); 3637 } 3638 #endif 3639 } 3640 3641 static int 3642 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3643 { 3644 struct emx_softc *sc = (void *)arg1; 3645 struct ifnet *ifp = &sc->arpcom.ac_if; 3646 int error, throttle; 3647 3648 throttle = sc->int_throttle_ceil; 3649 error = sysctl_handle_int(oidp, &throttle, 0, req); 3650 if (error || req->newptr == NULL) 3651 return error; 3652 if (throttle < 0 || throttle > 1000000000 / 256) 3653 return EINVAL; 3654 3655 if (throttle) { 3656 /* 3657 * Set the interrupt throttling rate in 256ns increments, 3658 * recalculate sysctl value assignment to get exact frequency. 3659 */ 3660 throttle = 1000000000 / 256 / throttle; 3661 3662 /* Upper 16bits of ITR is reserved and should be zero */ 3663 if (throttle & 0xffff0000) 3664 return EINVAL; 3665 } 3666 3667 ifnet_serialize_all(ifp); 3668 3669 if (throttle) 3670 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3671 else 3672 sc->int_throttle_ceil = 0; 3673 3674 if (ifp->if_flags & IFF_RUNNING) 3675 emx_set_itr(sc, throttle); 3676 3677 ifnet_deserialize_all(ifp); 3678 3679 if (bootverbose) { 3680 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3681 sc->int_throttle_ceil); 3682 } 3683 return 0; 3684 } 3685 3686 static int 3687 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS) 3688 { 3689 struct emx_softc *sc = (void *)arg1; 3690 struct ifnet *ifp = &sc->arpcom.ac_if; 3691 struct emx_txdata *tdata = &sc->tx_data[0]; 3692 int error, segs; 3693 3694 segs = tdata->tx_intr_nsegs; 3695 error = sysctl_handle_int(oidp, &segs, 0, req); 3696 if (error || req->newptr == NULL) 3697 return error; 3698 if (segs <= 0) 3699 return EINVAL; 3700 3701 ifnet_serialize_all(ifp); 3702 3703 /* 3704 * Don't allow tx_intr_nsegs to become: 3705 * o Less the oact_tx_desc 3706 * o Too large that no TX desc will cause TX interrupt to 3707 * be generated (OACTIVE will never recover) 3708 * o Too small that will cause tx_dd[] overflow 3709 */ 3710 if (segs < tdata->oact_tx_desc || 3711 segs >= tdata->num_tx_desc - tdata->oact_tx_desc || 3712 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) { 3713 error = EINVAL; 3714 } else { 3715 int i; 3716 3717 error = 0; 3718 for (i = 0; i < sc->tx_ring_cnt; ++i) 3719 sc->tx_data[i].tx_intr_nsegs = segs; 3720 } 3721 3722 ifnet_deserialize_all(ifp); 3723 3724 return error; 3725 } 3726 3727 static int 3728 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS) 3729 { 3730 struct emx_softc *sc = (void *)arg1; 3731 struct ifnet *ifp = &sc->arpcom.ac_if; 3732 int error, nsegs, i; 3733 3734 nsegs = sc->tx_data[0].tx_wreg_nsegs; 3735 error = sysctl_handle_int(oidp, &nsegs, 0, req); 3736 if (error || req->newptr == NULL) 3737 return error; 3738 3739 ifnet_serialize_all(ifp); 3740 for (i = 0; i < sc->tx_ring_cnt; ++i) 3741 sc->tx_data[i].tx_wreg_nsegs =nsegs; 3742 ifnet_deserialize_all(ifp); 3743 3744 return 0; 3745 } 3746 3747 #ifdef IFPOLL_ENABLE 3748 3749 static int 3750 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3751 { 3752 struct emx_softc *sc = (void *)arg1; 3753 struct ifnet *ifp = &sc->arpcom.ac_if; 3754 int error, off; 3755 3756 off = sc->rx_npoll_off; 3757 error = sysctl_handle_int(oidp, &off, 0, req); 3758 if (error || req->newptr == NULL) 3759 return error; 3760 if (off < 0) 3761 return EINVAL; 3762 3763 ifnet_serialize_all(ifp); 3764 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) { 3765 error = EINVAL; 3766 } else { 3767 error = 0; 3768 sc->rx_npoll_off = off; 3769 } 3770 ifnet_deserialize_all(ifp); 3771 3772 return error; 3773 } 3774 3775 static int 3776 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3777 { 3778 struct emx_softc *sc = (void *)arg1; 3779 struct ifnet *ifp = &sc->arpcom.ac_if; 3780 int error, off; 3781 3782 off = sc->tx_npoll_off; 3783 error = sysctl_handle_int(oidp, &off, 0, req); 3784 if (error || req->newptr == NULL) 3785 return error; 3786 if (off < 0) 3787 return EINVAL; 3788 3789 ifnet_serialize_all(ifp); 3790 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) { 3791 error = EINVAL; 3792 } else { 3793 error = 0; 3794 sc->tx_npoll_off = off; 3795 } 3796 ifnet_deserialize_all(ifp); 3797 3798 return error; 3799 } 3800 3801 #endif /* IFPOLL_ENABLE */ 3802 3803 static int 3804 emx_dma_alloc(struct emx_softc *sc) 3805 { 3806 int error, i; 3807 3808 /* 3809 * Create top level busdma tag 3810 */ 3811 error = bus_dma_tag_create(NULL, 1, 0, 3812 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3813 NULL, NULL, 3814 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3815 0, &sc->parent_dtag); 3816 if (error) { 3817 device_printf(sc->dev, "could not create top level DMA tag\n"); 3818 return error; 3819 } 3820 3821 /* 3822 * Allocate transmit descriptors ring and buffers 3823 */ 3824 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3825 error = emx_create_tx_ring(&sc->tx_data[i]); 3826 if (error) { 3827 device_printf(sc->dev, 3828 "Could not setup transmit structures\n"); 3829 return error; 3830 } 3831 } 3832 3833 /* 3834 * Allocate receive descriptors ring and buffers 3835 */ 3836 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3837 error = emx_create_rx_ring(&sc->rx_data[i]); 3838 if (error) { 3839 device_printf(sc->dev, 3840 "Could not setup receive structures\n"); 3841 return error; 3842 } 3843 } 3844 return 0; 3845 } 3846 3847 static void 3848 emx_dma_free(struct emx_softc *sc) 3849 { 3850 int i; 3851 3852 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3853 emx_destroy_tx_ring(&sc->tx_data[i], 3854 sc->tx_data[i].num_tx_desc); 3855 } 3856 3857 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3858 emx_destroy_rx_ring(&sc->rx_data[i], 3859 sc->rx_data[i].num_rx_desc); 3860 } 3861 3862 /* Free top level busdma tag */ 3863 if (sc->parent_dtag != NULL) 3864 bus_dma_tag_destroy(sc->parent_dtag); 3865 } 3866 3867 static void 3868 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3869 { 3870 struct emx_softc *sc = ifp->if_softc; 3871 3872 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz); 3873 } 3874 3875 static void 3876 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3877 { 3878 struct emx_softc *sc = ifp->if_softc; 3879 3880 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz); 3881 } 3882 3883 static int 3884 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3885 { 3886 struct emx_softc *sc = ifp->if_softc; 3887 3888 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz); 3889 } 3890 3891 static void 3892 emx_serialize_skipmain(struct emx_softc *sc) 3893 { 3894 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3895 } 3896 3897 static void 3898 emx_deserialize_skipmain(struct emx_softc *sc) 3899 { 3900 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3901 } 3902 3903 #ifdef INVARIANTS 3904 3905 static void 3906 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3907 boolean_t serialized) 3908 { 3909 struct emx_softc *sc = ifp->if_softc; 3910 3911 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3912 slz, serialized); 3913 } 3914 3915 #endif /* INVARIANTS */ 3916 3917 #ifdef IFPOLL_ENABLE 3918 3919 static void 3920 emx_npoll_status(struct ifnet *ifp) 3921 { 3922 struct emx_softc *sc = ifp->if_softc; 3923 uint32_t reg_icr; 3924 3925 ASSERT_SERIALIZED(&sc->main_serialize); 3926 3927 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3928 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3929 callout_stop(&sc->timer); 3930 sc->hw.mac.get_link_status = 1; 3931 emx_update_link_status(sc); 3932 callout_reset(&sc->timer, hz, emx_timer, sc); 3933 } 3934 } 3935 3936 static void 3937 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3938 { 3939 struct emx_txdata *tdata = arg; 3940 3941 ASSERT_SERIALIZED(&tdata->tx_serialize); 3942 3943 emx_txeof(tdata); 3944 if (!ifsq_is_empty(tdata->ifsq)) 3945 ifsq_devstart(tdata->ifsq); 3946 } 3947 3948 static void 3949 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3950 { 3951 struct emx_rxdata *rdata = arg; 3952 3953 ASSERT_SERIALIZED(&rdata->rx_serialize); 3954 3955 emx_rxeof(rdata, cycle); 3956 } 3957 3958 static void 3959 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3960 { 3961 struct emx_softc *sc = ifp->if_softc; 3962 int i, txr_cnt; 3963 3964 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3965 3966 if (info) { 3967 int off; 3968 3969 info->ifpi_status.status_func = emx_npoll_status; 3970 info->ifpi_status.serializer = &sc->main_serialize; 3971 3972 txr_cnt = emx_get_txring_inuse(sc, TRUE); 3973 off = sc->tx_npoll_off; 3974 for (i = 0; i < txr_cnt; ++i) { 3975 struct emx_txdata *tdata = &sc->tx_data[i]; 3976 int idx = i + off; 3977 3978 KKASSERT(idx < ncpus2); 3979 info->ifpi_tx[idx].poll_func = emx_npoll_tx; 3980 info->ifpi_tx[idx].arg = tdata; 3981 info->ifpi_tx[idx].serializer = &tdata->tx_serialize; 3982 ifsq_set_cpuid(tdata->ifsq, idx); 3983 } 3984 3985 off = sc->rx_npoll_off; 3986 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3987 struct emx_rxdata *rdata = &sc->rx_data[i]; 3988 int idx = i + off; 3989 3990 KKASSERT(idx < ncpus2); 3991 info->ifpi_rx[idx].poll_func = emx_npoll_rx; 3992 info->ifpi_rx[idx].arg = rdata; 3993 info->ifpi_rx[idx].serializer = &rdata->rx_serialize; 3994 } 3995 3996 if (ifp->if_flags & IFF_RUNNING) { 3997 if (txr_cnt == sc->tx_ring_inuse) 3998 emx_disable_intr(sc); 3999 else 4000 emx_init(sc); 4001 } 4002 } else { 4003 for (i = 0; i < sc->tx_ring_cnt; ++i) { 4004 struct emx_txdata *tdata = &sc->tx_data[i]; 4005 4006 ifsq_set_cpuid(tdata->ifsq, 4007 rman_get_cpuid(sc->intr_res)); 4008 } 4009 4010 if (ifp->if_flags & IFF_RUNNING) { 4011 txr_cnt = emx_get_txring_inuse(sc, FALSE); 4012 if (txr_cnt == sc->tx_ring_inuse) 4013 emx_enable_intr(sc); 4014 else 4015 emx_init(sc); 4016 } 4017 } 4018 } 4019 4020 #endif /* IFPOLL_ENABLE */ 4021 4022 static void 4023 emx_set_itr(struct emx_softc *sc, uint32_t itr) 4024 { 4025 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 4026 if (sc->hw.mac.type == e1000_82574) { 4027 int i; 4028 4029 /* 4030 * When using MSIX interrupts we need to 4031 * throttle using the EITR register 4032 */ 4033 for (i = 0; i < 4; ++i) 4034 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 4035 } 4036 } 4037 4038 /* 4039 * Disable the L0s, 82574L Errata #20 4040 */ 4041 static void 4042 emx_disable_aspm(struct emx_softc *sc) 4043 { 4044 uint16_t link_cap, link_ctrl, disable; 4045 uint8_t pcie_ptr, reg; 4046 device_t dev = sc->dev; 4047 4048 switch (sc->hw.mac.type) { 4049 case e1000_82571: 4050 case e1000_82572: 4051 case e1000_82573: 4052 /* 4053 * 82573 specification update 4054 * errata #8 disable L0s 4055 * errata #41 disable L1 4056 * 4057 * 82571/82572 specification update 4058 # errata #13 disable L1 4059 * errata #68 disable L0s 4060 */ 4061 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4062 break; 4063 4064 case e1000_82574: 4065 /* 4066 * 82574 specification update errata #20 4067 * 4068 * There is no need to disable L1 4069 */ 4070 disable = PCIEM_LNKCTL_ASPM_L0S; 4071 break; 4072 4073 default: 4074 return; 4075 } 4076 4077 pcie_ptr = pci_get_pciecap_ptr(dev); 4078 if (pcie_ptr == 0) 4079 return; 4080 4081 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4082 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4083 return; 4084 4085 if (bootverbose) 4086 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable); 4087 4088 reg = pcie_ptr + PCIER_LINKCTRL; 4089 link_ctrl = pci_read_config(dev, reg, 2); 4090 link_ctrl &= ~disable; 4091 pci_write_config(dev, reg, link_ctrl, 2); 4092 } 4093 4094 static int 4095 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp) 4096 { 4097 int iphlen, hoff, thoff, ex = 0; 4098 struct mbuf *m; 4099 struct ip *ip; 4100 4101 m = *mp; 4102 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4103 4104 iphlen = m->m_pkthdr.csum_iphlen; 4105 thoff = m->m_pkthdr.csum_thlen; 4106 hoff = m->m_pkthdr.csum_lhlen; 4107 4108 KASSERT(iphlen > 0, ("invalid ip hlen")); 4109 KASSERT(thoff > 0, ("invalid tcp hlen")); 4110 KASSERT(hoff > 0, ("invalid ether hlen")); 4111 4112 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX) 4113 ex = 4; 4114 4115 if (m->m_len < hoff + iphlen + thoff + ex) { 4116 m = m_pullup(m, hoff + iphlen + thoff + ex); 4117 if (m == NULL) { 4118 *mp = NULL; 4119 return ENOBUFS; 4120 } 4121 *mp = m; 4122 } 4123 ip = mtodoff(m, struct ip *, hoff); 4124 ip->ip_len = 0; 4125 4126 return 0; 4127 } 4128 4129 static int 4130 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp, 4131 uint32_t *txd_upper, uint32_t *txd_lower) 4132 { 4133 struct e1000_context_desc *TXD; 4134 int hoff, iphlen, thoff, hlen; 4135 int mss, pktlen, curr_txd; 4136 4137 #ifdef EMX_TSO_DEBUG 4138 tdata->tso_segments++; 4139 #endif 4140 4141 iphlen = mp->m_pkthdr.csum_iphlen; 4142 thoff = mp->m_pkthdr.csum_thlen; 4143 hoff = mp->m_pkthdr.csum_lhlen; 4144 mss = mp->m_pkthdr.tso_segsz; 4145 pktlen = mp->m_pkthdr.len; 4146 4147 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 4148 tdata->csum_flags == CSUM_TSO && 4149 tdata->csum_iphlen == iphlen && 4150 tdata->csum_lhlen == hoff && 4151 tdata->csum_thlen == thoff && 4152 tdata->csum_mss == mss && 4153 tdata->csum_pktlen == pktlen) { 4154 *txd_upper = tdata->csum_txd_upper; 4155 *txd_lower = tdata->csum_txd_lower; 4156 #ifdef EMX_TSO_DEBUG 4157 tdata->tso_ctx_reused++; 4158 #endif 4159 return 0; 4160 } 4161 hlen = hoff + iphlen + thoff; 4162 4163 /* 4164 * Setup a new TSO context. 4165 */ 4166 4167 curr_txd = tdata->next_avail_tx_desc; 4168 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 4169 4170 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4171 E1000_TXD_DTYP_D | /* Data descr type */ 4172 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4173 4174 /* IP and/or TCP header checksum calculation and insertion. */ 4175 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4176 4177 /* 4178 * Start offset for header checksum calculation. 4179 * End offset for header checksum calculation. 4180 * Offset of place put the checksum. 4181 */ 4182 TXD->lower_setup.ip_fields.ipcss = hoff; 4183 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4184 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4185 4186 /* 4187 * Start offset for payload checksum calculation. 4188 * End offset for payload checksum calculation. 4189 * Offset of place to put the checksum. 4190 */ 4191 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4192 TXD->upper_setup.tcp_fields.tucse = 0; 4193 TXD->upper_setup.tcp_fields.tucso = 4194 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4195 4196 /* 4197 * Payload size per packet w/o any headers. 4198 * Length of all headers up to payload. 4199 */ 4200 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4201 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4202 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4203 E1000_TXD_CMD_DEXT | /* Extended descr */ 4204 E1000_TXD_CMD_TSE | /* TSE context */ 4205 E1000_TXD_CMD_IP | /* Do IP csum */ 4206 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4207 (pktlen - hlen)); /* Total len */ 4208 4209 /* Save the information for this TSO context */ 4210 tdata->csum_flags = CSUM_TSO; 4211 tdata->csum_lhlen = hoff; 4212 tdata->csum_iphlen = iphlen; 4213 tdata->csum_thlen = thoff; 4214 tdata->csum_mss = mss; 4215 tdata->csum_pktlen = pktlen; 4216 tdata->csum_txd_upper = *txd_upper; 4217 tdata->csum_txd_lower = *txd_lower; 4218 4219 if (++curr_txd == tdata->num_tx_desc) 4220 curr_txd = 0; 4221 4222 KKASSERT(tdata->num_tx_desc_avail > 0); 4223 tdata->num_tx_desc_avail--; 4224 4225 tdata->next_avail_tx_desc = curr_txd; 4226 return 1; 4227 } 4228 4229 static int 4230 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling) 4231 { 4232 if (polling) 4233 return sc->tx_ring_cnt; 4234 else 4235 return 1; 4236 } 4237