1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EM_H_ 33 #define _IF_EM_H_ 34 35 /* Tunables */ 36 37 /* 38 * EM_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256 for 82542 and 82543-based adapters 40 * 256-4096 for others 41 * Default Value: 256 42 * This value is the number of transmit descriptors allocated by the driver. 43 * Increasing this value allows the driver to queue more transmits. Each 44 * descriptor is 16 bytes. 45 * Since TDLEN should be multiple of 128bytes, the number of transmit 46 * desscriptors should meet the following condition. 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 48 */ 49 #define EM_MIN_TXD 256 50 #define EM_MAX_TXD_82543 EM_MIN_TXD 51 #define EM_MAX_TXD 4096 52 #define EM_DEFAULT_TXD EM_MIN_TXD 53 54 /* 55 * EM_RXD - Maximum number of receive Descriptors 56 * Valid Range: 256 for 82542 and 82543-based adapters 57 * 256-4096 for others 58 * Default Value: 256 59 * This value is the number of receive descriptors allocated by the driver. 60 * Increasing this value allows the driver to buffer more incoming packets. 61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 62 * descriptor. The maximum MTU size is 16110. 63 * Since TDLEN should be multiple of 128bytes, the number of transmit 64 * desscriptors should meet the following condition. 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 66 */ 67 #define EM_MIN_RXD 256 68 #define EM_MAX_RXD_82543 EM_MIN_RXD 69 #define EM_MAX_RXD 4096 70 #define EM_DEFAULT_RXD EM_MIN_RXD 71 72 /* 73 * EM_TIDV - Transmit Interrupt Delay Value 74 * Valid Range: 0-65535 (0=off) 75 * Default Value: 64 76 * This value delays the generation of transmit interrupts in units of 77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 78 * efficiency if properly tuned for specific network traffic. If the 79 * system is reporting dropped transmits, this value may be set too high 80 * causing the driver to run out of available transmit descriptors. 81 */ 82 #define EM_TIDV 64 83 84 /* 85 * EM_TADV - Transmit Absolute Interrupt Delay Value 86 * (Not valid for 82542/82543/82544) 87 * Valid Range: 0-65535 (0=off) 88 * Default Value: 64 89 * This value, in units of 1.024 microseconds, limits the delay in which a 90 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 91 * this value ensures that an interrupt is generated after the initial 92 * packet is sent on the wire within the set amount of time. Proper tuning, 93 * along with EM_TIDV, may improve traffic throughput in specific 94 * network conditions. 95 */ 96 #define EM_TADV 64 97 98 /* 99 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 100 * Valid Range: 0-65535 (0=off) 101 * Default Value: 0 102 * This value delays the generation of receive interrupts in units of 1.024 103 * microseconds. Receive interrupt reduction can improve CPU efficiency if 104 * properly tuned for specific network traffic. Increasing this value adds 105 * extra latency to frame reception and can end up decreasing the throughput 106 * of TCP traffic. If the system is reporting dropped receives, this value 107 * may be set too high, causing the driver to run out of available receive 108 * descriptors. 109 * 110 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 111 * may hang (stop transmitting) under certain network conditions. 112 * If this occurs a WATCHDOG message is logged in the system 113 * event log. In addition, the controller is automatically reset, 114 * restoring the network connection. To eliminate the potential 115 * for the hang ensure that EM_RDTR is set to 0. 116 */ 117 #define EM_RDTR 0 118 119 /* 120 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 121 * Valid Range: 0-65535 (0=off) 122 * Default Value: 64 123 * This value, in units of 1.024 microseconds, limits the delay in which a 124 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 125 * this value ensures that an interrupt is generated after the initial 126 * packet is received within the set amount of time. Proper tuning, 127 * along with EM_RDTR, may improve traffic throughput in specific network 128 * conditions. 129 */ 130 #define EM_RADV 64 131 132 /* 133 * This parameter controls the duration of transmit watchdog timer. 134 */ 135 #define EM_TX_TIMEOUT 5 136 137 /* One for TX csum offloading desc, the other is reserved */ 138 #define EM_TX_RESERVED 2 139 140 /* Large enough for 16K jumbo frame */ 141 #define EM_TX_SPARE 8 142 143 #define EM_TX_OACTIVE_MAX 64 144 145 /* Interrupt throttle rate */ 146 #define EM_DEFAULT_ITR 10000 147 148 /* 149 * This parameter controls whether or not autonegotation is enabled. 150 * 0 - Disable autonegotiation 151 * 1 - Enable autonegotiation 152 */ 153 #define DO_AUTO_NEG 1 154 155 /* 156 * This parameter control whether or not the driver will wait for 157 * autonegotiation to complete. 158 * 1 - Wait for autonegotiation to complete 159 * 0 - Don't wait for autonegotiation to complete 160 */ 161 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 162 163 /* Tunables -- End */ 164 165 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 166 ADVERTISE_10_FULL | \ 167 ADVERTISE_100_HALF | \ 168 ADVERTISE_100_FULL | \ 169 ADVERTISE_1000_FULL) 170 171 #define AUTO_ALL_MODES 0 172 173 /* PHY master/slave setting */ 174 #define EM_MASTER_SLAVE e1000_ms_hw_default 175 176 /* 177 * Micellaneous constants 178 */ 179 #define EM_VENDOR_ID 0x8086 180 181 #define EM_BAR_MEM PCIR_BAR(0) 182 #define EM_BAR_FLASH PCIR_BAR(1) 183 184 #define EM_JUMBO_PBA 0x00000028 185 #define EM_DEFAULT_PBA 0x00000030 186 #define EM_SMARTSPEED_DOWNSHIFT 3 187 #define EM_SMARTSPEED_MAX 15 188 #define EM_MAX_INTR 10 189 190 #define MAX_NUM_MULTICAST_ADDRESSES 128 191 #define PCI_ANY_ID (~0U) 192 #define EM_FC_PAUSE_TIME 1000 193 #define EM_EEPROM_APME 0x400; 194 195 /* 196 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 197 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 198 * also optimize cache line size effect. H/W supports up to cache line size 128. 199 */ 200 #define EM_DBA_ALIGN 128 201 202 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 203 204 /* PCI Config defines */ 205 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 206 #define EM_BAR_TYPE_MASK 0x00000001 207 #define EM_BAR_TYPE_MMEM 0x00000000 208 #define EM_BAR_TYPE_IO 0x00000001 209 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 210 #define EM_BAR_MEM_TYPE_MASK 0x00000006 211 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 212 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 213 214 #define EM_MAX_SCATTER 64 215 #define EM_TSO_SIZE (65535 + \ 216 sizeof(struct ether_vlan_header)) 217 #define EM_MAX_SEGSIZE 4096 218 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 219 #define ETH_ZLEN 60 220 221 #define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 222 #define EM_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */ 223 #define EM_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \ 224 EM_IPVHL_SIZE) 225 226 /* 227 * 82574 has a nonstandard address for EIAC 228 * and since its only used in MSIX, and in 229 * the em driver only 82574 uses MSIX we can 230 * solve it just using this define. 231 */ 232 #define EM_EIAC 0x000DC 233 234 /* Used in for 82547 10Mb Half workaround */ 235 #define EM_PBA_BYTES_SHIFT 0xA 236 #define EM_TX_HEAD_ADDR_SHIFT 7 237 #define EM_PBA_TX_MASK 0xFFFF0000 238 #define EM_FIFO_HDR 0x10 239 #define EM_82547_PKT_THRESH 0x3e0 240 241 struct adapter; 242 243 struct em_int_delay_info { 244 struct adapter *adapter; /* Back-pointer to the adapter struct */ 245 int offset; /* Register offset to read/write */ 246 int value; /* Current value in usecs */ 247 }; 248 249 /* 250 * Bus dma allocation structure used by 251 * e1000_dma_malloc and e1000_dma_free. 252 */ 253 struct em_dma_alloc { 254 bus_addr_t dma_paddr; 255 void *dma_vaddr; 256 bus_dma_tag_t dma_tag; 257 bus_dmamap_t dma_map; 258 }; 259 260 /* Our adapter structure */ 261 struct adapter { 262 struct arpcom arpcom; 263 struct e1000_hw hw; 264 265 /* DragonFly operating-system-specific structures. */ 266 struct e1000_osdep osdep; 267 device_t dev; 268 269 bus_dma_tag_t parent_dtag; 270 271 struct resource *memory; 272 int memory_rid; 273 struct resource *flash; 274 int flash_rid; 275 276 struct resource *ioport; 277 int io_rid; 278 279 struct resource *intr_res; 280 void *intr_tag; 281 int intr_rid; 282 283 struct ifmedia media; 284 struct callout timer; 285 struct callout tx_fifo_timer; 286 int if_flags; 287 int max_frame_size; 288 int min_frame_size; 289 290 /* Management and WOL features */ 291 int wol; 292 int has_manage; 293 294 /* Info about the board itself */ 295 uint8_t link_active; 296 uint16_t link_speed; 297 uint16_t link_duplex; 298 uint32_t smartspeed; 299 struct em_int_delay_info tx_int_delay; 300 struct em_int_delay_info tx_abs_int_delay; 301 struct em_int_delay_info rx_int_delay; 302 struct em_int_delay_info rx_abs_int_delay; 303 int int_throttle_ceil; 304 305 /* 306 * Transmit definitions 307 * 308 * We have an array of num_tx_desc descriptors (handled 309 * by the controller) paired with an array of tx_buffers 310 * (at tx_buffer_area). 311 * The index of the next available descriptor is next_avail_tx_desc. 312 * The number of remaining tx_desc is num_tx_desc_avail. 313 */ 314 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 315 struct e1000_tx_desc *tx_desc_base; 316 struct em_buffer *tx_buffer_area; 317 uint32_t next_avail_tx_desc; 318 uint32_t next_tx_to_clean; 319 int num_tx_desc_avail; 320 int num_tx_desc; 321 uint32_t txd_cmd; 322 bus_dma_tag_t txtag; /* dma tag for tx */ 323 int spare_tx_desc; 324 int oact_tx_desc; 325 326 /* Saved csum offloading context information */ 327 int csum_flags; 328 int csum_ehlen; 329 int csum_iphlen; 330 uint32_t csum_txd_upper; 331 uint32_t csum_txd_lower; 332 333 /* 334 * Variables used to reduce TX interrupt rate and 335 * number of device's TX ring write requests. 336 * 337 * tx_nsegs: 338 * Number of TX descriptors setup so far. 339 * 340 * tx_int_nsegs: 341 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 342 * in the last TX descriptor of the packet, and 343 * tx_nsegs will be reset to 0. So TX interrupt and 344 * TX ring write request should be generated roughly 345 * every tx_int_nsegs TX descriptors. 346 * 347 * tx_dd[]: 348 * Index of the TX descriptors which have RS bit set, 349 * i.e. DD bit will be set on this TX descriptor after 350 * the data of the TX descriptor are transfered to 351 * hardware's internal packet buffer. Only the TX 352 * descriptors listed in tx_dd[] will be checked upon 353 * TX interrupt. This array is used as circular ring. 354 * 355 * tx_dd_tail, tx_dd_head: 356 * Tail and head index of valid elements in tx_dd[]. 357 * tx_dd_tail == tx_dd_head means there is no valid 358 * elements in tx_dd[]. tx_dd_tail points to the position 359 * which is one beyond the last valid element in tx_dd[]. 360 * tx_dd_head points to the first valid element in 361 * tx_dd[]. 362 */ 363 int tx_int_nsegs; 364 int tx_nsegs; 365 int tx_dd_tail; 366 int tx_dd_head; 367 #define EM_TXDD_MAX 64 368 #define EM_TXDD_SAFE 50 /* must be less than EM_TXDD_MAX */ 369 int tx_dd[EM_TXDD_MAX]; 370 371 /* 372 * Receive definitions 373 * 374 * we have an array of num_rx_desc rx_desc (handled by the 375 * controller), and paired with an array of rx_buffers 376 * (at rx_buffer_area). 377 * The next pair to check on receive is at offset next_rx_desc_to_check 378 */ 379 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 380 struct e1000_rx_desc *rx_desc_base; 381 uint32_t next_rx_desc_to_check; 382 uint32_t rx_buffer_len; 383 int num_rx_desc; 384 struct em_buffer *rx_buffer_area; 385 bus_dma_tag_t rxtag; 386 bus_dmamap_t rx_sparemap; 387 388 /* 389 * First/last mbuf pointers, for 390 * collecting multisegment RX packets. 391 */ 392 struct mbuf *fmp; 393 struct mbuf *lmp; 394 395 /* Misc stats maintained by the driver */ 396 unsigned long dropped_pkts; 397 unsigned long mbuf_alloc_failed; 398 unsigned long mbuf_cluster_failed; 399 unsigned long no_tx_desc_avail1; 400 unsigned long no_tx_desc_avail2; 401 unsigned long no_tx_map_avail; 402 unsigned long no_tx_dma_setup; 403 unsigned long watchdog_events; 404 unsigned long rx_overruns; 405 unsigned long rx_irq; 406 unsigned long tx_irq; 407 unsigned long link_irq; 408 unsigned long tx_csum_try_pullup; 409 unsigned long tx_csum_pullup1; 410 unsigned long tx_csum_pullup1_failed; 411 unsigned long tx_csum_pullup2; 412 unsigned long tx_csum_pullup2_failed; 413 unsigned long tx_csum_drop1; 414 unsigned long tx_csum_drop2; 415 416 /* sysctl tree glue */ 417 struct sysctl_ctx_list sysctl_ctx; 418 struct sysctl_oid *sysctl_tree; 419 420 /* 82547 workaround */ 421 uint32_t tx_fifo_size; 422 uint32_t tx_fifo_head; 423 uint32_t tx_fifo_head_addr; 424 uint64_t tx_fifo_reset_cnt; 425 uint64_t tx_fifo_wrk_cnt; 426 uint32_t tx_head_addr; 427 428 /* For 82544 PCIX Workaround */ 429 boolean_t pcix_82544; 430 boolean_t in_detach; 431 432 struct e1000_hw_stats stats; 433 }; 434 435 struct em_vendor_info { 436 uint16_t vendor_id; 437 uint16_t device_id; 438 const char *desc; 439 }; 440 441 struct em_buffer { 442 struct mbuf *m_head; 443 bus_dmamap_t map; /* bus_dma map for packet */ 444 }; 445 446 /* For 82544 PCIX Workaround */ 447 typedef struct _ADDRESS_LENGTH_PAIR { 448 uint64_t address; 449 uint32_t length; 450 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 451 452 typedef struct _DESCRIPTOR_PAIR { 453 ADDRESS_LENGTH_PAIR descriptor[4]; 454 uint32_t elements; 455 } DESC_ARRAY, *PDESC_ARRAY; 456 457 #define EM_IS_OACTIVE(adapter) \ 458 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc) 459 460 #define EM_INC_TXDD_IDX(idx) \ 461 do { \ 462 if (++(idx) == EM_TXDD_MAX) \ 463 (idx) = 0; \ 464 } while (0) 465 466 #endif /* _IF_EM_H_ */ 467