1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EM_H_ 33 #define _IF_EM_H_ 34 35 /* Tunables */ 36 37 /* 38 * EM_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 80-256 for 82542 and 82543-based adapters 40 * 80-4096 for others 41 * Default Value: 256 42 * This value is the number of transmit descriptors allocated by the driver. 43 * Increasing this value allows the driver to queue more transmits. Each 44 * descriptor is 16 bytes. 45 * Since TDLEN should be multiple of 128bytes, the number of transmit 46 * desscriptors should meet the following condition. 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 48 */ 49 #define EM_MIN_TXD 80 50 #define EM_MAX_TXD_82543 256 51 #define EM_MAX_TXD 4096 52 #define EM_DEFAULT_TXD EM_MAX_TXD_82543 53 54 /* 55 * EM_RXD - Maximum number of receive Descriptors 56 * Valid Range: 80-256 for 82542 and 82543-based adapters 57 * 80-4096 for others 58 * Default Value: 256 59 * This value is the number of receive descriptors allocated by the driver. 60 * Increasing this value allows the driver to buffer more incoming packets. 61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 62 * descriptor. The maximum MTU size is 16110. 63 * Since TDLEN should be multiple of 128bytes, the number of transmit 64 * desscriptors should meet the following condition. 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 66 */ 67 #define EM_MIN_RXD 80 68 #define EM_MAX_RXD_82543 256 69 #define EM_MAX_RXD 4096 70 #define EM_DEFAULT_RXD EM_MAX_RXD_82543 71 72 /* 73 * EM_TIDV - Transmit Interrupt Delay Value 74 * Valid Range: 0-65535 (0=off) 75 * Default Value: 64 76 * This value delays the generation of transmit interrupts in units of 77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 78 * efficiency if properly tuned for specific network traffic. If the 79 * system is reporting dropped transmits, this value may be set too high 80 * causing the driver to run out of available transmit descriptors. 81 */ 82 #define EM_TIDV 64 83 84 /* 85 * EM_TADV - Transmit Absolute Interrupt Delay Value 86 * (Not valid for 82542/82543/82544) 87 * Valid Range: 0-65535 (0=off) 88 * Default Value: 64 89 * This value, in units of 1.024 microseconds, limits the delay in which a 90 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 91 * this value ensures that an interrupt is generated after the initial 92 * packet is sent on the wire within the set amount of time. Proper tuning, 93 * along with EM_TIDV, may improve traffic throughput in specific 94 * network conditions. 95 */ 96 #define EM_TADV 64 97 98 /* 99 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 100 * Valid Range: 0-65535 (0=off) 101 * Default Value: 0 102 * This value delays the generation of receive interrupts in units of 1.024 103 * microseconds. Receive interrupt reduction can improve CPU efficiency if 104 * properly tuned for specific network traffic. Increasing this value adds 105 * extra latency to frame reception and can end up decreasing the throughput 106 * of TCP traffic. If the system is reporting dropped receives, this value 107 * may be set too high, causing the driver to run out of available receive 108 * descriptors. 109 * 110 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 111 * may hang (stop transmitting) under certain network conditions. 112 * If this occurs a WATCHDOG message is logged in the system 113 * event log. In addition, the controller is automatically reset, 114 * restoring the network connection. To eliminate the potential 115 * for the hang ensure that EM_RDTR is set to 0. 116 */ 117 #define EM_RDTR 0 118 119 /* 120 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 121 * Valid Range: 0-65535 (0=off) 122 * Default Value: 64 123 * This value, in units of 1.024 microseconds, limits the delay in which a 124 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 125 * this value ensures that an interrupt is generated after the initial 126 * packet is received within the set amount of time. Proper tuning, 127 * along with EM_RDTR, may improve traffic throughput in specific network 128 * conditions. 129 */ 130 #define EM_RADV 64 131 132 /* 133 * This parameter controls the duration of transmit watchdog timer. 134 */ 135 #define EM_TX_TIMEOUT 5 136 137 /* One for TX csum offloading desc, the other is reserved */ 138 #define EM_TX_RESERVED 2 139 140 /* Large enough for 16K jumbo frame */ 141 #define EM_TX_SPARE 8 142 143 /* Interrupt throttle rate */ 144 #define EM_DEFAULT_ITR 10000 145 146 /* 147 * This parameter controls when the driver calls the routine to reclaim 148 * transmit descriptors. 149 */ 150 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 151 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 152 153 /* 154 * This parameter controls whether or not autonegotation is enabled. 155 * 0 - Disable autonegotiation 156 * 1 - Enable autonegotiation 157 */ 158 #define DO_AUTO_NEG 1 159 160 /* 161 * This parameter control whether or not the driver will wait for 162 * autonegotiation to complete. 163 * 1 - Wait for autonegotiation to complete 164 * 0 - Don't wait for autonegotiation to complete 165 */ 166 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 167 168 /* Tunables -- End */ 169 170 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 171 ADVERTISE_10_FULL | \ 172 ADVERTISE_100_HALF | \ 173 ADVERTISE_100_FULL | \ 174 ADVERTISE_1000_FULL) 175 176 #define AUTO_ALL_MODES 0 177 178 /* PHY master/slave setting */ 179 #define EM_MASTER_SLAVE e1000_ms_hw_default 180 181 /* 182 * Micellaneous constants 183 */ 184 #define EM_VENDOR_ID 0x8086 185 186 #define EM_BAR_MEM PCIR_BAR(0) 187 #define EM_BAR_FLASH PCIR_BAR(1) 188 189 #define EM_JUMBO_PBA 0x00000028 190 #define EM_DEFAULT_PBA 0x00000030 191 #define EM_SMARTSPEED_DOWNSHIFT 3 192 #define EM_SMARTSPEED_MAX 15 193 #define EM_MAX_INTR 10 194 195 #define MAX_NUM_MULTICAST_ADDRESSES 128 196 #define PCI_ANY_ID (~0U) 197 #define EM_FC_PAUSE_TIME 1000 198 #define EM_EEPROM_APME 0x400; 199 200 /* 201 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 202 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 203 * also optimize cache line size effect. H/W supports up to cache line size 128. 204 */ 205 #define EM_DBA_ALIGN 128 206 207 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 208 209 /* PCI Config defines */ 210 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 211 #define EM_BAR_TYPE_MASK 0x00000001 212 #define EM_BAR_TYPE_MMEM 0x00000000 213 #define EM_BAR_TYPE_IO 0x00000001 214 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 215 #define EM_BAR_MEM_TYPE_MASK 0x00000006 216 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 217 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 218 219 #define EM_MAX_SCATTER 64 220 #define EM_TSO_SIZE (65535 + \ 221 sizeof(struct ether_vlan_header)) 222 #define EM_MAX_SEGSIZE 4096 223 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 224 #define ETH_ZLEN 60 225 226 #define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 227 #define CSUM_OFFLOAD (CSUM_IP | CSUM_TCP | CSUM_UDP) 228 229 /* 230 * 82574 has a nonstandard address for EIAC 231 * and since its only used in MSIX, and in 232 * the em driver only 82574 uses MSIX we can 233 * solve it just using this define. 234 */ 235 #define EM_EIAC 0x000DC 236 237 /* Used in for 82547 10Mb Half workaround */ 238 #define EM_PBA_BYTES_SHIFT 0xA 239 #define EM_TX_HEAD_ADDR_SHIFT 7 240 #define EM_PBA_TX_MASK 0xFFFF0000 241 #define EM_FIFO_HDR 0x10 242 #define EM_82547_PKT_THRESH 0x3e0 243 244 struct adapter; 245 246 struct em_int_delay_info { 247 struct adapter *adapter; /* Back-pointer to the adapter struct */ 248 int offset; /* Register offset to read/write */ 249 int value; /* Current value in usecs */ 250 }; 251 252 /* 253 * Bus dma allocation structure used by 254 * e1000_dma_malloc and e1000_dma_free. 255 */ 256 struct em_dma_alloc { 257 bus_addr_t dma_paddr; 258 void *dma_vaddr; 259 bus_dma_tag_t dma_tag; 260 bus_dmamap_t dma_map; 261 }; 262 263 /* Our adapter structure */ 264 struct adapter { 265 struct arpcom arpcom; 266 struct e1000_hw hw; 267 268 /* DragonFly operating-system-specific structures. */ 269 struct e1000_osdep osdep; 270 device_t dev; 271 272 bus_dma_tag_t parent_dtag; 273 274 struct resource *memory; 275 int memory_rid; 276 struct resource *flash; 277 int flash_rid; 278 279 struct resource *ioport; 280 int io_rid; 281 282 struct resource *intr_res; 283 void *intr_tag; 284 int intr_rid; 285 286 struct ifmedia media; 287 struct callout timer; 288 struct callout tx_fifo_timer; 289 int if_flags; 290 int max_frame_size; 291 int min_frame_size; 292 293 /* Management and WOL features */ 294 int wol; 295 int has_manage; 296 297 /* Info about the board itself */ 298 uint8_t link_active; 299 uint16_t link_speed; 300 uint16_t link_duplex; 301 uint32_t smartspeed; 302 struct em_int_delay_info tx_int_delay; 303 struct em_int_delay_info tx_abs_int_delay; 304 struct em_int_delay_info rx_int_delay; 305 struct em_int_delay_info rx_abs_int_delay; 306 int int_throttle_ceil; 307 308 /* 309 * Transmit definitions 310 * 311 * We have an array of num_tx_desc descriptors (handled 312 * by the controller) paired with an array of tx_buffers 313 * (at tx_buffer_area). 314 * The index of the next available descriptor is next_avail_tx_desc. 315 * The number of remaining tx_desc is num_tx_desc_avail. 316 */ 317 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 318 struct e1000_tx_desc *tx_desc_base; 319 uint32_t next_avail_tx_desc; 320 uint32_t next_tx_to_clean; 321 int num_tx_desc_avail; 322 int num_tx_desc; 323 uint32_t txd_cmd; 324 struct em_buffer *tx_buffer_area; 325 bus_dma_tag_t txtag; /* dma tag for tx */ 326 int spare_tx_desc; 327 328 /* 329 * Receive definitions 330 * 331 * we have an array of num_rx_desc rx_desc (handled by the 332 * controller), and paired with an array of rx_buffers 333 * (at rx_buffer_area). 334 * The next pair to check on receive is at offset next_rx_desc_to_check 335 */ 336 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 337 struct e1000_rx_desc *rx_desc_base; 338 uint32_t next_rx_desc_to_check; 339 uint32_t rx_buffer_len; 340 int num_rx_desc; 341 struct em_buffer *rx_buffer_area; 342 bus_dma_tag_t rxtag; 343 bus_dmamap_t rx_sparemap; 344 345 /* 346 * First/last mbuf pointers, for 347 * collecting multisegment RX packets. 348 */ 349 struct mbuf *fmp; 350 struct mbuf *lmp; 351 352 /* Misc stats maintained by the driver */ 353 unsigned long dropped_pkts; 354 unsigned long mbuf_alloc_failed; 355 unsigned long mbuf_cluster_failed; 356 unsigned long no_tx_desc_avail1; 357 unsigned long no_tx_desc_avail2; 358 unsigned long no_tx_map_avail; 359 unsigned long no_tx_dma_setup; 360 unsigned long watchdog_events; 361 unsigned long rx_overruns; 362 unsigned long rx_irq; 363 unsigned long tx_irq; 364 unsigned long link_irq; 365 366 /* sysctl tree glue */ 367 struct sysctl_ctx_list sysctl_ctx; 368 struct sysctl_oid *sysctl_tree; 369 370 /* 82547 workaround */ 371 uint32_t tx_fifo_size; 372 uint32_t tx_fifo_head; 373 uint32_t tx_fifo_head_addr; 374 uint64_t tx_fifo_reset_cnt; 375 uint64_t tx_fifo_wrk_cnt; 376 uint32_t tx_head_addr; 377 378 /* For 82544 PCIX Workaround */ 379 boolean_t pcix_82544; 380 boolean_t in_detach; 381 382 struct e1000_hw_stats stats; 383 }; 384 385 struct em_vendor_info { 386 uint16_t vendor_id; 387 uint16_t device_id; 388 const char *desc; 389 }; 390 391 struct em_buffer { 392 int next_eop; /* Index of the desc to watch */ 393 struct mbuf *m_head; 394 bus_dmamap_t map; /* bus_dma map for packet */ 395 }; 396 397 /* For 82544 PCIX Workaround */ 398 typedef struct _ADDRESS_LENGTH_PAIR { 399 uint64_t address; 400 uint32_t length; 401 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 402 403 typedef struct _DESCRIPTOR_PAIR { 404 ADDRESS_LENGTH_PAIR descriptor[4]; 405 uint32_t elements; 406 } DESC_ARRAY, *PDESC_ARRAY; 407 408 #define EM_IS_OACTIVE(adapter) \ 409 ((adapter)->num_tx_desc_avail < \ 410 (adapter)->spare_tx_desc + EM_TX_RESERVED) 411 412 #endif /* _IF_EM_H_ */ 413