1 /************************************************************************** 2 3 Copyright (c) 2001-2006, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /*$FreeBSD: src/sys/dev/em/if_em.h,v 1.1.2.13 2003/06/09 21:43:41 pdeuskar Exp $*/ 35 /*$DragonFly: src/sys/dev/netif/em/if_em.h,v 1.17 2006/10/25 20:55:56 dillon Exp $*/ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/mbuf.h> 43 #include <sys/protosw.h> 44 #include <sys/socket.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/ktr.h> 50 #include <sys/endian.h> 51 #include <sys/proc.h> 52 #include <sys/sysctl.h> 53 #include <sys/bus.h> 54 #include <sys/rman.h> 55 #include <sys/serialize.h> 56 #include <sys/thread2.h> 57 58 #include <net/if.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 64 #include <net/bpf.h> 65 #include <net/if_types.h> 66 #include <net/vlan/if_vlan_var.h> 67 68 #include <netinet/in_systm.h> 69 #include <netinet/in.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 77 #include <machine/clock.h> 78 79 #include <bus/pci/pcivar.h> 80 #include <bus/pci/pcireg.h> 81 82 #include <dev/netif/em/if_em_hw.h> 83 84 /* Tunables */ 85 86 /* 87 * EM_TXD: Maximum number of Transmit Descriptors 88 * Valid Range: 80-256 for 82542 and 82543-based adapters 89 * 80-4096 for others 90 * Default Value: 256 91 * This value is the number of transmit descriptors allocated by the driver. 92 * Increasing this value allows the driver to queue more transmits. Each 93 * descriptor is 16 bytes. 94 * Since TDLEN should be multiple of 128bytes, the number of transmit 95 * desscriptors should meet the following condition. 96 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 97 */ 98 #define EM_MIN_TXD 80 99 #define EM_MAX_TXD_82543 256 100 #define EM_MAX_TXD 4096 101 #define EM_DEFAULT_TXD EM_MAX_TXD_82543 102 103 /* 104 * EM_RXD - Maximum number of receive Descriptors 105 * Valid Range: 80-256 for 82542 and 82543-based adapters 106 * 80-4096 for others 107 * Default Value: 256 108 * This value is the number of receive descriptors allocated by the driver. 109 * Increasing this value allows the driver to buffer more incoming packets. 110 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 111 * descriptor. The maximum MTU size is 16110. 112 * Since TDLEN should be multiple of 128bytes, the number of transmit 113 * desscriptors should meet the following condition. 114 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 115 */ 116 #define EM_MIN_RXD 80 117 #define EM_MAX_RXD_82543 256 118 #define EM_MAX_RXD 4096 119 #define EM_DEFAULT_RXD EM_MAX_RXD_82543 120 121 /* 122 * EM_TIDV - Transmit Interrupt Delay Value 123 * Valid Range: 0-65535 (0=off) 124 * Default Value: 64 125 * This value delays the generation of transmit interrupts in units of 126 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 127 * efficiency if properly tuned for specific network traffic. If the 128 * system is reporting dropped transmits, this value may be set too high 129 * causing the driver to run out of available transmit descriptors. 130 */ 131 #define EM_TIDV 64 132 133 /* 134 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 135 * Valid Range: 0-65535 (0=off) 136 * Default Value: 64 137 * This value, in units of 1.024 microseconds, limits the delay in which a 138 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 139 * this value ensures that an interrupt is generated after the initial 140 * packet is sent on the wire within the set amount of time. Proper tuning, 141 * along with EM_TIDV, may improve traffic throughput in specific 142 * network conditions. 143 */ 144 #define EM_TADV 64 145 146 /* 147 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 148 * Valid Range: 0-65535 (0=off) 149 * Default Value: 0 150 * This value delays the generation of receive interrupts in units of 1.024 151 * microseconds. Receive interrupt reduction can improve CPU efficiency if 152 * properly tuned for specific network traffic. Increasing this value adds 153 * extra latency to frame reception and can end up decreasing the throughput 154 * of TCP traffic. If the system is reporting dropped receives, this value 155 * may be set too high, causing the driver to run out of available receive 156 * descriptors. 157 * 158 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 159 * may hang (stop transmitting) under certain network conditions. 160 * If this occurs a WATCHDOG message is logged in the system event log. 161 * In addition, the controller is automatically reset, restoring the 162 * network connection. To eliminate the potential for the hang 163 * ensure that EM_RDTR is set to 0. 164 */ 165 #define EM_RDTR 0 166 167 /* 168 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 169 * Valid Range: 0-65535 (0=off) 170 * Default Value: 64 171 * This value, in units of 1.024 microseconds, limits the delay in which a 172 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 173 * this value ensures that an interrupt is generated after the initial 174 * packet is received within the set amount of time. Proper tuning, 175 * along with EM_RDTR, may improve traffic throughput in specific network 176 * conditions. 177 */ 178 #define EM_RADV 64 179 180 /* 181 * Inform the stack about transmit checksum offload capabilities. 182 */ 183 #define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 184 185 /* 186 * This parameter controls the duration of transmit watchdog timer. 187 */ 188 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 189 190 /* 191 * This parameter controls when the driver calls the routine to reclaim 192 * transmit descriptors. 193 */ 194 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 195 196 /* 197 * This parameter controls whether or not autonegotation is enabled. 198 * 0 - Disable autonegotiation 199 * 1 - Enable autonegotiation 200 */ 201 #define DO_AUTO_NEG 1 202 203 /* 204 * This parameter control whether or not the driver will wait for 205 * autonegotiation to complete. 206 * 1 - Wait for autonegotiation to complete 207 * 0 - Don't wait for autonegotiation to complete 208 */ 209 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 210 211 /* 212 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 213 * compatibility issue with 82541/82547 devices and some switches. 214 * See the "Known Limitations" section of the README file for a complete 215 * description and a list of affected switches. 216 * 217 * 0 = Hardware default 218 * 1 = Master mode 219 * 2 = Slave mode 220 * 3 = Auto master/slave 221 */ 222 /* #define EM_MASTER_SLAVE 2 */ 223 224 /* Tunables -- End */ 225 226 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 227 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 228 ADVERTISE_1000_FULL) 229 230 #define EM_VENDOR_ID 0x8086 231 #define EM_MMBA 0x0010 /* Mem base address */ 232 #define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 233 234 #define EM_JUMBO_PBA 0x00000028 235 #define EM_DEFAULT_PBA 0x00000030 236 #define EM_SMARTSPEED_DOWNSHIFT 3 237 #define EM_SMARTSPEED_MAX 15 238 239 240 #define MAX_NUM_MULTICAST_ADDRESSES 128 241 #define PCI_ANY_ID (~0U) 242 #define ETHER_ALIGN 2 243 #define EM_DBA_ALIGN 128 244 245 /* Defines for printing debug information */ 246 #define DEBUG_INIT 0 247 #define DEBUG_IOCTL 0 248 #define DEBUG_HW 0 249 250 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 251 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 252 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 253 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 254 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 255 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 256 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 257 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 258 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 259 260 261 /* Supported RX Buffer Sizes */ 262 #define EM_RXBUFFER_2048 2048 263 #define EM_RXBUFFER_4096 4096 264 #define EM_RXBUFFER_8192 8192 265 #define EM_RXBUFFER_16384 16384 266 267 #define EM_MAX_SCATTER 64 268 269 /* ****************************************************************************** 270 * vendor_info_array 271 * 272 * This array contains the list of Subvendor/Subdevice IDs on which the driver 273 * should load. 274 * 275 * ******************************************************************************/ 276 typedef struct _em_vendor_info_t { 277 unsigned int vendor_id; 278 unsigned int device_id; 279 unsigned int subvendor_id; 280 unsigned int subdevice_id; 281 unsigned int index; 282 } em_vendor_info_t; 283 284 285 struct em_buffer { 286 struct mbuf *m_head; 287 bus_dmamap_t map; /* bus_dma map for packet */ 288 }; 289 290 struct em_q { 291 int nsegs; /* # of segments/descriptors */ 292 bus_dma_segment_t segs[EM_MAX_SCATTER]; 293 }; 294 295 /* 296 * Bus dma allocation structure used by 297 * em_dma_malloc and em_dma_free. 298 */ 299 struct em_dma_alloc { 300 bus_addr_t dma_paddr; 301 caddr_t dma_vaddr; 302 bus_dma_tag_t dma_tag; 303 bus_dmamap_t dma_map; 304 bus_dma_segment_t dma_seg; 305 bus_size_t dma_size; 306 int dma_nseg; 307 }; 308 309 typedef enum _XSUM_CONTEXT_T { 310 OFFLOAD_NONE, 311 OFFLOAD_TCP_IP, 312 OFFLOAD_UDP_IP 313 } XSUM_CONTEXT_T; 314 315 struct adapter; 316 struct em_int_delay_info { 317 struct adapter *adapter; /* Back-pointer to the adapter struct */ 318 int offset; /* Register offset to read/write */ 319 int value; /* Current value in usecs */ 320 }; 321 322 /* For 82544 PCIX Workaround */ 323 typedef struct _ADDRESS_LENGTH_PAIR 324 { 325 u_int64_t address; 326 u_int32_t length; 327 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 328 329 typedef struct _DESCRIPTOR_PAIR 330 { 331 ADDRESS_LENGTH_PAIR descriptor[4]; 332 u_int32_t elements; 333 } DESC_ARRAY, *PDESC_ARRAY; 334 335 /* Our adapter structure */ 336 struct adapter { 337 struct arpcom interface_data; 338 struct em_hw hw; 339 340 /* Operating-system-specific structures */ 341 struct em_osdep osdep; 342 struct device *dev; 343 struct resource *res_memory; 344 struct resource *flash_mem; 345 struct resource *res_ioport; 346 struct resource *res_interrupt; 347 void *int_handler_tag; 348 struct ifmedia media; 349 struct callout timer; 350 struct callout tx_fifo_timer; 351 int io_rid; 352 int em_insert_vlan_header; 353 354 /* Info about the board itself */ 355 u_int32_t part_num; 356 u_int8_t link_active; 357 u_int16_t link_speed; 358 u_int16_t link_duplex; 359 u_int32_t smartspeed; 360 struct em_int_delay_info tx_int_delay; 361 struct em_int_delay_info tx_abs_int_delay; 362 struct em_int_delay_info rx_int_delay; 363 struct em_int_delay_info rx_abs_int_delay; 364 365 XSUM_CONTEXT_T active_checksum_context; 366 367 /* 368 * Transmit definitions 369 * 370 * We have an array of num_tx_desc descriptors (handled 371 * by the controller) paired with an array of tx_buffers 372 * (at tx_buffer_area). 373 * The index of the next available descriptor is next_avail_tx_desc. 374 * The number of remaining tx_desc is num_tx_desc_avail. 375 */ 376 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 377 struct em_tx_desc *tx_desc_base; 378 u_int32_t next_avail_tx_desc; 379 u_int32_t oldest_used_tx_desc; 380 volatile u_int16_t num_tx_desc_avail; 381 u_int16_t num_tx_desc; 382 u_int32_t txd_cmd; 383 struct em_buffer *tx_buffer_area; 384 bus_dma_tag_t txtag; /* dma tag for tx */ 385 386 /* 387 * Receive definitions 388 * 389 * we have an array of num_rx_desc rx_desc (handled by the 390 * controller), and paired with an array of rx_buffers 391 * (at rx_buffer_area). 392 * The next pair to check on receive is at offset next_rx_desc_to_check 393 */ 394 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 395 struct em_rx_desc *rx_desc_base; 396 u_int32_t next_rx_desc_to_check; 397 u_int16_t num_rx_desc; 398 u_int32_t rx_buffer_len; 399 struct em_buffer *rx_buffer_area; 400 bus_dma_tag_t rxtag; 401 402 /* Jumbo frame */ 403 struct mbuf *fmp; 404 struct mbuf *lmp; 405 406 struct sysctl_ctx_list sysctl_ctx; 407 struct sysctl_oid *sysctl_tree; 408 409 /* Misc stats maintained by the driver */ 410 unsigned long dropped_pkts; 411 unsigned long mbuf_alloc_failed; 412 unsigned long mbuf_cluster_failed; 413 unsigned long no_tx_desc_avail1; 414 unsigned long no_tx_desc_avail2; 415 unsigned long no_tx_map_avail; 416 unsigned long no_tx_dma_setup; 417 unsigned long rx_overruns; 418 unsigned long watchdog_timeouts; 419 420 /* Used in for 82547 10Mb Half workaround */ 421 u_int32_t tx_fifo_size; 422 u_int32_t tx_fifo_head; 423 u_int32_t tx_fifo_head_addr; 424 u_int64_t tx_fifo_reset_cnt; 425 u_int64_t tx_fifo_wrk_cnt; 426 u_int32_t tx_head_addr; 427 428 #define EM_PBA_BYTES_SHIFT 0xA 429 #define EM_TX_HEAD_ADDR_SHIFT 7 430 #define EM_PBA_TX_MASK 0xFFFF0000 431 #define EM_FIFO_HDR 0x10 432 #define EM_82547_PKT_THRESH 0x3e0 433 434 /* For 82544 PCIX Workaround */ 435 boolean_t pcix_82544; 436 boolean_t in_detach; 437 438 struct em_hw_stats stats; 439 }; 440 441 #endif /* !_EM_H_DEFINED_ */ 442