1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/em/if_em.h> 115 116 #define DEBUG_HW 0 117 118 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 119 #define EM_VER " 7.3.4" 120 121 #define _EM_DEVICE(id, ret) \ 122 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 123 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 124 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 125 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 126 127 static const struct em_vendor_info em_vendor_info_array[] = { 128 EM_DEVICE(82540EM), 129 EM_DEVICE(82540EM_LOM), 130 EM_DEVICE(82540EP), 131 EM_DEVICE(82540EP_LOM), 132 EM_DEVICE(82540EP_LP), 133 134 EM_DEVICE(82541EI), 135 EM_DEVICE(82541ER), 136 EM_DEVICE(82541ER_LOM), 137 EM_DEVICE(82541EI_MOBILE), 138 EM_DEVICE(82541GI), 139 EM_DEVICE(82541GI_LF), 140 EM_DEVICE(82541GI_MOBILE), 141 142 EM_DEVICE(82542), 143 144 EM_DEVICE(82543GC_FIBER), 145 EM_DEVICE(82543GC_COPPER), 146 147 EM_DEVICE(82544EI_COPPER), 148 EM_DEVICE(82544EI_FIBER), 149 EM_DEVICE(82544GC_COPPER), 150 EM_DEVICE(82544GC_LOM), 151 152 EM_DEVICE(82545EM_COPPER), 153 EM_DEVICE(82545EM_FIBER), 154 EM_DEVICE(82545GM_COPPER), 155 EM_DEVICE(82545GM_FIBER), 156 EM_DEVICE(82545GM_SERDES), 157 158 EM_DEVICE(82546EB_COPPER), 159 EM_DEVICE(82546EB_FIBER), 160 EM_DEVICE(82546EB_QUAD_COPPER), 161 EM_DEVICE(82546GB_COPPER), 162 EM_DEVICE(82546GB_FIBER), 163 EM_DEVICE(82546GB_SERDES), 164 EM_DEVICE(82546GB_PCIE), 165 EM_DEVICE(82546GB_QUAD_COPPER), 166 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 167 168 EM_DEVICE(82547EI), 169 EM_DEVICE(82547EI_MOBILE), 170 EM_DEVICE(82547GI), 171 172 EM_EMX_DEVICE(82571EB_COPPER), 173 EM_EMX_DEVICE(82571EB_FIBER), 174 EM_EMX_DEVICE(82571EB_SERDES), 175 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 176 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 177 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 180 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 181 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 182 183 EM_EMX_DEVICE(82572EI_COPPER), 184 EM_EMX_DEVICE(82572EI_FIBER), 185 EM_EMX_DEVICE(82572EI_SERDES), 186 EM_EMX_DEVICE(82572EI), 187 188 EM_EMX_DEVICE(82573E), 189 EM_EMX_DEVICE(82573E_IAMT), 190 EM_EMX_DEVICE(82573L), 191 192 EM_DEVICE(82583V), 193 194 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 195 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 197 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 198 199 EM_DEVICE(ICH8_IGP_M_AMT), 200 EM_DEVICE(ICH8_IGP_AMT), 201 EM_DEVICE(ICH8_IGP_C), 202 EM_DEVICE(ICH8_IFE), 203 EM_DEVICE(ICH8_IFE_GT), 204 EM_DEVICE(ICH8_IFE_G), 205 EM_DEVICE(ICH8_IGP_M), 206 EM_DEVICE(ICH8_82567V_3), 207 208 EM_DEVICE(ICH9_IGP_M_AMT), 209 EM_DEVICE(ICH9_IGP_AMT), 210 EM_DEVICE(ICH9_IGP_C), 211 EM_DEVICE(ICH9_IGP_M), 212 EM_DEVICE(ICH9_IGP_M_V), 213 EM_DEVICE(ICH9_IFE), 214 EM_DEVICE(ICH9_IFE_GT), 215 EM_DEVICE(ICH9_IFE_G), 216 EM_DEVICE(ICH9_BM), 217 218 EM_EMX_DEVICE(82574L), 219 EM_EMX_DEVICE(82574LA), 220 221 EM_DEVICE(ICH10_R_BM_LM), 222 EM_DEVICE(ICH10_R_BM_LF), 223 EM_DEVICE(ICH10_R_BM_V), 224 EM_DEVICE(ICH10_D_BM_LM), 225 EM_DEVICE(ICH10_D_BM_LF), 226 EM_DEVICE(ICH10_D_BM_V), 227 228 EM_DEVICE(PCH_M_HV_LM), 229 EM_DEVICE(PCH_M_HV_LC), 230 EM_DEVICE(PCH_D_HV_DM), 231 EM_DEVICE(PCH_D_HV_DC), 232 233 EM_DEVICE(PCH2_LV_LM), 234 EM_DEVICE(PCH2_LV_V), 235 236 /* required last entry */ 237 EM_DEVICE_NULL 238 }; 239 240 static int em_probe(device_t); 241 static int em_attach(device_t); 242 static int em_detach(device_t); 243 static int em_shutdown(device_t); 244 static int em_suspend(device_t); 245 static int em_resume(device_t); 246 247 static void em_init(void *); 248 static void em_stop(struct adapter *); 249 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 250 static void em_start(struct ifnet *, struct ifaltq_subque *); 251 #ifdef IFPOLL_ENABLE 252 static void em_npoll(struct ifnet *, struct ifpoll_info *); 253 static void em_npoll_compat(struct ifnet *, void *, int); 254 #endif 255 static void em_watchdog(struct ifnet *); 256 static void em_media_status(struct ifnet *, struct ifmediareq *); 257 static int em_media_change(struct ifnet *); 258 static void em_timer(void *); 259 260 static void em_intr(void *); 261 static void em_intr_mask(void *); 262 static void em_intr_body(struct adapter *, boolean_t); 263 static void em_rxeof(struct adapter *, int); 264 static void em_txeof(struct adapter *); 265 static void em_tx_collect(struct adapter *); 266 static void em_tx_purge(struct adapter *); 267 static void em_enable_intr(struct adapter *); 268 static void em_disable_intr(struct adapter *); 269 270 static int em_dma_malloc(struct adapter *, bus_size_t, 271 struct em_dma_alloc *); 272 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 273 static void em_init_tx_ring(struct adapter *); 274 static int em_init_rx_ring(struct adapter *); 275 static int em_create_tx_ring(struct adapter *); 276 static int em_create_rx_ring(struct adapter *); 277 static void em_destroy_tx_ring(struct adapter *, int); 278 static void em_destroy_rx_ring(struct adapter *, int); 279 static int em_newbuf(struct adapter *, int, int); 280 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 281 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 282 struct mbuf *); 283 static int em_txcsum(struct adapter *, struct mbuf *, 284 uint32_t *, uint32_t *); 285 static int em_tso_pullup(struct adapter *, struct mbuf **); 286 static int em_tso_setup(struct adapter *, struct mbuf *, 287 uint32_t *, uint32_t *); 288 289 static int em_get_hw_info(struct adapter *); 290 static int em_is_valid_eaddr(const uint8_t *); 291 static int em_alloc_pci_res(struct adapter *); 292 static void em_free_pci_res(struct adapter *); 293 static int em_reset(struct adapter *); 294 static void em_setup_ifp(struct adapter *); 295 static void em_init_tx_unit(struct adapter *); 296 static void em_init_rx_unit(struct adapter *); 297 static void em_update_stats(struct adapter *); 298 static void em_set_promisc(struct adapter *); 299 static void em_disable_promisc(struct adapter *); 300 static void em_set_multi(struct adapter *); 301 static void em_update_link_status(struct adapter *); 302 static void em_smartspeed(struct adapter *); 303 static void em_set_itr(struct adapter *, uint32_t); 304 static void em_disable_aspm(struct adapter *); 305 306 /* Hardware workarounds */ 307 static int em_82547_fifo_workaround(struct adapter *, int); 308 static void em_82547_update_fifo_head(struct adapter *, int); 309 static int em_82547_tx_fifo_reset(struct adapter *); 310 static void em_82547_move_tail(void *); 311 static void em_82547_move_tail_serialized(struct adapter *); 312 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 313 314 static void em_print_debug_info(struct adapter *); 315 static void em_print_nvm_info(struct adapter *); 316 static void em_print_hw_stats(struct adapter *); 317 318 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 319 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 320 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 321 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 322 static void em_add_sysctl(struct adapter *adapter); 323 324 /* Management and WOL Support */ 325 static void em_get_mgmt(struct adapter *); 326 static void em_rel_mgmt(struct adapter *); 327 static void em_get_hw_control(struct adapter *); 328 static void em_rel_hw_control(struct adapter *); 329 static void em_enable_wol(device_t); 330 331 static device_method_t em_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, em_probe), 334 DEVMETHOD(device_attach, em_attach), 335 DEVMETHOD(device_detach, em_detach), 336 DEVMETHOD(device_shutdown, em_shutdown), 337 DEVMETHOD(device_suspend, em_suspend), 338 DEVMETHOD(device_resume, em_resume), 339 DEVMETHOD_END 340 }; 341 342 static driver_t em_driver = { 343 "em", 344 em_methods, 345 sizeof(struct adapter), 346 }; 347 348 static devclass_t em_devclass; 349 350 DECLARE_DUMMY_MODULE(if_em); 351 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 352 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 353 354 /* 355 * Tunables 356 */ 357 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 358 static int em_rxd = EM_DEFAULT_RXD; 359 static int em_txd = EM_DEFAULT_TXD; 360 static int em_smart_pwr_down = 0; 361 362 /* Controls whether promiscuous also shows bad packets */ 363 static int em_debug_sbp = FALSE; 364 365 static int em_82573_workaround = 1; 366 static int em_msi_enable = 1; 367 368 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 369 TUNABLE_INT("hw.em.rxd", &em_rxd); 370 TUNABLE_INT("hw.em.txd", &em_txd); 371 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 372 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 373 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 374 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 375 376 /* Global used in WOL setup with multiport cards */ 377 static int em_global_quad_port_a = 0; 378 379 /* Set this to one to display debug statistics */ 380 static int em_display_debug_stats = 0; 381 382 #if !defined(KTR_IF_EM) 383 #define KTR_IF_EM KTR_ALL 384 #endif 385 KTR_INFO_MASTER(if_em); 386 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 387 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 388 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 389 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 390 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 391 #define logif(name) KTR_LOG(if_em_ ## name) 392 393 static int 394 em_probe(device_t dev) 395 { 396 const struct em_vendor_info *ent; 397 uint16_t vid, did; 398 399 vid = pci_get_vendor(dev); 400 did = pci_get_device(dev); 401 402 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 403 if (vid == ent->vendor_id && did == ent->device_id) { 404 device_set_desc(dev, ent->desc); 405 device_set_async_attach(dev, TRUE); 406 return (ent->ret); 407 } 408 } 409 return (ENXIO); 410 } 411 412 static int 413 em_attach(device_t dev) 414 { 415 struct adapter *adapter = device_get_softc(dev); 416 struct ifnet *ifp = &adapter->arpcom.ac_if; 417 int tsize, rsize; 418 int error = 0; 419 uint16_t eeprom_data, device_id, apme_mask; 420 driver_intr_t *intr_func; 421 422 adapter->dev = adapter->osdep.dev = dev; 423 424 callout_init_mp(&adapter->timer); 425 callout_init_mp(&adapter->tx_fifo_timer); 426 427 /* Determine hardware and mac info */ 428 error = em_get_hw_info(adapter); 429 if (error) { 430 device_printf(dev, "Identify hardware failed\n"); 431 goto fail; 432 } 433 434 /* Setup PCI resources */ 435 error = em_alloc_pci_res(adapter); 436 if (error) { 437 device_printf(dev, "Allocation of PCI resources failed\n"); 438 goto fail; 439 } 440 441 /* 442 * For ICH8 and family we need to map the flash memory, 443 * and this must happen after the MAC is identified. 444 */ 445 if (adapter->hw.mac.type == e1000_ich8lan || 446 adapter->hw.mac.type == e1000_ich9lan || 447 adapter->hw.mac.type == e1000_ich10lan || 448 adapter->hw.mac.type == e1000_pchlan || 449 adapter->hw.mac.type == e1000_pch2lan) { 450 adapter->flash_rid = EM_BAR_FLASH; 451 452 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 453 &adapter->flash_rid, RF_ACTIVE); 454 if (adapter->flash == NULL) { 455 device_printf(dev, "Mapping of Flash failed\n"); 456 error = ENXIO; 457 goto fail; 458 } 459 adapter->osdep.flash_bus_space_tag = 460 rman_get_bustag(adapter->flash); 461 adapter->osdep.flash_bus_space_handle = 462 rman_get_bushandle(adapter->flash); 463 464 /* 465 * This is used in the shared code 466 * XXX this goof is actually not used. 467 */ 468 adapter->hw.flash_address = (uint8_t *)adapter->flash; 469 } 470 471 switch (adapter->hw.mac.type) { 472 case e1000_82571: 473 case e1000_82572: 474 /* 475 * Pullup extra 4bytes into the first data segment, see: 476 * 82571/82572 specification update errata #7 477 * 478 * NOTE: 479 * 4bytes instead of 2bytes, which are mentioned in the 480 * errata, are pulled; mainly to keep rest of the data 481 * properly aligned. 482 */ 483 adapter->flags |= EM_FLAG_TSO_PULLEX; 484 /* FALL THROUGH */ 485 486 case e1000_82573: 487 case e1000_82574: 488 case e1000_80003es2lan: 489 adapter->flags |= EM_FLAG_TSO; 490 break; 491 492 default: 493 break; 494 } 495 496 /* Do Shared Code initialization */ 497 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 498 device_printf(dev, "Setup of Shared code failed\n"); 499 error = ENXIO; 500 goto fail; 501 } 502 503 e1000_get_bus_info(&adapter->hw); 504 505 /* 506 * Validate number of transmit and receive descriptors. It 507 * must not exceed hardware maximum, and must be multiple 508 * of E1000_DBA_ALIGN. 509 */ 510 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 511 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 512 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 513 em_txd < EM_MIN_TXD) { 514 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 515 EM_DEFAULT_TXD, em_txd); 516 adapter->num_tx_desc = EM_DEFAULT_TXD; 517 } else { 518 adapter->num_tx_desc = em_txd; 519 } 520 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 521 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 522 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 523 em_rxd < EM_MIN_RXD) { 524 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 525 EM_DEFAULT_RXD, em_rxd); 526 adapter->num_rx_desc = EM_DEFAULT_RXD; 527 } else { 528 adapter->num_rx_desc = em_rxd; 529 } 530 531 adapter->hw.mac.autoneg = DO_AUTO_NEG; 532 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 533 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 534 adapter->rx_buffer_len = MCLBYTES; 535 536 /* 537 * Interrupt throttle rate 538 */ 539 if (em_int_throttle_ceil == 0) { 540 adapter->int_throttle_ceil = 0; 541 } else { 542 int throttle = em_int_throttle_ceil; 543 544 if (throttle < 0) 545 throttle = EM_DEFAULT_ITR; 546 547 /* Recalculate the tunable value to get the exact frequency. */ 548 throttle = 1000000000 / 256 / throttle; 549 550 /* Upper 16bits of ITR is reserved and should be zero */ 551 if (throttle & 0xffff0000) 552 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 553 554 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 555 } 556 557 e1000_init_script_state_82541(&adapter->hw, TRUE); 558 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 559 560 /* Copper options */ 561 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 562 adapter->hw.phy.mdix = AUTO_ALL_MODES; 563 adapter->hw.phy.disable_polarity_correction = FALSE; 564 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 565 } 566 567 /* Set the frame limits assuming standard ethernet sized frames. */ 568 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 569 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 570 571 /* This controls when hardware reports transmit completion status. */ 572 adapter->hw.mac.report_tx_early = 1; 573 574 /* 575 * Create top level busdma tag 576 */ 577 error = bus_dma_tag_create(NULL, 1, 0, 578 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 579 NULL, NULL, 580 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 581 0, &adapter->parent_dtag); 582 if (error) { 583 device_printf(dev, "could not create top level DMA tag\n"); 584 goto fail; 585 } 586 587 /* 588 * Allocate Transmit Descriptor ring 589 */ 590 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 591 EM_DBA_ALIGN); 592 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 593 if (error) { 594 device_printf(dev, "Unable to allocate tx_desc memory\n"); 595 goto fail; 596 } 597 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 598 599 /* 600 * Allocate Receive Descriptor ring 601 */ 602 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 603 EM_DBA_ALIGN); 604 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 605 if (error) { 606 device_printf(dev, "Unable to allocate rx_desc memory\n"); 607 goto fail; 608 } 609 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 610 611 /* Allocate multicast array memory. */ 612 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 613 M_DEVBUF, M_WAITOK); 614 615 /* Indicate SOL/IDER usage */ 616 if (e1000_check_reset_block(&adapter->hw)) { 617 device_printf(dev, 618 "PHY reset is blocked due to SOL/IDER session.\n"); 619 } 620 621 /* 622 * Start from a known state, this is important in reading the 623 * nvm and mac from that. 624 */ 625 e1000_reset_hw(&adapter->hw); 626 627 /* Make sure we have a good EEPROM before we read from it */ 628 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 629 /* 630 * Some PCI-E parts fail the first check due to 631 * the link being in sleep state, call it again, 632 * if it fails a second time its a real issue. 633 */ 634 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 635 device_printf(dev, 636 "The EEPROM Checksum Is Not Valid\n"); 637 error = EIO; 638 goto fail; 639 } 640 } 641 642 /* Copy the permanent MAC address out of the EEPROM */ 643 if (e1000_read_mac_addr(&adapter->hw) < 0) { 644 device_printf(dev, "EEPROM read error while reading MAC" 645 " address\n"); 646 error = EIO; 647 goto fail; 648 } 649 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 650 device_printf(dev, "Invalid MAC address\n"); 651 error = EIO; 652 goto fail; 653 } 654 655 /* Allocate transmit descriptors and buffers */ 656 error = em_create_tx_ring(adapter); 657 if (error) { 658 device_printf(dev, "Could not setup transmit structures\n"); 659 goto fail; 660 } 661 662 /* Allocate receive descriptors and buffers */ 663 error = em_create_rx_ring(adapter); 664 if (error) { 665 device_printf(dev, "Could not setup receive structures\n"); 666 goto fail; 667 } 668 669 /* Manually turn off all interrupts */ 670 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 671 672 /* Determine if we have to control management hardware */ 673 if (e1000_enable_mng_pass_thru(&adapter->hw)) 674 adapter->flags |= EM_FLAG_HAS_MGMT; 675 676 /* 677 * Setup Wake-on-Lan 678 */ 679 apme_mask = EM_EEPROM_APME; 680 eeprom_data = 0; 681 switch (adapter->hw.mac.type) { 682 case e1000_82542: 683 case e1000_82543: 684 break; 685 686 case e1000_82573: 687 case e1000_82583: 688 adapter->flags |= EM_FLAG_HAS_AMT; 689 /* FALL THROUGH */ 690 691 case e1000_82546: 692 case e1000_82546_rev_3: 693 case e1000_82571: 694 case e1000_82572: 695 case e1000_80003es2lan: 696 if (adapter->hw.bus.func == 1) { 697 e1000_read_nvm(&adapter->hw, 698 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 699 } else { 700 e1000_read_nvm(&adapter->hw, 701 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 702 } 703 break; 704 705 case e1000_ich8lan: 706 case e1000_ich9lan: 707 case e1000_ich10lan: 708 case e1000_pchlan: 709 case e1000_pch2lan: 710 apme_mask = E1000_WUC_APME; 711 adapter->flags |= EM_FLAG_HAS_AMT; 712 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 713 break; 714 715 default: 716 e1000_read_nvm(&adapter->hw, 717 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 718 break; 719 } 720 if (eeprom_data & apme_mask) 721 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 722 723 /* 724 * We have the eeprom settings, now apply the special cases 725 * where the eeprom may be wrong or the board won't support 726 * wake on lan on a particular port 727 */ 728 device_id = pci_get_device(dev); 729 switch (device_id) { 730 case E1000_DEV_ID_82546GB_PCIE: 731 adapter->wol = 0; 732 break; 733 734 case E1000_DEV_ID_82546EB_FIBER: 735 case E1000_DEV_ID_82546GB_FIBER: 736 case E1000_DEV_ID_82571EB_FIBER: 737 /* 738 * Wake events only supported on port A for dual fiber 739 * regardless of eeprom setting 740 */ 741 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 742 E1000_STATUS_FUNC_1) 743 adapter->wol = 0; 744 break; 745 746 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 747 case E1000_DEV_ID_82571EB_QUAD_COPPER: 748 case E1000_DEV_ID_82571EB_QUAD_FIBER: 749 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 750 /* if quad port adapter, disable WoL on all but port A */ 751 if (em_global_quad_port_a != 0) 752 adapter->wol = 0; 753 /* Reset for multiple quad port adapters */ 754 if (++em_global_quad_port_a == 4) 755 em_global_quad_port_a = 0; 756 break; 757 } 758 759 /* XXX disable wol */ 760 adapter->wol = 0; 761 762 /* Setup OS specific network interface */ 763 em_setup_ifp(adapter); 764 765 /* Add sysctl tree, must after em_setup_ifp() */ 766 em_add_sysctl(adapter); 767 768 #ifdef IFPOLL_ENABLE 769 /* Polling setup */ 770 ifpoll_compat_setup(&adapter->npoll, 771 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev), 772 ifp->if_serializer); 773 #endif 774 775 /* Reset the hardware */ 776 error = em_reset(adapter); 777 if (error) { 778 device_printf(dev, "Unable to reset the hardware\n"); 779 goto fail; 780 } 781 782 /* Initialize statistics */ 783 em_update_stats(adapter); 784 785 adapter->hw.mac.get_link_status = 1; 786 em_update_link_status(adapter); 787 788 /* Do we need workaround for 82544 PCI-X adapter? */ 789 if (adapter->hw.bus.type == e1000_bus_type_pcix && 790 adapter->hw.mac.type == e1000_82544) 791 adapter->pcix_82544 = TRUE; 792 else 793 adapter->pcix_82544 = FALSE; 794 795 if (adapter->pcix_82544) { 796 /* 797 * 82544 on PCI-X may split one TX segment 798 * into two TX descs, so we double its number 799 * of spare TX desc here. 800 */ 801 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 802 } else { 803 adapter->spare_tx_desc = EM_TX_SPARE; 804 } 805 if (adapter->flags & EM_FLAG_TSO) 806 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 807 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 808 809 /* 810 * Keep following relationship between spare_tx_desc, oact_tx_desc 811 * and tx_int_nsegs: 812 * (spare_tx_desc + EM_TX_RESERVED) <= 813 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 814 */ 815 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 816 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 817 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 818 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 819 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 820 821 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 822 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 823 adapter->tx_int_nsegs = adapter->oact_tx_desc; 824 825 /* Non-AMT based hardware can now take control from firmware */ 826 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 827 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 828 em_get_hw_control(adapter); 829 830 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 831 832 /* 833 * Missing Interrupt Following ICR read: 834 * 835 * 82571/82572 specification update errata #76 836 * 82573 specification update errata #31 837 * 82574 specification update errata #12 838 * 82583 specification update errata #4 839 */ 840 intr_func = em_intr; 841 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 842 (adapter->hw.mac.type == e1000_82571 || 843 adapter->hw.mac.type == e1000_82572 || 844 adapter->hw.mac.type == e1000_82573 || 845 adapter->hw.mac.type == e1000_82574 || 846 adapter->hw.mac.type == e1000_82583)) 847 intr_func = em_intr_mask; 848 849 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 850 intr_func, adapter, &adapter->intr_tag, 851 ifp->if_serializer); 852 if (error) { 853 device_printf(dev, "Failed to register interrupt handler"); 854 ether_ifdetach(&adapter->arpcom.ac_if); 855 goto fail; 856 } 857 return (0); 858 fail: 859 em_detach(dev); 860 return (error); 861 } 862 863 static int 864 em_detach(device_t dev) 865 { 866 struct adapter *adapter = device_get_softc(dev); 867 868 if (device_is_attached(dev)) { 869 struct ifnet *ifp = &adapter->arpcom.ac_if; 870 871 lwkt_serialize_enter(ifp->if_serializer); 872 873 em_stop(adapter); 874 875 e1000_phy_hw_reset(&adapter->hw); 876 877 em_rel_mgmt(adapter); 878 em_rel_hw_control(adapter); 879 880 if (adapter->wol) { 881 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 882 E1000_WUC_PME_EN); 883 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 884 em_enable_wol(dev); 885 } 886 887 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 888 889 lwkt_serialize_exit(ifp->if_serializer); 890 891 ether_ifdetach(ifp); 892 } else if (adapter->memory != NULL) { 893 em_rel_hw_control(adapter); 894 } 895 bus_generic_detach(dev); 896 897 em_free_pci_res(adapter); 898 899 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 900 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 901 902 /* Free Transmit Descriptor ring */ 903 if (adapter->tx_desc_base) 904 em_dma_free(adapter, &adapter->txdma); 905 906 /* Free Receive Descriptor ring */ 907 if (adapter->rx_desc_base) 908 em_dma_free(adapter, &adapter->rxdma); 909 910 /* Free top level busdma tag */ 911 if (adapter->parent_dtag != NULL) 912 bus_dma_tag_destroy(adapter->parent_dtag); 913 914 /* Free sysctl tree */ 915 if (adapter->sysctl_tree != NULL) 916 sysctl_ctx_free(&adapter->sysctl_ctx); 917 918 if (adapter->mta != NULL) 919 kfree(adapter->mta, M_DEVBUF); 920 921 return (0); 922 } 923 924 static int 925 em_shutdown(device_t dev) 926 { 927 return em_suspend(dev); 928 } 929 930 static int 931 em_suspend(device_t dev) 932 { 933 struct adapter *adapter = device_get_softc(dev); 934 struct ifnet *ifp = &adapter->arpcom.ac_if; 935 936 lwkt_serialize_enter(ifp->if_serializer); 937 938 em_stop(adapter); 939 940 em_rel_mgmt(adapter); 941 em_rel_hw_control(adapter); 942 943 if (adapter->wol) { 944 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 945 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 946 em_enable_wol(dev); 947 } 948 949 lwkt_serialize_exit(ifp->if_serializer); 950 951 return bus_generic_suspend(dev); 952 } 953 954 static int 955 em_resume(device_t dev) 956 { 957 struct adapter *adapter = device_get_softc(dev); 958 struct ifnet *ifp = &adapter->arpcom.ac_if; 959 960 lwkt_serialize_enter(ifp->if_serializer); 961 962 if (adapter->hw.mac.type == e1000_pch2lan) 963 e1000_resume_workarounds_pchlan(&adapter->hw); 964 965 em_init(adapter); 966 em_get_mgmt(adapter); 967 if_devstart(ifp); 968 969 lwkt_serialize_exit(ifp->if_serializer); 970 971 return bus_generic_resume(dev); 972 } 973 974 static void 975 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 976 { 977 struct adapter *adapter = ifp->if_softc; 978 struct mbuf *m_head; 979 int idx = -1, nsegs = 0; 980 981 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 982 ASSERT_SERIALIZED(ifp->if_serializer); 983 984 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 985 return; 986 987 if (!adapter->link_active) { 988 ifq_purge(&ifp->if_snd); 989 return; 990 } 991 992 while (!ifq_is_empty(&ifp->if_snd)) { 993 /* Now do we at least have a minimal? */ 994 if (EM_IS_OACTIVE(adapter)) { 995 em_tx_collect(adapter); 996 if (EM_IS_OACTIVE(adapter)) { 997 ifq_set_oactive(&ifp->if_snd); 998 adapter->no_tx_desc_avail1++; 999 break; 1000 } 1001 } 1002 1003 logif(pkt_txqueue); 1004 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1005 if (m_head == NULL) 1006 break; 1007 1008 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1009 IFNET_STAT_INC(ifp, oerrors, 1); 1010 em_tx_collect(adapter); 1011 continue; 1012 } 1013 1014 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1015 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1016 nsegs = 0; 1017 idx = -1; 1018 } 1019 1020 /* Send a copy of the frame to the BPF listener */ 1021 ETHER_BPF_MTAP(ifp, m_head); 1022 1023 /* Set timeout in case hardware has problems transmitting. */ 1024 ifp->if_timer = EM_TX_TIMEOUT; 1025 } 1026 if (idx >= 0) 1027 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1028 } 1029 1030 static int 1031 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1032 { 1033 struct adapter *adapter = ifp->if_softc; 1034 struct ifreq *ifr = (struct ifreq *)data; 1035 uint16_t eeprom_data = 0; 1036 int max_frame_size, mask, reinit; 1037 int error = 0; 1038 1039 ASSERT_SERIALIZED(ifp->if_serializer); 1040 1041 switch (command) { 1042 case SIOCSIFMTU: 1043 switch (adapter->hw.mac.type) { 1044 case e1000_82573: 1045 /* 1046 * 82573 only supports jumbo frames 1047 * if ASPM is disabled. 1048 */ 1049 e1000_read_nvm(&adapter->hw, 1050 NVM_INIT_3GIO_3, 1, &eeprom_data); 1051 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1052 max_frame_size = ETHER_MAX_LEN; 1053 break; 1054 } 1055 /* FALL THROUGH */ 1056 1057 /* Limit Jumbo Frame size */ 1058 case e1000_82571: 1059 case e1000_82572: 1060 case e1000_ich9lan: 1061 case e1000_ich10lan: 1062 case e1000_pch2lan: 1063 case e1000_82574: 1064 case e1000_82583: 1065 case e1000_80003es2lan: 1066 max_frame_size = 9234; 1067 break; 1068 1069 case e1000_pchlan: 1070 max_frame_size = 4096; 1071 break; 1072 1073 /* Adapters that do not support jumbo frames */ 1074 case e1000_82542: 1075 case e1000_ich8lan: 1076 max_frame_size = ETHER_MAX_LEN; 1077 break; 1078 1079 default: 1080 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1081 break; 1082 } 1083 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1084 ETHER_CRC_LEN) { 1085 error = EINVAL; 1086 break; 1087 } 1088 1089 ifp->if_mtu = ifr->ifr_mtu; 1090 adapter->max_frame_size = 1091 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1092 1093 if (ifp->if_flags & IFF_RUNNING) 1094 em_init(adapter); 1095 break; 1096 1097 case SIOCSIFFLAGS: 1098 if (ifp->if_flags & IFF_UP) { 1099 if ((ifp->if_flags & IFF_RUNNING)) { 1100 if ((ifp->if_flags ^ adapter->if_flags) & 1101 (IFF_PROMISC | IFF_ALLMULTI)) { 1102 em_disable_promisc(adapter); 1103 em_set_promisc(adapter); 1104 } 1105 } else { 1106 em_init(adapter); 1107 } 1108 } else if (ifp->if_flags & IFF_RUNNING) { 1109 em_stop(adapter); 1110 } 1111 adapter->if_flags = ifp->if_flags; 1112 break; 1113 1114 case SIOCADDMULTI: 1115 case SIOCDELMULTI: 1116 if (ifp->if_flags & IFF_RUNNING) { 1117 em_disable_intr(adapter); 1118 em_set_multi(adapter); 1119 if (adapter->hw.mac.type == e1000_82542 && 1120 adapter->hw.revision_id == E1000_REVISION_2) 1121 em_init_rx_unit(adapter); 1122 #ifdef IFPOLL_ENABLE 1123 if (!(ifp->if_flags & IFF_NPOLLING)) 1124 #endif 1125 em_enable_intr(adapter); 1126 } 1127 break; 1128 1129 case SIOCSIFMEDIA: 1130 /* Check SOL/IDER usage */ 1131 if (e1000_check_reset_block(&adapter->hw)) { 1132 device_printf(adapter->dev, "Media change is" 1133 " blocked due to SOL/IDER session.\n"); 1134 break; 1135 } 1136 /* FALL THROUGH */ 1137 1138 case SIOCGIFMEDIA: 1139 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1140 break; 1141 1142 case SIOCSIFCAP: 1143 reinit = 0; 1144 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1145 if (mask & IFCAP_RXCSUM) { 1146 ifp->if_capenable ^= IFCAP_RXCSUM; 1147 reinit = 1; 1148 } 1149 if (mask & IFCAP_TXCSUM) { 1150 ifp->if_capenable ^= IFCAP_TXCSUM; 1151 if (ifp->if_capenable & IFCAP_TXCSUM) 1152 ifp->if_hwassist |= EM_CSUM_FEATURES; 1153 else 1154 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1155 } 1156 if (mask & IFCAP_TSO) { 1157 ifp->if_capenable ^= IFCAP_TSO; 1158 if (ifp->if_capenable & IFCAP_TSO) 1159 ifp->if_hwassist |= CSUM_TSO; 1160 else 1161 ifp->if_hwassist &= ~CSUM_TSO; 1162 } 1163 if (mask & IFCAP_VLAN_HWTAGGING) { 1164 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1165 reinit = 1; 1166 } 1167 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1168 em_init(adapter); 1169 break; 1170 1171 default: 1172 error = ether_ioctl(ifp, command, data); 1173 break; 1174 } 1175 return (error); 1176 } 1177 1178 static void 1179 em_watchdog(struct ifnet *ifp) 1180 { 1181 struct adapter *adapter = ifp->if_softc; 1182 1183 ASSERT_SERIALIZED(ifp->if_serializer); 1184 1185 /* 1186 * The timer is set to 5 every time start queues a packet. 1187 * Then txeof keeps resetting it as long as it cleans at 1188 * least one descriptor. 1189 * Finally, anytime all descriptors are clean the timer is 1190 * set to 0. 1191 */ 1192 1193 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1194 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1195 /* 1196 * If we reach here, all TX jobs are completed and 1197 * the TX engine should have been idled for some time. 1198 * We don't need to call if_devstart() here. 1199 */ 1200 ifq_clr_oactive(&ifp->if_snd); 1201 ifp->if_timer = 0; 1202 return; 1203 } 1204 1205 /* 1206 * If we are in this routine because of pause frames, then 1207 * don't reset the hardware. 1208 */ 1209 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1210 E1000_STATUS_TXOFF) { 1211 ifp->if_timer = EM_TX_TIMEOUT; 1212 return; 1213 } 1214 1215 if (e1000_check_for_link(&adapter->hw) == 0) 1216 if_printf(ifp, "watchdog timeout -- resetting\n"); 1217 1218 IFNET_STAT_INC(ifp, oerrors, 1); 1219 adapter->watchdog_events++; 1220 1221 em_init(adapter); 1222 1223 if (!ifq_is_empty(&ifp->if_snd)) 1224 if_devstart(ifp); 1225 } 1226 1227 static void 1228 em_init(void *xsc) 1229 { 1230 struct adapter *adapter = xsc; 1231 struct ifnet *ifp = &adapter->arpcom.ac_if; 1232 device_t dev = adapter->dev; 1233 1234 ASSERT_SERIALIZED(ifp->if_serializer); 1235 1236 em_stop(adapter); 1237 1238 /* Get the latest mac address, User can use a LAA */ 1239 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1240 1241 /* Put the address into the Receive Address Array */ 1242 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1243 1244 /* 1245 * With the 82571 adapter, RAR[0] may be overwritten 1246 * when the other port is reset, we make a duplicate 1247 * in RAR[14] for that eventuality, this assures 1248 * the interface continues to function. 1249 */ 1250 if (adapter->hw.mac.type == e1000_82571) { 1251 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1252 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1253 E1000_RAR_ENTRIES - 1); 1254 } 1255 1256 /* Reset the hardware */ 1257 if (em_reset(adapter)) { 1258 device_printf(dev, "Unable to reset the hardware\n"); 1259 /* XXX em_stop()? */ 1260 return; 1261 } 1262 em_update_link_status(adapter); 1263 1264 /* Setup VLAN support, basic and offload if available */ 1265 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1266 1267 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1268 uint32_t ctrl; 1269 1270 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1271 ctrl |= E1000_CTRL_VME; 1272 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1273 } 1274 1275 /* Configure for OS presence */ 1276 em_get_mgmt(adapter); 1277 1278 /* Prepare transmit descriptors and buffers */ 1279 em_init_tx_ring(adapter); 1280 em_init_tx_unit(adapter); 1281 1282 /* Setup Multicast table */ 1283 em_set_multi(adapter); 1284 1285 /* Prepare receive descriptors and buffers */ 1286 if (em_init_rx_ring(adapter)) { 1287 device_printf(dev, "Could not setup receive structures\n"); 1288 em_stop(adapter); 1289 return; 1290 } 1291 em_init_rx_unit(adapter); 1292 1293 /* Don't lose promiscuous settings */ 1294 em_set_promisc(adapter); 1295 1296 ifp->if_flags |= IFF_RUNNING; 1297 ifq_clr_oactive(&ifp->if_snd); 1298 1299 callout_reset(&adapter->timer, hz, em_timer, adapter); 1300 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1301 1302 /* MSI/X configuration for 82574 */ 1303 if (adapter->hw.mac.type == e1000_82574) { 1304 int tmp; 1305 1306 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1307 tmp |= E1000_CTRL_EXT_PBA_CLR; 1308 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1309 /* 1310 * XXX MSIX 1311 * Set the IVAR - interrupt vector routing. 1312 * Each nibble represents a vector, high bit 1313 * is enable, other 3 bits are the MSIX table 1314 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1315 * Link (other) to 2, hence the magic number. 1316 */ 1317 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1318 } 1319 1320 #ifdef IFPOLL_ENABLE 1321 /* 1322 * Only enable interrupts if we are not polling, make sure 1323 * they are off otherwise. 1324 */ 1325 if (ifp->if_flags & IFF_NPOLLING) 1326 em_disable_intr(adapter); 1327 else 1328 #endif /* IFPOLL_ENABLE */ 1329 em_enable_intr(adapter); 1330 1331 /* AMT based hardware can now take control from firmware */ 1332 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1333 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1334 adapter->hw.mac.type >= e1000_82571) 1335 em_get_hw_control(adapter); 1336 } 1337 1338 #ifdef IFPOLL_ENABLE 1339 1340 static void 1341 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1342 { 1343 struct adapter *adapter = ifp->if_softc; 1344 1345 ASSERT_SERIALIZED(ifp->if_serializer); 1346 1347 if (adapter->npoll.ifpc_stcount-- == 0) { 1348 uint32_t reg_icr; 1349 1350 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1351 1352 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1353 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1354 callout_stop(&adapter->timer); 1355 adapter->hw.mac.get_link_status = 1; 1356 em_update_link_status(adapter); 1357 callout_reset(&adapter->timer, hz, em_timer, adapter); 1358 } 1359 } 1360 1361 em_rxeof(adapter, count); 1362 em_txeof(adapter); 1363 1364 if (!ifq_is_empty(&ifp->if_snd)) 1365 if_devstart(ifp); 1366 } 1367 1368 static void 1369 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1370 { 1371 struct adapter *adapter = ifp->if_softc; 1372 1373 ASSERT_SERIALIZED(ifp->if_serializer); 1374 1375 if (info != NULL) { 1376 int cpuid = adapter->npoll.ifpc_cpuid; 1377 1378 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1379 info->ifpi_rx[cpuid].arg = NULL; 1380 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1381 1382 if (ifp->if_flags & IFF_RUNNING) 1383 em_disable_intr(adapter); 1384 ifq_set_cpuid(&ifp->if_snd, cpuid); 1385 } else { 1386 if (ifp->if_flags & IFF_RUNNING) 1387 em_enable_intr(adapter); 1388 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1389 } 1390 } 1391 1392 #endif /* IFPOLL_ENABLE */ 1393 1394 static void 1395 em_intr(void *xsc) 1396 { 1397 em_intr_body(xsc, TRUE); 1398 } 1399 1400 static void 1401 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1402 { 1403 struct ifnet *ifp = &adapter->arpcom.ac_if; 1404 uint32_t reg_icr; 1405 1406 logif(intr_beg); 1407 ASSERT_SERIALIZED(ifp->if_serializer); 1408 1409 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1410 1411 if (chk_asserted && 1412 ((adapter->hw.mac.type >= e1000_82571 && 1413 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1414 reg_icr == 0)) { 1415 logif(intr_end); 1416 return; 1417 } 1418 1419 /* 1420 * XXX: some laptops trigger several spurious interrupts 1421 * on em(4) when in the resume cycle. The ICR register 1422 * reports all-ones value in this case. Processing such 1423 * interrupts would lead to a freeze. I don't know why. 1424 */ 1425 if (reg_icr == 0xffffffff) { 1426 logif(intr_end); 1427 return; 1428 } 1429 1430 if (ifp->if_flags & IFF_RUNNING) { 1431 if (reg_icr & 1432 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1433 em_rxeof(adapter, -1); 1434 if (reg_icr & E1000_ICR_TXDW) { 1435 em_txeof(adapter); 1436 if (!ifq_is_empty(&ifp->if_snd)) 1437 if_devstart(ifp); 1438 } 1439 } 1440 1441 /* Link status change */ 1442 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1443 callout_stop(&adapter->timer); 1444 adapter->hw.mac.get_link_status = 1; 1445 em_update_link_status(adapter); 1446 1447 /* Deal with TX cruft when link lost */ 1448 em_tx_purge(adapter); 1449 1450 callout_reset(&adapter->timer, hz, em_timer, adapter); 1451 } 1452 1453 if (reg_icr & E1000_ICR_RXO) 1454 adapter->rx_overruns++; 1455 1456 logif(intr_end); 1457 } 1458 1459 static void 1460 em_intr_mask(void *xsc) 1461 { 1462 struct adapter *adapter = xsc; 1463 1464 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1465 /* 1466 * NOTE: 1467 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1468 * so don't check it. 1469 */ 1470 em_intr_body(adapter, FALSE); 1471 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1472 } 1473 1474 static void 1475 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1476 { 1477 struct adapter *adapter = ifp->if_softc; 1478 u_char fiber_type = IFM_1000_SX; 1479 1480 ASSERT_SERIALIZED(ifp->if_serializer); 1481 1482 em_update_link_status(adapter); 1483 1484 ifmr->ifm_status = IFM_AVALID; 1485 ifmr->ifm_active = IFM_ETHER; 1486 1487 if (!adapter->link_active) 1488 return; 1489 1490 ifmr->ifm_status |= IFM_ACTIVE; 1491 1492 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1493 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1494 if (adapter->hw.mac.type == e1000_82545) 1495 fiber_type = IFM_1000_LX; 1496 ifmr->ifm_active |= fiber_type | IFM_FDX; 1497 } else { 1498 switch (adapter->link_speed) { 1499 case 10: 1500 ifmr->ifm_active |= IFM_10_T; 1501 break; 1502 case 100: 1503 ifmr->ifm_active |= IFM_100_TX; 1504 break; 1505 1506 case 1000: 1507 ifmr->ifm_active |= IFM_1000_T; 1508 break; 1509 } 1510 if (adapter->link_duplex == FULL_DUPLEX) 1511 ifmr->ifm_active |= IFM_FDX; 1512 else 1513 ifmr->ifm_active |= IFM_HDX; 1514 } 1515 } 1516 1517 static int 1518 em_media_change(struct ifnet *ifp) 1519 { 1520 struct adapter *adapter = ifp->if_softc; 1521 struct ifmedia *ifm = &adapter->media; 1522 1523 ASSERT_SERIALIZED(ifp->if_serializer); 1524 1525 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1526 return (EINVAL); 1527 1528 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1529 case IFM_AUTO: 1530 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1531 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1532 break; 1533 1534 case IFM_1000_LX: 1535 case IFM_1000_SX: 1536 case IFM_1000_T: 1537 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1538 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1539 break; 1540 1541 case IFM_100_TX: 1542 adapter->hw.mac.autoneg = FALSE; 1543 adapter->hw.phy.autoneg_advertised = 0; 1544 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1545 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1546 else 1547 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1548 break; 1549 1550 case IFM_10_T: 1551 adapter->hw.mac.autoneg = FALSE; 1552 adapter->hw.phy.autoneg_advertised = 0; 1553 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1554 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1555 else 1556 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1557 break; 1558 1559 default: 1560 if_printf(ifp, "Unsupported media type\n"); 1561 break; 1562 } 1563 1564 em_init(adapter); 1565 1566 return (0); 1567 } 1568 1569 static int 1570 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1571 int *segs_used, int *idx) 1572 { 1573 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1574 bus_dmamap_t map; 1575 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1576 struct e1000_tx_desc *ctxd = NULL; 1577 struct mbuf *m_head = *m_headp; 1578 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1579 int maxsegs, nsegs, i, j, first, last = 0, error; 1580 1581 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1582 error = em_tso_pullup(adapter, m_headp); 1583 if (error) 1584 return error; 1585 m_head = *m_headp; 1586 } 1587 1588 txd_upper = txd_lower = 0; 1589 txd_used = 0; 1590 1591 /* 1592 * Capture the first descriptor index, this descriptor 1593 * will have the index of the EOP which is the only one 1594 * that now gets a DONE bit writeback. 1595 */ 1596 first = adapter->next_avail_tx_desc; 1597 tx_buffer = &adapter->tx_buffer_area[first]; 1598 tx_buffer_mapped = tx_buffer; 1599 map = tx_buffer->map; 1600 1601 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1602 KASSERT(maxsegs >= adapter->spare_tx_desc, 1603 ("not enough spare TX desc")); 1604 if (adapter->pcix_82544) { 1605 /* Half it; see the comment in em_attach() */ 1606 maxsegs >>= 1; 1607 } 1608 if (maxsegs > EM_MAX_SCATTER) 1609 maxsegs = EM_MAX_SCATTER; 1610 1611 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1612 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1613 if (error) { 1614 if (error == ENOBUFS) 1615 adapter->mbuf_alloc_failed++; 1616 else 1617 adapter->no_tx_dma_setup++; 1618 1619 m_freem(*m_headp); 1620 *m_headp = NULL; 1621 return error; 1622 } 1623 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1624 1625 m_head = *m_headp; 1626 adapter->tx_nsegs += nsegs; 1627 *segs_used += nsegs; 1628 1629 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1630 /* TSO will consume one TX desc */ 1631 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1632 adapter->tx_nsegs += i; 1633 *segs_used += i; 1634 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1635 /* TX csum offloading will consume one TX desc */ 1636 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1637 adapter->tx_nsegs += i; 1638 *segs_used += i; 1639 } 1640 i = adapter->next_avail_tx_desc; 1641 1642 /* Set up our transmit descriptors */ 1643 for (j = 0; j < nsegs; j++) { 1644 /* If adapter is 82544 and on PCIX bus */ 1645 if(adapter->pcix_82544) { 1646 DESC_ARRAY desc_array; 1647 uint32_t array_elements, counter; 1648 1649 /* 1650 * Check the Address and Length combination and 1651 * split the data accordingly 1652 */ 1653 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1654 segs[j].ds_len, &desc_array); 1655 for (counter = 0; counter < array_elements; counter++) { 1656 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1657 1658 tx_buffer = &adapter->tx_buffer_area[i]; 1659 ctxd = &adapter->tx_desc_base[i]; 1660 1661 ctxd->buffer_addr = htole64( 1662 desc_array.descriptor[counter].address); 1663 ctxd->lower.data = htole32( 1664 E1000_TXD_CMD_IFCS | txd_lower | 1665 desc_array.descriptor[counter].length); 1666 ctxd->upper.data = htole32(txd_upper); 1667 1668 last = i; 1669 if (++i == adapter->num_tx_desc) 1670 i = 0; 1671 1672 txd_used++; 1673 } 1674 } else { 1675 tx_buffer = &adapter->tx_buffer_area[i]; 1676 ctxd = &adapter->tx_desc_base[i]; 1677 1678 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1679 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1680 txd_lower | segs[j].ds_len); 1681 ctxd->upper.data = htole32(txd_upper); 1682 1683 last = i; 1684 if (++i == adapter->num_tx_desc) 1685 i = 0; 1686 } 1687 } 1688 1689 adapter->next_avail_tx_desc = i; 1690 if (adapter->pcix_82544) { 1691 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1692 adapter->num_tx_desc_avail -= txd_used; 1693 } else { 1694 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1695 adapter->num_tx_desc_avail -= nsegs; 1696 } 1697 1698 /* Handle VLAN tag */ 1699 if (m_head->m_flags & M_VLANTAG) { 1700 /* Set the vlan id. */ 1701 ctxd->upper.fields.special = 1702 htole16(m_head->m_pkthdr.ether_vlantag); 1703 1704 /* Tell hardware to add tag */ 1705 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1706 } 1707 1708 tx_buffer->m_head = m_head; 1709 tx_buffer_mapped->map = tx_buffer->map; 1710 tx_buffer->map = map; 1711 1712 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1713 adapter->tx_nsegs = 0; 1714 1715 /* 1716 * Report Status (RS) is turned on 1717 * every tx_int_nsegs descriptors. 1718 */ 1719 cmd = E1000_TXD_CMD_RS; 1720 1721 /* 1722 * Keep track of the descriptor, which will 1723 * be written back by hardware. 1724 */ 1725 adapter->tx_dd[adapter->tx_dd_tail] = last; 1726 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1727 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1728 } 1729 1730 /* 1731 * Last Descriptor of Packet needs End Of Packet (EOP) 1732 */ 1733 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1734 1735 if (adapter->hw.mac.type == e1000_82547) { 1736 /* 1737 * Advance the Transmit Descriptor Tail (TDT), this tells the 1738 * E1000 that this frame is available to transmit. 1739 */ 1740 if (adapter->link_duplex == HALF_DUPLEX) { 1741 em_82547_move_tail_serialized(adapter); 1742 } else { 1743 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1744 em_82547_update_fifo_head(adapter, 1745 m_head->m_pkthdr.len); 1746 } 1747 } else { 1748 /* 1749 * Defer TDT updating, until enough descriptors are setup 1750 */ 1751 *idx = i; 1752 } 1753 return (0); 1754 } 1755 1756 /* 1757 * 82547 workaround to avoid controller hang in half-duplex environment. 1758 * The workaround is to avoid queuing a large packet that would span 1759 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1760 * in this case. We do that only when FIFO is quiescent. 1761 */ 1762 static void 1763 em_82547_move_tail_serialized(struct adapter *adapter) 1764 { 1765 struct e1000_tx_desc *tx_desc; 1766 uint16_t hw_tdt, sw_tdt, length = 0; 1767 bool eop = 0; 1768 1769 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1770 1771 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1772 sw_tdt = adapter->next_avail_tx_desc; 1773 1774 while (hw_tdt != sw_tdt) { 1775 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1776 length += tx_desc->lower.flags.length; 1777 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1778 if (++hw_tdt == adapter->num_tx_desc) 1779 hw_tdt = 0; 1780 1781 if (eop) { 1782 if (em_82547_fifo_workaround(adapter, length)) { 1783 adapter->tx_fifo_wrk_cnt++; 1784 callout_reset(&adapter->tx_fifo_timer, 1, 1785 em_82547_move_tail, adapter); 1786 break; 1787 } 1788 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1789 em_82547_update_fifo_head(adapter, length); 1790 length = 0; 1791 } 1792 } 1793 } 1794 1795 static void 1796 em_82547_move_tail(void *xsc) 1797 { 1798 struct adapter *adapter = xsc; 1799 struct ifnet *ifp = &adapter->arpcom.ac_if; 1800 1801 lwkt_serialize_enter(ifp->if_serializer); 1802 em_82547_move_tail_serialized(adapter); 1803 lwkt_serialize_exit(ifp->if_serializer); 1804 } 1805 1806 static int 1807 em_82547_fifo_workaround(struct adapter *adapter, int len) 1808 { 1809 int fifo_space, fifo_pkt_len; 1810 1811 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1812 1813 if (adapter->link_duplex == HALF_DUPLEX) { 1814 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1815 1816 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1817 if (em_82547_tx_fifo_reset(adapter)) 1818 return (0); 1819 else 1820 return (1); 1821 } 1822 } 1823 return (0); 1824 } 1825 1826 static void 1827 em_82547_update_fifo_head(struct adapter *adapter, int len) 1828 { 1829 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1830 1831 /* tx_fifo_head is always 16 byte aligned */ 1832 adapter->tx_fifo_head += fifo_pkt_len; 1833 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1834 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1835 } 1836 1837 static int 1838 em_82547_tx_fifo_reset(struct adapter *adapter) 1839 { 1840 uint32_t tctl; 1841 1842 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1843 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1844 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1845 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1846 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1847 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1848 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1849 /* Disable TX unit */ 1850 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1851 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1852 tctl & ~E1000_TCTL_EN); 1853 1854 /* Reset FIFO pointers */ 1855 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1856 adapter->tx_head_addr); 1857 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1858 adapter->tx_head_addr); 1859 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1860 adapter->tx_head_addr); 1861 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1862 adapter->tx_head_addr); 1863 1864 /* Re-enable TX unit */ 1865 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1866 E1000_WRITE_FLUSH(&adapter->hw); 1867 1868 adapter->tx_fifo_head = 0; 1869 adapter->tx_fifo_reset_cnt++; 1870 1871 return (TRUE); 1872 } else { 1873 return (FALSE); 1874 } 1875 } 1876 1877 static void 1878 em_set_promisc(struct adapter *adapter) 1879 { 1880 struct ifnet *ifp = &adapter->arpcom.ac_if; 1881 uint32_t reg_rctl; 1882 1883 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1884 1885 if (ifp->if_flags & IFF_PROMISC) { 1886 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1887 /* Turn this on if you want to see bad packets */ 1888 if (em_debug_sbp) 1889 reg_rctl |= E1000_RCTL_SBP; 1890 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1891 } else if (ifp->if_flags & IFF_ALLMULTI) { 1892 reg_rctl |= E1000_RCTL_MPE; 1893 reg_rctl &= ~E1000_RCTL_UPE; 1894 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1895 } 1896 } 1897 1898 static void 1899 em_disable_promisc(struct adapter *adapter) 1900 { 1901 uint32_t reg_rctl; 1902 1903 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1904 1905 reg_rctl &= ~E1000_RCTL_UPE; 1906 reg_rctl &= ~E1000_RCTL_MPE; 1907 reg_rctl &= ~E1000_RCTL_SBP; 1908 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1909 } 1910 1911 static void 1912 em_set_multi(struct adapter *adapter) 1913 { 1914 struct ifnet *ifp = &adapter->arpcom.ac_if; 1915 struct ifmultiaddr *ifma; 1916 uint32_t reg_rctl = 0; 1917 uint8_t *mta; 1918 int mcnt = 0; 1919 1920 mta = adapter->mta; 1921 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1922 1923 if (adapter->hw.mac.type == e1000_82542 && 1924 adapter->hw.revision_id == E1000_REVISION_2) { 1925 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1926 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1927 e1000_pci_clear_mwi(&adapter->hw); 1928 reg_rctl |= E1000_RCTL_RST; 1929 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1930 msec_delay(5); 1931 } 1932 1933 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1934 if (ifma->ifma_addr->sa_family != AF_LINK) 1935 continue; 1936 1937 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1938 break; 1939 1940 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1941 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1942 mcnt++; 1943 } 1944 1945 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1946 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1947 reg_rctl |= E1000_RCTL_MPE; 1948 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1949 } else { 1950 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1951 } 1952 1953 if (adapter->hw.mac.type == e1000_82542 && 1954 adapter->hw.revision_id == E1000_REVISION_2) { 1955 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1956 reg_rctl &= ~E1000_RCTL_RST; 1957 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1958 msec_delay(5); 1959 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1960 e1000_pci_set_mwi(&adapter->hw); 1961 } 1962 } 1963 1964 /* 1965 * This routine checks for link status and updates statistics. 1966 */ 1967 static void 1968 em_timer(void *xsc) 1969 { 1970 struct adapter *adapter = xsc; 1971 struct ifnet *ifp = &adapter->arpcom.ac_if; 1972 1973 lwkt_serialize_enter(ifp->if_serializer); 1974 1975 em_update_link_status(adapter); 1976 em_update_stats(adapter); 1977 1978 /* Reset LAA into RAR[0] on 82571 */ 1979 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1980 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1981 1982 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1983 em_print_hw_stats(adapter); 1984 1985 em_smartspeed(adapter); 1986 1987 callout_reset(&adapter->timer, hz, em_timer, adapter); 1988 1989 lwkt_serialize_exit(ifp->if_serializer); 1990 } 1991 1992 static void 1993 em_update_link_status(struct adapter *adapter) 1994 { 1995 struct e1000_hw *hw = &adapter->hw; 1996 struct ifnet *ifp = &adapter->arpcom.ac_if; 1997 device_t dev = adapter->dev; 1998 uint32_t link_check = 0; 1999 2000 /* Get the cached link value or read phy for real */ 2001 switch (hw->phy.media_type) { 2002 case e1000_media_type_copper: 2003 if (hw->mac.get_link_status) { 2004 /* Do the work to read phy */ 2005 e1000_check_for_link(hw); 2006 link_check = !hw->mac.get_link_status; 2007 if (link_check) /* ESB2 fix */ 2008 e1000_cfg_on_link_up(hw); 2009 } else { 2010 link_check = TRUE; 2011 } 2012 break; 2013 2014 case e1000_media_type_fiber: 2015 e1000_check_for_link(hw); 2016 link_check = 2017 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2018 break; 2019 2020 case e1000_media_type_internal_serdes: 2021 e1000_check_for_link(hw); 2022 link_check = adapter->hw.mac.serdes_has_link; 2023 break; 2024 2025 case e1000_media_type_unknown: 2026 default: 2027 break; 2028 } 2029 2030 /* Now check for a transition */ 2031 if (link_check && adapter->link_active == 0) { 2032 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2033 &adapter->link_duplex); 2034 2035 /* 2036 * Check if we should enable/disable SPEED_MODE bit on 2037 * 82571/82572 2038 */ 2039 if (adapter->link_speed != SPEED_1000 && 2040 (hw->mac.type == e1000_82571 || 2041 hw->mac.type == e1000_82572)) { 2042 int tarc0; 2043 2044 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2045 tarc0 &= ~SPEED_MODE_BIT; 2046 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2047 } 2048 if (bootverbose) { 2049 device_printf(dev, "Link is up %d Mbps %s\n", 2050 adapter->link_speed, 2051 ((adapter->link_duplex == FULL_DUPLEX) ? 2052 "Full Duplex" : "Half Duplex")); 2053 } 2054 adapter->link_active = 1; 2055 adapter->smartspeed = 0; 2056 ifp->if_baudrate = adapter->link_speed * 1000000; 2057 ifp->if_link_state = LINK_STATE_UP; 2058 if_link_state_change(ifp); 2059 } else if (!link_check && adapter->link_active == 1) { 2060 ifp->if_baudrate = adapter->link_speed = 0; 2061 adapter->link_duplex = 0; 2062 if (bootverbose) 2063 device_printf(dev, "Link is Down\n"); 2064 adapter->link_active = 0; 2065 #if 0 2066 /* Link down, disable watchdog */ 2067 if->if_timer = 0; 2068 #endif 2069 ifp->if_link_state = LINK_STATE_DOWN; 2070 if_link_state_change(ifp); 2071 } 2072 } 2073 2074 static void 2075 em_stop(struct adapter *adapter) 2076 { 2077 struct ifnet *ifp = &adapter->arpcom.ac_if; 2078 int i; 2079 2080 ASSERT_SERIALIZED(ifp->if_serializer); 2081 2082 em_disable_intr(adapter); 2083 2084 callout_stop(&adapter->timer); 2085 callout_stop(&adapter->tx_fifo_timer); 2086 2087 ifp->if_flags &= ~IFF_RUNNING; 2088 ifq_clr_oactive(&ifp->if_snd); 2089 ifp->if_timer = 0; 2090 2091 e1000_reset_hw(&adapter->hw); 2092 if (adapter->hw.mac.type >= e1000_82544) 2093 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2094 2095 for (i = 0; i < adapter->num_tx_desc; i++) { 2096 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2097 2098 if (tx_buffer->m_head != NULL) { 2099 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2100 m_freem(tx_buffer->m_head); 2101 tx_buffer->m_head = NULL; 2102 } 2103 } 2104 2105 for (i = 0; i < adapter->num_rx_desc; i++) { 2106 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2107 2108 if (rx_buffer->m_head != NULL) { 2109 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2110 m_freem(rx_buffer->m_head); 2111 rx_buffer->m_head = NULL; 2112 } 2113 } 2114 2115 if (adapter->fmp != NULL) 2116 m_freem(adapter->fmp); 2117 adapter->fmp = NULL; 2118 adapter->lmp = NULL; 2119 2120 adapter->csum_flags = 0; 2121 adapter->csum_lhlen = 0; 2122 adapter->csum_iphlen = 0; 2123 adapter->csum_thlen = 0; 2124 adapter->csum_mss = 0; 2125 adapter->csum_pktlen = 0; 2126 2127 adapter->tx_dd_head = 0; 2128 adapter->tx_dd_tail = 0; 2129 adapter->tx_nsegs = 0; 2130 } 2131 2132 static int 2133 em_get_hw_info(struct adapter *adapter) 2134 { 2135 device_t dev = adapter->dev; 2136 2137 /* Save off the information about this board */ 2138 adapter->hw.vendor_id = pci_get_vendor(dev); 2139 adapter->hw.device_id = pci_get_device(dev); 2140 adapter->hw.revision_id = pci_get_revid(dev); 2141 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2142 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2143 2144 /* Do Shared Code Init and Setup */ 2145 if (e1000_set_mac_type(&adapter->hw)) 2146 return ENXIO; 2147 return 0; 2148 } 2149 2150 static int 2151 em_alloc_pci_res(struct adapter *adapter) 2152 { 2153 device_t dev = adapter->dev; 2154 u_int intr_flags; 2155 int val, rid, msi_enable; 2156 2157 /* Enable bus mastering */ 2158 pci_enable_busmaster(dev); 2159 2160 adapter->memory_rid = EM_BAR_MEM; 2161 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2162 &adapter->memory_rid, RF_ACTIVE); 2163 if (adapter->memory == NULL) { 2164 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2165 return (ENXIO); 2166 } 2167 adapter->osdep.mem_bus_space_tag = 2168 rman_get_bustag(adapter->memory); 2169 adapter->osdep.mem_bus_space_handle = 2170 rman_get_bushandle(adapter->memory); 2171 2172 /* XXX This is quite goofy, it is not actually used */ 2173 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2174 2175 /* Only older adapters use IO mapping */ 2176 if (adapter->hw.mac.type > e1000_82543 && 2177 adapter->hw.mac.type < e1000_82571) { 2178 /* Figure our where our IO BAR is ? */ 2179 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2180 val = pci_read_config(dev, rid, 4); 2181 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2182 adapter->io_rid = rid; 2183 break; 2184 } 2185 rid += 4; 2186 /* check for 64bit BAR */ 2187 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2188 rid += 4; 2189 } 2190 if (rid >= PCIR_CARDBUSCIS) { 2191 device_printf(dev, "Unable to locate IO BAR\n"); 2192 return (ENXIO); 2193 } 2194 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2195 &adapter->io_rid, RF_ACTIVE); 2196 if (adapter->ioport == NULL) { 2197 device_printf(dev, "Unable to allocate bus resource: " 2198 "ioport\n"); 2199 return (ENXIO); 2200 } 2201 adapter->hw.io_base = 0; 2202 adapter->osdep.io_bus_space_tag = 2203 rman_get_bustag(adapter->ioport); 2204 adapter->osdep.io_bus_space_handle = 2205 rman_get_bushandle(adapter->ioport); 2206 } 2207 2208 /* 2209 * Don't enable MSI-X on 82574, see: 2210 * 82574 specification update errata #15 2211 * 2212 * Don't enable MSI on PCI/PCI-X chips, see: 2213 * 82540 specification update errata #6 2214 * 82545 specification update errata #4 2215 * 2216 * Don't enable MSI on 82571/82572, see: 2217 * 82571/82572 specification update errata #63 2218 */ 2219 msi_enable = em_msi_enable; 2220 if (msi_enable && 2221 (!pci_is_pcie(dev) || 2222 adapter->hw.mac.type == e1000_82571 || 2223 adapter->hw.mac.type == e1000_82572)) 2224 msi_enable = 0; 2225 2226 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2227 &adapter->intr_rid, &intr_flags); 2228 2229 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2230 int unshared; 2231 2232 unshared = device_getenv_int(dev, "irq.unshared", 0); 2233 if (!unshared) { 2234 adapter->flags |= EM_FLAG_SHARED_INTR; 2235 if (bootverbose) 2236 device_printf(dev, "IRQ shared\n"); 2237 } else { 2238 intr_flags &= ~RF_SHAREABLE; 2239 if (bootverbose) 2240 device_printf(dev, "IRQ unshared\n"); 2241 } 2242 } 2243 2244 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2245 &adapter->intr_rid, intr_flags); 2246 if (adapter->intr_res == NULL) { 2247 device_printf(dev, "Unable to allocate bus resource: " 2248 "interrupt\n"); 2249 return (ENXIO); 2250 } 2251 2252 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2253 adapter->hw.back = &adapter->osdep; 2254 return (0); 2255 } 2256 2257 static void 2258 em_free_pci_res(struct adapter *adapter) 2259 { 2260 device_t dev = adapter->dev; 2261 2262 if (adapter->intr_res != NULL) { 2263 bus_release_resource(dev, SYS_RES_IRQ, 2264 adapter->intr_rid, adapter->intr_res); 2265 } 2266 2267 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2268 pci_release_msi(dev); 2269 2270 if (adapter->memory != NULL) { 2271 bus_release_resource(dev, SYS_RES_MEMORY, 2272 adapter->memory_rid, adapter->memory); 2273 } 2274 2275 if (adapter->flash != NULL) { 2276 bus_release_resource(dev, SYS_RES_MEMORY, 2277 adapter->flash_rid, adapter->flash); 2278 } 2279 2280 if (adapter->ioport != NULL) { 2281 bus_release_resource(dev, SYS_RES_IOPORT, 2282 adapter->io_rid, adapter->ioport); 2283 } 2284 } 2285 2286 static int 2287 em_reset(struct adapter *adapter) 2288 { 2289 device_t dev = adapter->dev; 2290 uint16_t rx_buffer_size; 2291 uint32_t pba; 2292 2293 /* When hardware is reset, fifo_head is also reset */ 2294 adapter->tx_fifo_head = 0; 2295 2296 /* Set up smart power down as default off on newer adapters. */ 2297 if (!em_smart_pwr_down && 2298 (adapter->hw.mac.type == e1000_82571 || 2299 adapter->hw.mac.type == e1000_82572)) { 2300 uint16_t phy_tmp = 0; 2301 2302 /* Speed up time to link by disabling smart power down. */ 2303 e1000_read_phy_reg(&adapter->hw, 2304 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2305 phy_tmp &= ~IGP02E1000_PM_SPD; 2306 e1000_write_phy_reg(&adapter->hw, 2307 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2308 } 2309 2310 /* 2311 * Packet Buffer Allocation (PBA) 2312 * Writing PBA sets the receive portion of the buffer 2313 * the remainder is used for the transmit buffer. 2314 * 2315 * Devices before the 82547 had a Packet Buffer of 64K. 2316 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2317 * After the 82547 the buffer was reduced to 40K. 2318 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2319 * Note: default does not leave enough room for Jumbo Frame >10k. 2320 */ 2321 switch (adapter->hw.mac.type) { 2322 case e1000_82547: 2323 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2324 if (adapter->max_frame_size > 8192) 2325 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2326 else 2327 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2328 adapter->tx_fifo_head = 0; 2329 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2330 adapter->tx_fifo_size = 2331 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2332 break; 2333 2334 /* Total Packet Buffer on these is 48K */ 2335 case e1000_82571: 2336 case e1000_82572: 2337 case e1000_80003es2lan: 2338 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2339 break; 2340 2341 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2342 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2343 break; 2344 2345 case e1000_82574: 2346 case e1000_82583: 2347 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2348 break; 2349 2350 case e1000_ich8lan: 2351 pba = E1000_PBA_8K; 2352 break; 2353 2354 case e1000_ich9lan: 2355 case e1000_ich10lan: 2356 #define E1000_PBA_10K 0x000A 2357 pba = E1000_PBA_10K; 2358 break; 2359 2360 case e1000_pchlan: 2361 case e1000_pch2lan: 2362 pba = E1000_PBA_26K; 2363 break; 2364 2365 default: 2366 /* Devices before 82547 had a Packet Buffer of 64K. */ 2367 if (adapter->max_frame_size > 8192) 2368 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2369 else 2370 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2371 } 2372 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2373 2374 /* 2375 * These parameters control the automatic generation (Tx) and 2376 * response (Rx) to Ethernet PAUSE frames. 2377 * - High water mark should allow for at least two frames to be 2378 * received after sending an XOFF. 2379 * - Low water mark works best when it is very near the high water mark. 2380 * This allows the receiver to restart by sending XON when it has 2381 * drained a bit. Here we use an arbitary value of 1500 which will 2382 * restart after one full frame is pulled from the buffer. There 2383 * could be several smaller frames in the buffer and if so they will 2384 * not trigger the XON until their total number reduces the buffer 2385 * by 1500. 2386 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2387 */ 2388 rx_buffer_size = 2389 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2390 2391 adapter->hw.fc.high_water = rx_buffer_size - 2392 roundup2(adapter->max_frame_size, 1024); 2393 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2394 2395 if (adapter->hw.mac.type == e1000_80003es2lan) 2396 adapter->hw.fc.pause_time = 0xFFFF; 2397 else 2398 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2399 2400 adapter->hw.fc.send_xon = TRUE; 2401 2402 adapter->hw.fc.requested_mode = e1000_fc_full; 2403 2404 /* 2405 * Device specific overrides/settings 2406 */ 2407 switch (adapter->hw.mac.type) { 2408 case e1000_pchlan: 2409 /* Workaround: no TX flow ctrl for PCH */ 2410 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2411 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2412 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2413 adapter->hw.fc.high_water = 0x3500; 2414 adapter->hw.fc.low_water = 0x1500; 2415 } else { 2416 adapter->hw.fc.high_water = 0x5000; 2417 adapter->hw.fc.low_water = 0x3000; 2418 } 2419 adapter->hw.fc.refresh_time = 0x1000; 2420 break; 2421 2422 case e1000_pch2lan: 2423 adapter->hw.fc.high_water = 0x5C20; 2424 adapter->hw.fc.low_water = 0x5048; 2425 adapter->hw.fc.pause_time = 0x0650; 2426 adapter->hw.fc.refresh_time = 0x0400; 2427 /* Jumbos need adjusted PBA */ 2428 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2429 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2430 else 2431 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2432 break; 2433 2434 case e1000_ich9lan: 2435 case e1000_ich10lan: 2436 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2437 adapter->hw.fc.high_water = 0x2800; 2438 adapter->hw.fc.low_water = 2439 adapter->hw.fc.high_water - 8; 2440 break; 2441 } 2442 /* FALL THROUGH */ 2443 default: 2444 if (adapter->hw.mac.type == e1000_80003es2lan) 2445 adapter->hw.fc.pause_time = 0xFFFF; 2446 break; 2447 } 2448 2449 /* Issue a global reset */ 2450 e1000_reset_hw(&adapter->hw); 2451 if (adapter->hw.mac.type >= e1000_82544) 2452 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2453 em_disable_aspm(adapter); 2454 2455 if (e1000_init_hw(&adapter->hw) < 0) { 2456 device_printf(dev, "Hardware Initialization Failed\n"); 2457 return (EIO); 2458 } 2459 2460 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2461 e1000_get_phy_info(&adapter->hw); 2462 e1000_check_for_link(&adapter->hw); 2463 2464 return (0); 2465 } 2466 2467 static void 2468 em_setup_ifp(struct adapter *adapter) 2469 { 2470 struct ifnet *ifp = &adapter->arpcom.ac_if; 2471 2472 if_initname(ifp, device_get_name(adapter->dev), 2473 device_get_unit(adapter->dev)); 2474 ifp->if_softc = adapter; 2475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2476 ifp->if_init = em_init; 2477 ifp->if_ioctl = em_ioctl; 2478 ifp->if_start = em_start; 2479 #ifdef IFPOLL_ENABLE 2480 ifp->if_npoll = em_npoll; 2481 #endif 2482 ifp->if_watchdog = em_watchdog; 2483 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2484 ifq_set_ready(&ifp->if_snd); 2485 2486 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2487 2488 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2489 if (adapter->hw.mac.type >= e1000_82543) 2490 ifp->if_capabilities |= IFCAP_HWCSUM; 2491 if (adapter->flags & EM_FLAG_TSO) 2492 ifp->if_capabilities |= IFCAP_TSO; 2493 ifp->if_capenable = ifp->if_capabilities; 2494 2495 if (ifp->if_capenable & IFCAP_TXCSUM) 2496 ifp->if_hwassist |= EM_CSUM_FEATURES; 2497 if (ifp->if_capenable & IFCAP_TSO) 2498 ifp->if_hwassist |= CSUM_TSO; 2499 2500 /* 2501 * Tell the upper layer(s) we support long frames. 2502 */ 2503 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2504 2505 /* 2506 * Specify the media types supported by this adapter and register 2507 * callbacks to update media and link information 2508 */ 2509 ifmedia_init(&adapter->media, IFM_IMASK, 2510 em_media_change, em_media_status); 2511 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2512 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2513 u_char fiber_type = IFM_1000_SX; /* default type */ 2514 2515 if (adapter->hw.mac.type == e1000_82545) 2516 fiber_type = IFM_1000_LX; 2517 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2518 0, NULL); 2519 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2520 } else { 2521 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2522 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2523 0, NULL); 2524 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2525 0, NULL); 2526 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2527 0, NULL); 2528 if (adapter->hw.phy.type != e1000_phy_ife) { 2529 ifmedia_add(&adapter->media, 2530 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2531 ifmedia_add(&adapter->media, 2532 IFM_ETHER | IFM_1000_T, 0, NULL); 2533 } 2534 } 2535 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2536 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2537 } 2538 2539 2540 /* 2541 * Workaround for SmartSpeed on 82541 and 82547 controllers 2542 */ 2543 static void 2544 em_smartspeed(struct adapter *adapter) 2545 { 2546 uint16_t phy_tmp; 2547 2548 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2549 adapter->hw.mac.autoneg == 0 || 2550 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2551 return; 2552 2553 if (adapter->smartspeed == 0) { 2554 /* 2555 * If Master/Slave config fault is asserted twice, 2556 * we assume back-to-back 2557 */ 2558 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2559 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2560 return; 2561 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2562 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2563 e1000_read_phy_reg(&adapter->hw, 2564 PHY_1000T_CTRL, &phy_tmp); 2565 if (phy_tmp & CR_1000T_MS_ENABLE) { 2566 phy_tmp &= ~CR_1000T_MS_ENABLE; 2567 e1000_write_phy_reg(&adapter->hw, 2568 PHY_1000T_CTRL, phy_tmp); 2569 adapter->smartspeed++; 2570 if (adapter->hw.mac.autoneg && 2571 !e1000_phy_setup_autoneg(&adapter->hw) && 2572 !e1000_read_phy_reg(&adapter->hw, 2573 PHY_CONTROL, &phy_tmp)) { 2574 phy_tmp |= MII_CR_AUTO_NEG_EN | 2575 MII_CR_RESTART_AUTO_NEG; 2576 e1000_write_phy_reg(&adapter->hw, 2577 PHY_CONTROL, phy_tmp); 2578 } 2579 } 2580 } 2581 return; 2582 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2583 /* If still no link, perhaps using 2/3 pair cable */ 2584 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2585 phy_tmp |= CR_1000T_MS_ENABLE; 2586 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2587 if (adapter->hw.mac.autoneg && 2588 !e1000_phy_setup_autoneg(&adapter->hw) && 2589 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2590 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2591 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2592 } 2593 } 2594 2595 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2596 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2597 adapter->smartspeed = 0; 2598 } 2599 2600 static int 2601 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2602 struct em_dma_alloc *dma) 2603 { 2604 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2605 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2606 &dma->dma_tag, &dma->dma_map, 2607 &dma->dma_paddr); 2608 if (dma->dma_vaddr == NULL) 2609 return ENOMEM; 2610 else 2611 return 0; 2612 } 2613 2614 static void 2615 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2616 { 2617 if (dma->dma_tag == NULL) 2618 return; 2619 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2620 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2621 bus_dma_tag_destroy(dma->dma_tag); 2622 } 2623 2624 static int 2625 em_create_tx_ring(struct adapter *adapter) 2626 { 2627 device_t dev = adapter->dev; 2628 struct em_buffer *tx_buffer; 2629 int error, i; 2630 2631 adapter->tx_buffer_area = 2632 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2633 M_DEVBUF, M_WAITOK | M_ZERO); 2634 2635 /* 2636 * Create DMA tags for tx buffers 2637 */ 2638 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2639 1, 0, /* alignment, bounds */ 2640 BUS_SPACE_MAXADDR, /* lowaddr */ 2641 BUS_SPACE_MAXADDR, /* highaddr */ 2642 NULL, NULL, /* filter, filterarg */ 2643 EM_TSO_SIZE, /* maxsize */ 2644 EM_MAX_SCATTER, /* nsegments */ 2645 PAGE_SIZE, /* maxsegsize */ 2646 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2647 BUS_DMA_ONEBPAGE, /* flags */ 2648 &adapter->txtag); 2649 if (error) { 2650 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2651 kfree(adapter->tx_buffer_area, M_DEVBUF); 2652 adapter->tx_buffer_area = NULL; 2653 return error; 2654 } 2655 2656 /* 2657 * Create DMA maps for tx buffers 2658 */ 2659 for (i = 0; i < adapter->num_tx_desc; i++) { 2660 tx_buffer = &adapter->tx_buffer_area[i]; 2661 2662 error = bus_dmamap_create(adapter->txtag, 2663 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2664 &tx_buffer->map); 2665 if (error) { 2666 device_printf(dev, "Unable to create TX DMA map\n"); 2667 em_destroy_tx_ring(adapter, i); 2668 return error; 2669 } 2670 } 2671 return (0); 2672 } 2673 2674 static void 2675 em_init_tx_ring(struct adapter *adapter) 2676 { 2677 /* Clear the old ring contents */ 2678 bzero(adapter->tx_desc_base, 2679 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2680 2681 /* Reset state */ 2682 adapter->next_avail_tx_desc = 0; 2683 adapter->next_tx_to_clean = 0; 2684 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2685 } 2686 2687 static void 2688 em_init_tx_unit(struct adapter *adapter) 2689 { 2690 uint32_t tctl, tarc, tipg = 0; 2691 uint64_t bus_addr; 2692 2693 /* Setup the Base and Length of the Tx Descriptor Ring */ 2694 bus_addr = adapter->txdma.dma_paddr; 2695 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2696 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2697 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2698 (uint32_t)(bus_addr >> 32)); 2699 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2700 (uint32_t)bus_addr); 2701 /* Setup the HW Tx Head and Tail descriptor pointers */ 2702 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2703 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2704 2705 /* Set the default values for the Tx Inter Packet Gap timer */ 2706 switch (adapter->hw.mac.type) { 2707 case e1000_82542: 2708 tipg = DEFAULT_82542_TIPG_IPGT; 2709 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2710 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2711 break; 2712 2713 case e1000_80003es2lan: 2714 tipg = DEFAULT_82543_TIPG_IPGR1; 2715 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2716 E1000_TIPG_IPGR2_SHIFT; 2717 break; 2718 2719 default: 2720 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2721 adapter->hw.phy.media_type == 2722 e1000_media_type_internal_serdes) 2723 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2724 else 2725 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2726 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2727 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2728 break; 2729 } 2730 2731 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2732 2733 /* NOTE: 0 is not allowed for TIDV */ 2734 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2735 if(adapter->hw.mac.type >= e1000_82540) 2736 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2737 2738 if (adapter->hw.mac.type == e1000_82571 || 2739 adapter->hw.mac.type == e1000_82572) { 2740 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2741 tarc |= SPEED_MODE_BIT; 2742 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2743 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2744 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2745 tarc |= 1; 2746 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2747 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2748 tarc |= 1; 2749 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2750 } 2751 2752 /* Program the Transmit Control Register */ 2753 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2754 tctl &= ~E1000_TCTL_CT; 2755 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2756 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2757 2758 if (adapter->hw.mac.type >= e1000_82571) 2759 tctl |= E1000_TCTL_MULR; 2760 2761 /* This write will effectively turn on the transmit unit. */ 2762 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2763 2764 if (adapter->hw.mac.type == e1000_82571 || 2765 adapter->hw.mac.type == e1000_82572 || 2766 adapter->hw.mac.type == e1000_80003es2lan) { 2767 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2768 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2769 tarc &= ~(1 << 28); 2770 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2771 } 2772 } 2773 2774 static void 2775 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2776 { 2777 struct em_buffer *tx_buffer; 2778 int i; 2779 2780 if (adapter->tx_buffer_area == NULL) 2781 return; 2782 2783 for (i = 0; i < ndesc; i++) { 2784 tx_buffer = &adapter->tx_buffer_area[i]; 2785 2786 KKASSERT(tx_buffer->m_head == NULL); 2787 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2788 } 2789 bus_dma_tag_destroy(adapter->txtag); 2790 2791 kfree(adapter->tx_buffer_area, M_DEVBUF); 2792 adapter->tx_buffer_area = NULL; 2793 } 2794 2795 /* 2796 * The offload context needs to be set when we transfer the first 2797 * packet of a particular protocol (TCP/UDP). This routine has been 2798 * enhanced to deal with inserted VLAN headers. 2799 * 2800 * If the new packet's ether header length, ip header length and 2801 * csum offloading type are same as the previous packet, we should 2802 * avoid allocating a new csum context descriptor; mainly to take 2803 * advantage of the pipeline effect of the TX data read request. 2804 * 2805 * This function returns number of TX descrptors allocated for 2806 * csum context. 2807 */ 2808 static int 2809 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2810 uint32_t *txd_upper, uint32_t *txd_lower) 2811 { 2812 struct e1000_context_desc *TXD; 2813 int curr_txd, ehdrlen, csum_flags; 2814 uint32_t cmd, hdr_len, ip_hlen; 2815 2816 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2817 ip_hlen = mp->m_pkthdr.csum_iphlen; 2818 ehdrlen = mp->m_pkthdr.csum_lhlen; 2819 2820 if (adapter->csum_lhlen == ehdrlen && 2821 adapter->csum_iphlen == ip_hlen && 2822 adapter->csum_flags == csum_flags) { 2823 /* 2824 * Same csum offload context as the previous packets; 2825 * just return. 2826 */ 2827 *txd_upper = adapter->csum_txd_upper; 2828 *txd_lower = adapter->csum_txd_lower; 2829 return 0; 2830 } 2831 2832 /* 2833 * Setup a new csum offload context. 2834 */ 2835 2836 curr_txd = adapter->next_avail_tx_desc; 2837 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2838 2839 cmd = 0; 2840 2841 /* Setup of IP header checksum. */ 2842 if (csum_flags & CSUM_IP) { 2843 /* 2844 * Start offset for header checksum calculation. 2845 * End offset for header checksum calculation. 2846 * Offset of place to put the checksum. 2847 */ 2848 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2849 TXD->lower_setup.ip_fields.ipcse = 2850 htole16(ehdrlen + ip_hlen - 1); 2851 TXD->lower_setup.ip_fields.ipcso = 2852 ehdrlen + offsetof(struct ip, ip_sum); 2853 cmd |= E1000_TXD_CMD_IP; 2854 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2855 } 2856 hdr_len = ehdrlen + ip_hlen; 2857 2858 if (csum_flags & CSUM_TCP) { 2859 /* 2860 * Start offset for payload checksum calculation. 2861 * End offset for payload checksum calculation. 2862 * Offset of place to put the checksum. 2863 */ 2864 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2865 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2866 TXD->upper_setup.tcp_fields.tucso = 2867 hdr_len + offsetof(struct tcphdr, th_sum); 2868 cmd |= E1000_TXD_CMD_TCP; 2869 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2870 } else if (csum_flags & CSUM_UDP) { 2871 /* 2872 * Start offset for header checksum calculation. 2873 * End offset for header checksum calculation. 2874 * Offset of place to put the checksum. 2875 */ 2876 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2877 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2878 TXD->upper_setup.tcp_fields.tucso = 2879 hdr_len + offsetof(struct udphdr, uh_sum); 2880 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2881 } 2882 2883 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2884 E1000_TXD_DTYP_D; /* Data descr */ 2885 2886 /* Save the information for this csum offloading context */ 2887 adapter->csum_lhlen = ehdrlen; 2888 adapter->csum_iphlen = ip_hlen; 2889 adapter->csum_flags = csum_flags; 2890 adapter->csum_txd_upper = *txd_upper; 2891 adapter->csum_txd_lower = *txd_lower; 2892 2893 TXD->tcp_seg_setup.data = htole32(0); 2894 TXD->cmd_and_length = 2895 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2896 2897 if (++curr_txd == adapter->num_tx_desc) 2898 curr_txd = 0; 2899 2900 KKASSERT(adapter->num_tx_desc_avail > 0); 2901 adapter->num_tx_desc_avail--; 2902 2903 adapter->next_avail_tx_desc = curr_txd; 2904 return 1; 2905 } 2906 2907 static void 2908 em_txeof(struct adapter *adapter) 2909 { 2910 struct ifnet *ifp = &adapter->arpcom.ac_if; 2911 struct em_buffer *tx_buffer; 2912 int first, num_avail; 2913 2914 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2915 return; 2916 2917 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2918 return; 2919 2920 num_avail = adapter->num_tx_desc_avail; 2921 first = adapter->next_tx_to_clean; 2922 2923 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2924 struct e1000_tx_desc *tx_desc; 2925 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2926 2927 tx_desc = &adapter->tx_desc_base[dd_idx]; 2928 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2929 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2930 2931 if (++dd_idx == adapter->num_tx_desc) 2932 dd_idx = 0; 2933 2934 while (first != dd_idx) { 2935 logif(pkt_txclean); 2936 2937 num_avail++; 2938 2939 tx_buffer = &adapter->tx_buffer_area[first]; 2940 if (tx_buffer->m_head) { 2941 IFNET_STAT_INC(ifp, opackets, 1); 2942 bus_dmamap_unload(adapter->txtag, 2943 tx_buffer->map); 2944 m_freem(tx_buffer->m_head); 2945 tx_buffer->m_head = NULL; 2946 } 2947 2948 if (++first == adapter->num_tx_desc) 2949 first = 0; 2950 } 2951 } else { 2952 break; 2953 } 2954 } 2955 adapter->next_tx_to_clean = first; 2956 adapter->num_tx_desc_avail = num_avail; 2957 2958 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2959 adapter->tx_dd_head = 0; 2960 adapter->tx_dd_tail = 0; 2961 } 2962 2963 if (!EM_IS_OACTIVE(adapter)) { 2964 ifq_clr_oactive(&ifp->if_snd); 2965 2966 /* All clean, turn off the timer */ 2967 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2968 ifp->if_timer = 0; 2969 } 2970 } 2971 2972 static void 2973 em_tx_collect(struct adapter *adapter) 2974 { 2975 struct ifnet *ifp = &adapter->arpcom.ac_if; 2976 struct em_buffer *tx_buffer; 2977 int tdh, first, num_avail, dd_idx = -1; 2978 2979 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2980 return; 2981 2982 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2983 if (tdh == adapter->next_tx_to_clean) 2984 return; 2985 2986 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2987 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2988 2989 num_avail = adapter->num_tx_desc_avail; 2990 first = adapter->next_tx_to_clean; 2991 2992 while (first != tdh) { 2993 logif(pkt_txclean); 2994 2995 num_avail++; 2996 2997 tx_buffer = &adapter->tx_buffer_area[first]; 2998 if (tx_buffer->m_head) { 2999 IFNET_STAT_INC(ifp, opackets, 1); 3000 bus_dmamap_unload(adapter->txtag, 3001 tx_buffer->map); 3002 m_freem(tx_buffer->m_head); 3003 tx_buffer->m_head = NULL; 3004 } 3005 3006 if (first == dd_idx) { 3007 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3008 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3009 adapter->tx_dd_head = 0; 3010 adapter->tx_dd_tail = 0; 3011 dd_idx = -1; 3012 } else { 3013 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3014 } 3015 } 3016 3017 if (++first == adapter->num_tx_desc) 3018 first = 0; 3019 } 3020 adapter->next_tx_to_clean = first; 3021 adapter->num_tx_desc_avail = num_avail; 3022 3023 if (!EM_IS_OACTIVE(adapter)) { 3024 ifq_clr_oactive(&ifp->if_snd); 3025 3026 /* All clean, turn off the timer */ 3027 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3028 ifp->if_timer = 0; 3029 } 3030 } 3031 3032 /* 3033 * When Link is lost sometimes there is work still in the TX ring 3034 * which will result in a watchdog, rather than allow that do an 3035 * attempted cleanup and then reinit here. Note that this has been 3036 * seens mostly with fiber adapters. 3037 */ 3038 static void 3039 em_tx_purge(struct adapter *adapter) 3040 { 3041 struct ifnet *ifp = &adapter->arpcom.ac_if; 3042 3043 if (!adapter->link_active && ifp->if_timer) { 3044 em_tx_collect(adapter); 3045 if (ifp->if_timer) { 3046 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3047 ifp->if_timer = 0; 3048 em_init(adapter); 3049 } 3050 } 3051 } 3052 3053 static int 3054 em_newbuf(struct adapter *adapter, int i, int init) 3055 { 3056 struct mbuf *m; 3057 bus_dma_segment_t seg; 3058 bus_dmamap_t map; 3059 struct em_buffer *rx_buffer; 3060 int error, nseg; 3061 3062 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3063 if (m == NULL) { 3064 adapter->mbuf_cluster_failed++; 3065 if (init) { 3066 if_printf(&adapter->arpcom.ac_if, 3067 "Unable to allocate RX mbuf\n"); 3068 } 3069 return (ENOBUFS); 3070 } 3071 m->m_len = m->m_pkthdr.len = MCLBYTES; 3072 3073 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 3074 m_adj(m, ETHER_ALIGN); 3075 3076 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3077 adapter->rx_sparemap, m, 3078 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3079 if (error) { 3080 m_freem(m); 3081 if (init) { 3082 if_printf(&adapter->arpcom.ac_if, 3083 "Unable to load RX mbuf\n"); 3084 } 3085 return (error); 3086 } 3087 3088 rx_buffer = &adapter->rx_buffer_area[i]; 3089 if (rx_buffer->m_head != NULL) 3090 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3091 3092 map = rx_buffer->map; 3093 rx_buffer->map = adapter->rx_sparemap; 3094 adapter->rx_sparemap = map; 3095 3096 rx_buffer->m_head = m; 3097 3098 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3099 return (0); 3100 } 3101 3102 static int 3103 em_create_rx_ring(struct adapter *adapter) 3104 { 3105 device_t dev = adapter->dev; 3106 struct em_buffer *rx_buffer; 3107 int i, error; 3108 3109 adapter->rx_buffer_area = 3110 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3111 M_DEVBUF, M_WAITOK | M_ZERO); 3112 3113 /* 3114 * Create DMA tag for rx buffers 3115 */ 3116 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3117 1, 0, /* alignment, bounds */ 3118 BUS_SPACE_MAXADDR, /* lowaddr */ 3119 BUS_SPACE_MAXADDR, /* highaddr */ 3120 NULL, NULL, /* filter, filterarg */ 3121 MCLBYTES, /* maxsize */ 3122 1, /* nsegments */ 3123 MCLBYTES, /* maxsegsize */ 3124 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3125 &adapter->rxtag); 3126 if (error) { 3127 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3128 kfree(adapter->rx_buffer_area, M_DEVBUF); 3129 adapter->rx_buffer_area = NULL; 3130 return error; 3131 } 3132 3133 /* 3134 * Create spare DMA map for rx buffers 3135 */ 3136 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3137 &adapter->rx_sparemap); 3138 if (error) { 3139 device_printf(dev, "Unable to create spare RX DMA map\n"); 3140 bus_dma_tag_destroy(adapter->rxtag); 3141 kfree(adapter->rx_buffer_area, M_DEVBUF); 3142 adapter->rx_buffer_area = NULL; 3143 return error; 3144 } 3145 3146 /* 3147 * Create DMA maps for rx buffers 3148 */ 3149 for (i = 0; i < adapter->num_rx_desc; i++) { 3150 rx_buffer = &adapter->rx_buffer_area[i]; 3151 3152 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3153 &rx_buffer->map); 3154 if (error) { 3155 device_printf(dev, "Unable to create RX DMA map\n"); 3156 em_destroy_rx_ring(adapter, i); 3157 return error; 3158 } 3159 } 3160 return (0); 3161 } 3162 3163 static int 3164 em_init_rx_ring(struct adapter *adapter) 3165 { 3166 int i, error; 3167 3168 /* Reset descriptor ring */ 3169 bzero(adapter->rx_desc_base, 3170 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3171 3172 /* Allocate new ones. */ 3173 for (i = 0; i < adapter->num_rx_desc; i++) { 3174 error = em_newbuf(adapter, i, 1); 3175 if (error) 3176 return (error); 3177 } 3178 3179 /* Setup our descriptor pointers */ 3180 adapter->next_rx_desc_to_check = 0; 3181 3182 return (0); 3183 } 3184 3185 static void 3186 em_init_rx_unit(struct adapter *adapter) 3187 { 3188 struct ifnet *ifp = &adapter->arpcom.ac_if; 3189 uint64_t bus_addr; 3190 uint32_t rctl; 3191 3192 /* 3193 * Make sure receives are disabled while setting 3194 * up the descriptor ring 3195 */ 3196 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3197 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3198 3199 if (adapter->hw.mac.type >= e1000_82540) { 3200 uint32_t itr; 3201 3202 /* 3203 * Set the interrupt throttling rate. Value is calculated 3204 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3205 */ 3206 if (adapter->int_throttle_ceil) 3207 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3208 else 3209 itr = 0; 3210 em_set_itr(adapter, itr); 3211 } 3212 3213 /* Disable accelerated ackknowledge */ 3214 if (adapter->hw.mac.type == e1000_82574) { 3215 E1000_WRITE_REG(&adapter->hw, 3216 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3217 } 3218 3219 /* Receive Checksum Offload for TCP and UDP */ 3220 if (ifp->if_capenable & IFCAP_RXCSUM) { 3221 uint32_t rxcsum; 3222 3223 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3224 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3225 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3226 } 3227 3228 /* 3229 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3230 * long latencies are observed, like Lenovo X60. This 3231 * change eliminates the problem, but since having positive 3232 * values in RDTR is a known source of problems on other 3233 * platforms another solution is being sought. 3234 */ 3235 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3236 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3237 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3238 } 3239 3240 /* 3241 * Setup the Base and Length of the Rx Descriptor Ring 3242 */ 3243 bus_addr = adapter->rxdma.dma_paddr; 3244 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3245 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3246 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3247 (uint32_t)(bus_addr >> 32)); 3248 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3249 (uint32_t)bus_addr); 3250 3251 /* 3252 * Setup the HW Rx Head and Tail Descriptor Pointers 3253 */ 3254 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3255 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3256 3257 /* Set PTHRESH for improved jumbo performance */ 3258 if (((adapter->hw.mac.type == e1000_ich9lan) || 3259 (adapter->hw.mac.type == e1000_pch2lan) || 3260 (adapter->hw.mac.type == e1000_ich10lan)) && 3261 (ifp->if_mtu > ETHERMTU)) { 3262 uint32_t rxdctl; 3263 3264 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3265 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3266 } 3267 3268 if (adapter->hw.mac.type == e1000_pch2lan) { 3269 if (ifp->if_mtu > ETHERMTU) 3270 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3271 else 3272 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3273 } 3274 3275 /* Setup the Receive Control Register */ 3276 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3277 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3278 E1000_RCTL_RDMTS_HALF | 3279 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3280 3281 /* Make sure VLAN Filters are off */ 3282 rctl &= ~E1000_RCTL_VFE; 3283 3284 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3285 rctl |= E1000_RCTL_SBP; 3286 else 3287 rctl &= ~E1000_RCTL_SBP; 3288 3289 switch (adapter->rx_buffer_len) { 3290 default: 3291 case 2048: 3292 rctl |= E1000_RCTL_SZ_2048; 3293 break; 3294 3295 case 4096: 3296 rctl |= E1000_RCTL_SZ_4096 | 3297 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3298 break; 3299 3300 case 8192: 3301 rctl |= E1000_RCTL_SZ_8192 | 3302 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3303 break; 3304 3305 case 16384: 3306 rctl |= E1000_RCTL_SZ_16384 | 3307 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3308 break; 3309 } 3310 3311 if (ifp->if_mtu > ETHERMTU) 3312 rctl |= E1000_RCTL_LPE; 3313 else 3314 rctl &= ~E1000_RCTL_LPE; 3315 3316 /* Enable Receives */ 3317 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3318 } 3319 3320 static void 3321 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3322 { 3323 struct em_buffer *rx_buffer; 3324 int i; 3325 3326 if (adapter->rx_buffer_area == NULL) 3327 return; 3328 3329 for (i = 0; i < ndesc; i++) { 3330 rx_buffer = &adapter->rx_buffer_area[i]; 3331 3332 KKASSERT(rx_buffer->m_head == NULL); 3333 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3334 } 3335 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3336 bus_dma_tag_destroy(adapter->rxtag); 3337 3338 kfree(adapter->rx_buffer_area, M_DEVBUF); 3339 adapter->rx_buffer_area = NULL; 3340 } 3341 3342 static void 3343 em_rxeof(struct adapter *adapter, int count) 3344 { 3345 struct ifnet *ifp = &adapter->arpcom.ac_if; 3346 uint8_t status, accept_frame = 0, eop = 0; 3347 uint16_t len, desc_len, prev_len_adj; 3348 struct e1000_rx_desc *current_desc; 3349 struct mbuf *mp; 3350 int i; 3351 3352 i = adapter->next_rx_desc_to_check; 3353 current_desc = &adapter->rx_desc_base[i]; 3354 3355 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3356 return; 3357 3358 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3359 struct mbuf *m = NULL; 3360 3361 logif(pkt_receive); 3362 3363 mp = adapter->rx_buffer_area[i].m_head; 3364 3365 /* 3366 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3367 * needs to access the last received byte in the mbuf. 3368 */ 3369 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3370 BUS_DMASYNC_POSTREAD); 3371 3372 accept_frame = 1; 3373 prev_len_adj = 0; 3374 desc_len = le16toh(current_desc->length); 3375 status = current_desc->status; 3376 if (status & E1000_RXD_STAT_EOP) { 3377 count--; 3378 eop = 1; 3379 if (desc_len < ETHER_CRC_LEN) { 3380 len = 0; 3381 prev_len_adj = ETHER_CRC_LEN - desc_len; 3382 } else { 3383 len = desc_len - ETHER_CRC_LEN; 3384 } 3385 } else { 3386 eop = 0; 3387 len = desc_len; 3388 } 3389 3390 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3391 uint8_t last_byte; 3392 uint32_t pkt_len = desc_len; 3393 3394 if (adapter->fmp != NULL) 3395 pkt_len += adapter->fmp->m_pkthdr.len; 3396 3397 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3398 if (TBI_ACCEPT(&adapter->hw, status, 3399 current_desc->errors, pkt_len, last_byte, 3400 adapter->min_frame_size, adapter->max_frame_size)) { 3401 e1000_tbi_adjust_stats_82543(&adapter->hw, 3402 &adapter->stats, pkt_len, 3403 adapter->hw.mac.addr, 3404 adapter->max_frame_size); 3405 if (len > 0) 3406 len--; 3407 } else { 3408 accept_frame = 0; 3409 } 3410 } 3411 3412 if (accept_frame) { 3413 if (em_newbuf(adapter, i, 0) != 0) { 3414 IFNET_STAT_INC(ifp, iqdrops, 1); 3415 goto discard; 3416 } 3417 3418 /* Assign correct length to the current fragment */ 3419 mp->m_len = len; 3420 3421 if (adapter->fmp == NULL) { 3422 mp->m_pkthdr.len = len; 3423 adapter->fmp = mp; /* Store the first mbuf */ 3424 adapter->lmp = mp; 3425 } else { 3426 /* 3427 * Chain mbuf's together 3428 */ 3429 3430 /* 3431 * Adjust length of previous mbuf in chain if 3432 * we received less than 4 bytes in the last 3433 * descriptor. 3434 */ 3435 if (prev_len_adj > 0) { 3436 adapter->lmp->m_len -= prev_len_adj; 3437 adapter->fmp->m_pkthdr.len -= 3438 prev_len_adj; 3439 } 3440 adapter->lmp->m_next = mp; 3441 adapter->lmp = adapter->lmp->m_next; 3442 adapter->fmp->m_pkthdr.len += len; 3443 } 3444 3445 if (eop) { 3446 adapter->fmp->m_pkthdr.rcvif = ifp; 3447 IFNET_STAT_INC(ifp, ipackets, 1); 3448 3449 if (ifp->if_capenable & IFCAP_RXCSUM) { 3450 em_rxcsum(adapter, current_desc, 3451 adapter->fmp); 3452 } 3453 3454 if (status & E1000_RXD_STAT_VP) { 3455 adapter->fmp->m_pkthdr.ether_vlantag = 3456 (le16toh(current_desc->special) & 3457 E1000_RXD_SPC_VLAN_MASK); 3458 adapter->fmp->m_flags |= M_VLANTAG; 3459 } 3460 m = adapter->fmp; 3461 adapter->fmp = NULL; 3462 adapter->lmp = NULL; 3463 } 3464 } else { 3465 IFNET_STAT_INC(ifp, ierrors, 1); 3466 discard: 3467 #ifdef foo 3468 /* Reuse loaded DMA map and just update mbuf chain */ 3469 mp = adapter->rx_buffer_area[i].m_head; 3470 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3471 mp->m_data = mp->m_ext.ext_buf; 3472 mp->m_next = NULL; 3473 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3474 m_adj(mp, ETHER_ALIGN); 3475 #endif 3476 if (adapter->fmp != NULL) { 3477 m_freem(adapter->fmp); 3478 adapter->fmp = NULL; 3479 adapter->lmp = NULL; 3480 } 3481 m = NULL; 3482 } 3483 3484 /* Zero out the receive descriptors status. */ 3485 current_desc->status = 0; 3486 3487 if (m != NULL) 3488 ifp->if_input(ifp, m); 3489 3490 /* Advance our pointers to the next descriptor. */ 3491 if (++i == adapter->num_rx_desc) 3492 i = 0; 3493 current_desc = &adapter->rx_desc_base[i]; 3494 } 3495 adapter->next_rx_desc_to_check = i; 3496 3497 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3498 if (--i < 0) 3499 i = adapter->num_rx_desc - 1; 3500 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3501 } 3502 3503 static void 3504 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3505 struct mbuf *mp) 3506 { 3507 /* 82543 or newer only */ 3508 if (adapter->hw.mac.type < e1000_82543 || 3509 /* Ignore Checksum bit is set */ 3510 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3511 return; 3512 3513 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3514 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3515 /* IP Checksum Good */ 3516 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3517 } 3518 3519 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3520 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3521 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3522 CSUM_PSEUDO_HDR | 3523 CSUM_FRAG_NOT_CHECKED; 3524 mp->m_pkthdr.csum_data = htons(0xffff); 3525 } 3526 } 3527 3528 static void 3529 em_enable_intr(struct adapter *adapter) 3530 { 3531 uint32_t ims_mask = IMS_ENABLE_MASK; 3532 3533 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3534 3535 #if 0 3536 /* XXX MSIX */ 3537 if (adapter->hw.mac.type == e1000_82574) { 3538 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3539 ims_mask |= EM_MSIX_MASK; 3540 } 3541 #endif 3542 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3543 } 3544 3545 static void 3546 em_disable_intr(struct adapter *adapter) 3547 { 3548 uint32_t clear = 0xffffffff; 3549 3550 /* 3551 * The first version of 82542 had an errata where when link was forced 3552 * it would stay up even up even if the cable was disconnected. 3553 * Sequence errors were used to detect the disconnect and then the 3554 * driver would unforce the link. This code in the in the ISR. For 3555 * this to work correctly the Sequence error interrupt had to be 3556 * enabled all the time. 3557 */ 3558 if (adapter->hw.mac.type == e1000_82542 && 3559 adapter->hw.revision_id == E1000_REVISION_2) 3560 clear &= ~E1000_ICR_RXSEQ; 3561 else if (adapter->hw.mac.type == e1000_82574) 3562 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3563 3564 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3565 3566 adapter->npoll.ifpc_stcount = 0; 3567 3568 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3569 } 3570 3571 /* 3572 * Bit of a misnomer, what this really means is 3573 * to enable OS management of the system... aka 3574 * to disable special hardware management features 3575 */ 3576 static void 3577 em_get_mgmt(struct adapter *adapter) 3578 { 3579 /* A shared code workaround */ 3580 #define E1000_82542_MANC2H E1000_MANC2H 3581 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3582 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3583 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3584 3585 /* disable hardware interception of ARP */ 3586 manc &= ~(E1000_MANC_ARP_EN); 3587 3588 /* enable receiving management packets to the host */ 3589 if (adapter->hw.mac.type >= e1000_82571) { 3590 manc |= E1000_MANC_EN_MNG2HOST; 3591 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3592 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3593 manc2h |= E1000_MNG2HOST_PORT_623; 3594 manc2h |= E1000_MNG2HOST_PORT_664; 3595 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3596 } 3597 3598 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3599 } 3600 } 3601 3602 /* 3603 * Give control back to hardware management 3604 * controller if there is one. 3605 */ 3606 static void 3607 em_rel_mgmt(struct adapter *adapter) 3608 { 3609 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3610 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3611 3612 /* re-enable hardware interception of ARP */ 3613 manc |= E1000_MANC_ARP_EN; 3614 3615 if (adapter->hw.mac.type >= e1000_82571) 3616 manc &= ~E1000_MANC_EN_MNG2HOST; 3617 3618 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3619 } 3620 } 3621 3622 /* 3623 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3624 * For ASF and Pass Through versions of f/w this means that 3625 * the driver is loaded. For AMT version (only with 82573) 3626 * of the f/w this means that the network i/f is open. 3627 */ 3628 static void 3629 em_get_hw_control(struct adapter *adapter) 3630 { 3631 /* Let firmware know the driver has taken over */ 3632 if (adapter->hw.mac.type == e1000_82573) { 3633 uint32_t swsm; 3634 3635 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3636 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3637 swsm | E1000_SWSM_DRV_LOAD); 3638 } else { 3639 uint32_t ctrl_ext; 3640 3641 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3642 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3643 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3644 } 3645 adapter->flags |= EM_FLAG_HW_CTRL; 3646 } 3647 3648 /* 3649 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3650 * For ASF and Pass Through versions of f/w this means that the 3651 * driver is no longer loaded. For AMT version (only with 82573) 3652 * of the f/w this means that the network i/f is closed. 3653 */ 3654 static void 3655 em_rel_hw_control(struct adapter *adapter) 3656 { 3657 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3658 return; 3659 adapter->flags &= ~EM_FLAG_HW_CTRL; 3660 3661 /* Let firmware taken over control of h/w */ 3662 if (adapter->hw.mac.type == e1000_82573) { 3663 uint32_t swsm; 3664 3665 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3666 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3667 swsm & ~E1000_SWSM_DRV_LOAD); 3668 } else { 3669 uint32_t ctrl_ext; 3670 3671 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3672 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3673 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3674 } 3675 } 3676 3677 static int 3678 em_is_valid_eaddr(const uint8_t *addr) 3679 { 3680 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3681 3682 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3683 return (FALSE); 3684 3685 return (TRUE); 3686 } 3687 3688 /* 3689 * Enable PCI Wake On Lan capability 3690 */ 3691 void 3692 em_enable_wol(device_t dev) 3693 { 3694 uint16_t cap, status; 3695 uint8_t id; 3696 3697 /* First find the capabilities pointer*/ 3698 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3699 3700 /* Read the PM Capabilities */ 3701 id = pci_read_config(dev, cap, 1); 3702 if (id != PCIY_PMG) /* Something wrong */ 3703 return; 3704 3705 /* 3706 * OK, we have the power capabilities, 3707 * so now get the status register 3708 */ 3709 cap += PCIR_POWER_STATUS; 3710 status = pci_read_config(dev, cap, 2); 3711 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3712 pci_write_config(dev, cap, status, 2); 3713 } 3714 3715 3716 /* 3717 * 82544 Coexistence issue workaround. 3718 * There are 2 issues. 3719 * 1. Transmit Hang issue. 3720 * To detect this issue, following equation can be used... 3721 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3722 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3723 * 3724 * 2. DAC issue. 3725 * To detect this issue, following equation can be used... 3726 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3727 * If SUM[3:0] is in between 9 to c, we will have this issue. 3728 * 3729 * WORKAROUND: 3730 * Make sure we do not have ending address 3731 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3732 */ 3733 static uint32_t 3734 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3735 { 3736 uint32_t safe_terminator; 3737 3738 /* 3739 * Since issue is sensitive to length and address. 3740 * Let us first check the address... 3741 */ 3742 if (length <= 4) { 3743 desc_array->descriptor[0].address = address; 3744 desc_array->descriptor[0].length = length; 3745 desc_array->elements = 1; 3746 return (desc_array->elements); 3747 } 3748 3749 safe_terminator = 3750 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3751 3752 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3753 if (safe_terminator == 0 || 3754 (safe_terminator > 4 && safe_terminator < 9) || 3755 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3756 desc_array->descriptor[0].address = address; 3757 desc_array->descriptor[0].length = length; 3758 desc_array->elements = 1; 3759 return (desc_array->elements); 3760 } 3761 3762 desc_array->descriptor[0].address = address; 3763 desc_array->descriptor[0].length = length - 4; 3764 desc_array->descriptor[1].address = address + (length - 4); 3765 desc_array->descriptor[1].length = 4; 3766 desc_array->elements = 2; 3767 return (desc_array->elements); 3768 } 3769 3770 static void 3771 em_update_stats(struct adapter *adapter) 3772 { 3773 struct ifnet *ifp = &adapter->arpcom.ac_if; 3774 3775 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3776 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3777 adapter->stats.symerrs += 3778 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3779 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3780 } 3781 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3782 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3783 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3784 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3785 3786 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3787 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3788 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3789 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3790 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3791 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3792 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3793 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3794 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3795 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3796 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3797 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3798 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3799 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3800 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3801 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3802 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3803 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3804 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3805 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3806 3807 /* For the 64-bit byte counters the low dword must be read first. */ 3808 /* Both registers clear on the read of the high dword */ 3809 3810 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3811 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3812 3813 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3814 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3815 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3816 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3817 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3818 3819 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3820 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3821 3822 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3823 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3824 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3825 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3826 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3827 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3828 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3829 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3830 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3831 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3832 3833 if (adapter->hw.mac.type >= e1000_82543) { 3834 adapter->stats.algnerrc += 3835 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3836 adapter->stats.rxerrc += 3837 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3838 adapter->stats.tncrs += 3839 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3840 adapter->stats.cexterr += 3841 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3842 adapter->stats.tsctc += 3843 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3844 adapter->stats.tsctfc += 3845 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3846 } 3847 3848 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 3849 3850 /* Rx Errors */ 3851 IFNET_STAT_SET(ifp, ierrors, 3852 adapter->dropped_pkts + adapter->stats.rxerrc + 3853 adapter->stats.crcerrs + adapter->stats.algnerrc + 3854 adapter->stats.ruc + adapter->stats.roc + 3855 adapter->stats.mpc + adapter->stats.cexterr); 3856 3857 /* Tx Errors */ 3858 IFNET_STAT_SET(ifp, oerrors, 3859 adapter->stats.ecol + adapter->stats.latecol + 3860 adapter->watchdog_events); 3861 } 3862 3863 static void 3864 em_print_debug_info(struct adapter *adapter) 3865 { 3866 device_t dev = adapter->dev; 3867 uint8_t *hw_addr = adapter->hw.hw_addr; 3868 3869 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3870 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3871 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3872 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3873 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3874 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3875 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3876 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3877 adapter->hw.fc.high_water, 3878 adapter->hw.fc.low_water); 3879 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3880 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3881 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3882 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3883 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3884 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3885 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3886 (long long)adapter->tx_fifo_wrk_cnt, 3887 (long long)adapter->tx_fifo_reset_cnt); 3888 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3889 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3890 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3891 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3892 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3893 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3894 device_printf(dev, "Num Tx descriptors avail = %d\n", 3895 adapter->num_tx_desc_avail); 3896 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3897 adapter->no_tx_desc_avail1); 3898 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3899 adapter->no_tx_desc_avail2); 3900 device_printf(dev, "Std mbuf failed = %ld\n", 3901 adapter->mbuf_alloc_failed); 3902 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3903 adapter->mbuf_cluster_failed); 3904 device_printf(dev, "Driver dropped packets = %ld\n", 3905 adapter->dropped_pkts); 3906 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3907 adapter->no_tx_dma_setup); 3908 } 3909 3910 static void 3911 em_print_hw_stats(struct adapter *adapter) 3912 { 3913 device_t dev = adapter->dev; 3914 3915 device_printf(dev, "Excessive collisions = %lld\n", 3916 (long long)adapter->stats.ecol); 3917 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3918 device_printf(dev, "Symbol errors = %lld\n", 3919 (long long)adapter->stats.symerrs); 3920 #endif 3921 device_printf(dev, "Sequence errors = %lld\n", 3922 (long long)adapter->stats.sec); 3923 device_printf(dev, "Defer count = %lld\n", 3924 (long long)adapter->stats.dc); 3925 device_printf(dev, "Missed Packets = %lld\n", 3926 (long long)adapter->stats.mpc); 3927 device_printf(dev, "Receive No Buffers = %lld\n", 3928 (long long)adapter->stats.rnbc); 3929 /* RLEC is inaccurate on some hardware, calculate our own. */ 3930 device_printf(dev, "Receive Length Errors = %lld\n", 3931 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3932 device_printf(dev, "Receive errors = %lld\n", 3933 (long long)adapter->stats.rxerrc); 3934 device_printf(dev, "Crc errors = %lld\n", 3935 (long long)adapter->stats.crcerrs); 3936 device_printf(dev, "Alignment errors = %lld\n", 3937 (long long)adapter->stats.algnerrc); 3938 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3939 (long long)adapter->stats.cexterr); 3940 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3941 device_printf(dev, "watchdog timeouts = %ld\n", 3942 adapter->watchdog_events); 3943 device_printf(dev, "XON Rcvd = %lld\n", 3944 (long long)adapter->stats.xonrxc); 3945 device_printf(dev, "XON Xmtd = %lld\n", 3946 (long long)adapter->stats.xontxc); 3947 device_printf(dev, "XOFF Rcvd = %lld\n", 3948 (long long)adapter->stats.xoffrxc); 3949 device_printf(dev, "XOFF Xmtd = %lld\n", 3950 (long long)adapter->stats.xofftxc); 3951 device_printf(dev, "Good Packets Rcvd = %lld\n", 3952 (long long)adapter->stats.gprc); 3953 device_printf(dev, "Good Packets Xmtd = %lld\n", 3954 (long long)adapter->stats.gptc); 3955 } 3956 3957 static void 3958 em_print_nvm_info(struct adapter *adapter) 3959 { 3960 uint16_t eeprom_data; 3961 int i, j, row = 0; 3962 3963 /* Its a bit crude, but it gets the job done */ 3964 kprintf("\nInterface EEPROM Dump:\n"); 3965 kprintf("Offset\n0x0000 "); 3966 for (i = 0, j = 0; i < 32; i++, j++) { 3967 if (j == 8) { /* Make the offset block */ 3968 j = 0; ++row; 3969 kprintf("\n0x00%x0 ",row); 3970 } 3971 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3972 kprintf("%04x ", eeprom_data); 3973 } 3974 kprintf("\n"); 3975 } 3976 3977 static int 3978 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3979 { 3980 struct adapter *adapter; 3981 struct ifnet *ifp; 3982 int error, result; 3983 3984 result = -1; 3985 error = sysctl_handle_int(oidp, &result, 0, req); 3986 if (error || !req->newptr) 3987 return (error); 3988 3989 adapter = (struct adapter *)arg1; 3990 ifp = &adapter->arpcom.ac_if; 3991 3992 lwkt_serialize_enter(ifp->if_serializer); 3993 3994 if (result == 1) 3995 em_print_debug_info(adapter); 3996 3997 /* 3998 * This value will cause a hex dump of the 3999 * first 32 16-bit words of the EEPROM to 4000 * the screen. 4001 */ 4002 if (result == 2) 4003 em_print_nvm_info(adapter); 4004 4005 lwkt_serialize_exit(ifp->if_serializer); 4006 4007 return (error); 4008 } 4009 4010 static int 4011 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4012 { 4013 int error, result; 4014 4015 result = -1; 4016 error = sysctl_handle_int(oidp, &result, 0, req); 4017 if (error || !req->newptr) 4018 return (error); 4019 4020 if (result == 1) { 4021 struct adapter *adapter = (struct adapter *)arg1; 4022 struct ifnet *ifp = &adapter->arpcom.ac_if; 4023 4024 lwkt_serialize_enter(ifp->if_serializer); 4025 em_print_hw_stats(adapter); 4026 lwkt_serialize_exit(ifp->if_serializer); 4027 } 4028 return (error); 4029 } 4030 4031 static void 4032 em_add_sysctl(struct adapter *adapter) 4033 { 4034 sysctl_ctx_init(&adapter->sysctl_ctx); 4035 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 4036 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 4037 device_get_nameunit(adapter->dev), 4038 CTLFLAG_RD, 0, ""); 4039 if (adapter->sysctl_tree == NULL) { 4040 device_printf(adapter->dev, "can't add sysctl node\n"); 4041 } else { 4042 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4043 SYSCTL_CHILDREN(adapter->sysctl_tree), 4044 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4045 em_sysctl_debug_info, "I", "Debug Information"); 4046 4047 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4048 SYSCTL_CHILDREN(adapter->sysctl_tree), 4049 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4050 em_sysctl_stats, "I", "Statistics"); 4051 4052 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4053 SYSCTL_CHILDREN(adapter->sysctl_tree), 4054 OID_AUTO, "rxd", CTLFLAG_RD, 4055 &adapter->num_rx_desc, 0, NULL); 4056 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4057 SYSCTL_CHILDREN(adapter->sysctl_tree), 4058 OID_AUTO, "txd", CTLFLAG_RD, 4059 &adapter->num_tx_desc, 0, NULL); 4060 4061 if (adapter->hw.mac.type >= e1000_82540) { 4062 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4063 SYSCTL_CHILDREN(adapter->sysctl_tree), 4064 OID_AUTO, "int_throttle_ceil", 4065 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4066 em_sysctl_int_throttle, "I", 4067 "interrupt throttling rate"); 4068 } 4069 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4070 SYSCTL_CHILDREN(adapter->sysctl_tree), 4071 OID_AUTO, "int_tx_nsegs", 4072 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4073 em_sysctl_int_tx_nsegs, "I", 4074 "# segments per TX interrupt"); 4075 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4076 SYSCTL_CHILDREN(adapter->sysctl_tree), 4077 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4078 &adapter->tx_wreg_nsegs, 0, 4079 "# segments before write to hardware register"); 4080 } 4081 } 4082 4083 static int 4084 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4085 { 4086 struct adapter *adapter = (void *)arg1; 4087 struct ifnet *ifp = &adapter->arpcom.ac_if; 4088 int error, throttle; 4089 4090 throttle = adapter->int_throttle_ceil; 4091 error = sysctl_handle_int(oidp, &throttle, 0, req); 4092 if (error || req->newptr == NULL) 4093 return error; 4094 if (throttle < 0 || throttle > 1000000000 / 256) 4095 return EINVAL; 4096 4097 if (throttle) { 4098 /* 4099 * Set the interrupt throttling rate in 256ns increments, 4100 * recalculate sysctl value assignment to get exact frequency. 4101 */ 4102 throttle = 1000000000 / 256 / throttle; 4103 4104 /* Upper 16bits of ITR is reserved and should be zero */ 4105 if (throttle & 0xffff0000) 4106 return EINVAL; 4107 } 4108 4109 lwkt_serialize_enter(ifp->if_serializer); 4110 4111 if (throttle) 4112 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4113 else 4114 adapter->int_throttle_ceil = 0; 4115 4116 if (ifp->if_flags & IFF_RUNNING) 4117 em_set_itr(adapter, throttle); 4118 4119 lwkt_serialize_exit(ifp->if_serializer); 4120 4121 if (bootverbose) { 4122 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4123 adapter->int_throttle_ceil); 4124 } 4125 return 0; 4126 } 4127 4128 static int 4129 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4130 { 4131 struct adapter *adapter = (void *)arg1; 4132 struct ifnet *ifp = &adapter->arpcom.ac_if; 4133 int error, segs; 4134 4135 segs = adapter->tx_int_nsegs; 4136 error = sysctl_handle_int(oidp, &segs, 0, req); 4137 if (error || req->newptr == NULL) 4138 return error; 4139 if (segs <= 0) 4140 return EINVAL; 4141 4142 lwkt_serialize_enter(ifp->if_serializer); 4143 4144 /* 4145 * Don't allow int_tx_nsegs to become: 4146 * o Less the oact_tx_desc 4147 * o Too large that no TX desc will cause TX interrupt to 4148 * be generated (OACTIVE will never recover) 4149 * o Too small that will cause tx_dd[] overflow 4150 */ 4151 if (segs < adapter->oact_tx_desc || 4152 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4153 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4154 error = EINVAL; 4155 } else { 4156 error = 0; 4157 adapter->tx_int_nsegs = segs; 4158 } 4159 4160 lwkt_serialize_exit(ifp->if_serializer); 4161 4162 return error; 4163 } 4164 4165 static void 4166 em_set_itr(struct adapter *adapter, uint32_t itr) 4167 { 4168 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4169 if (adapter->hw.mac.type == e1000_82574) { 4170 int i; 4171 4172 /* 4173 * When using MSIX interrupts we need to 4174 * throttle using the EITR register 4175 */ 4176 for (i = 0; i < 4; ++i) { 4177 E1000_WRITE_REG(&adapter->hw, 4178 E1000_EITR_82574(i), itr); 4179 } 4180 } 4181 } 4182 4183 static void 4184 em_disable_aspm(struct adapter *adapter) 4185 { 4186 uint16_t link_cap, link_ctrl, disable; 4187 uint8_t pcie_ptr, reg; 4188 device_t dev = adapter->dev; 4189 4190 switch (adapter->hw.mac.type) { 4191 case e1000_82571: 4192 case e1000_82572: 4193 case e1000_82573: 4194 /* 4195 * 82573 specification update 4196 * errata #8 disable L0s 4197 * errata #41 disable L1 4198 * 4199 * 82571/82572 specification update 4200 # errata #13 disable L1 4201 * errata #68 disable L0s 4202 */ 4203 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4204 break; 4205 4206 case e1000_82574: 4207 case e1000_82583: 4208 /* 4209 * 82574 specification update errata #20 4210 * 82583 specification update errata #9 4211 * 4212 * There is no need to disable L1 4213 */ 4214 disable = PCIEM_LNKCTL_ASPM_L0S; 4215 break; 4216 4217 default: 4218 return; 4219 } 4220 4221 pcie_ptr = pci_get_pciecap_ptr(dev); 4222 if (pcie_ptr == 0) 4223 return; 4224 4225 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4226 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4227 return; 4228 4229 if (bootverbose) { 4230 if_printf(&adapter->arpcom.ac_if, 4231 "disable ASPM %#02x\n", disable); 4232 } 4233 4234 reg = pcie_ptr + PCIER_LINKCTRL; 4235 link_ctrl = pci_read_config(dev, reg, 2); 4236 link_ctrl &= ~disable; 4237 pci_write_config(dev, reg, link_ctrl, 2); 4238 } 4239 4240 static int 4241 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4242 { 4243 int iphlen, hoff, thoff, ex = 0; 4244 struct mbuf *m; 4245 struct ip *ip; 4246 4247 m = *mp; 4248 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4249 4250 iphlen = m->m_pkthdr.csum_iphlen; 4251 thoff = m->m_pkthdr.csum_thlen; 4252 hoff = m->m_pkthdr.csum_lhlen; 4253 4254 KASSERT(iphlen > 0, ("invalid ip hlen")); 4255 KASSERT(thoff > 0, ("invalid tcp hlen")); 4256 KASSERT(hoff > 0, ("invalid ether hlen")); 4257 4258 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4259 ex = 4; 4260 4261 if (m->m_len < hoff + iphlen + thoff + ex) { 4262 m = m_pullup(m, hoff + iphlen + thoff + ex); 4263 if (m == NULL) { 4264 *mp = NULL; 4265 return ENOBUFS; 4266 } 4267 *mp = m; 4268 } 4269 ip = mtodoff(m, struct ip *, hoff); 4270 ip->ip_len = 0; 4271 4272 return 0; 4273 } 4274 4275 static int 4276 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4277 uint32_t *txd_upper, uint32_t *txd_lower) 4278 { 4279 struct e1000_context_desc *TXD; 4280 int hoff, iphlen, thoff, hlen; 4281 int mss, pktlen, curr_txd; 4282 4283 iphlen = mp->m_pkthdr.csum_iphlen; 4284 thoff = mp->m_pkthdr.csum_thlen; 4285 hoff = mp->m_pkthdr.csum_lhlen; 4286 mss = mp->m_pkthdr.tso_segsz; 4287 pktlen = mp->m_pkthdr.len; 4288 4289 if (adapter->csum_flags == CSUM_TSO && 4290 adapter->csum_iphlen == iphlen && 4291 adapter->csum_lhlen == hoff && 4292 adapter->csum_thlen == thoff && 4293 adapter->csum_mss == mss && 4294 adapter->csum_pktlen == pktlen) { 4295 *txd_upper = adapter->csum_txd_upper; 4296 *txd_lower = adapter->csum_txd_lower; 4297 return 0; 4298 } 4299 hlen = hoff + iphlen + thoff; 4300 4301 /* 4302 * Setup a new TSO context. 4303 */ 4304 4305 curr_txd = adapter->next_avail_tx_desc; 4306 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4307 4308 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4309 E1000_TXD_DTYP_D | /* Data descr type */ 4310 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4311 4312 /* IP and/or TCP header checksum calculation and insertion. */ 4313 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4314 4315 /* 4316 * Start offset for header checksum calculation. 4317 * End offset for header checksum calculation. 4318 * Offset of place put the checksum. 4319 */ 4320 TXD->lower_setup.ip_fields.ipcss = hoff; 4321 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4322 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4323 4324 /* 4325 * Start offset for payload checksum calculation. 4326 * End offset for payload checksum calculation. 4327 * Offset of place to put the checksum. 4328 */ 4329 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4330 TXD->upper_setup.tcp_fields.tucse = 0; 4331 TXD->upper_setup.tcp_fields.tucso = 4332 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4333 4334 /* 4335 * Payload size per packet w/o any headers. 4336 * Length of all headers up to payload. 4337 */ 4338 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4339 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4340 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4341 E1000_TXD_CMD_DEXT | /* Extended descr */ 4342 E1000_TXD_CMD_TSE | /* TSE context */ 4343 E1000_TXD_CMD_IP | /* Do IP csum */ 4344 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4345 (pktlen - hlen)); /* Total len */ 4346 4347 /* Save the information for this TSO context */ 4348 adapter->csum_flags = CSUM_TSO; 4349 adapter->csum_lhlen = hoff; 4350 adapter->csum_iphlen = iphlen; 4351 adapter->csum_thlen = thoff; 4352 adapter->csum_mss = mss; 4353 adapter->csum_pktlen = pktlen; 4354 adapter->csum_txd_upper = *txd_upper; 4355 adapter->csum_txd_lower = *txd_lower; 4356 4357 if (++curr_txd == adapter->num_tx_desc) 4358 curr_txd = 0; 4359 4360 KKASSERT(adapter->num_tx_desc_avail > 0); 4361 adapter->num_tx_desc_avail--; 4362 4363 adapter->next_avail_tx_desc = curr_txd; 4364 return 1; 4365 } 4366